[AIX] Update data directives for AIX assembly

[daltenty]

Summary

The standard data emission directives (e.g. .short, .long) in the AIX assembler
have the unintended consequence of aligning their output to the natural byte
boundary. This cause problems because we aren't expecting behavior from the
Data*bitsDirectives, so the final alignment of data isn't correct in some cases
on AIX.

This patch updated the Data*bitsDirectives to use .vbyte pseudo-ops instead to emit the
data, since we will emit the .align directives as needed. We update the existing
testcases and add a test for emission of struct data.

[Xiangling_L]

llvm/lib/MC/MCAsmInfoXCOFF.cpp

33

Just a question here.
I checked the XL behavior, in the following case:

struct {
  int i;
  double n;
} a[] = {
         {9, 1.5},
};

test.s:

.csect  a{RW}, 3
.long   0x00000009              # "\0\0\0\t"
.long   0x3ff80000              # "?\370\0\0"
.long   0x00000000              # "\0\0\0\0"

Under 32-bit mode, XL split a double to two .long. So I am wondering can we do the same in LLVM?

llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll

29

I am wondering do you make it align to 1 due to any special reason? If not, according to AIX power alignment rule, this struct is supposed to be aligned to 4.

And also, we may want to add a more interesting case where the double is the first member of the struct, which is 8-byte aligned.
e.g.

%struct.anon = type <{ double, i32 }>
@astruct = global [1 x %struct.anon] [%struct.anon <{ double 7.000000e+00 , i32 1}>], align 8

By doing that, we can see how the padding is added using vbyte.

[daltenty]

llvm/lib/MC/MCAsmInfoXCOFF.cpp

33

Currently we cannot (we'll split it into two .vbyte 4, the way gcc does), as .long has implicit alignment behaviour (i.e. what we are trying to avoid in this patch) and at the point of value emission we don't have enough context to tell if it's safe to use.

AFAIK the streamer is expecting alignment constraints to already be taken care of explicitly by emission of .align,etc. by the time we get to emitting values, so we can't use any of the implicitly aligned directives.

llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll

29

I am wondering do you make it align to 1 due to any special reason? If not, according to AIX power alignment rule, this struct is supposed to be aligned to 4.

IIUC, we needn't be concerned with this adhering to AIX power alignment rules, we can validly generate this packed form out of clang with __attribute__ ((packed)). I had used the packed form since we were mainly interested in observing the effect of data directives (and thus any implicit alignment) used to write out the members, rather than anything from the ABI.

And also, we may want to add a more interesting case where the double is the first member of the struct, which is 8-byte aligned.
By doing that, we can see how the padding is added using vbyte.

The padding is actually emitted using .space directives, so I'm not sure if it buys us much in the context of this change, but I'll add this as a non-packed case for completeness.

[hubert.reinterpretcast]

llvm/lib/MC/MCAsmInfoXCOFF.cpp

32

I'm sure that "standard" is the right word for classifying the directives that happen to be similarly named to ones on some other platforms.

Suggestion:
Use .vbyte for data definition to avoid directives that apply an implicit alignment.

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp

63

s/on/under/;

llvm/test/CodeGen/PowerPC/aix-extern-weak.ll

54

Even if we aren't consistent on how many spaces we use for where the tabs are in the real output, let's be consistent at least on having exactly one space after the comma.

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

51

Same comment re: spaces after the comma. Please address throughout.

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

102

Whichever patch, between this and D80831, that lands later is going to have to deal with the merge conflict.

llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll

124

Please adjust the spacing to get the directives to align within at least the block (with indentation in relation to the label).

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

31

Same comment re: aligning the lines. Please fix throughout.

[daltenty]

• Update comments
• Add unpacked struct case and add tests
• Fix asm whitespace and block spacing in tests

[jasonliu]

llvm/lib/MC/MCAsmInfoXCOFF.cpp

23

I think the reason this was here is that we want to keep the same order as it is in the base class MCAsmInfo.
Is that something we still want to do? (which means Data16bitsDirective and Data32bitsDirective needs to go here?)

[daltenty]

llvm/lib/MC/MCAsmInfoXCOFF.cpp

23

I think it makes sense to move it here

[daltenty]

• Move directives in AsmInfo into base class order

[jasonliu]

Thanks. LGTM.

[hubert.reinterpretcast]

LGTM with minor nit.

llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll

31–33

Adjust spacing here.

45–47

Same here and in other places within this file.

[daltenty]

• Fix directive spacing

llvm/lib/MC/MCAsmInfoXCOFF.cpp

 MCAsmInfoXCOFF::MCAsmInfoXCOFF() {
   IsLittleEndian = false;
   SupportsQuotedNames = false;
   UseDotAlignForAlignment = true;
   ZeroDirective = "\t.space\t";
   ZeroDirectiveSupportsNonZeroValue = false;
   AsciiDirective = nullptr; // not supported
   AscizDirective = nullptr; // not supported
-  Data64bitsDirective = "\t.llong\t";
   COMMDirectiveAlignmentIsInBytes = false;
   LCOMMDirectiveAlignmentType = LCOMM::Log2Alignment;
   HasDotTypeDotSizeDirective = false;
   HasDotExternDirective = true;
   HasDotLGloblDirective = true;
   SymbolsHaveSMC = true;
   UseIntegratedAssembler = false;
   NeedsFunctionDescriptors = true;
+
+  // The standard AIX assembly directives auto-align, so they are not usable.
+  Data16bitsDirective = "\t.vbyte\t2, ";
+  Data32bitsDirective = "\t.vbyte\t4, ";
 }
 
 bool MCAsmInfoXCOFF::isAcceptableChar(char C) const {
   // QualName is allowed for a MCSymbolXCOFF, and
   // QualName contains '[' and ']'.
   if (C == '[' || C == ']')
     return true;
 
   return MCAsmInfo::isAcceptableChar(C);
 }

llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp

 }
 
 void PPCXCOFFMCAsmInfo::anchor() {}
 
 PPCXCOFFMCAsmInfo::PPCXCOFFMCAsmInfo(bool Is64Bit, const Triple &T) {
   if (T.getArch() == Triple::ppc64le)
     report_fatal_error("XCOFF is not supported for little-endian targets");
   CodePointerSize = CalleeSaveStackSlotSize = Is64Bit ? 8 : 4;
+
+  // A size of 8 is only supported by the assembler on 64-bit.
+  Data64bitsDirective = Is64Bit ? "\t.vbyte\t8, " : nullptr;
 }

llvm/test/CodeGen/PowerPC/aix-extern-weak.ll

 }
 
 declare extern_weak void @foo_ext_weak(i32*)
 
 ; COMMON:         .globl  main[DS]                # -- Begin function main
 ; COMMON-NEXT:    .globl  .main
 ; COMMON-NEXT:    .align  4
 ; COMMON-NEXT:    .csect main[DS]
-; BIT32-NEXT:     .long .main                   # @main
-; BIT32-NEXT:     .long TOC[TC0]
-; BIT32-NEXT:     .long 0
-; BIT64-NEXT:     .llong  .main                   # @main
-; BIT64-NEXT:     .llong  TOC[TC0]
-; BIT64-NEXT:     .llong  0
+; BIT32-NEXT:     .vbyte  4, .main                   # @main
+; BIT32-NEXT:     .vbyte  4, TOC[TC0]
+; BIT32-NEXT:     .vbyte  4, 0
+; BIT64-NEXT:     .vbyte  8, .main                   # @main
+; BIT64-NEXT:     .vbyte  8, TOC[TC0]
+; BIT64-NEXT:     .vbyte  8, 0
 ; COMMON-NEXT:    .csect  .text[PR]
 ; COMMON-NEXT:    .main:
 
 ; COMMON:         .csect  .data[RW]
 ; COMMON:         .globl  foo_ext_weak_p
 ; BIT32-NEXT:     .align  2
 ; BIT64-NEXT:     .align  3
 ; COMMON-NEXT: foo_ext_weak_p:
-; BIT32-NEXT:     .long foo_ext_weak_ref[DS]
-; BIT64-NEXT:     .llong  foo_ext_weak_ref[DS]
+; BIT32-NEXT:     .vbyte  4, foo_ext_weak_ref[DS]
+; BIT64-NEXT:     .vbyte  8,  foo_ext_weak_ref[DS]
 ; COMMON-NEXT:    .weak   b_w[UA]
 ; COMMON-NEXT:    .weak   foo_ext_weak_ref[DS]
 ; COMMON-NEXT:    .weak   .foo_ext_weak
 ; COMMON-NEXT:    .weak   foo_ext_weak[DS]
 ; COMMON-NEXT:    .toc
 ; COMMON-NEXT: LC0:
 ; COMMON-NEXT:    .tc foo_ext_weak_p[TC],foo_ext_weak_p
 ; COMMON-NEXT: LC1:

llvm/test/CodeGen/PowerPC/aix-extern.ll

 
 declare i32 @bar_extern(i32*)
 
 
 ; COMMON:           .globl  foo[DS]                 # -- Begin function foo
 ; COMMON-NEXT:      .globl  .foo
 ; COMMON-NEXT:      .align  4
 ; COMMON-NEXT:      .csect foo[DS]
-; BIT32-NEXT:       .long .foo                    # @foo
-; BIT32-NEXT:       .long TOC[TC0]
-; BIT32-NEXT:       .long 0
-; BIT64-NEXT:       .llong  .foo                    # @foo
-; BIT64-NEXT:       .llong  TOC[TC0]
-; BIT64-NEXT:       .llong  0
+; BIT32-NEXT:       .vbyte  4, .foo                    # @foo
+; BIT32-NEXT:       .vbyte  4, TOC[TC0]
+; BIT32-NEXT:       .vbyte  4, 0
+; BIT64-NEXT:       .vbyte  8, .foo                    # @foo
+; BIT64-NEXT:       .vbyte  8, TOC[TC0]
+; BIT64-NEXT:       .vbyte  8, 0
 ; COMMON-NEXT:      .csect .text[PR]
 ; COMMON-NEXT: .foo:
 
 ; COMMON:           .globl  main[DS]                # -- Begin function main
 ; COMMON-NEXT:      .globl  .main
 ; COMMON-NEXT:      .align  4
 ; COMMON-NEXT:      .csect main[DS]
-; BIT32-NEXT:       .long .main                   # @main
-; BIT32-NEXT:       .long TOC[TC0]
-; BIT32-NEXT:       .long 0
-; BIT64-NEXT:       .llong  .main                   # @main
-; BIT64-NEXT:       .llong  TOC[TC0]
-; BIT64-NEXT:       .llong  0
+; BIT32-NEXT:       .vbyte  4, .main                   # @main
+; BIT32-NEXT:       .vbyte  4, TOC[TC0]
+; BIT32-NEXT:       .vbyte  4, 0
+; BIT64-NEXT:       .vbyte  8, .main                   # @main
+; BIT64-NEXT:       .vbyte  8, TOC[TC0]
+; BIT64-NEXT:       .vbyte  8, 0
 ; COMMON-NEXT:      .csect .text[PR]
 ; COMMON-NEXT: .main:
 
 ; COMMON:           .csect .data[RW]
 ; COMMON-NEXT:      .globl  bar_p
 ; BIT32-NEXT:       .align  2
 ; BIT64-NEXT:       .align  3
 ; COMMON-NEXT: bar_p:
-; BIT32-NEXT:       .long bar_ref[DS]
-; BIT64-NEXT:       .llong  bar_ref[DS]
+; BIT32-NEXT:       .vbyte  4, bar_ref[DS]
+; BIT64-NEXT:       .vbyte  8, bar_ref[DS]
 ; COMMON-NEXT:      .extern b_e[UA]
 ; COMMON-NEXT:      .extern .bar_ref
 ; COMMON-NEXT:      .extern bar_ref[DS]
 ; COMMON-NEXT:      .extern .bar_extern
 ; COMMON-NEXT:      .extern     bar_extern[DS]
 ; COMMON-NEXT:      .toc
 ; COMMON-NEXT: LC0:
 ; COMMON-NEXT:      .tc b_e[TC],b_e[UA]

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %const.0
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %const.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $x[[REG2]] :: (load 4 from constant-pool)
 
 ; 32SMALL-ASM:         .csect .rodata[RO],2
 ; 32SMALL-ASM:         .align  2
 ; 32SMALL-ASM: .LCPI0_0:
-; 32SMALL-ASM:         .long  0x40b00000
+; 32SMALL-ASM:         .vbyte 4,  0x40b00000
 ; 32SMALL-ASM: .test_float:
 ; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
 ; 32SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 32SMALL-ASM:         blr
 
 ; 32LARGE-ASM:         .csect .rodata[RO],2
 ; 32LARGE-ASM:         .align  2
 ; 32LARGE-ASM: .LCPI0_0:
-; 32LARGE-ASM:         .long   0x40b00000
+; 32LARGE-ASM:         .vbyte 4,   0x40b00000
 ; 32LARGE-ASM: .test_float:
 ; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 32LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 32LARGE-ASM:         blr
 
 ; 64SMALL-ASM:         .csect .rodata[RO],2
 ; 64SMALL-ASM:         .align  2
 ; 64SMALL-ASM: .LCPI0_0:
-; 64SMALL-ASM:         .long   0x40b00000
+; 64SMALL-ASM:         .vbyte 4,   0x40b00000
 ; 64SMALL-ASM: .test_float:
 ; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
 ; 64SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 64SMALL-ASM:         blr
 
 ; 64LARGE-ASM:         .csect .rodata[RO],2
 ; 64LARGE-ASM:         .align  2
 ; 64LARGE-ASM: .LCPI0_0:
-; 64LARGE-ASM:         .long   0x40b00000
+; 64LARGE-ASM:         .vbyte 4,   0x40b00000
 ; 64LARGE-ASM: .test_float:
 ; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 64LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 64LARGE-ASM:         blr
 
 ; CHECK: .toc
 ; CHECK: .tc .LCPI0_0[TC],.LCPI0_0

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

 ; 32SMALL-ASM: LBB0_4:
 ; 32SMALL-ASM: LBB0_5:
 ; 32SMALL-ASM: LBB0_6:
 ; 32SMALL-ASM:      li 3, 0
 ; 32SMALL-ASM:      blr
 ; 32SMALL-ASM:      .csect .rodata[RO],2
 ; 32SMALL-ASM:      .align  2
 ; 32SMALL-ASM: .LJTI0_0:
-; 32SMALL-ASM:      .long   LBB0_2-.LJTI0_0
-; 32SMALL-ASM:      .long   LBB0_3-.LJTI0_0
-; 32SMALL-ASM:      .long   LBB0_4-.LJTI0_0
-; 32SMALL-ASM:      .long   LBB0_5-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4,   LBB0_2-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4,   LBB0_3-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4,   LBB0_4-.LJTI0_0
+; 32SMALL-ASM:      .vbyte  4,   LBB0_5-.LJTI0_0
 
 ; 32LARGE-ASM-LABEL: jump_table
 ; 32LARGE-ASM: .jump_table:
 ; 32LARGE-ASM:      addi 3, 3, -1
 ; 32LARGE-ASM:      cmplwi  3, 3
 ; 32LARGE-ASM:      bgt     0, LBB0_6
 ; 32LARGE-ASM:      addis 4, LC0@u(2)
 ; 32LARGE-ASM:      slwi 3, 3, 2
 ; 32LARGE-ASM:      lwz 4, LC0@l(4)
 ; 32LARGE-ASM:      lwzx 3, 3, 4
 ; 32LARGE-ASM:      add 3, 3, 4
 ; 32LARGE-ASM:      mtctr 3
 ; 32LARGE-ASM:      bctr
 ; 32LARGE-ASM: LBB0_2:
 ; 32LARGE-ASM: LBB0_3:
 ; 32LARGE-ASM: LBB0_4:
 ; 32LARGE-ASM: LBB0_5:
 ; 32LARGE-ASM: LBB0_6:
 ; 32LARGE-ASM:      li 3, 0
 ; 32LARGE-ASM:      blr
 ; 32LARGE-ASM:      .csect .rodata[RO],2
 ; 32LARGE-ASM:      .align  2
 ; 32LARGE-ASM: .LJTI0_0:
-; 32LARGE-ASM:      .long   LBB0_2-.LJTI0_0
-; 32LARGE-ASM:      .long   LBB0_3-.LJTI0_0
-; 32LARGE-ASM:      .long   LBB0_4-.LJTI0_0
-; 32LARGE-ASM:      .long   LBB0_5-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4,   LBB0_2-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4,   LBB0_3-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4,   LBB0_4-.LJTI0_0
+; 32LARGE-ASM:      .vbyte  4,   LBB0_5-.LJTI0_0
 
 ; 64SMALL-ASM-LABEL: jump_table
 ; 64SMALL-ASM: .jump_table:
 ; 64SMALL-ASM:      addi 3, 3, -1
 ; 64SMALL-ASM:      cmplwi  3, 3
 ; 64SMALL-ASM:      bgt     0, LBB0_6
 ; 64SMALL-ASM:      ld 4, LC0(2)
 ; 64SMALL-ASM:      rldic 3, 3, 2, 30
 ; 64SMALL-ASM:      lwax 3, 3, 4
 ; 64SMALL-ASM:      add 3, 3, 4
 ; 64SMALL-ASM:      mtctr 3
 ; 64SMALL-ASM:      bctr
 ; 64SMALL-ASM: LBB0_2:
 ; 64SMALL-ASM: LBB0_3:
 ; 64SMALL-ASM: LBB0_4:
 ; 64SMALL-ASM: LBB0_5:
 ; 64SMALL-ASM: LBB0_6:
 ; 64SMALL-ASM:      li 3, 0
 ; 64SMALL-ASM:      blr
 ; 64SMALL-ASM:      .csect .rodata[RO],2
 ; 64SMALL-ASM:      .align  2
 ; 64SMALL-ASM: .LJTI0_0:
-; 64SMALL-ASM:      .long   LBB0_2-.LJTI0_0
-; 64SMALL-ASM:      .long   LBB0_3-.LJTI0_0
-; 64SMALL-ASM:      .long   LBB0_4-.LJTI0_0
-; 64SMALL-ASM:      .long   LBB0_5-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4,   LBB0_2-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4,   LBB0_3-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4,   LBB0_4-.LJTI0_0
+; 64SMALL-ASM:      .vbyte  4,   LBB0_5-.LJTI0_0
 
 ; 64LARGE-ASM-LABEL: jump_table
 ; 64LARGE-ASM: .jump_table:
 ; 64LARGE-ASM:      addi 3, 3, -1
 ; 64LARGE-ASM:      cmplwi  3, 3
 ; 64LARGE-ASM:      bgt     0, LBB0_6
 ; 64LARGE-ASM:      addis 4, LC0@u(2)
 ; 64LARGE-ASM:      rldic 3, 3, 2, 30
 ; 64LARGE-ASM:      ld 4, LC0@l(4)
 ; 64LARGE-ASM:      lwax 3, 3, 4
 ; 64LARGE-ASM:      add 3, 3, 4
 ; 64LARGE-ASM:      mtctr 3
 ; 64LARGE-ASM:      bctr
 ; 64LARGE-ASM: LBB0_2:
 ; 64LARGE-ASM: LBB0_3:
 ; 64LARGE-ASM: LBB0_4:
 ; 64LARGE-ASM: LBB0_5:
 ; 64LARGE-ASM: LBB0_6:
 ; 64LARGE-ASM:      li 3, 0
 ; 64LARGE-ASM:      blr
 ; 64LARGE-ASM:      .csect .rodata[RO],2
 ; 64LARGE-ASM:      .align  2
 ; 64LARGE-ASM: .LJTI0_0:
-; 64LARGE-ASM:      .long   LBB0_2-.LJTI0_0
-; 64LARGE-ASM:      .long   LBB0_3-.LJTI0_0
-; 64LARGE-ASM:      .long   LBB0_4-.LJTI0_0
-; 64LARGE-ASM:      .long   LBB0_5-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4,   LBB0_2-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4,   LBB0_3-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4,   LBB0_4-.LJTI0_0
+; 64LARGE-ASM:      .vbyte  4,   LBB0_5-.LJTI0_0
 
 ; CHECK: .toc
 ; CHECK: .tc .LJTI0_0[TC],.LJTI0_0

llvm/test/CodeGen/PowerPC/aix-readonly-with-relocation.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff --relocation-model=pic < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff --relocation-model=pic < %s | FileCheck --check-prefix=CHECK64 %s
 
 @a = common global i32 0
 @b = constant i32* @a
 
 ;CHECK:         .comm   a[RW],4,2
 ;CHECK-NEXT:    .csect .data[RW],2
 ;CHECK-NEXT:    .globl  b
 ;CHECK-NEXT:    .align  2
 ;CHECK-NEXT: b:
-;CHECK-NEXT:    .long   a
+;CHECK-NEXT:    .vbyte  4,   a
 
 ;CHECK64:       .comm   a[RW],4,2
 ;CHECK64-NEXT:  .csect .data[RW],3
 ;CHECK64-NEXT:  .globl  b
 ;CHECK64-NEXT:  .align  3
 ;CHECK64-NEXT: b:
-;CHECK64-NEXT:  .llong  a
+;CHECK64-NEXT:  .vbyte  8,  a

llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

entry:
   ret void
 }
 
 
 ;CHECK:          .csect .data[RW],2
 ;CHECK-NEXT:     .globl  foo_ptr
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     foo_ptr:
-;CHECK-NEXT:     .long   foo[DS]
+;CHECK-NEXT:     .vbyte 4,   foo[DS]
 ;CHECK-NEXT:     .globl  bar_ptr1
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     bar_ptr1:
-;CHECK-NEXT:     .long   bar[DS]
+;CHECK-NEXT:     .vbyte 4,   bar[DS]
 ;CHECK-NEXT:     .extern foo[DS]
 
 ;CHECK64:         .csect .data[RW],3
 ;CHECK64-NEXT:         .globl  foo_ptr
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    foo_ptr:
-;CHECK64-NEXT:         .llong  foo[DS]
+;CHECK64-NEXT:         .vbyte 8,  foo[DS]
 ;CHECK64-NEXT:         .globl  bar_ptr1
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    bar_ptr1:
-;CHECK64-NEXT:         .llong  bar[DS]
+;CHECK64-NEXT:         .vbyte 8,  bar[DS]
 ;CHECK64-NEXT:         .extern foo[DS]

llvm/test/CodeGen/PowerPC/aix-weak.ll

entry:
   call void @foo_ref_weak()
   ret i32 0
 }
 
 ; COMMON:               .weak foo_weak[DS]            # -- Begin function foo_weak
 ; COMMON-NEXT:          .weak .foo_weak
 ; COMMON-NEXT:          .align  4
 ; COMMON-NEXT:          .csect foo_weak[DS]
-; BIT32-NEXT:           .long .foo_weak               # @foo_weak
-; BIT32-NEXT:           .long TOC[TC0]
-; BIT32-NEXT:           .long 0
-; BIT64-NEXT:           .llong  .foo_weak               # @foo_weak
-; BIT64-NEXT:           .llong  TOC[TC0]
-; BIT64-NEXT:           .llong  0
+; BIT32-NEXT:           .vbyte  4, .foo_weak               # @foo_weak
+; BIT32-NEXT:           .vbyte  4, TOC[TC0]
+; BIT32-NEXT:           .vbyte  4, 0
+; BIT64-NEXT:           .vbyte  8, .foo_weak               # @foo_weak
+; BIT64-NEXT:           .vbyte  8, TOC[TC0]
+; BIT64-NEXT:           .vbyte  8, 0
 ; COMMON-NEXT:          .csect .text[PR]
 ; COMMON-NEXT:  .foo_weak:
 
 ; COMMON:               .weak   foo_ref_weak[DS]        # -- Begin function foo_ref_weak
 ; COMMON-NEXT:          .weak .foo_ref_weak
 ; COMMON-NEXT:          .align  4
 ; COMMON-NEXT:          .csect foo_ref_weak[DS]
-; BIT32-NEXT:           .long .foo_ref_weak           # @foo_ref_weak
-; BIT32-NEXT:           .long TOC[TC0]
-; BIT32-NEXT:           .long 0
-; BIT64-NEXT:           .llong  .foo_ref_weak           # @foo_ref_weak
-; BIT64-NEXT:           .llong  TOC[TC0]
-; BIT64-NEXT:           .llong  0
+; BIT32-NEXT:           .vbyte  4, .foo_ref_weak           # @foo_ref_weak
+; BIT32-NEXT:           .vbyte  4, TOC[TC0]
+; BIT32-NEXT:           .vbyte  4, 0
+; BIT64-NEXT:           .vbyte  8, .foo_ref_weak           # @foo_ref_weak
+; BIT64-NEXT:           .vbyte  8, TOC[TC0]
+; BIT64-NEXT:           .vbyte  8, 0
 ; COMMON-NEXT:          .csect .text[PR]
 ; COMMON-NEXT:  .foo_ref_weak:
 
 ; COMMON:               .globl  main[DS]                # -- Begin function main
 ; COMMON-NEXT:          .globl  .main
 ; COMMON-NEXT:          .align  4
 ; COMMON-NEXT:          .csect main[DS]
-; BIT32-NEXT:           .long .main                   # @main
-; BIT32-NEXT:           .long TOC[TC0]
-; BIT32-NEXT:           .long 0
-; BIT64-NEXT:           .llong  .main                   # @main
-; BIT64-NEXT:           .llong  TOC[TC0]
-; BIT64-NEXT:           .llong  0
+; BIT32-NEXT:           .vbyte  4, .main                   # @main
+; BIT32-NEXT:           .vbyte  4, TOC[TC0]
+; BIT32-NEXT:           .vbyte  4, 0
+; BIT64-NEXT:           .vbyte  8, .main                   # @main
+; BIT64-NEXT:           .vbyte  8, TOC[TC0]
+; BIT64-NEXT:           .vbyte  8, 0
 ; COMMON-NEXT:          .csect .text[PR]
 ; COMMON-NEXT:  .main:
 
 ; COMMON:               .csect .data[RW]
 ; COMMON-NEXT:          .globl  foo_weak_p
 ; BIT32-NEXT:           .align  2
 ; BIT64-NEXT:           .align  3
 ; COMMON-NEXT:  foo_weak_p:
-; BIT32-NEXT:           .long foo_ref_weak[DS]
-; BIT64-NEXT:           .llong  foo_ref_weak[DS]
+; BIT32-NEXT:           .vbyte  4, foo_ref_weak[DS]
+; BIT64-NEXT:           .vbyte  8, foo_ref_weak[DS]
 ; COMMON-NEXT:          .weak b
 ; COMMON-NEXT:          .align  2
 ; COMMON-NEXT:  b:
-; COMMON-NEXT:          .long 0                       # 0x0
+; COMMON-NEXT:          .vbyte  4, 0                       # 0x0
 ; COMMON-NEXT:          .toc
 ; COMMON-NEXT:  LC0:
 ; COMMON-NEXT:          .tc foo_weak_p[TC],foo_weak_p
 ; COMMON-NEXT:  LC1:
 ; COMMON-NEXT:          .tc b[TC],b
 
 
 ; CHECKSYM:      Symbols [

llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll

 ; This file tests the codegen of initialized and common variables in AIX
 ; assembly and XCOFF object files.
 
-; RUN: llc -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,CHECK32 %s
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,CHECK64 %s
 
 ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --section-headers --file-header %t.o | \
 ; RUN: FileCheck --check-prefix=OBJ %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
 
 ; RUN: not --crash llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN: FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @ivar = local_unnamed_addr global i32 35, align 4
 @llvar = local_unnamed_addr global i64 36, align 8
 @svar = local_unnamed_addr global i16 37, align 2
 @fvar = local_unnamed_addr global float 8.000000e+02, align 4
 @dvar = local_unnamed_addr global double 9.000000e+02, align 8
 @over_aligned = local_unnamed_addr global double 9.000000e+02, align 32
 @chrarray = local_unnamed_addr global [4 x i8] c"abcd", align 1
 @dblarr = local_unnamed_addr global [4 x double] [double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00], align 8
 @d_0 = global double 0.000000e+00, align 8
 @s_0 = global i16 0, align 2
 @f_0 = global float 0.000000e+00, align 4
 
+%struct.anon = type <{ i32, double }>
+@astruct = global [1 x %struct.anon] [%struct.anon <{ i32 1, double 7.000000e+00 }>], align 1
+
 @a = common global i32 0, align 4
 @b = common global i64 0, align 8
 @c = common global i16 0, align 2
 
 @d = common local_unnamed_addr global double 0.000000e+00, align 8
 @f = common local_unnamed_addr global float 0.000000e+00, align 4
 
 @over_aligned_comm = common local_unnamed_addr global double 0.000000e+00, align 32
 
 @array = common local_unnamed_addr global [33 x i8] zeroinitializer, align 1
 
 ; CHECK-NOT: .toc
 
 ; CHECK:      .csect .text[PR],2
 ; CHECK-NEXT:  .file
 
 ; CHECK:      .csect .data[RW],5
 ; CHECK-NEXT: .globl  ivar
 ; CHECK-NEXT: .align  2
 ; CHECK-NEXT: ivar:
-; CHECK-NEXT: .long   35
+; CHECK-NEXT: .vbyte  4,   35
 
 ; CHECK:      .globl  llvar
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: llvar:
-; CHECK-NEXT: .llong  36
+; CHECK32-NEXT: .vbyte  4,  0
+; CHECK32-NEXT: .vbyte  4,  36
+; CHECK64-NEXT: .vbyte  8,  36
 
 ; CHECK:      .globl  svar
 ; CHECK-NEXT: .align  1
 ; CHECK-NEXT: svar:
-; CHECK-NEXT: .short  37
+; CHECK-NEXT: .vbyte  2,  37
 
 ; CHECK:      .globl  fvar
 ; CHECK-NEXT: .align  2
 ; CHECK-NEXT: fvar:
-; CHECK-NEXT: .long   0x44480000
+; CHECK-NEXT: .vbyte  4,   0x44480000
 
 ; CHECK:      .globl  dvar
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: dvar:
-; CHECK-NEXT: .llong  0x408c200000000000
+; CHECK32-NEXT: .vbyte  4, 1082925056
+; CHECK32-NEXT: .vbyte  4, 0
+; CHECK64-NEXT: .vbyte  8,  0x408c200000000000
 
 ; CHECK:      .globl  over_aligned
 ; CHECK-NEXT: .align  5
 ; CHECK-NEXT: over_aligned:
-; CHECK-NEXT: .llong  0x408c200000000000
+; CHECK32-NEXT: .vbyte  4, 1082925056
+; CHECK32-NEXT: .vbyte  4, 0
+; CHECK64-NEXT: .vbyte  8,  0x408c200000000000
 
 ; CHECK:      .globl  chrarray
 ; CHECK-NEXT: chrarray:
 ; CHECK-NEXT: .byte   97
 ; CHECK-NEXT: .byte   98
 ; CHECK-NEXT: .byte   99
 ; CHECK-NEXT: .byte   100
 
 ; CHECK:      .globl  dblarr
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: dblarr:
-; CHECK-NEXT: .llong  0x3ff0000000000000
-; CHECK-NEXT: .llong  0x4000000000000000
-; CHECK-NEXT: .llong  0x4008000000000000
-; CHECK-NEXT: .llong  0x4010000000000000
+; CHECK32-NEXT: .vbyte  4,  1072693248
+; CHECK32-NEXT: .vbyte  4,  0
+; CHECK64-NEXT: .vbyte  8,  0x3ff0000000000000
+; CHECK32-NEXT: .vbyte  4,  1073741824
+; CHECK32-NEXT: .vbyte  4,  0
+; CHECK64-NEXT: .vbyte  8,  0x4000000000000000
+; CHECK32-NEXT: .vbyte  4,  1074266112
+; CHECK32-NEXT: .vbyte  4,  0
+; CHECK64-NEXT: .vbyte  8,  0x4008000000000000
+; CHECK32-NEXT: .vbyte  4,  1074790400
+; CHECK32-NEXT: .vbyte  4,  0
+; CHECK64-NEXT: .vbyte  8,  0x4010000000000000
 
 ; CHECK:      .globl  d_0
 ; CHECK-NEXT: .align 3
 ; CHECK-NEXT: d_0:
-; CHECK-NEXT: .llong 0
+; CHECK32-NEXT: .vbyte  4, 0
+; CHECK32-NEXT: .vbyte  4, 0
+; CHECK64-NEXT: .vbyte  8, 0
 
 ; CHECK:      .globl  s_0
 ; CHECK-NEXT: .align  1
 ; CHECK-NEXT: s_0:
-; CHECK-NEXT: .short 0
+; CHECK-NEXT: .vbyte  2, 0
 
 ; CHECK:      .globl f_0
 ; CHECK-NEXT: .align 2
 ; CHECK-NEXT: f_0:
-; CHECK-NEXT: .long 0
+; CHECK-NEXT: .vbyte  4, 0
+
+; CHECK:      .globl astruct
+; CHECK-NEXT: astruct:
+; CHECK-NEXT: .vbyte  4, 1
+; CHECK32-NEXT: .vbyte  4, 1075576832
+; CHECK32-NEXT: .vbyte  4, 0
+; CHECK64-NEXT: .vbyte  8, 0x401c000000000000
 
 ; CHECK-NEXT: .comm   a[RW],4,2
 ; CHECK-NEXT: .comm   b[RW],8,3
 ; CHECK-NEXT: .comm   c[RW],2,1
 ; CHECK-NEXT: .comm   d[RW],8,3
 ; CHECK-NEXT: .comm   f[RW],4,2
 ; CHECK-NEXT: .comm   over_aligned_comm[RW],8,5
 ; CHECK-NEXT: .comm   array[RW],33,0
 
 ; OBJ:      File: {{.*}}aix-xcoff-data.ll.tmp.o
 ; OBJ-NEXT: Format: aixcoff-rs6000
 ; OBJ-NEXT: Arch: powerpc
 ; OBJ-NEXT: AddressSize: 32bit
 ; OBJ-NEXT: FileHeader {
 ; OBJ-NEXT:   Magic: 0x1DF
 ; OBJ-NEXT:   NumberOfSections: 3
 ; OBJ-NEXT:   TimeStamp:
-; OBJ-NEXT:   SymbolTableOffset: 0xEC
-; OBJ-NEXT:   SymbolTableEntries: 40
+; OBJ-NEXT:   SymbolTableOffset: 0xF8
+; OBJ-NEXT:   SymbolTableEntries: 42
 ; OBJ-NEXT:   OptionalHeaderSize: 0x0
 ; OBJ-NEXT:   Flags: 0x0
 ; OBJ-NEXT: }
 
 ; OBJ:      Sections [
 ; OBJ:        Section {
 ; OBJ-NEXT:     Index: 1
 ; OBJ-NEXT:     Name: .text
 ; OBJ-NEXT:     PhysicalAddress: 0x0
 ; OBJ-NEXT:     VirtualAddress: 0x0
 ; OBJ-NEXT:     Size: 0x0
 ; OBJ-NEXT:     RawDataOffset: 0x8C
 ; OBJ-NEXT:     RelocationPointer: 0x0
 ; OBJ-NEXT:     LineNumberPointer: 0x0
 ; OBJ-NEXT:     NumberOfRelocations: 0
 ; OBJ-NEXT:     NumberOfLineNumbers: 0
 ; OBJ-NEXT:     Type: STYP_TEXT (0x20)
 ; OBJ-NEXT:   }
 
 ; OBJ:        Section {
 ; OBJ-NEXT:     Index: 2
 ; OBJ-NEXT:     Name: .data
 ; OBJ-NEXT:     PhysicalAddress: 0x0
 ; OBJ-NEXT:     VirtualAddress: 0x0
-; OBJ-NEXT:     Size: 0x60
+; OBJ-NEXT:     Size: 0x6C
 ; OBJ-NEXT:     RawDataOffset: 0x8C
 ; OBJ-NEXT:     RelocationPointer: 0x0
 ; OBJ-NEXT:     LineNumberPointer: 0x0
 ; OBJ-NEXT:     NumberOfRelocations: 0
 ; OBJ-NEXT:     NumberOfLineNumbers: 0
 ; OBJ-NEXT:     Type: STYP_DATA (0x40)
 ; OBJ-NEXT:   }
 
 ; OBJ:        Section {
 ; OBJ-NEXT:     Index: 3
 ; OBJ-NEXT:     Name: .bss
-; OBJ-NEXT:     PhysicalAddress: 0x60
-; OBJ-NEXT:     VirtualAddress: 0x60
-; OBJ-NEXT:     Size: 0x6C
+; OBJ-NEXT:     PhysicalAddress: 0x6C
+; OBJ-NEXT:     VirtualAddress: 0x6C
+; OBJ-NEXT:     Size: 0x60
 ; OBJ-NEXT:     RawDataOffset: 0x0
 ; OBJ-NEXT:     RelocationPointer: 0x0
 ; OBJ-NEXT:     LineNumberPointer: 0x0
 ; OBJ-NEXT:     NumberOfRelocations: 0
 ; OBJ-NEXT:     NumberOfLineNumbers: 0
 ; OBJ-NEXT:     Type: STYP_BSS (0x80)
 ; OBJ-NEXT:   }
 ; OBJ:      ]

 ; SYMS-NEXT:     Name: .data
 ; SYMS-NEXT:     Value (RelocatableAddress): 0x0
 ; SYMS-NEXT:     Section: .data
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_HIDEXT (0x6B)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
 ; SYMS-NEXT:       Index: [[#INDX+3]]
-; SYMS-NEXT:       SectionLen: 96
+; SYMS-NEXT:       SectionLen: 108
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 5
 ; SYMS-NEXT:       SymbolType: XTY_SD (0x1)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }

 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {
 ; SYMS-NEXT:     Index: [[#INDX+26]]
-; SYMS-NEXT:     Name: a
+; SYMS-NEXT:     Name: astruct
 ; SYMS-NEXT:     Value (RelocatableAddress): 0x60
-; SYMS-NEXT:     Section: .bss
+; SYMS-NEXT:     Section: .data
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_EXT (0x2)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
 ; SYMS-NEXT:       Index: [[#INDX+27]]
+; SYMS-NEXT:       ContainingCsectSymbolIndex: [[#INDX+2]]
+; SYMS-NEXT:       ParameterHashIndex: 0x0
+; SYMS-NEXT:       TypeChkSectNum: 0x0
+; SYMS-NEXT:       SymbolAlignmentLog2: 0
+; SYMS-NEXT:       SymbolType: XTY_LD (0x2)
+; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
+; SYMS-NEXT:       StabInfoIndex: 0x0
+; SYMS-NEXT:       StabSectNum: 0x0
+; SYMS-NEXT:     }
+; SYMS-NEXT:   }
+
+; SYMS:        Symbol {
+; SYMS-NEXT:     Index: [[#INDX+28]]
+; SYMS-NEXT:     Name: a
+; SYMS-NEXT:     Value (RelocatableAddress): 0x6C
+; SYMS-NEXT:     Section: .bss
+; SYMS-NEXT:     Type: 0x0
+; SYMS-NEXT:     StorageClass: C_EXT (0x2)
+; SYMS-NEXT:     NumberOfAuxEntries: 1
+; SYMS-NEXT:     CSECT Auxiliary Entry {
+; SYMS-NEXT:       Index: [[#INDX+29]]
 ; SYMS-NEXT:       SectionLen: 4
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 2
 ; SYMS-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {
-; SYMS-NEXT:     Index: [[#INDX+28]]
+; SYMS-NEXT:     Index: [[#INDX+30]]
 ; SYMS-NEXT:     Name: b
-; SYMS-NEXT:     Value (RelocatableAddress): 0x68
+; SYMS-NEXT:     Value (RelocatableAddress): 0x70
 ; SYMS-NEXT:     Section: .bss
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_EXT (0x2)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
-; SYMS-NEXT:       Index: [[#INDX+29]]
+; SYMS-NEXT:       Index: [[#INDX+31]]
 ; SYMS-NEXT:       SectionLen: 8
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 3
 ; SYMS-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {
-; SYMS-NEXT:     Index: [[#INDX+30]]
+; SYMS-NEXT:     Index: [[#INDX+32]]
 ; SYMS-NEXT:     Name: c
-; SYMS-NEXT:     Value (RelocatableAddress): 0x70
+; SYMS-NEXT:     Value (RelocatableAddress): 0x78
 ; SYMS-NEXT:     Section: .bss
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_EXT (0x2)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
-; SYMS-NEXT:       Index: [[#INDX+31]]
+; SYMS-NEXT:       Index: [[#INDX+33]]
 ; SYMS-NEXT:       SectionLen: 2
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 1
 ; SYMS-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {
-; SYMS-NEXT:     Index: [[#INDX+32]]
+; SYMS-NEXT:     Index: [[#INDX+34]]
 ; SYMS-NEXT:     Name: d
-; SYMS-NEXT:     Value (RelocatableAddress): 0x78
+; SYMS-NEXT:     Value (RelocatableAddress): 0x80
 ; SYMS-NEXT:     Section: .bss
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_EXT (0x2)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
-; SYMS-NEXT:       Index: [[#INDX+33]]
+; SYMS-NEXT:       Index: [[#INDX+35]]
 ; SYMS-NEXT:       SectionLen: 8
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 3
 ; SYMS-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {
-; SYMS-NEXT:     Index: [[#INDX+34]]
+; SYMS-NEXT:     Index: [[#INDX+36]]
 ; SYMS-NEXT:     Name: f
-; SYMS-NEXT:     Value (RelocatableAddress): 0x80
+; SYMS-NEXT:     Value (RelocatableAddress): 0x88
 ; SYMS-NEXT:     Section: .bss
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_EXT (0x2)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
-; SYMS-NEXT:       Index: [[#INDX+35]]
+; SYMS-NEXT:       Index: [[#INDX+37]]
 ; SYMS-NEXT:       SectionLen: 4
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 2
 ; SYMS-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {
-; SYMS-NEXT:     Index: [[#INDX+36]]
+; SYMS-NEXT:     Index: [[#INDX+38]]
 ; SYMS-NEXT:     Name: over_aligned_comm
 ; SYMS-NEXT:     Value (RelocatableAddress): 0xA0
 ; SYMS-NEXT:     Section: .bss
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_EXT (0x2)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
-; SYMS-NEXT:       Index: [[#INDX+37]]
+; SYMS-NEXT:       Index: [[#INDX+39]]
 ; SYMS-NEXT:       SectionLen: 8
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 5
 ; SYMS-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 
 ; SYMS:        Symbol {
-; SYMS-NEXT:     Index: [[#INDX+38]]
+; SYMS-NEXT:     Index: [[#INDX+40]]
 ; SYMS-NEXT:     Name: array
 ; SYMS-NEXT:     Value (RelocatableAddress): 0xA8
 ; SYMS-NEXT:     Section: .bss
 ; SYMS-NEXT:     Type: 0x0
 ; SYMS-NEXT:     StorageClass: C_EXT (0x2)
 ; SYMS-NEXT:     NumberOfAuxEntries: 1
 ; SYMS-NEXT:     CSECT Auxiliary Entry {
-; SYMS-NEXT:       Index: [[#INDX+39]]
+; SYMS-NEXT:       Index: [[#INDX+41]]
 ; SYMS-NEXT:       SectionLen: 33
 ; SYMS-NEXT:       ParameterHashIndex: 0x0
 ; SYMS-NEXT:       TypeChkSectNum: 0x0
 ; SYMS-NEXT:       SymbolAlignmentLog2: 0
 ; SYMS-NEXT:       SymbolType: XTY_CM (0x3)
 ; SYMS-NEXT:       StorageMappingClass: XMC_RW (0x5)
 ; SYMS-NEXT:       StabInfoIndex: 0x0
 ; SYMS-NEXT:       StabSectNum: 0x0
 ; SYMS-NEXT:     }
 ; SYMS-NEXT:   }
 ; SYMS:      ]

llvm/test/CodeGen/PowerPC/aix-xcoff-lower-comm.ll

 
 ; CHECK:             .comm   common[RW],4,2
 ; ASM32-NEXT:        .csect .data[RW],2
 ; ASM64-NEXT:        .csect .data[RW],3
 ; CHECK-NEXT:        .globl  pointer
 ; ASM32-NEXT:        .align  2
 ; ASM64-NEXT:        .align  3
 ; CHECK-NEXT:pointer:
-; ASM32-NEXT:        .long   common[RW]
-; ASM64-NEXT:        .llong   common[RW]
+; ASM32-NEXT:        .vbyte 4,   common[RW]
+; ASM64-NEXT:        .vbyte 8,   common[RW]
 
 
 ; RELOC:      Relocations [
 ; RELOC-NEXT:   Section (index: {{[0-9]+}}) .data {
 ; RELOC-NEXT:   Relocation {
 ; RELOC-NEXT:     Virtual Address: 0x0
 ; RELOC-NEXT:     Symbol: common ([[#COM_INDX:]])
 ; RELOC-NEXT:     IsSigned: No

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

 ; This file tests the codegen of mergeable const in AIX assembly.
 ; This file also tests mergeable const in XCOFF object file generation.
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,CHECK32 %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,CHECK64 %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=CHECKOBJ %s
 ; RUN: llvm-readobj -syms %t.o | FileCheck --check-prefix=CHECKSYM %s
 
 %struct.Merge_cnst32 = type { i64, i32, i64, i32 }
 %struct.Merge_cnst16 = type { i64, i32 }
 %struct.Merge_cnst8 = type { i32, i32 }
 %struct.Merge_cnst4 = type { i16, i8 }
 
 @__const.main.cnst32 = private unnamed_addr constant %struct.Merge_cnst32 { i64 4611686018427387954, i32 0, i64 0, i32 0 }
 @__const.main.cnst16 = private unnamed_addr constant %struct.Merge_cnst16 { i64 4611686018427387926, i32 0 }
 @__const.main.cnst8 = private unnamed_addr constant %struct.Merge_cnst8 { i32 1073741832, i32 0 }
 @__const.main.cnst4 = private unnamed_addr constant %struct.Merge_cnst4 { i16 16392, i8 0 }
 
 ; Function Attrs: noinline nounwind optnone
 define i32 @main() #0 {
 entry:
   ret i32 0
 }
 
 ;CHECK:         .csect .rodata[RO],4
 ;CHECK-NEXT:         .align  4
 ;CHECK-NEXT: .L__const.main.cnst32:
-;CHECK-NEXT:         .llong  4611686018427387954
-;CHECK-NEXT:         .long   0                       # 0x0
+;CHECK32-NEXT:         .vbyte 4, 1073741824
+;CHECK32-NEXT:         .vbyte 4,  50
+;CHECK64-NEXT:         .vbyte 8,  4611686018427387954
+;CHECK-NEXT:         .vbyte 4,   0                       # 0x0
 ;CHECK-NEXT:         .space  4
-;CHECK-NEXT:         .llong  0
-;CHECK-NEXT:         .long   0                       # 0x0
+;CHECK32-NEXT:         .vbyte 4,  0
+;CHECK32-NEXT:         .vbyte 4,  0
+;CHECK64-NEXT:         .vbyte 8,  0
+;CHECK-NEXT:         .vbyte 4,   0                       # 0x0
 ;CHECK-NEXT:         .space  4
 ;CHECK-NEXT:         .align  3
 ;CHECK-NEXT: .L__const.main.cnst16:
-;CHECK-NEXT:         .llong  4611686018427387926
-;CHECK-NEXT:         .long   0                       # 0x0
+;CHECK32-NEXT:         .vbyte 4, 1073741824
+;CHECK32-NEXT:         .vbyte 4, 22
+;CHECK64-NEXT:         .vbyte 8,  4611686018427387926
+;CHECK-NEXT:         .vbyte 4,   0                       # 0x0
 ;CHECK-NEXT:         .space  4
 ;CHECK-NEXT:         .align  3
 ;CHECK-NEXT: .L__const.main.cnst8:
-;CHECK-NEXT:         .long   1073741832              # 0x40000008
-;CHECK-NEXT:         .long   0                       # 0x0
+;CHECK-NEXT:         .vbyte 4,   1073741832              # 0x40000008
+;CHECK-NEXT:         .vbyte 4,   0                       # 0x0
 ;CHECK-NEXT:         .align  3
 ;CHECK-NEXT: .L__const.main.cnst4:
-;CHECK-NEXT:         .short  16392                   # 0x4008
+;CHECK-NEXT:         .vbyte 2,  16392                   # 0x4008
 ;CHECK-NEXT:         .byte   0                       # 0x0
 ;CHECK-NEXT:         .space  1
 
 
 ;CHECKOBJ:      00000000 <.text>:
 ;CHECKOBJ-NEXT:        0: 38 60 00 00                    li 3, 0
 ;CHECKOBJ-NEXT:        4: 4e 80 00 20                    blr
 ;CHECKOBJ-NEXT:          ...{{[[:space:]] *}}

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

entry:
   %0 = load i8*, i8** @p, align 4
   %1 = load i8, i8* %0, align 1
   ret i8 %1
 }
 
 ; CHECK:   .csect .rodata.str2.2[RO],2
 ; CHECK-NEXT:   .align  1
 ; CHECK-NEXT: .Lmagic16:
-; CHECK-NEXT:   .short  264                     # 0x108
-; CHECK-NEXT:   .short  272                     # 0x110
-; CHECK-NEXT:   .short  213                     # 0xd5
-; CHECK-NEXT:   .short  0                       # 0x0
+; CHECK-NEXT:   .vbyte  2,  264                     # 0x108
+; CHECK-NEXT:   .vbyte  2,  272                     # 0x110
+; CHECK-NEXT:   .vbyte  2,  213                     # 0xd5
+; CHECK-NEXT:   .vbyte  2,  0                       # 0x0
 ; CHECK-NEXT:   .csect .rodata.str4.4[RO],2
 ; CHECK-NEXT:   .align  2
 ; CHECK-NEXT: .Lmagic32:
-; CHECK-NEXT:   .long   464                     # 0x1d0
-; CHECK-NEXT:   .long   472                     # 0x1d8
-; CHECK-NEXT:   .long   413                     # 0x19d
-; CHECK-NEXT:   .long   0                       # 0x0
+; CHECK-NEXT:   .vbyte  4,   464                     # 0x1d0
+; CHECK-NEXT:   .vbyte  4,   472                     # 0x1d8
+; CHECK-NEXT:   .vbyte  4,   413                     # 0x19d
+; CHECK-NEXT:   .vbyte  4,   0                       # 0x0
 ; CHECK-NEXT:   .csect .rodata.str1.1[RO],2
 ; CHECK-NEXT: .LstrA:
 ; CHECK-NEXT: .byte   104
 ; CHECK-NEXT: .byte   101
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   111
 ; CHECK-NEXT: .byte   32

llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff  < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff  < %s | FileCheck --check-prefixes=CHECK,CHECK32 %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,CHECK64 %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj --section-headers --file-header %t.o | \
 ; RUN: FileCheck --check-prefix=OBJ %s
 ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYMS %s
 ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN: FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @const_ivar = constant i32 35, align 4
 @const_llvar = constant i64 36, align 8
 @const_svar = constant i16 37, align 2
 @const_fvar = constant float 8.000000e+02, align 4
 @const_dvar = constant double 9.000000e+02, align 8
 @const_over_aligned = constant double 9.000000e+02, align 32
 @const_chrarray = constant [4 x i8] c"abcd", align 1
 @const_dblarr = constant [4 x double] [double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00], align 8
 
 ; CHECK:               .csect .rodata[RO],5
 ; CHECK-NEXT:          .globl  const_ivar
 ; CHECK-NEXT:          .align  2
 ; CHECK-NEXT:  const_ivar:
-; CHECK-NEXT:          .long   35
+; CHECK-NEXT:          .vbyte 4,   35
 ; CHECK-NEXT:          .globl  const_llvar
 ; CHECK-NEXT:          .align  3
 ; CHECK-NEXT:  const_llvar:
-; CHECK-NEXT:          .llong  36
+; CHECK32-NEXT:          .vbyte 4,  0
+; CHECK32-NEXT:          .vbyte 4,  36
+; CHECK64-NEXT:          .vbyte 8,  36
 ; CHECK-NEXT:          .globl  const_svar
 ; CHECK-NEXT:          .align  1
 ; CHECK-NEXT:  const_svar:
-; CHECK-NEXT:          .short  37
+; CHECK-NEXT:          .vbyte 2,  37
 ; CHECK-NEXT:          .globl  const_fvar
 ; CHECK-NEXT:          .align  2
 ; CHECK-NEXT:  const_fvar:
-; CHECK-NEXT:          .long   0x44480000
+; CHECK-NEXT:          .vbyte 4,   0x44480000
 ; CHECK-NEXT:          .globl  const_dvar
 ; CHECK-NEXT:          .align  3
 ; CHECK-NEXT:  const_dvar:
-; CHECK-NEXT:          .llong  0x408c200000000000
+; CHECK32-NEXT:          .vbyte 4,  1082925056
+; CHECK32-NEXT:          .vbyte 4,  0
+; CHECK64-NEXT:          .vbyte 8,  0x408c200000000000
 ; CHECK-NEXT:          .globl  const_over_aligned
 ; CHECK-NEXT:          .align  5
 ; CHECK-NEXT:  const_over_aligned:
-; CHECK-NEXT:          .llong  0x408c200000000000
+; CHECK32-NEXT:          .vbyte 4,  1082925056
+; CHECK32-NEXT:          .vbyte 4,  0
+; CHECK64-NEXT:          .vbyte 8,  0x408c200000000000
 ; CHECK-NEXT:          .globl  const_chrarray
 ; CHECK-NEXT:  const_chrarray:
 ; CHECK-NEXT:          .byte   97
 ; CHECK-NEXT:          .byte   98
 ; CHECK-NEXT:          .byte   99
 ; CHECK-NEXT:          .byte   100
 ; CHECK-NEXT:          .globl  const_dblarr
 ; CHECK-NEXT:          .align  3
 ; CHECK-NEXT:  const_dblarr:
-; CHECK-NEXT:          .llong  0x3ff0000000000000
-; CHECK-NEXT:          .llong  0x4000000000000000
-; CHECK-NEXT:          .llong  0x4008000000000000
-; CHECK-NEXT:          .llong  0x4010000000000000
+; CHECK32-NEXT:          .vbyte 4,  1072693248
+; CHECK32-NEXT:          .vbyte 4,  0
+; CHECK64-NEXT:          .vbyte 8,  0x3ff0000000000000
+; CHECK32-NEXT:          .vbyte 4,  1073741824
+; CHECK32-NEXT:          .vbyte 4,  0
+; CHECK64-NEXT:          .vbyte 8,  0x4000000000000000
+; CHECK32-NEXT:          .vbyte 4,  1074266112
+; CHECK32-NEXT:          .vbyte 4,  0
+; CHECK64-NEXT:          .vbyte 8,  0x4008000000000000
+; CHECK32-NEXT:          .vbyte 4,  1074790400
+; CHECK32-NEXT:          .vbyte 4,  0
+; CHECK64-NEXT:          .vbyte 8,  0x4010000000000000
 
 
 ; OBJ:      File: {{.*}}aix-xcoff-rodata.ll.tmp.o
 ; OBJ-NEXT: Format: aixcoff-rs6000
 ; OBJ-NEXT: Arch: powerpc
 ; OBJ-NEXT: AddressSize: 32bit
 ; OBJ-NEXT: FileHeader {
 ; OBJ-NEXT:   Magic: 0x1DF

llvm/test/CodeGen/PowerPC/test_func_desc.ll

 define internal i32 @static_foo() {
 entry:
   ret i32 3
 }
 
 ; CHECK: .globl foo[DS]
 ; CHECK: .globl .foo
 ; 32BIT: .csect foo[DS],2
-; 32BIT-NEXT: .long .foo
-; 32BIT-NEXT: .long TOC[TC0]
-; 32BIT-NEXT: .long 0
+; 32BIT-NEXT: .vbyte  4, .foo
+; 32BIT-NEXT: .vbyte  4, TOC[TC0]
+; 32BIT-NEXT: .vbyte  4, 0
 ; 64BIT: .csect foo[DS],3
-; 64BIT-NEXT: .llong .foo
-; 64BIT-NEXT: .llong TOC[TC0]
-; 64BIT-NEXT: .llong 0
+; 64BIT-NEXT: .vbyte  8, .foo
+; 64BIT-NEXT: .vbyte  8, TOC[TC0]
+; 64BIT-NEXT: .vbyte  8, 0
 ; CHECK-NEXT: .csect .text[PR],2
 ; CHECK-LABEL: .foo:
 
 ; CHECK: .globl main[DS]
 ; CHECK: .globl .main
 ; 32BIT: .csect main[DS],2
-; 32BIT-NEXT: .long .main
-; 32BIT-NEXT: .long TOC[TC0]
-; 32BIT-NEXT: .long 0
+; 32BIT-NEXT: .vbyte  4, .main
+; 32BIT-NEXT: .vbyte  4, TOC[TC0]
+; 32BIT-NEXT: .vbyte  4, 0
 ; 64BIT: .csect main[DS],3
-; 64BIT-NEXT: .llong .main
-; 64BIT-NEXT: .llong TOC[TC0]
-; 64BIT-NEXT: .llong 0
+; 64BIT-NEXT: .vbyte  8, .main
+; 64BIT-NEXT: .vbyte  8, TOC[TC0]
+; 64BIT-NEXT: .vbyte  8, 0
 ; CHECK-NEXT: .csect .text[PR],2
 ; CHECK-LABEL: .main:
 ; CHECK: bl .foo
 ; CHECK: bl .extern_foo
 ; CHECK: bl .static_foo
 
 ; CHECK: .lglobl .static_foo
 ; 32BIT: .csect static_foo[DS],2
-; 32BIT-NEXT: .long .static_foo
-; 32BIT-NEXT: .long TOC[TC0]
-; 32BIT-NEXT: .long 0
+; 32BIT-NEXT: .vbyte  4, .static_foo
+; 32BIT-NEXT: .vbyte  4, TOC[TC0]
+; 32BIT-NEXT: .vbyte  4, 0
 ; 64BIT: .csect static_foo[DS],3
-; 64BIT-NEXT: .llong .static_foo
-; 64BIT-NEXT: .llong TOC[TC0]
-; 64BIT-NEXT: .llong 0
+; 64BIT-NEXT: .vbyte  8, .static_foo
+; 64BIT-NEXT: .vbyte  8, TOC[TC0]
+; 64BIT-NEXT: .vbyte  8, 0
 ; CHECK-NEXT: .csect .text[PR],2
 ; CHECK-LABEL: .static_foo:
 
 ; CHECK-NOT: .csect extern_foo
 
 ; CHECK: .toc
 ; CHECK-NOT: .tc