[SelectionDAGBuilder][WebAssembly] Omit range checks on jump tables

[tlively]

Summary

Jump tables on most platforms do not have a default branch target
built in, so LLVM emits a range check before each jump table as long
as the default target for the jump table is reachcable. WebAssembly,
however, implements jump tables using the br_table instruction, which
takes a default branch target as one of its arguments. Since
br_table handles branching to the default target when the argument is
out of range, the range check that LLVM emits is redundant.

This patch adds a TargetLowering setting that disables range checks on
jump tables and adds the default branch target to the end of the
branch target list for each jump table. This allows the WebAssembly
backend to take full advantage of the br_table instruction.

[hans]

Before digging into the code, would it be impractical to fold the range check into the br_table instruction in the wasm backend instead, "sniffing out the guard" and replacing it as suggested by that comment in WebAssemblyISelLowering.cpp?

Because I'm a little bit worried about this ipushing complexity up to the general switch lowering mechanism, for example breaking the invariant that jump tables have a size that matches their corresponding case range.

[tlively]

In D80778#2062416, @hans wrote:

Before digging into the code, would it be impractical to fold the range check into the br_table instruction in the wasm backend instead, "sniffing out the guard" and replacing it as suggested by that comment in WebAssemblyISelLowering.cpp?

Because I'm a little bit worried about this ipushing complexity up to the general switch lowering mechanism, for example breaking the invariant that jump tables have a size that matches their corresponding case range.

That's a fair concern. I'll try that approach and report back.

[tlively]

Doing this in the WebAssembly backend did not turn out to be as bad as I thought it might be. It is more complex than this solution, but probably more robust and certainly less intrusive as well. I'll close this review in favor of https://reviews.llvm.org/D80863.

[hans]

In D80778#2064756, @tlively wrote:

Doing this in the WebAssembly backend did not turn out to be as bad as I thought it might be. It is more complex than this solution, but probably more robust and certainly less intrusive as well. I'll close this review in favor of https://reviews.llvm.org/D80863.

Sounds good. Thanks!

llvm/include/llvm/CodeGen/TargetLowering.h

#include "llvm/IR/ConstrainedOps.def"
   unsigned getMinimumJumpTableDensity(bool OptForSize) const;
 
   /// Return upper limit for number of entries in a jump table.
   /// Zero if no limit.
   unsigned getMaximumJumpTableSize() const;
 
   virtual bool isJumpTableRelative() const;
 
+  /// Whether the default case should be included in the list of MBB jump table
+  /// destinations. It will be the final element in the list.
+  virtual bool isDefaultInJumpTable() const { return false; }
+
   /// Return true if a mulh[s|u] node for a specific type is cheaper than
   /// a multiply followed by a shift. This is false by default.
   virtual bool isMulhCheaperThanMulShift(EVT Type) const { return false; }
 
   /// If a physical register, this specifies the register that
   /// llvm.savestack/llvm.restorestack should save and restore.
   unsigned getStackPointerRegisterToSaveRestore() const {
     return StackPointerRegisterToSaveRestore;

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

switch (I->Kind) {
             JumpProb += DefaultProb / 2;
             FallthroughProb -= DefaultProb / 2;
             JumpMBB->setSuccProbability(SI, DefaultProb / 2);
             JumpMBB->normalizeSuccProbs();
             break;
           }
         }
 
-        if (FallthroughUnreachable) {
-          // Skip the range check if the fallthrough block is unreachable.
+        const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+
+        // Skip the range check if the jump table itself will handle the default
+        // case or if the fallthrough block is unreachable.
+        if (TLI.isDefaultInJumpTable() || FallthroughUnreachable)
           JTH->OmitRangeCheck = true;
-        }
 
         if (!JTH->OmitRangeCheck)
           addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
+
         addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
         CurMBB->normalizeSuccProbs();
 
         // The jump table header will be inserted in our current block, do the
         // range check, and fall through to our fallthrough block.
         JTH->HeaderBB = CurMBB;
         JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

for (unsigned i = 0, e = SDB->SL->JTCases.size(); i != e; ++i) {
 
     // Update PHI Nodes
     for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
          pi != pe; ++pi) {
       MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
       MachineBasicBlock *PHIBB = PHI->getParent();
       assert(PHI->isPHI() &&
              "This is not a machine PHI node that we are updating!");
-      // "default" BB. We can go there only from header BB.
-      if (PHIBB == SDB->SL->JTCases[i].second.Default)
-        PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
-           .addMBB(SDB->SL->JTCases[i].first.HeaderBB);
+      // "default" BB. We can go there only from header BB, unless the jump
+      // table includes the default destination.
+      if (PHIBB == SDB->SL->JTCases[i].second.Default) {
+        auto *SrcMBB = TLI->isDefaultInJumpTable()
+                           ? SDB->SL->JTCases[i].second.MBB
+                           : SDB->SL->JTCases[i].first.HeaderBB;
+        PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(SrcMBB);
+      }
       // JT BB. Just iterate over successors here
       if (FuncInfo->MBB->isSuccessor(PHIBB))
         PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
     }
   }
   SDB->SL->JTCases.clear();
 
   // If we generated any switch lowering information, build and codegen any

llvm/lib/CodeGen/SwitchLoweringUtils.cpp

 //===- SwitchLoweringUtils.cpp - Switch Lowering --------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains switch inst lowering optimizations and utilities for
 // codegen, so that it can be used for both SelectionDAG and GlobalISel.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/SwitchLoweringUtils.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
 using namespace SwitchCG;
 
 uint64_t SwitchCG::getJumpTableRange(const CaseClusterVector &Clusters,
                                      unsigned First, unsigned Last) {
   assert(Last >= First);
bool SwitchCG::SwitchLowering::buildJumpTable(const CaseClusterVector &Clusters,
                                               MachineBasicBlock *DefaultMBB,
                                               CaseCluster &JTCluster) {
   assert(First <= Last);
 
   auto Prob = BranchProbability::getZero();
   unsigned NumCmps = 0;
   std::vector<MachineBasicBlock*> Table;
   DenseMap<MachineBasicBlock*, BranchProbability> JTProbs;
+  MachineFunction *CurMF = FuncInfo.MF;
 
   // Initialize probabilities in JTProbs.
   for (unsigned I = First; I <= Last; ++I)
     JTProbs[Clusters[I].MBB] = BranchProbability::getZero();
 
   for (unsigned I = First; I <= Last; ++I) {
     assert(Clusters[I].Kind == CC_Range);
     Prob += Clusters[I].Prob;
if (I != First) {
         Table.push_back(DefaultMBB);
     }
     uint64_t ClusterSize = (High - Low).getLimitedValue() + 1;
     for (uint64_t J = 0; J < ClusterSize; ++J)
       Table.push_back(Clusters[I].MBB);
     JTProbs[Clusters[I].MBB] += Clusters[I].Prob;
   }
 
+  if (CurMF->getSubtarget().getTargetLowering()->isDefaultInJumpTable())
+    Table.push_back(DefaultMBB);
+
   unsigned NumDests = JTProbs.size();
   if (TLI->isSuitableForBitTests(NumDests, NumCmps,
                                  Clusters[First].Low->getValue(),
                                  Clusters[Last].High->getValue(), *DL)) {
     // Clusters[First..Last] should be lowered as bit tests instead.
     return false;
   }
 
   // Create the MBB that will load from and jump through the table.
   // Note: We create it here, but it's not inserted into the function yet.
-  MachineFunction *CurMF = FuncInfo.MF;
   MachineBasicBlock *JumpTableMBB =
       CurMF->CreateMachineBasicBlock(SI->getParent());
 
   // Add successors. Note: use table order for determinism.
   SmallPtrSet<MachineBasicBlock *, 8> Done;
   for (MachineBasicBlock *Succ : Table) {
     if (Done.count(Succ))
       continue;

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h

private:
   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
                              unsigned AS,
                              Instruction *I = nullptr) const override;
   bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, unsigned Align,
                                       MachineMemOperand::Flags Flags,
                                       bool *Fast) const override;
   bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
   bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
+  bool isDefaultInJumpTable() const override;
   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
                          EVT VT) const override;
   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
                           MachineFunction &MF,
                           unsigned Intrinsic) const override;
 
   SDValue LowerCall(CallLoweringInfo &CLI,
                     SmallVectorImpl<SDValue> &InVals) const override;

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

 bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
   MVT ExtT = ExtVal.getSimpleValueType();
   MVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getSimpleValueType(0);
   return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
          (ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
          (ExtT == MVT::v2i64 && MemT == MVT::v2i32);
 }
 
+bool WebAssemblyTargetLowering::isDefaultInJumpTable() const { return true; }
+
 EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL,
                                                   LLVMContext &C,
                                                   EVT VT) const {
   if (VT.isVector())
     return VT.changeVectorElementTypeToInteger();
 
   return TargetLowering::getSetCCResultType(DL, C, VT);
 }
SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
 
   MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
   const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
 
   // Add an operand for each case.
   for (auto MBB : MBBs)
     Ops.push_back(DAG.getBasicBlock(MBB));
 
-  // TODO: For now, we just pick something arbitrary for a default case for now.
-  // We really want to sniff out the guard and put in the real default case (and
-  // delete the guard).
-  Ops.push_back(DAG.getBasicBlock(MBBs[0]));
-
   return DAG.getNode(WebAssemblyISD::BR_TABLE, DL, MVT::Other, Ops);
 }
 
 SDValue WebAssemblyTargetLowering::LowerVASTART(SDValue Op,
                                                 SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT PtrVT = getPointerTy(DAG.getMachineFunction().getDataLayout());
 

llvm/test/CodeGen/WebAssembly/cfg-stackify.ll

if.end:
   call void @bar()
   br label %outer
 }
 
 ; Test switch lowering and block placement.
 
 ; CHECK-LABEL: test4:
 ; CHECK-NEXT: .functype test4 (i32) -> (){{$}}
-; CHECK:      block   {{$}}
 ; CHECK-NEXT: block   {{$}}
-; CHECK:      br_if     0, $pop{{[0-9]+}}{{$}}
-; CHECK:      br        1{{$}}
-; CHECK-NEXT: .LBB{{[0-9]+}}_2:
-; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: br_table   $0, 0, 0, 0, 0, 0, 0{{$}}
-; CHECK-NEXT: .LBB{{[0-9]+}}_3:
+; CHECK-NEXT: .LBB{{[0-9]+}}_1:
 ; CHECK-NEXT: end_block{{$}}
 ; CHECK-NEXT: return{{$}}
 define void @test4(i32 %t) {
 entry:
   switch i32 %t, label %default [
     i32 0, label %bb2
     i32 2, label %bb2
     i32 4, label %bb1

 ; CHECK:       .LBB{{[0-9]+}}_3:
 ; CHECK-NEXT:  block   {{$}}
 ; CHECK-NEXT:  loop    {{$}}
 ; CHECK:       .LBB{{[0-9]+}}_4:
 ; CHECK-NEXT:  loop    {{$}}
 ; CHECK:       br_if     0, {{[^,]+}}{{$}}
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NEXT:  block   {{$}}
-; CHECK:       br_if     0, {{[^,]+}}{{$}}
-; CHECK:       br        3{{$}}
-; CHECK-NEXT:  .LBB{{[0-9]+}}_7:
-; CHECK-NEXT:  end_block{{$}}
-; CHECK:       block   {{$}}
-; CHECK-NEXT:  br_table   $0, 0, 3, 1, 2, 0
-; CHECK-NEXT:  .LBB{{[0-9]+}}_8:
+; CHECK-NEXT:  i32.const
+; CHECK-NEXT:  i32.add    $push[[DEST:[0-9]+]]=,
+; CHECK-NEXT:  br_table   $pop[[DEST]], 0, 3, 1, 2, 3
+; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NEXT:  return{{$}}
-; CHECK-NEXT:  .LBB{{[0-9]+}}_9:
+; CHECK-NEXT:  .LBB{{[0-9]+}}_7:
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK:       br        0{{$}}
-; CHECK-NEXT:  .LBB{{[0-9]+}}_10:
+; CHECK-NEXT:  .LBB{{[0-9]+}}_8:
 ; CHECK-NEXT:  end_loop{{$}}
 define void @test10() {
 bb0:
   br label %bb1
 
 bb1:
   %tmp = phi i32 [ 2, %bb0 ], [ 3, %bb3 ]
   %tmp3 = phi i32 [ undef, %bb0 ], [ %tmp11, %bb3 ]
bb7:
   ret void
 bb8:
   store volatile i32 8, i32* null
   ret void
 }
 
 ; CHECK-LABEL: test12:
 ; CHECK:       .LBB{{[0-9]+}}_1:
-; CHECK-NEXT:  loop    {{$}}
-; CHECK-NEXT:  block   {{$}}
 ; CHECK-NEXT:  block   {{$}}
+; CHECK-NEXT:  loop    {{$}}
 ; CHECK-NEXT:  block   {{$}}
-; CHECK:       br_if     0, {{[^,]+}}{{$}}
-; CHECK:       br_if     2, {{[^,]+}}{{$}}
-; CHECK:       br_if     1, {{[^,]+}}{{$}}
-; CHECK-NEXT:  br        2{{$}}
-; CHECK-NEXT:  .LBB{{[0-9]+}}_4:
+; CHECK:       br_table   $pop{{[0-9]+}}, 0, 2, 2, 2, 0, 2{{$}}
+; CHECK-NEXT:  .LBB{{[0-9]+}}_2:
 ; CHECK-NEXT:  end_block{{$}}
-; CHECK-NEXT:  br_table   $2, 1, 0, 0, 0, 1, 1{{$}}
-; CHECK-NEXT:  .LBB{{[0-9]+}}_5:
+; CHECK:       br
+; CHECK-NEXT:  .LBB{{[0-9]+}}_3:
+; CHECK-NEXT:  end_loop{{$}}
 ; CHECK-NEXT:  end_block{{$}}
 ; CHECK-NEXT:  return{{$}}
-; CHECK-NEXT:  .LBB{{[0-9]+}}_6:
-; CHECK-NEXT:  end_block{{$}}
-; CHECK:       br        0{{$}}
-; CHECK-NEXT:  .LBB{{[0-9]+}}_7:
-; CHECK-NEXT:  end_loop{{$}}
 define void @test12(i8* %arg) {
 bb:
   br label %bb1
 
 bb1:
   %tmp = phi i32 [ 0, %bb ], [ %tmp5, %bb4 ]
   %tmp2 = getelementptr i8, i8* %arg, i32 %tmp
   %tmp3 = load i8, i8* %tmp2

llvm/test/CodeGen/WebAssembly/indirectbr.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
 
 ; This tests that indirectbr instructions are lowered to switches. Currently we
 ; just re-use the IndirectBrExpand Pass; it has its own IR-level test.
 ; So this test just ensures that the pass gets run and we can lower indirectbr
 
 target triple = "wasm32"
 
 @test1.targets = constant [4 x i8*] [i8* blockaddress(@test1, %bb0),
                                      i8* blockaddress(@test1, %bb1),
                                      i8* blockaddress(@test1, %bb2),
                                      i8* blockaddress(@test1, %bb3)]
 
 ; Just check the barest skeleton of the structure
 ; CHECK-LABEL: test1:
+; CHECK: block
+; CHECK: block
+; CHECK: block
+; CHECK: block
 ; CHECK: i32.load
-; CHECK: i32.load $[[DEST:.+]]=
+; CHECK: i32.const $push[[OFF:[0-9]+]]=, -2
+; CHECK: i32.add $push[[DEST:[0-9]+]]=, {{.*}}, $pop[[OFF]]
+; CHECK: br_table $pop[[DEST]]
 ; CHECK: loop
 ; CHECK: block
 ; CHECK: block
-; CHECK: end_block
 ; CHECK: block
 ; CHECK: block
-; CHECK: br_table $[[DEST]]
-; CHECK: end_block
-; CHECK: end_block
-; CHECK: i32.load $[[DEST]]=
+; CHECK: br_table
 ; CHECK: end_loop
 
 ; CHECK: test1.targets:
 ; CHECK-NEXT: .int32
 ; CHECK-NEXT: .int32
 ; CHECK-NEXT: .int32
 ; CHECK-NEXT: .int32
 

llvm/test/CodeGen/WebAssembly/stack-insts.ll

 ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-block-placement -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
 declare void @foo0()
 declare void @foo1()
 
 ; Tests if br_table is printed correctly with a tab.
 ; CHECK-LABEL: test0:
-; CHECK: br_table {0, 1, 0, 1, 0}
+; CHECK: br_table {0, 1, 0, 1, 2}
 define void @test0(i32 %n) {
 entry:
   switch i32 %n, label %sw.epilog [
     i32 0, label %sw.bb
     i32 1, label %sw.bb.1
     i32 2, label %sw.bb
     i32 3, label %sw.bb.1
   ]

llvm/test/CodeGen/WebAssembly/switch.ll

 ; CHECK-LABEL: bar32:
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
-; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 0{{$}}
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 6{{$}}
+; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK:   call foo0{{$}}
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK: .LBB{{[0-9]+}}_2:
 ; CHECK:   call foo1{{$}}
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: .LBB{{[0-9]+}}_3:
 ; CHECK:   call foo2{{$}}
-; CHECK: .LBB{{[0-9]+}}_5:
+; CHECK: .LBB{{[0-9]+}}_4:
 ; CHECK:   call foo3{{$}}
-; CHECK: .LBB{{[0-9]+}}_6:
+; CHECK: .LBB{{[0-9]+}}_5:
 ; CHECK:   call foo4{{$}}
-; CHECK: .LBB{{[0-9]+}}_7:
+; CHECK: .LBB{{[0-9]+}}_6:
 ; CHECK:   call foo5{{$}}
-; CHECK: .LBB{{[0-9]+}}_8:
+; CHECK: .LBB{{[0-9]+}}_7:
 ; CHECK:   return{{$}}
 define void @bar32(i32 %n) {
 entry:
   switch i32 %n, label %sw.epilog [
     i32 0, label %sw.bb
     i32 1, label %sw.bb
     i32 2, label %sw.bb
     i32 3, label %sw.bb

 ; CHECK-LABEL: bar64:
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
 ; CHECK: block   {{$}}
-; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 0{{$}}
-; CHECK: .LBB{{[0-9]+}}_2:
+; CHECK: br_table {{[^,]+}}, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 3, 4, 5, 6{{$}}
+; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK:   call foo0{{$}}
-; CHECK: .LBB{{[0-9]+}}_3:
+; CHECK: .LBB{{[0-9]+}}_2:
 ; CHECK:   call foo1{{$}}
-; CHECK: .LBB{{[0-9]+}}_4:
+; CHECK: .LBB{{[0-9]+}}_3:
 ; CHECK:   call foo2{{$}}
-; CHECK: .LBB{{[0-9]+}}_5:
+; CHECK: .LBB{{[0-9]+}}_4:
 ; CHECK:   call foo3{{$}}
-; CHECK: .LBB{{[0-9]+}}_6:
+; CHECK: .LBB{{[0-9]+}}_5:
 ; CHECK:   call foo4{{$}}
-; CHECK: .LBB{{[0-9]+}}_7:
+; CHECK: .LBB{{[0-9]+}}_6:
 ; CHECK:   call foo5{{$}}
-; CHECK: .LBB{{[0-9]+}}_8:
+; CHECK: .LBB{{[0-9]+}}_7:
 ; CHECK:   return{{$}}
 define void @bar64(i64 %n) {
 entry:
   switch i64 %n, label %sw.epilog [
     i64 0, label %sw.bb
     i64 1, label %sw.bb
     i64 2, label %sw.bb
     i64 3, label %sw.bb