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Differential D80470

AMDGPU: Start adding MODE register uses to instructions
ClosedPublic

Authored by arsenm on May 23 2020, 7:47 AM.

Details

Reviewers
rampitec
nhaehnle
foad
kerbowa
Summary

This is the groundwork required to implement strictfp. For now, this
should be NFC for regular instructions (many instructions just gain an
extra use of a reserved register). Regalloc won't rematerialize
instructions with reads of physical registers, but we were suffering
from that anyway with the exec reads.

Should add it for all the related FP uses (possibly with some
extras). I did not add it to either the gpr index mode instructions
or every single VALU instruction) since it's a ridiculous feature
already modeled as an arbitrary side effect.




Also work towards marking instructions with FP exceptions. This

doesn't actually set the bit yet since this would start to change

codegen. It seems nofpexcept is currently not implied from the regular

IR FP operations. Add it to some MIR tests where I think it might

matter.
Diff Detail
Event Timeline
arsenm created this revision.May 23 2020, 7:47 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptMay 23 2020, 7:47 AM
Herald added subscribers: javed.absar, hiraditya, t-tye and 8 others.  ·  View Herald Transcript
arsenm updated this revision to Diff 266514.May 27 2020, 6:25 AM
Add to interp instructions
arsenm added a child revision: D80630: AMDGPU: Set mayRaiseFPException.May 27 2020, 6:37 AM
rampitec accepted this revision.May 27 2020, 9:50 AM
LGTM
This revision is now accepted and ready to land.May 27 2020, 9:50 AM
arsenm closed this revision.May 27 2020, 11:47 AM
4b4496312e3380d8c427ef836f2b0a38d145652b
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Diff 266514
llvm/lib/Target/AMDGPU/SIInstrFormats.td
Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Linesclass InstSI <dag outs, dag ins, string asm = "",




  // This bit indicates that this is a D16 buffer instruction.
  // This bit indicates that this is a D16 buffer instruction.

  field bit D16Buf = 0;
  field bit D16Buf = 0;




  // This field indicates that FLAT instruction accesses FLAT_GLBL or
  // This field indicates that FLAT instruction accesses FLAT_GLBL or

  // FLAT_SCRATCH segment. Must be 0 for non-FLAT instructions.
  // FLAT_SCRATCH segment. Must be 0 for non-FLAT instructions.

  field bit IsNonFlatSeg = 0;
  field bit IsNonFlatSeg = 0;




  // Reads the mode register, usually for FP environment.

  field bit ReadsModeReg = 0;



  // This bit indicates that this uses the floating point double precision
  // This bit indicates that this uses the floating point double precision

  // rounding mode flags
  // rounding mode flags

  field bit FPDPRounding = 0;
  field bit FPDPRounding = 0;




  // Instruction is FP atomic.
  // Instruction is FP atomic.

  field bit FPAtomic = 0;
  field bit FPAtomic = 0;




  // This bit indicates that this is one of MFMA instructions.
  // This bit indicates that this is one of MFMA instructions.

▲ Show 20 Lines • Show All 249 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/SIInstructions.td
Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines



//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// VINTRP Instructions
// VINTRP Instructions

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




// Used to inject printing of "_e32" suffix for VI (there are "_e64" variants for VI)
// Used to inject printing of "_e32" suffix for VI (there are "_e64" variants for VI)

def VINTRPDst : VINTRPDstOperand <VGPR_32>;
def VINTRPDst : VINTRPDstOperand <VGPR_32>;




let Uses = [M0, EXEC] in {
let Uses = [MODE, M0, EXEC] in {




// FIXME: Specify SchedRW for VINTRP instructions.
// FIXME: Specify SchedRW for VINTRP instructions.




multiclass V_INTERP_P1_F32_m : VINTRP_m <
multiclass V_INTERP_P1_F32_m : VINTRP_m <

  0x00000000,
  0x00000000,

  (outs VINTRPDst:$vdst),
  (outs VINTRPDst:$vdst),

  (ins VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),
  (ins VGPR_32:$vsrc, Attr:$attr, AttrChan:$attrchan),

  "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",
  "v_interp_p1_f32$vdst, $vsrc, $attr$attrchan",

Show All 28 Lines
defm V_INTERP_MOV_F32 : VINTRP_m <
defm V_INTERP_MOV_F32 : VINTRP_m <

  0x00000002,
  0x00000002,

  (outs VINTRPDst:$vdst),
  (outs VINTRPDst:$vdst),

  (ins InterpSlot:$vsrc, Attr:$attr, AttrChan:$attrchan),
  (ins InterpSlot:$vsrc, Attr:$attr, AttrChan:$attrchan),

  "v_interp_mov_f32$vdst, $vsrc, $attr$attrchan",
  "v_interp_mov_f32$vdst, $vsrc, $attr$attrchan",

  [(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),
  [(set f32:$vdst, (int_amdgcn_interp_mov (i32 timm:$vsrc),

                   (i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
                   (i32 timm:$attrchan), (i32 timm:$attr), M0))]>;




} // End Uses = [M0, EXEC]
} // End Uses = [MODE, M0, EXEC]




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// Pseudo Instructions
// Pseudo Instructions

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

def ATOMIC_FENCE : SPseudoInstSI<
def ATOMIC_FENCE : SPseudoInstSI<

  (outs), (ins i32imm:$ordering, i32imm:$scope),
  (outs), (ins i32imm:$ordering, i32imm:$scope),

  [(atomic_fence (i32 timm:$ordering), (i32 timm:$scope))],
  [(atomic_fence (i32 timm:$ordering), (i32 timm:$scope))],

  "ATOMIC_FENCE $ordering, $scope"> {
  "ATOMIC_FENCE $ordering, $scope"> {

▲ Show 20 Lines • Show All 2,368 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/SOPInstructions.td
Show First 20 Lines • Show All 801 Lines • ▼ Show 20 Lines
}
}




let hasSideEffects = 1 in {
let hasSideEffects = 1 in {




def S_SETREG_B32 : SOPK_Pseudo <
def S_SETREG_B32 : SOPK_Pseudo <

  "s_setreg_b32",
  "s_setreg_b32",

  (outs), (ins SReg_32:$sdst, hwreg:$simm16),
  (outs), (ins SReg_32:$sdst, hwreg:$simm16),

  "$simm16, $sdst",
  "$simm16, $sdst",

  [(AMDGPUsetreg i32:$sdst, (i16 timm:$simm16))]
  [(AMDGPUsetreg i32:$sdst, (i16 timm:$simm16))]> {

>;
  let Defs = [MODE];

  let Uses = [MODE];

}




// FIXME: Not on SI?
// FIXME: Not on SI?

//def S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32">;
//def S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32">;




def S_SETREG_IMM32_B32 : SOPK_Pseudo <
def S_SETREG_IMM32_B32 : SOPK_Pseudo <

  "s_setreg_imm32_b32",
  "s_setreg_imm32_b32",

  (outs), (ins i32imm:$imm, hwreg:$simm16),
  (outs), (ins i32imm:$imm, hwreg:$simm16),

  "$simm16, $imm"> {
  "$simm16, $imm"> {

  let Size = 8; // Unlike every other SOPK instruction.
  let Size = 8; // Unlike every other SOPK instruction.

  let has_sdst = 0;
  let has_sdst = 0;

  let Defs = [MODE];

  let Uses = [MODE];

}
}




} // End hasSideEffects = 1
} // End hasSideEffects = 1




class SOPK_WAITCNT<string opName, list<dag> pat=[]> :
class SOPK_WAITCNT<string opName, list<dag> pat=[]> :

    SOPK_Pseudo<
    SOPK_Pseudo<

        opName,
        opName,

        (outs),
        (outs),

▲ Show 20 Lines • Show All 118 Lines • ▼ Show 20 Lines
def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;
def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;




let SubtargetPredicate = isGFX8Plus in {
let SubtargetPredicate = isGFX8Plus in {

def S_CMP_EQ_U64 : SOPC_CMP_64 <0x12, "s_cmp_eq_u64", COND_EQ>;
def S_CMP_EQ_U64 : SOPC_CMP_64 <0x12, "s_cmp_eq_u64", COND_EQ>;

def S_CMP_LG_U64 : SOPC_CMP_64 <0x13, "s_cmp_lg_u64", COND_NE>;
def S_CMP_LG_U64 : SOPC_CMP_64 <0x13, "s_cmp_lg_u64", COND_NE>;

} // End SubtargetPredicate = isGFX8Plus
} // End SubtargetPredicate = isGFX8Plus




let SubtargetPredicate = HasVGPRIndexMode in {
let SubtargetPredicate = HasVGPRIndexMode in {

// Setting the GPR index mode is really writing the fields in the mode

// register. We don't want to add mode register uses to every

// instruction, and it's too complicated to deal with anyway. This is

// modeled just as a side effect.

def S_SET_GPR_IDX_ON : SOPC <0x11,
def S_SET_GPR_IDX_ON : SOPC <0x11,

  (outs),
  (outs),

  (ins SSrc_b32:$src0, GPRIdxMode:$src1),
  (ins SSrc_b32:$src0, GPRIdxMode:$src1),

  "s_set_gpr_idx_on $src0,$src1"> {
  "s_set_gpr_idx_on $src0,$src1"> {

  let Defs = [M0]; // No scc def
  let Defs = [M0]; // No scc def

  let Uses = [M0]; // Other bits of m0 unmodified.
  let Uses = [M0]; // Other bits of m0 unmodified.

  let hasSideEffects = 1; // Sets mode.gpr_idx_en
  let hasSideEffects = 1; // Sets mode.gpr_idx_en

  let FixedSize = 1;
  let FixedSize = 1;

▲ Show 20 Lines • Show All 240 Lines • ▼ Show 20 Lineslet SubtargetPredicate = isGFX10Plus in {

  def S_CLAUSE :
  def S_CLAUSE :

    SOPP<0x021, (ins s16imm:$simm16), "s_clause $simm16">;
    SOPP<0x021, (ins s16imm:$simm16), "s_clause $simm16">;

  def S_WAITCNT_IDLE :
  def S_WAITCNT_IDLE :

    SOPP <0x022, (ins), "s_wait_idle"> {
    SOPP <0x022, (ins), "s_wait_idle"> {

      let simm16 = 0;
      let simm16 = 0;

    }
    }

  def S_WAITCNT_DEPCTR :
  def S_WAITCNT_DEPCTR :

    SOPP <0x023, (ins s16imm:$simm16), "s_waitcnt_depctr $simm16">;
    SOPP <0x023, (ins s16imm:$simm16), "s_waitcnt_depctr $simm16">;



  let hasSideEffects = 1, Uses = [MODE], Defs = [MODE] in {

    // FIXME: Should remove hasSideEffects

  def S_ROUND_MODE :
    def S_ROUND_MODE :

    SOPP<0x024, (ins s16imm:$simm16), "s_round_mode $simm16">;
      SOPP<0x024, (ins s16imm:$simm16), "s_round_mode $simm16">;

  def S_DENORM_MODE :
    def S_DENORM_MODE :

    SOPP<0x025, (ins i32imm:$simm16), "s_denorm_mode $simm16",
      SOPP<0x025, (ins i32imm:$simm16), "s_denorm_mode $simm16",

    [(SIdenorm_mode (i32 timm:$simm16))]> {
      [(SIdenorm_mode (i32 timm:$simm16))]>;

      let hasSideEffects = 1;

    }
  }



  def S_TTRACEDATA_IMM :
  def S_TTRACEDATA_IMM :

    SOPP<0x028, (ins s16imm:$simm16), "s_ttracedata_imm $simm16">;
    SOPP<0x028, (ins s16imm:$simm16), "s_ttracedata_imm $simm16">;

} // End SubtargetPredicate = isGFX10Plus
} // End SubtargetPredicate = isGFX10Plus




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// S_GETREG_B32 Intrinsic Pattern.
// S_GETREG_B32 Intrinsic Pattern.

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

def : GCNPat <
def : GCNPat <

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llvm/lib/Target/AMDGPU/VOP1Instructions.td
Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Linesclass VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], bit VOP1Only = 0> :




  let AsmOperands = P.Asm32;
  let AsmOperands = P.Asm32;




  let Size = 4;
  let Size = 4;

  let mayLoad = 0;
  let mayLoad = 0;

  let mayStore = 0;
  let mayStore = 0;

  let hasSideEffects = 0;
  let hasSideEffects = 0;




  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);



  // FIXME

  // let mayRaiseFPException = ReadsModeReg;



  let VOP1 = 1;
  let VOP1 = 1;

  let VALU = 1;
  let VALU = 1;

  let Uses = [EXEC];
  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);




  let AsmVariantName = AMDGPUAsmVariants.Default;
  let AsmVariantName = AMDGPUAsmVariants.Default;

}
}




class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :
class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :

  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,

  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
  SIMCInstr <ps.PseudoInstr, EncodingFamily> {




▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Linesdef V_READFIRSTLANE_B32 :

  let Inst{8-0}   = src0;
  let Inst{8-0}   = src0;

  let Inst{16-9}  = 0x2;
  let Inst{16-9}  = 0x2;

  let Inst{24-17} = vdst;
  let Inst{24-17} = vdst;

  let Inst{31-25} = 0x3f; //encoding
  let Inst{31-25} = 0x3f; //encoding

}
}




let SchedRW = [WriteDoubleCvt] in {
let SchedRW = [WriteDoubleCvt] in {

defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64,  fp_to_sint>;
defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64,  fp_to_sint>;



let mayRaiseFPException = 0 in {

defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP1_F64_I32, sint_to_fp>;
defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP1_F64_I32, sint_to_fp>;

}



defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64,  fpround>;
defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64,  fpround>;

defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32,  fpextend>;
defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32,  fpextend>;

defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64,  fp_to_uint>;
defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64,  fp_to_uint>;



let mayRaiseFPException = 0 in {

defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;
defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP1_F64_I32, uint_to_fp>;

}



} // End SchedRW = [WriteDoubleCvt]
} // End SchedRW = [WriteDoubleCvt]




let SchedRW = [WriteFloatCvt] in {
let SchedRW = [WriteFloatCvt] in {



// XXX: Does this really not raise exceptions? The manual claims the

// 16-bit ones can.

let mayRaiseFPException = 0 in {

defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP1_F32_I32, sint_to_fp>;
defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP1_F32_I32, sint_to_fp>;

defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;
defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP1_F32_I32, uint_to_fp>;

}



defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32, fp_to_uint>;
defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32, fp_to_uint>;

defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32, fp_to_sint>;
defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32, fp_to_sint>;

let FPDPRounding = 1 in {
let FPDPRounding = 1 in {

defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, fpround>;
defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, fpround>;

} // End FPDPRounding = 1
} // End FPDPRounding = 1



defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, fpextend>;
defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_F16, fpextend>;



let ReadsModeReg = 0, mayRaiseFPException = 0 in {

defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;
defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;

defm V_CVT_FLR_I32_F32 : VOP1Inst <"v_cvt_flr_i32_f32", VOP_I32_F32, cvt_flr_i32_f32>;
defm V_CVT_FLR_I32_F32 : VOP1Inst <"v_cvt_flr_i32_f32", VOP_I32_F32, cvt_flr_i32_f32>;

defm V_CVT_OFF_F32_I4 : VOP1Inst  <"v_cvt_off_f32_i4", VOP1_F32_I32>;
defm V_CVT_OFF_F32_I4 : VOP1Inst  <"v_cvt_off_f32_i4", VOP1_F32_I32>;

} // End ReadsModeReg = 0, mayRaiseFPException = 0

} // End SchedRW = [WriteFloatCvt]
} // End SchedRW = [WriteFloatCvt]




let ReadsModeReg = 0, mayRaiseFPException = 0 in {

defm V_CVT_F32_UBYTE0 : VOP1Inst <"v_cvt_f32_ubyte0", VOP1_F32_I32, AMDGPUcvt_f32_ubyte0>;
defm V_CVT_F32_UBYTE0 : VOP1Inst <"v_cvt_f32_ubyte0", VOP1_F32_I32, AMDGPUcvt_f32_ubyte0>;

defm V_CVT_F32_UBYTE1 : VOP1Inst <"v_cvt_f32_ubyte1", VOP1_F32_I32, AMDGPUcvt_f32_ubyte1>;
defm V_CVT_F32_UBYTE1 : VOP1Inst <"v_cvt_f32_ubyte1", VOP1_F32_I32, AMDGPUcvt_f32_ubyte1>;

defm V_CVT_F32_UBYTE2 : VOP1Inst <"v_cvt_f32_ubyte2", VOP1_F32_I32, AMDGPUcvt_f32_ubyte2>;
defm V_CVT_F32_UBYTE2 : VOP1Inst <"v_cvt_f32_ubyte2", VOP1_F32_I32, AMDGPUcvt_f32_ubyte2>;

defm V_CVT_F32_UBYTE3 : VOP1Inst <"v_cvt_f32_ubyte3", VOP1_F32_I32, AMDGPUcvt_f32_ubyte3>;
defm V_CVT_F32_UBYTE3 : VOP1Inst <"v_cvt_f32_ubyte3", VOP1_F32_I32, AMDGPUcvt_f32_ubyte3>;

} // ReadsModeReg = 0, mayRaiseFPException = 0




defm V_FRACT_F32 : VOP1Inst <"v_fract_f32", VOP_F32_F32, AMDGPUfract>;
defm V_FRACT_F32 : VOP1Inst <"v_fract_f32", VOP_F32_F32, AMDGPUfract>;

defm V_TRUNC_F32 : VOP1Inst <"v_trunc_f32", VOP_F32_F32, ftrunc>;
defm V_TRUNC_F32 : VOP1Inst <"v_trunc_f32", VOP_F32_F32, ftrunc>;

defm V_CEIL_F32 : VOP1Inst <"v_ceil_f32", VOP_F32_F32, fceil>;
defm V_CEIL_F32 : VOP1Inst <"v_ceil_f32", VOP_F32_F32, fceil>;

defm V_RNDNE_F32 : VOP1Inst <"v_rndne_f32", VOP_F32_F32, frint>;
defm V_RNDNE_F32 : VOP1Inst <"v_rndne_f32", VOP_F32_F32, frint>;

defm V_FLOOR_F32 : VOP1Inst <"v_floor_f32", VOP_F32_F32, ffloor>;
defm V_FLOOR_F32 : VOP1Inst <"v_floor_f32", VOP_F32_F32, ffloor>;




let SchedRW = [WriteQuarterRate32] in {
let SchedRW = [WriteQuarterRate32] in {

▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines
let SubtargetPredicate = isGFX9Plus in {
let SubtargetPredicate = isGFX9Plus in {

  def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {
  def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {

    let Constraints = "$vdst = $src1, $vdst1 = $src0";
    let Constraints = "$vdst = $src1, $vdst1 = $src0";

    let DisableEncoding = "$vdst1,$src1";
    let DisableEncoding = "$vdst1,$src1";

    let SchedRW = [Write64Bit, Write64Bit];
    let SchedRW = [Write64Bit, Write64Bit];

  }
  }




  defm V_SAT_PK_U8_I16    : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
  defm V_SAT_PK_U8_I16    : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;



  let mayRaiseFPException = 0 in {

  defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;
    defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16>;

  defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;
    defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16>;

  } // End mayRaiseFPException = 0

} // End SubtargetPredicate = isGFX9Plus
} // End SubtargetPredicate = isGFX9Plus




let SubtargetPredicate = isGFX9Only in {
let SubtargetPredicate = isGFX9Only in {

  defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;
  defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;

} // End SubtargetPredicate = isGFX9Only
} // End SubtargetPredicate = isGFX9Only




let SubtargetPredicate = isGFX10Plus in {
let SubtargetPredicate = isGFX10Plus in {

  defm V_PIPEFLUSH        : VOP1Inst<"v_pipeflush", VOP_NONE>;
  defm V_PIPEFLUSH        : VOP1Inst<"v_pipeflush", VOP_NONE>;

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llvm/lib/Target/AMDGPU/VOP2Instructions.td
Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesclass VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :




  let AsmOperands = P.Asm32;
  let AsmOperands = P.Asm32;




  let Size = 4;
  let Size = 4;

  let mayLoad = 0;
  let mayLoad = 0;

  let mayStore = 0;
  let mayStore = 0;

  let hasSideEffects = 0;
  let hasSideEffects = 0;




  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);



  // FIXME: Set this

  // let mayRaiseFPException = ReadsModeReg;



  let VOP2 = 1;
  let VOP2 = 1;

  let VALU = 1;
  let VALU = 1;

  let Uses = [EXEC];
  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);




  let AsmVariantName = AMDGPUAsmVariants.Default;
  let AsmVariantName = AMDGPUAsmVariants.Default;

}
}




class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :

  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,

  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
  SIMCInstr <ps.PseudoInstr, EncodingFamily> {




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} // End isConvergent = 1
} // End isConvergent = 1




defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;
defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_NO_EXT<VOP_I32_I32_I32>>;

defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;
defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, add_ctpop>;

defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;
defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_lo>;

defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;
defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_NO_EXT<VOP_I32_I32_I32>, int_amdgcn_mbcnt_hi>;

defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;
defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_NO_EXT<VOP_F32_F32_I32>, AMDGPUldexp>;

defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"
defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_NO_EXT<VOP_I32_F32_I32>>; // TODO: set "Uses = dst"



let ReadsModeReg = 0, mayRaiseFPException = 0 in {

defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;
defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_i16_f32>;

defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;
defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_NO_EXT<VOP_V2I16_F32_F32>, AMDGPUpknorm_u16_f32>;

}



defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;
defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_NO_EXT<VOP_V2F16_F32_F32>, AMDGPUpkrtz_f16_f32>;

defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;
defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_u16_u32>;

defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;
defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_NO_EXT<VOP_V2I16_I32_I32>, AMDGPUpk_i16_i32>;







let SubtargetPredicate = isGFX6GFX7 in {
let SubtargetPredicate = isGFX6GFX7 in {

defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;

defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;

▲ Show 20 Lines • Show All 1,057 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/VOP3Instructions.td
Show First 20 Lines • Show All 284 Lines • ▼ Show 20 Lines
}
}




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// VOP3 Instructions
// VOP3 Instructions

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




let isCommutable = 1 in {
let isCommutable = 1 in {




let mayRaiseFPException = 0 in {

def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;

def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;

}



def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;

def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;

def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;

def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;




let SchedRW = [WriteDoubleAdd] in {
let SchedRW = [WriteDoubleAdd] in {

let FPDPRounding = 1 in {
let FPDPRounding = 1 in {

def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;

def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;

def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;

} // End FPDPRounding = 1
} // End FPDPRounding = 1

def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>;
def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum_like, 1>;

def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>;
def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum_like, 1>;

} // End SchedRW = [WriteDoubleAdd]
} // End SchedRW = [WriteDoubleAdd]




let SchedRW = [WriteQuarterRate32] in {
let SchedRW = [WriteQuarterRate32] in {

def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>;
def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>, mul>;

def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;

def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;

def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;

} // End SchedRW = [WriteQuarterRate32]
} // End SchedRW = [WriteQuarterRate32]




let Uses = [VCC, EXEC] in {
let Uses = [MODE, VCC, EXEC] in {

// v_div_fmas_f32:
// v_div_fmas_f32:

//   result = src0 * src1 + src2
//   result = src0 * src1 + src2

//   if (vcc)
//   if (vcc)

//     result *= 2^32
//     result *= 2^32

//
//

def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> {
def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC, []> {

  let SchedRW = [WriteFloatFMA];
  let SchedRW = [WriteFloatFMA];

}
}

// v_div_fmas_f64:
// v_div_fmas_f64:

//   result = src0 * src1 + src2
//   result = src0 * src1 + src2

//   if (vcc)
//   if (vcc)

//     result *= 2^64
//     result *= 2^64

//
//

def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []> {
def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC, []> {

  let SchedRW = [WriteDouble];
  let SchedRW = [WriteDouble];

  let FPDPRounding = 1;
  let FPDPRounding = 1;

}
}

} // End Uses = [VCC, EXEC]
} // End Uses = [VCC, EXEC]




} // End isCommutable = 1
} // End isCommutable = 1




let mayRaiseFPException = 0 in {

def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;

def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;

def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;

def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;

} // End mayRaiseFPException



def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;

def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;

def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;

def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>;
def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, fshr>;

def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;



let mayRaiseFPException = 0 in { // XXX - Seems suspect but manual doesn't say it does

def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;

def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;

def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;

def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;

def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;

def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;

def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;

def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;

def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;

} // End mayRaiseFPException = 0



def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;

def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;

def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;

def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;

def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;

def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;




let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in {
let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in {

def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;

def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;

} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1
} // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1






let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does.

def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {

  let SchedRW = [WriteFloatFMA, WriteSALU];
  let SchedRW = [WriteFloatFMA, WriteSALU];

  let AsmMatchConverter = "";
  let AsmMatchConverter = "";

}
}




// Double precision division pre-scale.
// Double precision division pre-scale.

def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {

  let SchedRW = [WriteDouble, WriteSALU];
  let SchedRW = [WriteDouble, WriteSALU];

  let AsmMatchConverter = "";
  let AsmMatchConverter = "";

  let FPDPRounding = 1;
  let FPDPRounding = 1;

}
}

} // End mayRaiseFPException = 0




def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;




let Constraints = "@earlyclobber $vdst" in {
let Constraints = "@earlyclobber $vdst" in {

def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;

} // End Constraints = "@earlyclobber $vdst"
} // End Constraints = "@earlyclobber $vdst"




def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {

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let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {




let renamedInGFX9 = 1 in {
let renamedInGFX9 = 1 in {

def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;

def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;

let FPDPRounding = 1 in {
let FPDPRounding = 1 in {

def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;

let Uses = [M0, EXEC] in {
let Uses = [MODE, M0, EXEC] in {

// For some reason the intrinsic operands are in a different order
// For some reason the intrinsic operands are in a different order

// from the instruction operands.
// from the instruction operands.

def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>,
def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>,

       [(set f16:$vdst,
       [(set f16:$vdst,

         (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers),
         (int_amdgcn_interp_p2_f16 (VOP3Mods f32:$src2, i32:$src2_modifiers),

                                   (VOP3Mods f32:$src0, i32:$src0_modifiers),
                                   (VOP3Mods f32:$src0, i32:$src0_modifiers),

                                   (i32 timm:$attrchan),
                                   (i32 timm:$attrchan),

                                   (i32 timm:$attr),
                                   (i32 timm:$attr),

                                   (i1 timm:$high),
                                   (i1 timm:$high),

                                   M0))]>;
                                   M0))]>;

} // End Uses = [M0, EXEC]
} // End Uses = [M0, MODE, EXEC]

} // End FPDPRounding = 1
} // End FPDPRounding = 1

} // End renamedInGFX9 = 1
} // End renamedInGFX9 = 1




let SubtargetPredicate = isGFX9Only in {
let SubtargetPredicate = isGFX9Only in {

def V_MAD_F16_gfx9   : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> {
def V_MAD_F16_gfx9   : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>> {

  let FPDPRounding = 1;
  let FPDPRounding = 1;

}
}

} // End SubtargetPredicate = isGFX9Only
} // End SubtargetPredicate = isGFX9Only




let SubtargetPredicate = isGFX9Plus in {
let SubtargetPredicate = isGFX9Plus in {

def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_MAD_U16_gfx9   : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;

def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
def V_MAD_I16_gfx9   : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;

def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;

} // End SubtargetPredicate = isGFX9Plus
} // End SubtargetPredicate = isGFX9Plus




let Uses = [M0, EXEC], FPDPRounding = 1 in {
let Uses = [MODE, M0, EXEC], FPDPRounding = 1 in {

def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>,
def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>,

       [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers),
       [(set f32:$vdst, (int_amdgcn_interp_p1_f16 (VOP3Mods f32:$src0, i32:$src0_modifiers),

                                                  (i32 timm:$attrchan),
                                                  (i32 timm:$attrchan),

                                                  (i32 timm:$attr),
                                                  (i32 timm:$attr),

                                                  (i1 timm:$high), M0))]> {
                                                  (i1 timm:$high), M0))]> {

  // This predicate should only apply to the selection pattern. The
  // This predicate should only apply to the selection pattern. The

  // instruction still exists and should decode on subtargets with
  // instruction still exists and should decode on subtargets with

  // other bank counts.
  // other bank counts.

  let OtherPredicates = [has32BankLDS];
  let OtherPredicates = [has32BankLDS];

}
}







def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;

} // End Uses = [M0, EXEC], FPDPRounding = 1
} // End Uses = [MODE, M0, EXEC], FPDPRounding = 1




} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
} // End SubtargetPredicate = Has16BitInsts, isCommutable = 1




let SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC] in {
let SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC] in {

def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
def V_INTERP_P1_F32_e64  : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;

def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
def V_INTERP_P2_F32_e64  : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;

def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;

} // End SubtargetPredicate = isGFX8Plus, Uses = [M0, EXEC]
} // End SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC]




let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in {
let Predicates = [Has16BitInsts, isGFX6GFX7GFX8GFX9] in {




multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,

                             Instruction inst, SDPatternOperator op3> {
                             Instruction inst, SDPatternOperator op3> {

def : GCNPat <
def : GCNPat <

  (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
  (op2 (op1 i16:$src0, i16:$src1), i16:$src2),

  (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
  (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))

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llvm/lib/Target/AMDGPU/VOP3PInstructions.td
Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines    (v2f16 (mixhi_inst $hi_src0_modifiers, $hi_src0,

                                   $lo_src1_modifiers, $lo_src1,
                                   $lo_src1_modifiers, $lo_src1,

                                   $lo_src2_modifiers, $lo_src2,
                                   $lo_src2_modifiers, $lo_src2,

                                   DSTCLAMP.ENABLE,
                                   DSTCLAMP.ENABLE,

                                   (i32 (IMPLICIT_DEF)))))
                                   (i32 (IMPLICIT_DEF)))))

  >;
  >;

}
}




let SubtargetPredicate = HasMadMixInsts in {
let SubtargetPredicate = HasMadMixInsts in {



// These are VOP3a-like opcodes which accept no omod.
// These are VOP3a-like opcodes which accept no omod.

// Size of src arguments (16/32) is controlled by op_sel.
// Size of src arguments (16/32) is controlled by op_sel.

// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.
// For 16-bit src arguments their location (hi/lo) are controlled by op_sel_hi.

let isCommutable = 1 in {
let isCommutable = 1, mayRaiseFPException = 0 in {

def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>;
def V_MAD_MIX_F32 : VOP3_VOP3PInst<"v_mad_mix_f32", VOP3_Profile<VOP_F32_F16_F16_F16, VOP3_OPSEL>>;




let FPDPRounding = 1 in {
let FPDPRounding = 1 in {

// Clamp modifier is applied after conversion to f16.
// Clamp modifier is applied after conversion to f16.

def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;
def V_MAD_MIXLO_F16 : VOP3_VOP3PInst<"v_mad_mixlo_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;




let ClampLo = 0, ClampHi = 1 in {
let ClampLo = 0, ClampHi = 1 in {

def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;
def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, 1>;

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def VOPProfileMAI_F32_V4F16_X32 : VOPProfileMAI<VOP_V32F32_V4F16_V4F16_V32F32, AISrc_1024_b32, ADst_1024, AVSrc_64>;
def VOPProfileMAI_F32_V4F16_X32 : VOPProfileMAI<VOP_V32F32_V4F16_V4F16_V32F32, AISrc_1024_b32, ADst_1024, AVSrc_64>;




let Predicates = [HasMAIInsts] in {
let Predicates = [HasMAIInsts] in {

def V_ACCVGPR_READ_B32  : VOP3Inst<"v_accvgpr_read_b32",  VOPProfileAccRead>;
def V_ACCVGPR_READ_B32  : VOP3Inst<"v_accvgpr_read_b32",  VOPProfileAccRead>;

def V_ACCVGPR_WRITE_B32 : VOP3Inst<"v_accvgpr_write_b32", VOPProfileAccWrite> {
def V_ACCVGPR_WRITE_B32 : VOP3Inst<"v_accvgpr_write_b32", VOPProfileAccWrite> {

  let isMoveImm = 1;
  let isMoveImm = 1;

}
}




let isConvergent = 1 in {
// FP32 denorm mode is respected, rounding mode is not. Exceptions are not supported.

let isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1 in {

def V_MFMA_F32_4X4X1F32    : VOP3Inst<"v_mfma_f32_4x4x1f32",    VOPProfileMAI_F32_F32_X4,    int_amdgcn_mfma_f32_4x4x1f32>;
def V_MFMA_F32_4X4X1F32    : VOP3Inst<"v_mfma_f32_4x4x1f32",    VOPProfileMAI_F32_F32_X4,    int_amdgcn_mfma_f32_4x4x1f32>;

def V_MFMA_F32_4X4X4F16    : VOP3Inst<"v_mfma_f32_4x4x4f16",    VOPProfileMAI_F32_V4F16_X4,  int_amdgcn_mfma_f32_4x4x4f16>;
def V_MFMA_F32_4X4X4F16    : VOP3Inst<"v_mfma_f32_4x4x4f16",    VOPProfileMAI_F32_V4F16_X4,  int_amdgcn_mfma_f32_4x4x4f16>;

def V_MFMA_I32_4X4X4I8     : VOP3Inst<"v_mfma_i32_4x4x4i8",     VOPProfileMAI_I32_I32_X4,    int_amdgcn_mfma_i32_4x4x4i8>;
def V_MFMA_I32_4X4X4I8     : VOP3Inst<"v_mfma_i32_4x4x4i8",     VOPProfileMAI_I32_I32_X4,    int_amdgcn_mfma_i32_4x4x4i8>;

def V_MFMA_F32_4X4X2BF16   : VOP3Inst<"v_mfma_f32_4x4x2bf16",   VOPProfileMAI_F32_V2I16_X4,  int_amdgcn_mfma_f32_4x4x2bf16>;
def V_MFMA_F32_4X4X2BF16   : VOP3Inst<"v_mfma_f32_4x4x2bf16",   VOPProfileMAI_F32_V2I16_X4,  int_amdgcn_mfma_f32_4x4x2bf16>;

def V_MFMA_F32_16X16X1F32  : VOP3Inst<"v_mfma_f32_16x16x1f32",  VOPProfileMAI_F32_F32_X16,   int_amdgcn_mfma_f32_16x16x1f32>;
def V_MFMA_F32_16X16X1F32  : VOP3Inst<"v_mfma_f32_16x16x1f32",  VOPProfileMAI_F32_F32_X16,   int_amdgcn_mfma_f32_16x16x1f32>;

def V_MFMA_F32_16X16X4F32  : VOP3Inst<"v_mfma_f32_16x16x4f32",  VOPProfileMAI_F32_F32_X4,    int_amdgcn_mfma_f32_16x16x4f32>;
def V_MFMA_F32_16X16X4F32  : VOP3Inst<"v_mfma_f32_16x16x4f32",  VOPProfileMAI_F32_F32_X4,    int_amdgcn_mfma_f32_16x16x4f32>;

def V_MFMA_F32_16X16X4F16  : VOP3Inst<"v_mfma_f32_16x16x4f16",  VOPProfileMAI_F32_V4F16_X16, int_amdgcn_mfma_f32_16x16x4f16>;
def V_MFMA_F32_16X16X4F16  : VOP3Inst<"v_mfma_f32_16x16x4f16",  VOPProfileMAI_F32_V4F16_X16, int_amdgcn_mfma_f32_16x16x4f16>;

def V_MFMA_F32_16X16X16F16 : VOP3Inst<"v_mfma_f32_16x16x16f16", VOPProfileMAI_F32_V4F16_X4,  int_amdgcn_mfma_f32_16x16x16f16>;
def V_MFMA_F32_16X16X16F16 : VOP3Inst<"v_mfma_f32_16x16x16f16", VOPProfileMAI_F32_V4F16_X4,  int_amdgcn_mfma_f32_16x16x16f16>;

def V_MFMA_I32_16X16X4I8   : VOP3Inst<"v_mfma_i32_16x16x4i8",   VOPProfileMAI_I32_I32_X16,   int_amdgcn_mfma_i32_16x16x4i8>;
def V_MFMA_I32_16X16X4I8   : VOP3Inst<"v_mfma_i32_16x16x4i8",   VOPProfileMAI_I32_I32_X16,   int_amdgcn_mfma_i32_16x16x4i8>;

def V_MFMA_I32_16X16X16I8  : VOP3Inst<"v_mfma_i32_16x16x16i8",  VOPProfileMAI_I32_I32_X4,    int_amdgcn_mfma_i32_16x16x16i8>;
def V_MFMA_I32_16X16X16I8  : VOP3Inst<"v_mfma_i32_16x16x16i8",  VOPProfileMAI_I32_I32_X4,    int_amdgcn_mfma_i32_16x16x16i8>;

def V_MFMA_F32_16X16X2BF16 : VOP3Inst<"v_mfma_f32_16x16x2bf16", VOPProfileMAI_F32_V2I16_X16, int_amdgcn_mfma_f32_16x16x2bf16>;
def V_MFMA_F32_16X16X2BF16 : VOP3Inst<"v_mfma_f32_16x16x2bf16", VOPProfileMAI_F32_V2I16_X16, int_amdgcn_mfma_f32_16x16x2bf16>;

def V_MFMA_F32_16X16X8BF16 : VOP3Inst<"v_mfma_f32_16x16x8bf16", VOPProfileMAI_F32_V2I16_X4,  int_amdgcn_mfma_f32_16x16x8bf16>;
def V_MFMA_F32_16X16X8BF16 : VOP3Inst<"v_mfma_f32_16x16x8bf16", VOPProfileMAI_F32_V2I16_X4,  int_amdgcn_mfma_f32_16x16x8bf16>;

def V_MFMA_F32_32X32X1F32  : VOP3Inst<"v_mfma_f32_32x32x1f32",  VOPProfileMAI_F32_F32_X32,   int_amdgcn_mfma_f32_32x32x1f32>;
def V_MFMA_F32_32X32X1F32  : VOP3Inst<"v_mfma_f32_32x32x1f32",  VOPProfileMAI_F32_F32_X32,   int_amdgcn_mfma_f32_32x32x1f32>;

def V_MFMA_F32_32X32X2F32  : VOP3Inst<"v_mfma_f32_32x32x2f32",  VOPProfileMAI_F32_F32_X16,   int_amdgcn_mfma_f32_32x32x2f32>;
def V_MFMA_F32_32X32X2F32  : VOP3Inst<"v_mfma_f32_32x32x2f32",  VOPProfileMAI_F32_F32_X16,   int_amdgcn_mfma_f32_32x32x2f32>;

def V_MFMA_F32_32X32X4F16  : VOP3Inst<"v_mfma_f32_32x32x4f16",  VOPProfileMAI_F32_V4F16_X32, int_amdgcn_mfma_f32_32x32x4f16>;
def V_MFMA_F32_32X32X4F16  : VOP3Inst<"v_mfma_f32_32x32x4f16",  VOPProfileMAI_F32_V4F16_X32, int_amdgcn_mfma_f32_32x32x4f16>;

def V_MFMA_F32_32X32X8F16  : VOP3Inst<"v_mfma_f32_32x32x8f16",  VOPProfileMAI_F32_V4F16_X16, int_amdgcn_mfma_f32_32x32x8f16>;
def V_MFMA_F32_32X32X8F16  : VOP3Inst<"v_mfma_f32_32x32x8f16",  VOPProfileMAI_F32_V4F16_X16, int_amdgcn_mfma_f32_32x32x8f16>;

def V_MFMA_I32_32X32X4I8   : VOP3Inst<"v_mfma_i32_32x32x4i8",   VOPProfileMAI_I32_I32_X32,   int_amdgcn_mfma_i32_32x32x4i8>;
def V_MFMA_I32_32X32X4I8   : VOP3Inst<"v_mfma_i32_32x32x4i8",   VOPProfileMAI_I32_I32_X32,   int_amdgcn_mfma_i32_32x32x4i8>;

def V_MFMA_I32_32X32X8I8   : VOP3Inst<"v_mfma_i32_32x32x8i8",   VOPProfileMAI_I32_I32_X16,   int_amdgcn_mfma_i32_32x32x8i8>;
def V_MFMA_I32_32X32X8I8   : VOP3Inst<"v_mfma_i32_32x32x8i8",   VOPProfileMAI_I32_I32_X16,   int_amdgcn_mfma_i32_32x32x8i8>;

def V_MFMA_F32_32X32X2BF16 : VOP3Inst<"v_mfma_f32_32x32x2bf16", VOPProfileMAI_F32_V2I16_X32, int_amdgcn_mfma_f32_32x32x2bf16>;
def V_MFMA_F32_32X32X2BF16 : VOP3Inst<"v_mfma_f32_32x32x2bf16", VOPProfileMAI_F32_V2I16_X32, int_amdgcn_mfma_f32_32x32x2bf16>;

def V_MFMA_F32_32X32X4BF16 : VOP3Inst<"v_mfma_f32_32x32x4bf16", VOPProfileMAI_F32_V2I16_X16, int_amdgcn_mfma_f32_32x32x4bf16>;
def V_MFMA_F32_32X32X4BF16 : VOP3Inst<"v_mfma_f32_32x32x4bf16", VOPProfileMAI_F32_V2I16_X16, int_amdgcn_mfma_f32_32x32x4bf16>;

} // End isConvergent = 1
} // End isConvergent = 1, mayRaiseFPException = 0, ReadsModeReg = 1




} // End SubtargetPredicate = HasMAIInsts
} // End SubtargetPredicate = HasMAIInsts




def : MnemonicAlias<"v_accvgpr_read",  "v_accvgpr_read_b32">;
def : MnemonicAlias<"v_accvgpr_read",  "v_accvgpr_read_b32">;

def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">;
def : MnemonicAlias<"v_accvgpr_write", "v_accvgpr_write_b32">;




multiclass VOP3P_Real_vi<bits<10> op> {
multiclass VOP3P_Real_vi<bits<10> op> {

  def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
  def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,

▲ Show 20 Lines • Show All 148 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/VOPCInstructions.td
Show First 20 Lines • Show All 86 Lines • ▼ Show 20 Linesclass VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[],

  string Mnemonic = opName;
  string Mnemonic = opName;

  string AsmOperands = P.Asm32;
  string AsmOperands = P.Asm32;




  let Size = 4;
  let Size = 4;

  let mayLoad = 0;
  let mayLoad = 0;

  let mayStore = 0;
  let mayStore = 0;

  let hasSideEffects = 0;
  let hasSideEffects = 0;




  let ReadsModeReg = isFloatType<P.Src0VT>.ret;



  let VALU = 1;
  let VALU = 1;

  let VOPC = 1;
  let VOPC = 1;

  let Uses = [EXEC];
  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);

  let Defs = !if(DefVcc, [VCC], []);
  let Defs = !if(DefVcc, [VCC], []);




  VOPProfile Pfl = P;
  VOPProfile Pfl = P;

}
}




class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :
class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> :

  InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>,
  InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>,

  SIMCInstr <ps.PseudoInstr, EncodingFamily> {
  SIMCInstr <ps.PseudoInstr, EncodingFamily> {

▲ Show 20 Lines • Show All 627 Lines • ▼ Show 20 Linesmulticlass VOPCX_CLASS_F32 <string opName> :

  VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>;
  VOPCX_Class_Pseudos <opName, VOPC_I1_F32_I32, VOPC_F32_I32>;




multiclass VOPC_CLASS_F64 <string opName> :
multiclass VOPC_CLASS_F64 <string opName> :

  VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;
  VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>;




multiclass VOPCX_CLASS_F64 <string opName> :
multiclass VOPCX_CLASS_F64 <string opName> :

  VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>;
  VOPCX_Class_Pseudos <opName, VOPC_I1_F64_I32, VOPC_F64_I32>;




// cmp_class ignores the FP mode and faithfully reports the unmodified

// source value.

let ReadsModeReg = 0, mayRaiseFPException = 0 in {

defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;
defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">;

defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;
defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">;

defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;
defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">;

defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;
defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">;




let SubtargetPredicate = Has16BitInsts in {
let SubtargetPredicate = Has16BitInsts in {

defm V_CMP_CLASS_F16  : VOPC_CLASS_F16 <"v_cmp_class_f16">;
defm V_CMP_CLASS_F16  : VOPC_CLASS_F16 <"v_cmp_class_f16">;

defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;
defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">;

}
}

} // End ReadsModeReg = 0, mayRaiseFPException = 0




//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//

// V_ICMPIntrinsic Pattern.
// V_ICMPIntrinsic Pattern.

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith()
// We need to use COPY_TO_REGCLASS to w/a the problem when ReplaceAllUsesWith()

// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.
// complaints it cannot replace i1 <-> i64/i32 if node was not morphed in place.

multiclass ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {
multiclass ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> {

▲ Show 20 Lines • Show All 709 Lines • Show Last 20 Lines
llvm/lib/Target/AMDGPU/VOPInstructions.td
//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===//
//===-- VOPInstructions.td - Vector Instruction Definitions ---------------===//

//
//

// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.

// See https://llvm.org/LICENSE.txt for license information.
// See https://llvm.org/LICENSE.txt for license information.

// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception

//
//

//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//




// dummies for outer let
// dummies for outer let

class LetDummies {
class LetDummies {

  bit ReadsModeReg;

  bit mayRaiseFPException;

  bit isCommutable;
  bit isCommutable;

  bit isConvertibleToThreeAddress;
  bit isConvertibleToThreeAddress;

  bit isMoveImm;
  bit isMoveImm;

  bit isReMaterializable;
  bit isReMaterializable;

  bit isAsCheapAsAMove;
  bit isAsCheapAsAMove;

  bit VOPAsmPrefer32Bit;
  bit VOPAsmPrefer32Bit;

  bit FPDPRounding;
  bit FPDPRounding;

  Predicate SubtargetPredicate;
  Predicate SubtargetPredicate;

Show All 11 Lines
class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :
class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> :

    InstSI <outs, ins, asm, pattern> {
    InstSI <outs, ins, asm, pattern> {




  let mayLoad = 0;
  let mayLoad = 0;

  let mayStore = 0;
  let mayStore = 0;

  let hasSideEffects = 0;
  let hasSideEffects = 0;

  let UseNamedOperandTable = 1;
  let UseNamedOperandTable = 1;

  let VALU = 1;
  let VALU = 1;

  let Uses = [EXEC];
  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);

}
}




class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins,
class VOP_Pseudo <string opName, string suffix, VOPProfile P, dag outs, dag ins,

                  string asm, list<dag> pattern> :
                  string asm, list<dag> pattern> :

  InstSI <outs, ins, asm, pattern>,
  InstSI <outs, ins, asm, pattern>,

  VOP <opName>,
  VOP <opName>,

  SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {
  SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {

  let isPseudo = 1;
  let isPseudo = 1;

▲ Show 20 Lines • Show All 66 Lines • ▼ Show 20 Linesclass VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],




  let VOP3 = 1;
  let VOP3 = 1;

  let VALU = 1;
  let VALU = 1;

  let FPClamp = P.HasFPClamp;
  let FPClamp = P.HasFPClamp;

  let IntClamp = P.HasIntClamp;
  let IntClamp = P.HasIntClamp;

  let ClampLo = P.HasClampLo;
  let ClampLo = P.HasClampLo;

  let ClampHi = P.HasClampHi;
  let ClampHi = P.HasClampHi;




  let Uses = [EXEC];
  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);



  // FIXME: Set this. Right now it seems regular IR operations don't

  // automatically imply no FP exceptions.

  // let mayRaiseFPException = ReadsModeReg;

  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);




  let AsmVariantName = AMDGPUAsmVariants.VOP3;
  let AsmVariantName = AMDGPUAsmVariants.VOP3;

  let AsmMatchConverter =
  let AsmMatchConverter =

    !if(isVOP3P,
    !if(isVOP3P,

        "cvtVOP3P",
        "cvtVOP3P",

        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
        !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),

            "cvtVOP3",
            "cvtVOP3",

            ""));
            ""));

▲ Show 20 Lines • Show All 355 Lines • ▼ Show 20 Linesclass VOP_SDWA_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :




  let Size = 8;
  let Size = 8;

  let mayLoad = 0;
  let mayLoad = 0;

  let mayStore = 0;
  let mayStore = 0;

  let hasSideEffects = 0;
  let hasSideEffects = 0;




  let VALU = 1;
  let VALU = 1;

  let SDWA = 1;
  let SDWA = 1;

  let Uses = [EXEC];


  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);



  // FIXME: Set this. Right now it seems regular IR operations don't

  // automatically imply no FP exceptions.

  // let mayRaiseFPException = ReadsModeReg;

  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);




  let SubtargetPredicate = HasSDWA;
  let SubtargetPredicate = HasSDWA;

  let AssemblerPredicate = HasSDWA;
  let AssemblerPredicate = HasSDWA;

  let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,
  let AsmVariantName = !if(P.HasExtSDWA, AMDGPUAsmVariants.SDWA,

                                         AMDGPUAsmVariants.Disable);
                                         AMDGPUAsmVariants.Disable);

  let DecoderNamespace = "SDWA";
  let DecoderNamespace = "SDWA";




  VOPProfile Pfl = P;
  VOPProfile Pfl = P;

▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Linesclass VOP_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :

  let mayLoad = 0;
  let mayLoad = 0;

  let mayStore = 0;
  let mayStore = 0;

  let hasSideEffects = 0;
  let hasSideEffects = 0;

  let UseNamedOperandTable = 1;
  let UseNamedOperandTable = 1;




  let VALU = 1;
  let VALU = 1;

  let DPP = 1;
  let DPP = 1;

  let Size = 8;
  let Size = 8;

  let Uses = [EXEC];


  let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);



  // FIXME: Set this. Right now it seems regular IR operations don't

  // automatically imply no FP exceptions.

  // let mayRaiseFPException = ReadsModeReg;

  let Uses = !if(ReadsModeReg, [MODE, EXEC], [EXEC]);

  let isConvergent = 1;
  let isConvergent = 1;




  string Mnemonic = OpName;
  string Mnemonic = OpName;

  string AsmOperands = P.AsmDPP;
  string AsmOperands = P.AsmDPP;




  let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");
  let AsmMatchConverter = !if(!eq(P.HasModifiers,1), "cvtDPP", "");

  let SubtargetPredicate = HasDPP;
  let SubtargetPredicate = HasDPP;

  let AssemblerPredicate = HasDPP;
  let AssemblerPredicate = HasDPP;

▲ Show 20 Lines • Show All 152 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: cos_s32_vs
    ; CHECK-LABEL: name: cos_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: cos_s32_vv
name: cos_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: cos_s32_vv
    ; CHECK-LABEL: name: cos_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_COS_F32_e64_:%[0-9]+]]:vgpr_32 = V_COS_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
Show All 11 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: cos_s16_vs
    ; CHECK-LABEL: name: cos_s16_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: cos_s16_vv
name: cos_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: cos_s16_vv
    ; CHECK-LABEL: name: cos_s16_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_COS_F16_e64_:%[0-9]+]]:vgpr_32 = V_COS_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_COS_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.cos), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: cvt_pkrtz_vsv
    ; GCN-LABEL: name: cvt_pkrtz_vsv

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: cvt_pkrtz_vvs
name: cvt_pkrtz_vvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: cvt_pkrtz_vvs
    ; GCN-LABEL: name: cvt_pkrtz_vvs

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: cvt_pkrtz_vvv
name: cvt_pkrtz_vvv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GCN-LABEL: name: cvt_pkrtz_vvv
    ; GCN-LABEL: name: cvt_pkrtz_vvv

    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN: liveins: $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_CVT_PKRTZ_F16_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1
    %2:vgpr(<2 x s16>) = G_INTRINSIC intrinsic(@llvm.amdgcn.cvt.pkrtz), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
Show All 13 Linesbody: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GCN-LABEL: name: fmad_ftz_s32_vvvv
    ; GCN-LABEL: name: fmad_ftz_s32_vvvv

    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: fmad_ftz_s32_vsvv
name: fmad_ftz_s32_vsvv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1
    liveins: $sgpr0, $vgpr0, $vgpr1




    ; GCN-LABEL: name: fmad_ftz_s32_vsvv
    ; GCN-LABEL: name: fmad_ftz_s32_vsvv

    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: fmad_ftz_s32_vvsv
name: fmad_ftz_s32_vvsv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1
    liveins: $sgpr0, $vgpr0, $vgpr1




    ; GCN-LABEL: name: fmad_ftz_s32_vvsv
    ; GCN-LABEL: name: fmad_ftz_s32_vvsv

    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: fmad_ftz_s32_vvvs
name: fmad_ftz_s32_vvvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1
    liveins: $sgpr0, $vgpr0, $vgpr1




    ; GCN-LABEL: name: fmad_ftz_s32_vvvs
    ; GCN-LABEL: name: fmad_ftz_s32_vvvs

    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
    ; GCN: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY3]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:sgpr(s32) = COPY $sgpr0
    %2:sgpr(s32) = COPY $sgpr0

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...







# Same SGPR used, so doesn't violate the constant bus restriction.
# Same SGPR used, so doesn't violate the constant bus restriction.

---
---

name: fmad_ftz_s32_vssv
name: fmad_ftz_s32_vssv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmad_ftz_s32_vssv
    ; GCN-LABEL: name: fmad_ftz_s32_vssv

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %1
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fmad_ftz_s32_vsvs
name: fmad_ftz_s32_vsvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmad_ftz_s32_vsvs
    ; GCN-LABEL: name: fmad_ftz_s32_vsvs

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %0

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fmad_ftz_s32_vvss
name: fmad_ftz_s32_vvss

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmad_ftz_s32_vvss
    ; GCN-LABEL: name: fmad_ftz_s32_vvss

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %1, %0, %0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %1, %0, %0

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fmad_ftz_s32_vsss
name: fmad_ftz_s32_vsss

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmad_ftz_s32_vsss
    ; GCN-LABEL: name: fmad_ftz_s32_vsss

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %0, %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...







# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.
# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.

Show All 24 Linesbody: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GCN-LABEL: name: fmad_ftz_s32_vvv_fneg_v
    ; GCN-LABEL: name: fmad_ftz_s32_vvv_fneg_v

    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GCN: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %2
    %3:vgpr(s32) = G_FNEG %2

    %4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %3
    %4:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmad.ftz), %0, %1, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
Show All 10 Linesbody: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GCN-LABEL: name: fmed3_s32_vvvv
    ; GCN-LABEL: name: fmed3_s32_vvvv

    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: fmed3_s32_vsvv
name: fmed3_s32_vsvv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1
    liveins: $sgpr0, $vgpr0, $vgpr1




    ; GCN-LABEL: name: fmed3_s32_vsvv
    ; GCN-LABEL: name: fmed3_s32_vsvv

    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: fmed3_s32_vvsv
name: fmed3_s32_vvsv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1
    liveins: $sgpr0, $vgpr0, $vgpr1




    ; GCN-LABEL: name: fmed3_s32_vvsv
    ; GCN-LABEL: name: fmed3_s32_vvsv

    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: fmed3_s32_vvvs
name: fmed3_s32_vvvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1
    liveins: $sgpr0, $vgpr0, $vgpr1




    ; GCN-LABEL: name: fmed3_s32_vvvs
    ; GCN-LABEL: name: fmed3_s32_vvvs

    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:sgpr(s32) = COPY $sgpr0
    %2:sgpr(s32) = COPY $sgpr0

    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2
    %3:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...







# Same SGPR used, so doesn't violate the constant bus restriction.
# Same SGPR used, so doesn't violate the constant bus restriction.

---
---

name: fmed3_s32_vssv
name: fmed3_s32_vssv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmed3_s32_vssv
    ; GCN-LABEL: name: fmed3_s32_vssv

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fmed3_s32_vsvs
name: fmed3_s32_vsvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmed3_s32_vsvs
    ; GCN-LABEL: name: fmed3_s32_vsvs

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %1, %0

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fmed3_s32_vvss
name: fmed3_s32_vvss

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmed3_s32_vvss
    ; GCN-LABEL: name: fmed3_s32_vvss

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY1]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %1, %0, %0

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fmed3_s32_vsss
name: fmed3_s32_vsss

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0




    ; GCN-LABEL: name: fmed3_s32_vsss
    ; GCN-LABEL: name: fmed3_s32_vsss

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F32_:%[0-9]+]]:vgpr_32 = V_MED3_F32 0, [[COPY]], 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0, %0, %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...







# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.
# FIXME: This should probably have been fixed by RegBankSelect, but we should fail to select it.

Show All 16 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
Show All 15 Linesbody: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GCN-LABEL: name: fmed3_s16_vvvv
    ; GCN-LABEL: name: fmed3_s16_vvvv

    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2
    ; GCN: liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s16) = G_TRUNC %0
    %3:vgpr(s16) = G_TRUNC %0

    %4:vgpr(s16) = G_TRUNC %1
    %4:vgpr(s16) = G_TRUNC %1

    %5:vgpr(s16) = G_TRUNC %2
    %5:vgpr(s16) = G_TRUNC %2

    %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
    %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5

Show All 10 Linesbody: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1
    liveins: $sgpr0, $vgpr0, $vgpr1




    ; GCN-LABEL: name: fmed3_s16_vsvv
    ; GCN-LABEL: name: fmed3_s16_vsvv

    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1
    ; GCN: liveins: $sgpr0, $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MED3_F16_:%[0-9]+]]:vgpr_32 = V_MED3_F16 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]
    ; GCN: S_ENDPGM 0, implicit [[V_MED3_F16_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:sgpr(s16) = G_TRUNC %0
    %3:sgpr(s16) = G_TRUNC %0

    %4:vgpr(s16) = G_TRUNC %1
    %4:vgpr(s16) = G_TRUNC %1

    %5:vgpr(s16) = G_TRUNC %2
    %5:vgpr(s16) = G_TRUNC %2

    %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5
    %6:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %3, %4, %5

    S_ENDPGM 0, implicit %6
    S_ENDPGM 0, implicit %6

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: fract_s32_vs
    ; CHECK-LABEL: name: fract_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: fract_s32_vv
name: fract_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: fract_s32_vv
    ; CHECK-LABEL: name: fract_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FRACT_F32_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: fract_s64_vs
name: fract_s64_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1




    ; CHECK-LABEL: name: fract_s64_vs
    ; CHECK-LABEL: name: fract_s64_vs

    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: fract_s64_vv
name: fract_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; CHECK-LABEL: name: fract_s64_vv
    ; CHECK-LABEL: name: fract_s64_vv

    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: liveins: $vgpr0_vgpr1

    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FRACT_F64_e64_:%[0-9]+]]:vreg_64 = V_FRACT_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0
    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s




# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1:sgpr(s16) (in function: fract_s16_vs)
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1:sgpr(s16) (in function: fract_s16_vs)

# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1:vgpr(s16) (in function: fract_s16_vv)
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1:vgpr(s16) (in function: fract_s16_vv)




---



name: fract_s16_vs
name: fract_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: fract_s16_vs
    ; CHECK-LABEL: name: fract_s16_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fract_s16_vv
name: fract_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: fract_s16_vv
    ; CHECK-LABEL: name: fract_s16_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FRACT_F16_e64_:%[0-9]+]]:vgpr_32 = V_FRACT_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_FRACT_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.fract), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o -  | FileCheck -check-prefix=GCN %s




---
---

name: ldexp_s32_vsv
name: ldexp_s32_vsv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: ldexp_s32_vsv
    ; GCN-LABEL: name: ldexp_s32_vsv

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: ldexp_s32_vvs
name: ldexp_s32_vvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: ldexp_s32_vvs
    ; GCN-LABEL: name: ldexp_s32_vvs

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: ldexp_s32_vvv
name: ldexp_s32_vvv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GCN-LABEL: name: ldexp_s32_vvv
    ; GCN-LABEL: name: ldexp_s32_vvv

    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN: liveins: $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
    %2:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: ldexp_s64_vsv
name: ldexp_s64_vsv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $vgpr0
    liveins: $sgpr0_sgpr1, $vgpr0

    ; GCN-LABEL: name: ldexp_s64_vsv
    ; GCN-LABEL: name: ldexp_s64_vsv

    ; GCN: liveins: $sgpr0_sgpr1, $vgpr0
    ; GCN: liveins: $sgpr0_sgpr1, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
    %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: ldexp_s64_vvs
name: ldexp_s64_vvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $vgpr0
    liveins: $sgpr0_sgpr1, $vgpr0

    ; GCN-LABEL: name: ldexp_s64_vvs
    ; GCN-LABEL: name: ldexp_s64_vvs

    ; GCN: liveins: $sgpr0_sgpr1, $vgpr0
    ; GCN: liveins: $sgpr0_sgpr1, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
    %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: ldexp_s64_vvv
name: ldexp_s64_vvv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2
    liveins: $vgpr0_vgpr1, $vgpr2

    ; GCN-LABEL: name: ldexp_s64_vvv
    ; GCN-LABEL: name: ldexp_s64_vvv

    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2
    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2

    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F64_:%[0-9]+]]:vreg_64 = V_LDEXP_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s32) = COPY $vgpr2
    %1:vgpr(s32) = COPY $vgpr2

    %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1
    %2:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir
Show All 13 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: ldexp_s16_vsv
    ; GCN-LABEL: name: ldexp_s16_vsv

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:sgpr(s16) = G_TRUNC %0
    %2:sgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
    %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: ldexp_s16_vvs
name: ldexp_s16_vvs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: ldexp_s16_vvs
    ; GCN-LABEL: name: ldexp_s16_vvs

    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN: liveins: $sgpr0, $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
    %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




---
---

name: ldexp_s16_vvv
name: ldexp_s16_vvv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GCN-LABEL: name: ldexp_s16_vvv
    ; GCN-LABEL: name: ldexp_s16_vvv

    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN: liveins: $vgpr0, $vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_LDEXP_F16_e64_:%[0-9]+]]:vgpr_32 = V_LDEXP_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]
    ; GCN: S_ENDPGM 0, implicit [[V_LDEXP_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1
    %3:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.ldexp), %2, %1

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
Show All 14 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: rcp_legacy_s32_vs
    ; CHECK-LABEL: name: rcp_legacy_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rcp_legacy_s32_vv
name: rcp_legacy_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: rcp_legacy_s32_vv
    ; CHECK-LABEL: name: rcp_legacy_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_LEGACY_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: rcp_s32_vs
    ; CHECK-LABEL: name: rcp_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rcp_s32_vv
name: rcp_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: rcp_s32_vv
    ; CHECK-LABEL: name: rcp_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rcp_s64_vs
name: rcp_s64_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1




    ; CHECK-LABEL: name: rcp_s64_vs
    ; CHECK-LABEL: name: rcp_s64_vs

    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rcp_s64_vv
name: rcp_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; CHECK-LABEL: name: rcp_s64_vv
    ; CHECK-LABEL: name: rcp_s64_vv

    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: liveins: $vgpr0_vgpr1

    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_F64_e64_:%[0-9]+]]:vreg_64 = V_RCP_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0
    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*'  %s -o /dev/null 2>&1 | FileCheck -check-prefix=SI-ERR %s




# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1:sgpr(s16) (in function: rcp_s16_vs)
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1:sgpr(s16) (in function: rcp_s16_vs)

# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1:vgpr(s16) (in function: rcp_s16_vv)
# SI-ERR: remark: <unknown>:0:0: cannot select: %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1:vgpr(s16) (in function: rcp_s16_vv)




---

name: rcp_s16_vs
name: rcp_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: rcp_s16_vs
    ; CHECK-LABEL: name: rcp_s16_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: rcp_s16_vv
name: rcp_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: rcp_s16_vv
    ; CHECK-LABEL: name: rcp_s16_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RCP_F16_e64_:%[0-9]+]]:vgpr_32 = V_RCP_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RCP_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
Show All 14 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: rsq_clamp_s32_vs
    ; CHECK-LABEL: name: rsq_clamp_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rsq_clamp_s32_vv
name: rsq_clamp_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: rsq_clamp_s32_vv
    ; CHECK-LABEL: name: rsq_clamp_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_CLAMP_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_CLAMP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_CLAMP_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
Show All 14 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: rsq_legacy_s32_vs
    ; CHECK-LABEL: name: rsq_legacy_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rsq_legacy_s32_vv
name: rsq_legacy_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: rsq_legacy_s32_vv
    ; CHECK-LABEL: name: rsq_legacy_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_LEGACY_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_LEGACY_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_LEGACY_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.legacy), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: rsq_s32_vs
    ; CHECK-LABEL: name: rsq_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rsq_s32_vv
name: rsq_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: rsq_s32_vv
    ; CHECK-LABEL: name: rsq_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_F32_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rsq_s64_vs
name: rsq_s64_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1




    ; CHECK-LABEL: name: rsq_s64_vs
    ; CHECK-LABEL: name: rsq_s64_vs

    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; CHECK: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: rsq_s64_vv
name: rsq_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; CHECK-LABEL: name: rsq_s64_vv
    ; CHECK-LABEL: name: rsq_s64_vv

    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: liveins: $vgpr0_vgpr1

    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; CHECK: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_F64_e64_:%[0-9]+]]:vreg_64 = V_RSQ_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0
    %1:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
Show All 11 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: rsq_s16_vs
    ; CHECK-LABEL: name: rsq_s16_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: rsq_s16_vv
name: rsq_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: rsq_s16_vv
    ; CHECK-LABEL: name: rsq_s16_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_RSQ_F16_e64_:%[0-9]+]]:vgpr_32 = V_RSQ_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_RSQ_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: sin_s32_vs
    ; CHECK-LABEL: name: sin_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: sin_s32_vv
name: sin_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: sin_s32_vv
    ; CHECK-LABEL: name: sin_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_SIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0
    %1:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
Show All 11 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: sin_s16_vs
    ; CHECK-LABEL: name: sin_s16_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: sin_s16_vv
name: sin_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: sin_s16_vv
    ; CHECK-LABEL: name: sin_s16_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_SIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_SIN_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_SIN_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1
    %2:vgpr(s16) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s




---
---




name:            fadd_s16_vvv
name:            fadd_s16_vvv

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: fadd_s16_vvv
    ; GFX8-LABEL: name: fadd_s16_vvv

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FADD %2, %3
    %4:vgpr(s16) = G_FADD %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fadd_s16_vsv
name:            fadd_s16_vsv

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0
    liveins: $vgpr0, $sgpr0

    ; GFX8-LABEL: name: fadd_s16_vsv
    ; GFX8-LABEL: name: fadd_s16_vsv

    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:sgpr(s16) = G_TRUNC %0
    %2:sgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FADD %2, %3
    %4:vgpr(s16) = G_FADD %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fadd_s16_vvs
name:            fadd_s16_vvs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0
    liveins: $vgpr0, $sgpr0

    ; GFX8-LABEL: name: fadd_s16_vvs
    ; GFX8-LABEL: name: fadd_s16_vvs

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:sgpr(s16) = G_TRUNC %1
    %3:sgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FADD %2, %3
    %4:vgpr(s16) = G_FADD %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fadd_s16_vvv_fabs_lhs
name:            fadd_s16_vvv_fabs_lhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: fadd_s16_vvv_fabs_lhs
    ; GFX8-LABEL: name: fadd_s16_vvv_fabs_lhs

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FABS %2
    %4:vgpr(s16) = G_FABS %2

    %5:vgpr(s16) = G_FADD %4, %3
    %5:vgpr(s16) = G_FADD %4, %3

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5




...
...




---
---




name:            fadd_s16_vvv_fabs_rhs
name:            fadd_s16_vvv_fabs_rhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: fadd_s16_vvv_fabs_rhs
    ; GFX8-LABEL: name: fadd_s16_vvv_fabs_rhs

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 2, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 2, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FABS %3
    %4:vgpr(s16) = G_FABS %3

    %5:vgpr(s16) = G_FADD %2, %4
    %5:vgpr(s16) = G_FADD %2, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5




...
...




---
---




name:            fadd_s16_vvv_fneg_fabs_lhs
name:            fadd_s16_vvv_fneg_fabs_lhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_lhs
    ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_lhs

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FABS %2
    %4:vgpr(s16) = G_FABS %2

    %5:vgpr(s16) = G_FNEG %4
    %5:vgpr(s16) = G_FNEG %4

    %6:vgpr(s16) = G_FADD %5, %3
    %6:vgpr(s16) = G_FADD %5, %3

    S_ENDPGM 0, implicit %6
    S_ENDPGM 0, implicit %6




...
...




---
---




name:            fadd_s16_vvv_fneg_fabs_rhs
name:            fadd_s16_vvv_fneg_fabs_rhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_rhs
    ; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_rhs

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FABS %3
    %4:vgpr(s16) = G_FABS %3

    %5:vgpr(s16) = G_FNEG %4
    %5:vgpr(s16) = G_FNEG %4

    %6:vgpr(s16) = G_FADD %2, %5
    %6:vgpr(s16) = G_FADD %2, %5

    S_ENDPGM 0, implicit %6
    S_ENDPGM 0, implicit %6




...
...




---
---




name:            fadd_s16_fneg_copy_sgpr
name:            fadd_s16_fneg_copy_sgpr

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0
    liveins: $vgpr0, $sgpr0

    ; GFX8-LABEL: name: fadd_s16_fneg_copy_sgpr
    ; GFX8-LABEL: name: fadd_s16_fneg_copy_sgpr

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
    ; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:sgpr(s16) = G_TRUNC %1
    %3:sgpr(s16) = G_TRUNC %1

    %4:sgpr(s16) = G_FNEG %3
    %4:sgpr(s16) = G_FNEG %3

    %5:vgpr(s16) = G_FADD %2, %4
    %5:vgpr(s16) = G_FADD %2, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5




...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s




---
---




name:            fadd_s32_vvv
name:            fadd_s32_vvv

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: fadd_s32_vvv
    ; GFX6-LABEL: name: fadd_s32_vvv

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = G_FADD %0, %1
    %2:vgpr(s32) = G_FADD %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2




...
...




---
---




name:            fadd_s32_vsv
name:            fadd_s32_vsv

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0
    liveins: $vgpr0, $sgpr0

    ; GFX6-LABEL: name: fadd_s32_vsv
    ; GFX6-LABEL: name: fadd_s32_vsv

    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = G_FADD %0, %1
    %2:vgpr(s32) = G_FADD %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2




...
...




---
---




name:            fadd_s32_vvs
name:            fadd_s32_vvs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0
    liveins: $vgpr0, $sgpr0

    ; GFX6-LABEL: name: fadd_s32_vvs
    ; GFX6-LABEL: name: fadd_s32_vvs

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:vgpr(s32) = G_FADD %0, %1
    %2:vgpr(s32) = G_FADD %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2




...
...




---
---




name:            fadd_s32_vvv_fabs_lhs
name:            fadd_s32_vvv_fabs_lhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs
    ; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = G_FABS %0
    %2:vgpr(s32) = G_FABS %0

    %3:vgpr(s32) = G_FADD %2, %1
    %3:vgpr(s32) = G_FADD %2, %1

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3




...
...




---
---




name:            fadd_s32_vvv_fabs_rhs
name:            fadd_s32_vvv_fabs_rhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs
    ; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = G_FABS %1
    %2:vgpr(s32) = G_FABS %1

    %3:vgpr(s32) = G_FADD %1, %2
    %3:vgpr(s32) = G_FADD %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3




...
...




---
---




name:            fadd_s32_vvv_fneg_fabs_lhs
name:            fadd_s32_vvv_fneg_fabs_lhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs
    ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = G_FABS %0
    %2:vgpr(s32) = G_FABS %0

    %3:vgpr(s32) = G_FNEG %2
    %3:vgpr(s32) = G_FNEG %2

    %4:vgpr(s32) = G_FADD %3, %1
    %4:vgpr(s32) = G_FADD %3, %1

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fadd_s32_vvv_fneg_fabs_rhs
name:            fadd_s32_vvv_fneg_fabs_rhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs
    ; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = G_FABS %1
    %2:vgpr(s32) = G_FABS %1

    %3:vgpr(s32) = G_FNEG %2
    %3:vgpr(s32) = G_FNEG %2

    %4:vgpr(s32) = G_FADD %1, %3
    %4:vgpr(s32) = G_FADD %1, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




# Need to look through reg bank copy to find source modifiers
# Need to look through reg bank copy to find source modifiers

---
---




name:            fadd_s32_fneg_copy_sgpr
name:            fadd_s32_fneg_copy_sgpr

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0
    liveins: $vgpr0, $sgpr0

    ; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
    ; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:sgpr(s32) = G_FNEG %1
    %2:sgpr(s32) = G_FNEG %1

    %3:vgpr(s32) = COPY %2
    %3:vgpr(s32) = COPY %2

    %4:vgpr(s32) = G_FADD %0, %3
    %4:vgpr(s32) = G_FADD %0, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




# Need to look through copy in between fneg and fabs
# Need to look through copy in between fneg and fabs




---
---




name:            fadd_s32_copy_fneg_copy_fabs
name:            fadd_s32_copy_fneg_copy_fabs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0
    liveins: $vgpr0, $sgpr0

    ; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
    ; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr0

    %2:sgpr(s32) = G_FABS %1
    %2:sgpr(s32) = G_FABS %1

    %3:sgpr(s32) = COPY %2
    %3:sgpr(s32) = COPY %2

    %4:sgpr(s32) = G_FNEG %3
    %4:sgpr(s32) = G_FNEG %3

    %5:sgpr(s32) = COPY %4
    %5:sgpr(s32) = COPY %4

    %6:vgpr(s32) = G_FADD %0, %5
    %6:vgpr(s32) = G_FADD %0, %5

Show All 14 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

    ; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
    ; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

    ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
    ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s32) = COPY $sgpr1
    %1:sgpr(s32) = COPY $sgpr1

    %2:sgpr(s32) = G_FABS %0
    %2:sgpr(s32) = G_FABS %0

    %3:sgpr(s32) = G_FABS %1
    %3:sgpr(s32) = G_FABS %1

    %4:vgpr(s32) = COPY %2
    %4:vgpr(s32) = COPY %2

    %5:vgpr(s32) = COPY %3
    %5:vgpr(s32) = COPY %3

    %6:vgpr(s32) = G_FADD %4, %5
    %6:vgpr(s32) = G_FADD %4, %5

Show All 10 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

    ; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
    ; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

    ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
    ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s32) = COPY $sgpr1
    %1:sgpr(s32) = COPY $sgpr1

    %2:sgpr(s32) = G_FNEG %0
    %2:sgpr(s32) = G_FNEG %0

    %3:sgpr(s32) = G_FNEG %1
    %3:sgpr(s32) = G_FNEG %1

    %4:vgpr(s32) = COPY %2
    %4:vgpr(s32) = COPY %2

    %5:vgpr(s32) = COPY %3
    %5:vgpr(s32) = COPY %3

    %6:vgpr(s32) = G_FADD %4, %5
    %6:vgpr(s32) = G_FADD %4, %5

Show All 10 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

    ; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
    ; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]

    ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
    ; GFX6: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s32) = COPY $sgpr1
    %1:sgpr(s32) = COPY $sgpr1

    %2:sgpr(s32) = G_FABS %0
    %2:sgpr(s32) = G_FABS %0

    %3:sgpr(s32) = G_FABS %1
    %3:sgpr(s32) = G_FABS %1

    %4:sgpr(s32) = G_FNEG %2
    %4:sgpr(s32) = G_FNEG %2

    %5:sgpr(s32) = G_FNEG %3
    %5:sgpr(s32) = G_FNEG %3

    %6:vgpr(s32) = COPY %4
    %6:vgpr(s32) = COPY %4

    %7:vgpr(s32) = COPY %5
    %7:vgpr(s32) = COPY %5

    %8:vgpr(s32) = G_FADD %6, %7
    %8:vgpr(s32) = G_FADD %6, %7

    S_ENDPGM 0, implicit %8
    S_ENDPGM 0, implicit %8




...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s




---
---




name:            fadd_s64_vvv
name:            fadd_s64_vvv

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; GFX6-LABEL: name: fadd_s64_vvv
    ; GFX6-LABEL: name: fadd_s64_vvv

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vgpr(s64) = G_FADD %0, %1
    %2:vgpr(s64) = G_FADD %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2




...
...




---
---




name:            fadd_s64_vsv
name:            fadd_s64_vsv

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
    liveins: $vgpr0_vgpr1, $sgpr0_sgpr1

    ; GFX6-LABEL: name: fadd_s64_vsv
    ; GFX6-LABEL: name: fadd_s64_vsv

    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s64) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = COPY $vgpr0_vgpr1

    %2:vgpr(s64) = G_FADD %0, %1
    %2:vgpr(s64) = G_FADD %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2




...
...




---
---




name:            fadd_s64_vvs
name:            fadd_s64_vvs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
    liveins: $vgpr0_vgpr1, $sgpr0_sgpr1

    ; GFX6-LABEL: name: fadd_s64_vvs
    ; GFX6-LABEL: name: fadd_s64_vvs

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:sgpr(s64) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = COPY $sgpr0_sgpr1

    %2:vgpr(s64) = G_FADD %0, %1
    %2:vgpr(s64) = G_FADD %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2




...
...




---
---




name:            fadd_s64_vvv_fabs_lhs
name:            fadd_s64_vvv_fabs_lhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; GFX6-LABEL: name: fadd_s64_vvv_fabs_lhs
    ; GFX6-LABEL: name: fadd_s64_vvv_fabs_lhs

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vgpr(s64) = G_FABS %0
    %2:vgpr(s64) = G_FABS %0

    %3:vgpr(s64) = G_FADD %2, %1
    %3:vgpr(s64) = G_FADD %2, %1

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3




...
...




---
---




name:            fadd_s64_vvv_fabs_rhs
name:            fadd_s64_vvv_fabs_rhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; GFX6-LABEL: name: fadd_s64_vvv_fabs_rhs
    ; GFX6-LABEL: name: fadd_s64_vvv_fabs_rhs

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vgpr(s64) = G_FABS %1
    %2:vgpr(s64) = G_FABS %1

    %3:vgpr(s64) = G_FADD %1, %2
    %3:vgpr(s64) = G_FADD %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3




...
...




---
---




name:            fadd_s64_vvv_fneg_fabs_lhs
name:            fadd_s64_vvv_fneg_fabs_lhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_lhs
    ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_lhs

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vgpr(s64) = G_FABS %0
    %2:vgpr(s64) = G_FABS %0

    %3:vgpr(s64) = G_FNEG %2
    %3:vgpr(s64) = G_FNEG %2

    %4:vgpr(s64) = G_FADD %3, %1
    %4:vgpr(s64) = G_FADD %3, %1

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fadd_s64_vvv_fneg_fabs_rhs
name:            fadd_s64_vvv_fneg_fabs_rhs

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_rhs
    ; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_rhs

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = COPY $vgpr0_vgpr1

    %2:vgpr(s64) = G_FABS %1
    %2:vgpr(s64) = G_FABS %1

    %3:vgpr(s64) = G_FNEG %2
    %3:vgpr(s64) = G_FNEG %2

    %4:vgpr(s64) = G_FADD %1, %3
    %4:vgpr(s64) = G_FADD %1, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
    liveins: $vgpr0_vgpr1, $sgpr0_sgpr1

    ; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr
    ; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:sgpr(s64) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = COPY $sgpr0_sgpr1

    %2:sgpr(s64) = G_FNEG %1
    %2:sgpr(s64) = G_FNEG %1

    %3:vgpr(s64) = COPY %2
    %3:vgpr(s64) = COPY %2

    %4:vgpr(s64) = G_FADD %0, %3
    %4:vgpr(s64) = G_FADD %0, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




Show All 12 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3

    ; GFX6-LABEL: name: fadd_s64_copy_fabs_sgpr_copy_fabs_sgpr
    ; GFX6-LABEL: name: fadd_s64_copy_fabs_sgpr_copy_fabs_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3

    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]

    ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
    ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:sgpr(s64) = COPY $sgpr2_sgpr3
    %1:sgpr(s64) = COPY $sgpr2_sgpr3

    %2:sgpr(s64) = G_FABS %0
    %2:sgpr(s64) = G_FABS %0

    %3:sgpr(s64) = G_FABS %1
    %3:sgpr(s64) = G_FABS %1

    %4:vgpr(s64) = COPY %2
    %4:vgpr(s64) = COPY %2

    %5:vgpr(s64) = COPY %3
    %5:vgpr(s64) = COPY %3

    %6:vgpr(s64) = G_FADD %4, %5
    %6:vgpr(s64) = G_FADD %4, %5

Show All 10 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

    ; GFX6-LABEL: name: fadd_s64_copy_fneg_sgpr_copy_fneg_sgpr
    ; GFX6-LABEL: name: fadd_s64_copy_fneg_sgpr_copy_fneg_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3

    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]

    ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
    ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:sgpr(s64) = COPY $sgpr2_sgpr3
    %1:sgpr(s64) = COPY $sgpr2_sgpr3

    %2:sgpr(s64) = G_FNEG %0
    %2:sgpr(s64) = G_FNEG %0

    %3:sgpr(s64) = G_FNEG %1
    %3:sgpr(s64) = G_FNEG %1

    %4:vgpr(s64) = COPY %2
    %4:vgpr(s64) = COPY %2

    %5:vgpr(s64) = COPY %3
    %5:vgpr(s64) = COPY %3

    %6:vgpr(s64) = G_FADD %4, %5
    %6:vgpr(s64) = G_FADD %4, %5

Show All 10 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1

    ; GFX6-LABEL: name: fadd_s64_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
    ; GFX6-LABEL: name: fadd_s64_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr

    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3

    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]
    ; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[COPY]]

    ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]
    ; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[COPY1]]

    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $exec
    ; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:sgpr(s64) = COPY $sgpr2_sgpr3
    %1:sgpr(s64) = COPY $sgpr2_sgpr3

    %2:sgpr(s64) = G_FABS %0
    %2:sgpr(s64) = G_FABS %0

    %3:sgpr(s64) = G_FABS %1
    %3:sgpr(s64) = G_FABS %1

    %4:sgpr(s64) = G_FNEG %2
    %4:sgpr(s64) = G_FNEG %2

    %5:sgpr(s64) = G_FNEG %3
    %5:sgpr(s64) = G_FNEG %3

    %6:vgpr(s64) = COPY %4
    %6:vgpr(s64) = COPY %4

    %7:vgpr(s64) = COPY %5
    %7:vgpr(s64) = COPY %5

    %8:vgpr(s64) = G_FADD %6, %7
    %8:vgpr(s64) = G_FADD %6, %7

    S_ENDPGM 0, implicit %8
    S_ENDPGM 0, implicit %8




...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
Show All 11 Lines  mode:

    fp64-fp16-input-denormals: true
    fp64-fp16-input-denormals: true

    fp64-fp16-output-denormals: true
    fp64-fp16-output-denormals: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_f16_denorm
    ; GFX8-LABEL: name: fcanonicalize_f16_denorm

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_f16_denorm
    ; GFX9-LABEL: name: fcanonicalize_f16_denorm

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FCANONICALIZE %1
    %2:vgpr(s16) = G_FCANONICALIZE %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---




name:            fcanonicalize_f16_flush
name:            fcanonicalize_f16_flush

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp64-fp16-input-denormals: false
    fp64-fp16-input-denormals: false

    fp64-fp16-output-denormals: false
    fp64-fp16-output-denormals: false




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_f16_flush
    ; GFX8-LABEL: name: fcanonicalize_f16_flush

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, 15360, 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, 15360, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_f16_flush
    ; GFX9-LABEL: name: fcanonicalize_f16_flush

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FCANONICALIZE %1
    %2:vgpr(s16) = G_FCANONICALIZE %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---




name:            fcanonicalize_f32_denorm
name:            fcanonicalize_f32_denorm

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp32-input-denormals: true
    fp32-input-denormals: true

    fp32-output-denormals: true
    fp32-output-denormals: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GFX8-LABEL: name: fcanonicalize_f32_denorm
    ; GFX8-LABEL: name: fcanonicalize_f32_denorm

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_f32_denorm
    ; GFX9-LABEL: name: fcanonicalize_f32_denorm

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FCANONICALIZE %0
    %1:vgpr(s32) = G_FCANONICALIZE %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---




name:            fcanonicalize_f32_flush
name:            fcanonicalize_f32_flush

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp32-input-denormals: false
    fp32-input-denormals: false

    fp32-output-denormals: false
    fp32-output-denormals: false




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GFX8-LABEL: name: fcanonicalize_f32_flush
    ; GFX8-LABEL: name: fcanonicalize_f32_flush

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_f32_flush
    ; GFX9-LABEL: name: fcanonicalize_f32_flush

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FCANONICALIZE %0
    %1:vgpr(s32) = G_FCANONICALIZE %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---




name:            fcanonicalize_v2f16_denorm
name:            fcanonicalize_v2f16_denorm

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp64-fp16-input-denormals: true
    fp64-fp16-input-denormals: true

    fp64-fp16-output-denormals: true
    fp64-fp16-output-denormals: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GFX8-LABEL: name: fcanonicalize_v2f16_denorm
    ; GFX8-LABEL: name: fcanonicalize_v2f16_denorm

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX8: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]

    ; GFX9-LABEL: name: fcanonicalize_v2f16_denorm
    ; GFX9-LABEL: name: fcanonicalize_v2f16_denorm

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0
    %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---




name:            fcanonicalize_v2f16_flush
name:            fcanonicalize_v2f16_flush

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp64-fp16-input-denormals: false
    fp64-fp16-input-denormals: false

    fp64-fp16-output-denormals: false
    fp64-fp16-output-denormals: false




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GFX8-LABEL: name: fcanonicalize_v2f16_flush
    ; GFX8-LABEL: name: fcanonicalize_v2f16_flush

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 0, 15360, 8, [[COPY]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX8: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 0, 15360, 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]

    ; GFX9-LABEL: name: fcanonicalize_v2f16_flush
    ; GFX9-LABEL: name: fcanonicalize_v2f16_flush

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0
    %1:vgpr(<2 x s16>) = G_FCANONICALIZE %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---




name:            fcanonicalize_f64_denorm
name:            fcanonicalize_f64_denorm

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp64-fp16-input-denormals: true
    fp64-fp16-input-denormals: true

    fp64-fp16-output-denormals: true
    fp64-fp16-output-denormals: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; GFX8-LABEL: name: fcanonicalize_f64_denorm
    ; GFX8-LABEL: name: fcanonicalize_f64_denorm

    ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX8: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MAX_F64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MAX_F64_]]

    ; GFX9-LABEL: name: fcanonicalize_f64_denorm
    ; GFX9-LABEL: name: fcanonicalize_f64_denorm

    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX9: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_FCANONICALIZE %0
    %1:vgpr(s64) = G_FCANONICALIZE %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---




name:            fcanonicalize_f64_flush
name:            fcanonicalize_f64_flush

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp64-fp16-input-denormals: false
    fp64-fp16-input-denormals: false

    fp64-fp16-output-denormals: false
    fp64-fp16-output-denormals: false




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; GFX8-LABEL: name: fcanonicalize_f64_flush
    ; GFX8-LABEL: name: fcanonicalize_f64_flush

    ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX8: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, 4607182418800017408, 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, 4607182418800017408, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F64_]]

    ; GFX9-LABEL: name: fcanonicalize_f64_flush
    ; GFX9-LABEL: name: fcanonicalize_f64_flush

    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GFX9: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_FCANONICALIZE %0
    %1:vgpr(s64) = G_FCANONICALIZE %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---




name:            fcanonicalize_fabs_f32_denorm
name:            fcanonicalize_fabs_f32_denorm

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp32-input-denormals: true
    fp32-input-denormals: true

    fp32-output-denormals: true
    fp32-output-denormals: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_fabs_f32_denorm
    ; GFX8-LABEL: name: fcanonicalize_fabs_f32_denorm

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_fabs_f32_denorm
    ; GFX9-LABEL: name: fcanonicalize_fabs_f32_denorm

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FABS %0
    %1:vgpr(s32) = G_FABS %0

    %2:vgpr(s32) = G_FCANONICALIZE %1
    %2:vgpr(s32) = G_FCANONICALIZE %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...







---
---




name:            fcanonicalize_fabs_f32_flush
name:            fcanonicalize_fabs_f32_flush

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp32-input-denormals: false
    fp32-input-denormals: false

    fp32-output-denormals: false
    fp32-output-denormals: false




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_fabs_f32_flush
    ; GFX8-LABEL: name: fcanonicalize_fabs_f32_flush

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_fabs_f32_flush
    ; GFX9-LABEL: name: fcanonicalize_fabs_f32_flush

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FABS %0
    %1:vgpr(s32) = G_FABS %0

    %2:vgpr(s32) = G_FCANONICALIZE %1
    %2:vgpr(s32) = G_FCANONICALIZE %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---




name:            fcanonicalize_fneg_f32_denorm
name:            fcanonicalize_fneg_f32_denorm

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp32-input-denormals: true
    fp32-input-denormals: true

    fp32-output-denormals: true
    fp32-output-denormals: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_fneg_f32_denorm
    ; GFX8-LABEL: name: fcanonicalize_fneg_f32_denorm

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_fneg_f32_denorm
    ; GFX9-LABEL: name: fcanonicalize_fneg_f32_denorm

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FNEG %0
    %1:vgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FCANONICALIZE %1
    %2:vgpr(s32) = G_FCANONICALIZE %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---




name:            fcanonicalize_fneg_f32_flush
name:            fcanonicalize_fneg_f32_flush

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp32-input-denormals: false
    fp32-input-denormals: false

    fp32-output-denormals: false
    fp32-output-denormals: false




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_fneg_f32_flush
    ; GFX8-LABEL: name: fcanonicalize_fneg_f32_flush

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 3212836864, 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_fneg_f32_flush
    ; GFX9-LABEL: name: fcanonicalize_fneg_f32_flush

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FNEG %0
    %1:vgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FCANONICALIZE %1
    %2:vgpr(s32) = G_FCANONICALIZE %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---




name:            fcanonicalize_fneg_fabs_f32_denorm
name:            fcanonicalize_fneg_fabs_f32_denorm

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    fp32-input-denormals: true
    fp32-input-denormals: true

    fp32-output-denormals: true
    fp32-output-denormals: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm
    ; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
    ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm
    ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_denorm

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FNEG %0
    %1:vgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FABS %1
    %2:vgpr(s32) = G_FABS %1

    %3:vgpr(s32) = G_FCANONICALIZE %2
    %3:vgpr(s32) = G_FCANONICALIZE %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...




Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_flush
    ; GFX8-LABEL: name: fcanonicalize_fneg_fabs_f32_flush

    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
    ; GFX8: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX8: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec

    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
    ; GFX8: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, 1065353216, 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec

    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]
    ; GFX8: S_ENDPGM 0, implicit [[V_MUL_F32_e64_]]

    ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_flush
    ; GFX9-LABEL: name: fcanonicalize_fneg_fabs_f32_flush

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
    ; GFX9: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648

    ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GFX9: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec

    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $exec
    ; GFX9: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 2, [[V_XOR_B32_e32_]], 2, [[V_XOR_B32_e32_]], 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_MAX_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FNEG %0
    %1:vgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FABS %1
    %2:vgpr(s32) = G_FABS %1

    %3:vgpr(s32) = G_FCANONICALIZE %2
    %3:vgpr(s32) = G_FCANONICALIZE %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: fceil_s32_vv
name: fceil_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: fceil_s32_vv
    ; CHECK-LABEL: name: fceil_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_CEIL_F32_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_CEIL_F32_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_CEIL_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_CEIL_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FCEIL %0
    %1:vgpr(s32) = G_FCEIL %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: fceil_s32_vs
name: fceil_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: fceil_s32_vs
    ; CHECK-LABEL: name: fceil_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_CEIL_F32_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_CEIL_F32_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_CEIL_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_CEIL_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_FCEIL %0
    %1:vgpr(s32) = G_FCEIL %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: fceil_s64_sv
name: fceil_s64_sv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1




    ; CHECK-LABEL: name: fceil_s64_sv
    ; CHECK-LABEL: name: fceil_s64_sv

    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; CHECK: [[V_CEIL_F64_e64_:%[0-9]+]]:vreg_64 = V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_CEIL_F64_e64_:%[0-9]+]]:vreg_64 = V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0_vgpr1 = COPY [[V_CEIL_F64_e64_]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[V_CEIL_F64_e64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s64) = G_FCEIL %0
    %1:vgpr(s64) = G_FCEIL %0

    $vgpr0_vgpr1 = COPY %1
    $vgpr0_vgpr1 = COPY %1

...
...




---
---

name: fceil_s64_vv
name: fceil_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; CHECK-LABEL: name: fceil_s64_vv
    ; CHECK-LABEL: name: fceil_s64_vv

    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: liveins: $vgpr0_vgpr1

    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; CHECK: [[V_CEIL_F64_e64_:%[0-9]+]]:vreg_64 = V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_CEIL_F64_e64_:%[0-9]+]]:vreg_64 = V_CEIL_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0_vgpr1 = COPY [[V_CEIL_F64_e64_]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[V_CEIL_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_FCEIL %0
    %1:vgpr(s64) = G_FCEIL %0

    $vgpr0_vgpr1 = COPY %1
    $vgpr0_vgpr1 = COPY %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
Show All 32 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fceil_s16_vv
    ; GCN-LABEL: name: fceil_s16_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FCEIL %1
    %2:vgpr(s16) = G_FCEIL %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




---
---

name: fceil_s16_vs
name: fceil_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; GCN-LABEL: name: fceil_s16_vs
    ; GCN-LABEL: name: fceil_s16_vs

    ; GCN: liveins: $sgpr0
    ; GCN: liveins: $sgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FCEIL %1
    %2:vgpr(s16) = G_FCEIL %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




---
---

name: fceil_fneg_s16_vv
name: fceil_fneg_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fceil_fneg_s16_vv
    ; GCN-LABEL: name: fceil_fneg_s16_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CEIL_F16_e64_:%[0-9]+]]:vgpr_32 = V_CEIL_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_CEIL_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FNEG %1
    %2:vgpr(s16) = G_FNEG %1

    %3:vgpr(s16) = G_FCEIL %2
    %3:vgpr(s16) = G_FCEIL %2

    %4:vgpr(s32) = G_ANYEXT %3
    %4:vgpr(s32) = G_ANYEXT %3

    $vgpr0 = COPY %4
    $vgpr0 = COPY %4

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
Show All 31 Lines
regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_oeq_s32_vv
    ; WAVE64-LABEL: name: fcmp_oeq_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_oeq_s32_vv
    ; WAVE32-LABEL: name: fcmp_oeq_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ogt_s32_vv
name: fcmp_ogt_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ogt_s32_vv
    ; WAVE64-LABEL: name: fcmp_ogt_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_ogt_s32_vv
    ; WAVE32-LABEL: name: fcmp_ogt_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_oge_s32_vv
name: fcmp_oge_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_oge_s32_vv
    ; WAVE64-LABEL: name: fcmp_oge_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_oge_s32_vv
    ; WAVE32-LABEL: name: fcmp_oge_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_olt_s32_vv
name: fcmp_olt_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_olt_s32_vv
    ; WAVE64-LABEL: name: fcmp_olt_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_olt_s32_vv
    ; WAVE32-LABEL: name: fcmp_olt_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ole_s32_vv
name: fcmp_ole_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ole_s32_vv
    ; WAVE64-LABEL: name: fcmp_ole_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_ole_s32_vv
    ; WAVE32-LABEL: name: fcmp_ole_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_one_s32_vv
name: fcmp_one_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_one_s32_vv
    ; WAVE64-LABEL: name: fcmp_one_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_one_s32_vv
    ; WAVE32-LABEL: name: fcmp_one_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(one), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ord_s32_vv
name: fcmp_ord_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ord_s32_vv
    ; WAVE64-LABEL: name: fcmp_ord_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_ord_s32_vv
    ; WAVE32-LABEL: name: fcmp_ord_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_uno_s32_vv
name: fcmp_uno_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_uno_s32_vv
    ; WAVE64-LABEL: name: fcmp_uno_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_uno_s32_vv
    ; WAVE32-LABEL: name: fcmp_uno_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ueq_s32_vv
name: fcmp_ueq_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ueq_s32_vv
    ; WAVE64-LABEL: name: fcmp_ueq_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_ueq_s32_vv
    ; WAVE32-LABEL: name: fcmp_ueq_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ugt_s32_vv
name: fcmp_ugt_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ugt_s32_vv
    ; WAVE64-LABEL: name: fcmp_ugt_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_ugt_s32_vv
    ; WAVE32-LABEL: name: fcmp_ugt_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_uge_s32_vv
name: fcmp_uge_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_uge_s32_vv
    ; WAVE64-LABEL: name: fcmp_uge_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_uge_s32_vv
    ; WAVE32-LABEL: name: fcmp_uge_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ult_s32_vv
name: fcmp_ult_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ult_s32_vv
    ; WAVE64-LABEL: name: fcmp_ult_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_ult_s32_vv
    ; WAVE32-LABEL: name: fcmp_ult_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ule_s32_vv
name: fcmp_ule_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ule_s32_vv
    ; WAVE64-LABEL: name: fcmp_ule_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_ule_s32_vv
    ; WAVE32-LABEL: name: fcmp_ule_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_une_s32_vv
name: fcmp_une_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_une_s32_vv
    ; WAVE64-LABEL: name: fcmp_une_s32_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]

    ; WAVE32-LABEL: name: fcmp_une_s32_vv
    ; WAVE32-LABEL: name: fcmp_une_s32_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(une), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_oeq_s64_vv
    ; WAVE64-LABEL: name: fcmp_oeq_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_oeq_s64_vv
    ; WAVE32-LABEL: name: fcmp_oeq_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ogt_s64_vv
name: fcmp_ogt_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_ogt_s64_vv
    ; WAVE64-LABEL: name: fcmp_ogt_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_ogt_s64_vv
    ; WAVE32-LABEL: name: fcmp_ogt_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_oge_s64_vv
name: fcmp_oge_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_oge_s64_vv
    ; WAVE64-LABEL: name: fcmp_oge_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_oge_s64_vv
    ; WAVE32-LABEL: name: fcmp_oge_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(oge), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_olt_s64_vv
name: fcmp_olt_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_olt_s64_vv
    ; WAVE64-LABEL: name: fcmp_olt_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_olt_s64_vv
    ; WAVE32-LABEL: name: fcmp_olt_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(olt), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ole_s64_vv
name: fcmp_ole_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_ole_s64_vv
    ; WAVE64-LABEL: name: fcmp_ole_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_ole_s64_vv
    ; WAVE32-LABEL: name: fcmp_ole_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ole), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_one_s64_vv
name: fcmp_one_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_one_s64_vv
    ; WAVE64-LABEL: name: fcmp_one_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_one_s64_vv
    ; WAVE32-LABEL: name: fcmp_one_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(one), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(one), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ord_s64_vv
name: fcmp_ord_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_ord_s64_vv
    ; WAVE64-LABEL: name: fcmp_ord_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_ord_s64_vv
    ; WAVE32-LABEL: name: fcmp_ord_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ord), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_uno_s64_vv
name: fcmp_uno_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_uno_s64_vv
    ; WAVE64-LABEL: name: fcmp_uno_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_uno_s64_vv
    ; WAVE32-LABEL: name: fcmp_uno_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(uno), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ueq_s64_vv
name: fcmp_ueq_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_ueq_s64_vv
    ; WAVE64-LABEL: name: fcmp_ueq_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_ueq_s64_vv
    ; WAVE32-LABEL: name: fcmp_ueq_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ugt_s64_vv
name: fcmp_ugt_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_ugt_s64_vv
    ; WAVE64-LABEL: name: fcmp_ugt_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_ugt_s64_vv
    ; WAVE32-LABEL: name: fcmp_ugt_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_uge_s64_vv
name: fcmp_uge_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_uge_s64_vv
    ; WAVE64-LABEL: name: fcmp_uge_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_uge_s64_vv
    ; WAVE32-LABEL: name: fcmp_uge_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(uge), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ult_s64_vv
name: fcmp_ult_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_ult_s64_vv
    ; WAVE64-LABEL: name: fcmp_ult_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_ult_s64_vv
    ; WAVE32-LABEL: name: fcmp_ult_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ult), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_ule_s64_vv
name: fcmp_ule_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_ule_s64_vv
    ; WAVE64-LABEL: name: fcmp_ule_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_ule_s64_vv
    ; WAVE32-LABEL: name: fcmp_ule_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(ule), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fcmp_une_s64_vv
name: fcmp_une_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3

    ; WAVE64-LABEL: name: fcmp_une_s64_vv
    ; WAVE64-LABEL: name: fcmp_une_s64_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE64: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]

    ; WAVE32-LABEL: name: fcmp_une_s64_vv
    ; WAVE32-LABEL: name: fcmp_une_s64_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; WAVE32: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = COPY $vgpr2_vgpr3
    %1:vgpr(s64) = COPY $vgpr2_vgpr3

    %2:vcc(s1) = G_FCMP floatpred(une), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(une), %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

Show All 26 Lines
regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_oeq_s32_vv_select_user
    ; WAVE64-LABEL: name: fcmp_oeq_s32_vv_select_user

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec
    ; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]

    ; WAVE32-LABEL: name: fcmp_oeq_s32_vv_select_user
    ; WAVE32-LABEL: name: fcmp_oeq_s32_vv_select_user

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec
    ; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], [[V_CMP_EQ_F32_e64_]], implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
    %2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1

    %3:vgpr(s32) = G_SELECT %2, %0, %1
    %3:vgpr(s32) = G_SELECT %2, %0, %1

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
Show All 37 Lines
regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_oeq_s16_vv
    ; WAVE64-LABEL: name: fcmp_oeq_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_oeq_s16_vv
    ; WAVE32-LABEL: name: fcmp_oeq_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_ogt_s16_vv
name: fcmp_ogt_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ogt_s16_vv
    ; WAVE64-LABEL: name: fcmp_ogt_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_ogt_s16_vv
    ; WAVE32-LABEL: name: fcmp_ogt_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_oge_s16_vv
name: fcmp_oge_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_oge_s16_vv
    ; WAVE64-LABEL: name: fcmp_oge_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_oge_s16_vv
    ; WAVE32-LABEL: name: fcmp_oge_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(oge), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(oge), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_olt_s16_vv
name: fcmp_olt_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_olt_s16_vv
    ; WAVE64-LABEL: name: fcmp_olt_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_olt_s16_vv
    ; WAVE32-LABEL: name: fcmp_olt_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(olt), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(olt), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_ole_s16_vv
name: fcmp_ole_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ole_s16_vv
    ; WAVE64-LABEL: name: fcmp_ole_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_ole_s16_vv
    ; WAVE32-LABEL: name: fcmp_ole_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(ole), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(ole), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...

---
---

name: fcmp_one_s16_vv
name: fcmp_one_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_one_s16_vv
    ; WAVE64-LABEL: name: fcmp_one_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_one_s16_vv
    ; WAVE32-LABEL: name: fcmp_one_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(one), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_ord_s16_vv
name: fcmp_ord_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ord_s16_vv
    ; WAVE64-LABEL: name: fcmp_ord_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_ord_s16_vv
    ; WAVE32-LABEL: name: fcmp_ord_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(one), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(one), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_uno_s16_vv
name: fcmp_uno_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_uno_s16_vv
    ; WAVE64-LABEL: name: fcmp_uno_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_uno_s16_vv
    ; WAVE32-LABEL: name: fcmp_uno_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(uno), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(uno), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_ueq_s16_vv
name: fcmp_ueq_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ueq_s16_vv
    ; WAVE64-LABEL: name: fcmp_ueq_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_ueq_s16_vv
    ; WAVE32-LABEL: name: fcmp_ueq_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_ugt_s16_vv
name: fcmp_ugt_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ugt_s16_vv
    ; WAVE64-LABEL: name: fcmp_ugt_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_ugt_s16_vv
    ; WAVE32-LABEL: name: fcmp_ugt_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_uge_s16_vv
name: fcmp_uge_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_uge_s16_vv
    ; WAVE64-LABEL: name: fcmp_uge_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_uge_s16_vv
    ; WAVE32-LABEL: name: fcmp_uge_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(uge), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(uge), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_ult_s16_vv
name: fcmp_ult_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ult_s16_vv
    ; WAVE64-LABEL: name: fcmp_ult_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_ult_s16_vv
    ; WAVE32-LABEL: name: fcmp_ult_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(ult), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(ult), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_ule_s16_vv
name: fcmp_ule_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_ule_s16_vv
    ; WAVE64-LABEL: name: fcmp_ule_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_ule_s16_vv
    ; WAVE32-LABEL: name: fcmp_ule_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(ule), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(ule), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fcmp_une_s16_vv
name: fcmp_une_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1

    ; WAVE64-LABEL: name: fcmp_une_s16_vv
    ; WAVE64-LABEL: name: fcmp_une_s16_vv

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE64: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE64: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
    ; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]

    ; WAVE32-LABEL: name: fcmp_une_s16_vv
    ; WAVE32-LABEL: name: fcmp_une_s16_vv

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; WAVE32: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
    ; WAVE32: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec

    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
    ; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vcc(s1) = G_FCMP floatpred(une), %2, %3
    %4:vcc(s1) = G_FCMP floatpred(une), %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...

Show All 31 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s




---
---

name: fexp2_s32_vs
name: fexp2_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: fexp2_s32_vs
    ; CHECK-LABEL: name: fexp2_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_FEXP2 %0
    %1:vgpr(s32) = G_FEXP2 %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...




---
---

name: fexp2_s32_vv
name: fexp2_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: fexp2_s32_vv
    ; CHECK-LABEL: name: fexp2_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_EXP_F32_e64_:%[0-9]+]]:vgpr_32 = V_EXP_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_EXP_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FEXP2 %0
    %1:vgpr(s32) = G_FEXP2 %0

    S_ENDPGM 0, implicit %1
    S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
Show All 32 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; VI-LABEL: name: ffloor_s16_vv
    ; VI-LABEL: name: ffloor_s16_vv

    ; VI: liveins: $vgpr0
    ; VI: liveins: $vgpr0

    ; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]
    ; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FFLOOR %1
    %2:vgpr(s16) = G_FFLOOR %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




---
---

name: ffloor_s16_vs
name: ffloor_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; VI-LABEL: name: ffloor_s16_vs
    ; VI-LABEL: name: ffloor_s16_vs

    ; VI: liveins: $sgpr0
    ; VI: liveins: $sgpr0

    ; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]
    ; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FFLOOR %1
    %2:vgpr(s16) = G_FFLOOR %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




Show All 13 Lines  bb.0:

    ; SI: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
    ; SI: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)

    ; SI: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
    ; SI: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]

    ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]
    ; SI: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[FNEG]]

    ; SI: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FFLOOR]](s16)
    ; SI: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FFLOOR]](s16)

    ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
    ; SI: $vgpr0 = COPY [[ANYEXT]](s32)

    ; VI-LABEL: name: ffloor_fneg_s16_vv
    ; VI-LABEL: name: ffloor_fneg_s16_vv

    ; VI: liveins: $vgpr0
    ; VI: liveins: $vgpr0

    ; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 1, [[COPY]], 0, 0, implicit $exec
    ; VI: [[V_FLOOR_F16_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]
    ; VI: $vgpr0 = COPY [[V_FLOOR_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FNEG %1
    %2:vgpr(s16) = G_FNEG %1

    %3:vgpr(s16) = G_FFLOOR %2
    %3:vgpr(s16) = G_FFLOOR %2

    %4:vgpr(s32) = G_ANYEXT %3
    %4:vgpr(s32) = G_ANYEXT %3

    $vgpr0 = COPY %4
    $vgpr0 = COPY %4

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: ffloor_s32_vv
name: ffloor_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: ffloor_s32_vv
    ; CHECK-LABEL: name: ffloor_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FFLOOR %0
    %1:vgpr(s32) = G_FFLOOR %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: ffloor_s32_vs
name: ffloor_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: ffloor_s32_vs
    ; CHECK-LABEL: name: ffloor_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_FFLOOR %0
    %1:vgpr(s32) = G_FFLOOR %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: ffloor_fneg_s32_vs
name: ffloor_fneg_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: ffloor_fneg_s32_vs
    ; CHECK-LABEL: name: ffloor_fneg_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s32) = G_FNEG %0
    %1:sgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FFLOOR %1
    %2:vgpr(s32) = G_FFLOOR %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: ffloor_fneg_s32_vv
name: ffloor_fneg_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

    ; CHECK-LABEL: name: ffloor_fneg_s32_vv
    ; CHECK-LABEL: name: ffloor_fneg_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FLOOR_F32_e64_:%[0-9]+]]:vgpr_32 = V_FLOOR_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_FLOOR_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FNEG %0
    %1:vgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FFLOOR %1
    %2:vgpr(s32) = G_FFLOOR %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: ffloor_s64_vv
name: ffloor_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; CHECK-LABEL: name: ffloor_s64_vv
    ; CHECK-LABEL: name: ffloor_s64_vv

    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: liveins: $vgpr0_vgpr1

    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; CHECK: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = V_FLOOR_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = V_FLOOR_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0_vgpr1 = COPY [[V_FLOOR_F64_e64_]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[V_FLOOR_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_FFLOOR %0
    %1:vgpr(s64) = G_FFLOOR %0

    $vgpr0_vgpr1 = COPY %1
    $vgpr0_vgpr1 = COPY %1

...
...




# FIXME: Constant bus restriction
# FIXME: Constant bus restriction

# ---
# ---

Show All 19 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; CHECK-LABEL: name: ffloor_fneg_s64_vv
    ; CHECK-LABEL: name: ffloor_fneg_s64_vv

    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: liveins: $vgpr0_vgpr1

    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; CHECK: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = V_FLOOR_F64_e64 1, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_FLOOR_F64_e64_:%[0-9]+]]:vreg_64 = V_FLOOR_F64_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0_vgpr1 = COPY [[V_FLOOR_F64_e64_]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[V_FLOOR_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_FNEG %0
    %1:vgpr(s64) = G_FNEG %0

    %2:vgpr(s64) = G_FFLOOR %1
    %2:vgpr(s64) = G_FFLOOR %1

    $vgpr0_vgpr1 = COPY %2
    $vgpr0_vgpr1 = COPY %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
Show All 11 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fma_f32
    ; GFX6-LABEL: name: fma_f32

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX9-DL-LABEL: name: fma_f32
    ; GFX9-DL-LABEL: name: fma_f32

    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]
    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]

    ; GFX10-LABEL: name: fma_f32
    ; GFX10-LABEL: name: fma_f32

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FMA %0, %1, %2
    %3:vgpr(s32) = G_FMA %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3




...
...




---
---




name:            fma_f32_fneg_src0
name:            fma_f32_fneg_src0

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fma_f32_fneg_src0
    ; GFX6-LABEL: name: fma_f32_fneg_src0

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX9-DL-LABEL: name: fma_f32_fneg_src0
    ; GFX9-DL-LABEL: name: fma_f32_fneg_src0

    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]
    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]

    ; GFX10-LABEL: name: fma_f32_fneg_src0
    ; GFX10-LABEL: name: fma_f32_fneg_src0

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %0
    %3:vgpr(s32) = G_FNEG %0

    %4:vgpr(s32) = G_FMA %3, %1, %2
    %4:vgpr(s32) = G_FMA %3, %1, %2

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fma_f32_fneg_src1
name:            fma_f32_fneg_src1

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fma_f32_fneg_src1
    ; GFX6-LABEL: name: fma_f32_fneg_src1

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX9-DL-LABEL: name: fma_f32_fneg_src1
    ; GFX9-DL-LABEL: name: fma_f32_fneg_src1

    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX9-DL: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]
    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]

    ; GFX10-LABEL: name: fma_f32_fneg_src1
    ; GFX10-LABEL: name: fma_f32_fneg_src1

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_FMAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_FMAC_F32_e64 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_FMAC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %1
    %3:vgpr(s32) = G_FNEG %1

    %4:vgpr(s32) = G_FMA %0, %3, %2
    %4:vgpr(s32) = G_FMA %0, %3, %2

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fma_f32_fneg_src2
name:            fma_f32_fneg_src2

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fma_f32_fneg_src2
    ; GFX6-LABEL: name: fma_f32_fneg_src2

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX9-DL-LABEL: name: fma_f32_fneg_src2
    ; GFX9-DL-LABEL: name: fma_f32_fneg_src2

    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX10-LABEL: name: fma_f32_fneg_src2
    ; GFX10-LABEL: name: fma_f32_fneg_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %2
    %3:vgpr(s32) = G_FNEG %2

    %4:vgpr(s32) = G_FMA %0, %1, %3
    %4:vgpr(s32) = G_FMA %0, %1, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fma_f32_fabs_src2
name:            fma_f32_fabs_src2

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fma_f32_fabs_src2
    ; GFX6-LABEL: name: fma_f32_fabs_src2

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX9-DL-LABEL: name: fma_f32_fabs_src2
    ; GFX9-DL-LABEL: name: fma_f32_fabs_src2

    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX10-LABEL: name: fma_f32_fabs_src2
    ; GFX10-LABEL: name: fma_f32_fabs_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FABS %2
    %3:vgpr(s32) = G_FABS %2

    %4:vgpr(s32) = G_FMA %0, %1, %3
    %4:vgpr(s32) = G_FMA %0, %1, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fma_f32_copy_fneg_src2
name:            fma_f32_copy_fneg_src2

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fma_f32_copy_fneg_src2
    ; GFX6-LABEL: name: fma_f32_copy_fneg_src2

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX9-DL-LABEL: name: fma_f32_copy_fneg_src2
    ; GFX9-DL-LABEL: name: fma_f32_copy_fneg_src2

    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9-DL: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9-DL: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX9-DL: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX9-DL: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX9-DL: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    ; GFX10-LABEL: name: fma_f32_copy_fneg_src2
    ; GFX10-LABEL: name: fma_f32_copy_fneg_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_FMA_F32_:%[0-9]+]]:vgpr_32 = V_FMA_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_FMA_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %2
    %3:vgpr(s32) = G_FNEG %2

    %4:vgpr(s32) = COPY %3
    %4:vgpr(s32) = COPY %3

    %5:vgpr(s32) = G_FMA %0, %1, %4
    %5:vgpr(s32) = G_FMA %0, %1, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5




...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
Show All 10 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fmad_f32
    ; GFX6-LABEL: name: fmad_f32

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    ; GFX10-LABEL: name: fmad_f32
    ; GFX10-LABEL: name: fmad_f32

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_MAC_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_MAC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FMAD %0, %1, %2
    %3:vgpr(s32) = G_FMAD %0, %1, %2

    S_ENDPGM 0, implicit %3
    S_ENDPGM 0, implicit %3




...
...




---
---




name:            fmad_f32_fneg_src0
name:            fmad_f32_fneg_src0

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fmad_f32_fneg_src0
    ; GFX6-LABEL: name: fmad_f32_fneg_src0

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    ; GFX10-LABEL: name: fmad_f32_fneg_src0
    ; GFX10-LABEL: name: fmad_f32_fneg_src0

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 1, [[COPY]], 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %0
    %3:vgpr(s32) = G_FNEG %0

    %4:vgpr(s32) = G_FMAD %3, %1, %2
    %4:vgpr(s32) = G_FMAD %3, %1, %2

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fmad_f32_fneg_src1
name:            fmad_f32_fneg_src1

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fmad_f32_fneg_src1
    ; GFX6-LABEL: name: fmad_f32_fneg_src1

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    ; GFX10-LABEL: name: fmad_f32_fneg_src1
    ; GFX10-LABEL: name: fmad_f32_fneg_src1

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 1, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %1
    %3:vgpr(s32) = G_FNEG %1

    %4:vgpr(s32) = G_FMAD %0, %3, %2
    %4:vgpr(s32) = G_FMAD %0, %3, %2

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fmad_f32_fneg_src2
name:            fmad_f32_fneg_src2

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fmad_f32_fneg_src2
    ; GFX6-LABEL: name: fmad_f32_fneg_src2

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    ; GFX10-LABEL: name: fmad_f32_fneg_src2
    ; GFX10-LABEL: name: fmad_f32_fneg_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %2
    %3:vgpr(s32) = G_FNEG %2

    %4:vgpr(s32) = G_FMAD %0, %1, %3
    %4:vgpr(s32) = G_FMAD %0, %1, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fmad_f32_fabs_src2
name:            fmad_f32_fabs_src2

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fmad_f32_fabs_src2
    ; GFX6-LABEL: name: fmad_f32_fabs_src2

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    ; GFX10-LABEL: name: fmad_f32_fabs_src2
    ; GFX10-LABEL: name: fmad_f32_fabs_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 2, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FABS %2
    %3:vgpr(s32) = G_FABS %2

    %4:vgpr(s32) = G_FMAD %0, %1, %3
    %4:vgpr(s32) = G_FMAD %0, %1, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4




...
...




---
---




name:            fmad_f32_copy_fneg_src2
name:            fmad_f32_copy_fneg_src2

legalized:       true
legalized:       true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2
    liveins: $vgpr0, $vgpr1, $vgpr2




    ; GFX6-LABEL: name: fmad_f32_copy_fneg_src2
    ; GFX6-LABEL: name: fmad_f32_copy_fneg_src2

    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX6: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX6: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    ; GFX10-LABEL: name: fmad_f32_copy_fneg_src2
    ; GFX10-LABEL: name: fmad_f32_copy_fneg_src2

    ; GFX10: $vcc_hi = IMPLICIT_DEF
    ; GFX10: $vcc_hi = IMPLICIT_DEF

    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
    ; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2

    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $exec
    ; GFX10: [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[COPY]], 0, [[COPY1]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]
    ; GFX10: S_ENDPGM 0, implicit [[V_MAD_F32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s32) = G_FNEG %2
    %3:vgpr(s32) = G_FNEG %2

    %4:vgpr(s32) = COPY %3
    %4:vgpr(s32) = COPY %3

    %5:vgpr(s32) = G_FMAD %0, %1, %4
    %5:vgpr(s32) = G_FMAD %0, %1, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5




...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.mir
Show All 15 Lines  bb.0:

    ; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_on
    ; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_on

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines  bb.0:

    ; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_off
    ; GFX7-LABEL: name: fmaxnum_ieee_f32_f64_ieee_mode_off

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s




---
---

name: fmaxnum_ieee_f16_vv
name: fmaxnum_ieee_f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fmaxnum_ieee_f16_vv
    ; CHECK-LABEL: name: fmaxnum_ieee_f16_vv

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FMAXNUM_IEEE %2, %3
    %4:vgpr(s16) = G_FMAXNUM_IEEE %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fmaxnum_ieee_f16_v_fneg_v
name: fmaxnum_ieee_f16_v_fneg_v

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fmaxnum_ieee_f16_v_fneg_v
    ; CHECK-LABEL: name: fmaxnum_ieee_f16_v_fneg_v

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FNEG %3
    %4:vgpr(s16) = G_FNEG %3

    %5:vgpr(s16) = G_FMAXNUM_IEEE %2, %4
    %5:vgpr(s16) = G_FMAXNUM_IEEE %2, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s




---
---

name: fmaxnum_ieee_v2f16_vv
name: fmaxnum_ieee_v2f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1




    ; GFX9-LABEL: name: fmaxnum_ieee_v2f16_vv
    ; GFX9-LABEL: name: fmaxnum_ieee_v2f16_vv

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = COPY $vgpr1
    %1:vgpr(<2 x s16>) = COPY $vgpr1

    %2:vgpr(<2 x s16>) = G_FMAXNUM_IEEE %0, %1
    %2:vgpr(<2 x s16>) = G_FMAXNUM_IEEE %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.mir
Show All 16 Lines  bb.0:

    ; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_on
    ; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_on

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines  bb.0:

    ; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_off
    ; GFX7-LABEL: name: fmaxnum_f32_f64_ieee_mode_off

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MAX_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_1:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MAX_F64_2:%[0-9]+]]:vreg_64 = V_MAX_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MAX_F64_]], implicit [[V_MAX_F64_1]], implicit [[V_MAX_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s




---
---

name: fmaxnum_f16_vv
name: fmaxnum_f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fmaxnum_f16_vv
    ; CHECK-LABEL: name: fmaxnum_f16_vv

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FMAXNUM %2, %3
    %4:vgpr(s16) = G_FMAXNUM %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fmaxnum_f16_v_fneg_v
name: fmaxnum_f16_v_fneg_v

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fmaxnum_f16_v_fneg_v
    ; CHECK-LABEL: name: fmaxnum_f16_v_fneg_v

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MAX_F16_e64_:%[0-9]+]]:vgpr_32 = V_MAX_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MAX_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FNEG %3
    %4:vgpr(s16) = G_FNEG %3

    %5:vgpr(s16) = G_FMAXNUM %2, %4
    %5:vgpr(s16) = G_FMAXNUM %2, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s

# FIXME: Ideally this would fail to select with ieee mode enabled.
# FIXME: Ideally this would fail to select with ieee mode enabled.




---
---

name: fmaxnum_v2f16_vv
name: fmaxnum_v2f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1




    ; GFX9-LABEL: name: fmaxnum_v2f16_vv
    ; GFX9-LABEL: name: fmaxnum_v2f16_vv

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MAX_F16_:%[0-9]+]]:vgpr_32 = V_PK_MAX_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MAX_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = COPY $vgpr1
    %1:vgpr(<2 x s16>) = COPY $vgpr1

    %2:vgpr(<2 x s16>) = G_FMAXNUM %0, %1
    %2:vgpr(<2 x s16>) = G_FMAXNUM %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.mir
Show All 15 Lines  bb.0:

    ; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_on
    ; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_on

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines  bb.0:

    ; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_off
    ; GFX7-LABEL: name: fminnum_ieee_f32_f64_ieee_mode_off

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s




---
---

name: fminnum_ieee_f16_vv
name: fminnum_ieee_f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fminnum_ieee_f16_vv
    ; CHECK-LABEL: name: fminnum_ieee_f16_vv

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FMINNUM_IEEE %2, %3
    %4:vgpr(s16) = G_FMINNUM_IEEE %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fminnum_ieee_f16_v_fneg_v
name: fminnum_ieee_f16_v_fneg_v

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fminnum_ieee_f16_v_fneg_v
    ; CHECK-LABEL: name: fminnum_ieee_f16_v_fneg_v

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FNEG %3
    %4:vgpr(s16) = G_FNEG %3

    %5:vgpr(s16) = G_FMINNUM_IEEE %2, %4
    %5:vgpr(s16) = G_FMINNUM_IEEE %2, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s




---
---

name: fminnum_ieee_v2f16_vv
name: fminnum_ieee_v2f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1




    ; GFX9-LABEL: name: fminnum_ieee_v2f16_vv
    ; GFX9-LABEL: name: fminnum_ieee_v2f16_vv

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9: [[V_PK_MIN_F16_:%[0-9]+]]:vgpr_32 = V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MIN_F16_:%[0-9]+]]:vgpr_32 = V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MIN_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MIN_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = COPY $vgpr1
    %1:vgpr(<2 x s16>) = COPY $vgpr1

    %2:vgpr(<2 x s16>) = G_FMINNUM_IEEE %0, %1
    %2:vgpr(<2 x s16>) = G_FMINNUM_IEEE %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.mir
Show All 16 Lines  bb.0:

    ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on
    ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_on

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines  bb.0:

    ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off
    ; GFX7-LABEL: name: fminnum_f32_f64_ieee_mode_off

    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GFX7: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11
    ; GFX7: [[COPY4:%[0-9]+]]:sreg_64 = COPY $sgpr10_sgpr11

    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11
    ; GFX7: [[COPY5:%[0-9]+]]:vreg_64 = COPY $vgpr10_vgpr11

    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13
    ; GFX7: [[COPY6:%[0-9]+]]:vreg_64 = COPY $vgpr12_vgpr13

    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GFX7: FLAT_STORE_DWORD [[COPY3]], [[V_MIN_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY4]], 0, [[COPY5]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_1:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY4]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $exec
    ; GFX7: [[V_MIN_F64_2:%[0-9]+]]:vreg_64 = V_MIN_F64 0, [[COPY5]], 0, [[COPY6]], 0, 0, implicit $mode, implicit $exec

    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]
    ; GFX7: S_ENDPGM 0, implicit [[V_MIN_F64_]], implicit [[V_MIN_F64_1]], implicit [[V_MIN_F64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %10:sgpr(s64) = COPY $sgpr10_sgpr11
    %10:sgpr(s64) = COPY $sgpr10_sgpr11

    %11:vgpr(s64) = COPY $vgpr10_vgpr11
    %11:vgpr(s64) = COPY $vgpr10_vgpr11

Show All 28 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck %s




---
---

name: fminnum_f16_vv
name: fminnum_f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fminnum_f16_vv
    ; CHECK-LABEL: name: fminnum_f16_vv

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FMINNUM %2, %3
    %4:vgpr(s16) = G_FMINNUM %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...




---
---

name: fminnum_f16_v_fneg_v
name: fminnum_f16_v_fneg_v

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; CHECK-LABEL: name: fminnum_f16_v_fneg_v
    ; CHECK-LABEL: name: fminnum_f16_v_fneg_v

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
    ; CHECK: [[V_MIN_F16_e64_:%[0-9]+]]:vgpr_32 = V_MIN_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]
    ; CHECK: S_ENDPGM 0, implicit [[V_MIN_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s16) = G_TRUNC %0
    %2:vgpr(s16) = G_TRUNC %0

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FNEG %3
    %4:vgpr(s16) = G_FNEG %3

    %5:vgpr(s16) = G_FMINNUM %2, %4
    %5:vgpr(s16) = G_FMINNUM %2, %4

    S_ENDPGM 0, implicit %5
    S_ENDPGM 0, implicit %5

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s




---
---

name: fminnum_v2f16_vv
name: fminnum_v2f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1
    liveins: $sgpr0, $sgpr1




    ; GFX9-LABEL: name: fminnum_v2f16_vv
    ; GFX9-LABEL: name: fminnum_v2f16_vv

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9: [[V_PK_MIN_F16_:%[0-9]+]]:vgpr_32 = V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MIN_F16_:%[0-9]+]]:vgpr_32 = V_PK_MIN_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MIN_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MIN_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = COPY $vgpr1
    %1:vgpr(<2 x s16>) = COPY $vgpr1

    %2:vgpr(<2 x s16>) = G_FMINNUM %0, %1
    %2:vgpr(<2 x s16>) = G_FMINNUM %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
Show All 9 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4

    ; GCN-LABEL: name: fmul_f32
    ; GCN-LABEL: name: fmul_f32

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY3]], [[V_MUL_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




Show All 19 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1, $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
    liveins: $sgpr0_sgpr1, $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5

    ; GCN-LABEL: name: fmul_f64
    ; GCN-LABEL: name: fmul_f64

    ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GCN: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; GCN: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F64_1:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F64_1:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F64_2:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F64_2:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MUL_F64_]], implicit [[V_MUL_F64_1]], implicit [[V_MUL_F64_2]]
    ; GCN: S_ENDPGM 0, implicit [[V_MUL_F64_]], implicit [[V_MUL_F64_1]], implicit [[V_MUL_F64_2]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s64) = COPY $vgpr0_vgpr1
    %1:vgpr(s64) = COPY $vgpr0_vgpr1

    %2:vgpr(s64) = COPY $vgpr2_vgpr3
    %2:vgpr(s64) = COPY $vgpr2_vgpr3

    %3:vgpr(p1) = COPY $vgpr4_vgpr5
    %3:vgpr(p1) = COPY $vgpr4_vgpr5




    ; fmul vs
    ; fmul vs

    %4:vgpr(s64) = G_FMUL %1, %0
    %4:vgpr(s64) = G_FMUL %1, %0

Show All 14 Lines
regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
    liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4

    ; GCN-LABEL: name: fmul_f16
    ; GCN-LABEL: name: fmul_f16

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F16_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F16_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F16_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F16_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]], implicit [[V_MUL_F16_e64_1]], implicit [[V_MUL_F16_e64_2]]
    ; GCN: S_ENDPGM 0, implicit [[V_MUL_F16_e64_]], implicit [[V_MUL_F16_e64_1]], implicit [[V_MUL_F16_e64_2]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0

    %2:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr1

    %3:vgpr(p1) = COPY $vgpr3_vgpr4
    %3:vgpr(p1) = COPY $vgpr3_vgpr4




    %4:sgpr(s16) = G_TRUNC %0
    %4:sgpr(s16) = G_TRUNC %0

    %5:vgpr(s16) = G_TRUNC %1
    %5:vgpr(s16) = G_TRUNC %1

Show All 18 Lines
regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3
    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3

    ; GCN-LABEL: name: fmul_modifiers_f32
    ; GCN-LABEL: name: fmul_modifiers_f32

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
    ; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3

    ; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 2, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 2, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 2, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_3:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 1, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_3:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 1, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_4:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_4:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_5:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_5:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 1, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_6:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_6:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_7:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_7:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_8:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_8:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_MUL_F32_e64_9:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_MUL_F32_e64_9:%[0-9]+]]:vgpr_32 = V_MUL_F32_e64 3, [[COPY]], 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_3]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_3]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_4]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_4]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_5]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_5]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_6]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_6]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_7]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY1]], [[V_MUL_F32_e64_7]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s  | FileCheck -check-prefix=GFX9 %s




---
---

name: fmul_v2f16_vv
name: fmul_v2f16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; GFX9-LABEL: name: fmul_v2f16_vv
    ; GFX9-LABEL: name: fmul_v2f16_vv

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = COPY $vgpr1
    %1:vgpr(<2 x s16>) = COPY $vgpr1

    %2:vgpr(<2 x s16>) = G_FMUL %0, %1
    %2:vgpr(<2 x s16>) = G_FMUL %0, %1

    S_ENDPGM 0, implicit %2
    S_ENDPGM 0, implicit %2

...
...




---
---

name: fmul_v2f16_fneg_v_fneg_v
name: fmul_v2f16_fneg_v_fneg_v

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    ; GFX9-LABEL: name: fmul_v2f16_fneg_v_fneg_v
    ; GFX9-LABEL: name: fmul_v2f16_fneg_v_fneg_v

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1

    ; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(<2 x s16>) = COPY $vgpr1
    %1:vgpr(<2 x s16>) = COPY $vgpr1

    %2:vgpr(<2 x s16>) = G_FNEG %0
    %2:vgpr(<2 x s16>) = G_FNEG %0

    %3:vgpr(<2 x s16>) = G_FNEG %1
    %3:vgpr(<2 x s16>) = G_FNEG %1

    %4:vgpr(<2 x s16>) = G_FMUL %2, %3
    %4:vgpr(<2 x s16>) = G_FMUL %2, %3

    S_ENDPGM 0, implicit %4
    S_ENDPGM 0, implicit %4

...
...

Show All 10 Lines  bb.0:

    ; GFX9-LABEL: name: fmul_v2f16_fneg_lo_v_v
    ; GFX9-LABEL: name: fmul_v2f16_fneg_lo_v_v

    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32(<2 x s16>) = COPY $vgpr0
    ; GFX9: [[COPY:%[0-9]+]]:vgpr_32(<2 x s16>) = COPY $vgpr0

    ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1

    ; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; GFX9: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2

    ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
    ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)

    ; GFX9: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
    ; GFX9: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]

    ; GFX9: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FNEG]](s16)
    ; GFX9: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[FNEG]](s16)

    ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:vgpr_32(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY2]](s32)
    ; GFX9: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:vgpr_32(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[COPY2]](s32)

    ; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_PK_MUL_F16 8, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 8, [[COPY]](<2 x s16>), 0, 0, 0, 0, 0, implicit $exec
    ; GFX9: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32(<2 x s16>) = V_PK_MUL_F16 8, [[BUILD_VECTOR_TRUNC]](<2 x s16>), 8, [[COPY]](<2 x s16>), 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]](<2 x s16>)
    ; GFX9: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]](<2 x s16>)

    %0:vgpr(<2 x s16>) = COPY $vgpr0
    %0:vgpr(<2 x s16>) = COPY $vgpr0

    %1:vgpr(s32) = COPY $vgpr1
    %1:vgpr(s32) = COPY $vgpr1

    %2:vgpr(s32) = COPY $vgpr2
    %2:vgpr(s32) = COPY $vgpr2

    %3:vgpr(s16) = G_TRUNC %1
    %3:vgpr(s16) = G_TRUNC %1

    %4:vgpr(s16) = G_FNEG %3
    %4:vgpr(s16) = G_FNEG %3

    %5:vgpr(s32) = G_ANYEXT %4
    %5:vgpr(s32) = G_ANYEXT %4

    %6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %2
    %6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %2

    %7:vgpr(<2 x s16>) = G_FMUL %6, %0
    %7:vgpr(<2 x s16>) = G_FMUL %6, %0

    S_ENDPGM 0, implicit %7
    S_ENDPGM 0, implicit %7

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN




---
---

name: fptosi_s32_to_s32_vv
name: fptosi_s32_to_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fptosi_s32_to_s32_vv
    ; GCN-LABEL: name: fptosi_s32_to_s32_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FPTOSI %0
    %1:vgpr(s32) = G_FPTOSI %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: fptosi_s32_to_s32_vs
name: fptosi_s32_to_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; GCN-LABEL: name: fptosi_s32_to_s32_vs
    ; GCN-LABEL: name: fptosi_s32_to_s32_vs

    ; GCN: liveins: $sgpr0
    ; GCN: liveins: $sgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_FPTOSI %0
    %1:vgpr(s32) = G_FPTOSI %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: fptosi_s32_to_s32_fneg_vv
name: fptosi_s32_to_s32_fneg_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv
    ; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_I32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FNEG %0
    %1:vgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FPTOSI %1
    %2:vgpr(s32) = G_FPTOSI %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: fptosi_s16_to_s32_vv
name: fptosi_s16_to_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fptosi_s16_to_s32_vv
    ; GCN-LABEL: name: fptosi_s16_to_s32_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec

    ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s32) = G_FPTOSI %1
    %2:vgpr(s32) = G_FPTOSI %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: fptosi_s16_to_s32_vs
name: fptosi_s16_to_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; GCN-LABEL: name: fptosi_s16_to_s32_vs
    ; GCN-LABEL: name: fptosi_s16_to_s32_vs

    ; GCN: liveins: $sgpr0
    ; GCN: liveins: $sgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec

    ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s32) = G_FPTOSI %1
    %2:vgpr(s32) = G_FPTOSI %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: fptosi_s16_to_s32_fneg_vv
name: fptosi_s16_to_s32_fneg_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv
    ; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768

    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec

    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $exec
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec

    ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: [[V_CVT_I32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_I32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_I32_F32_e32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FNEG %1
    %2:vgpr(s16) = G_FNEG %1

    %3:vgpr(s32) = G_FPTOSI %2
    %3:vgpr(s32) = G_FPTOSI %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir
Show All 9 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
    liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4




    ; GCN-LABEL: name: fptoui
    ; GCN-LABEL: name: fptoui

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $exec
    ; GCN: [[V_CVT_U32_F32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; GCN: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_U32_F32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0




    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0




    %2:vgpr(p1) = COPY $vgpr3_vgpr4
    %2:vgpr(p1) = COPY $vgpr3_vgpr4




Show All 15 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fptoui_s16_to_s32_vv
    ; GCN-LABEL: name: fptoui_s16_to_s32_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec

    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s32) = G_FPTOUI %1
    %2:vgpr(s32) = G_FPTOUI %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: fptoui_s16_to_s32_vs
name: fptoui_s16_to_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; GCN-LABEL: name: fptoui_s16_to_s32_vs
    ; GCN-LABEL: name: fptoui_s16_to_s32_vs

    ; GCN: liveins: $sgpr0
    ; GCN: liveins: $sgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $exec
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec

    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s32) = G_FPTOUI %1
    %2:vgpr(s32) = G_FPTOUI %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: fptoui_s16_to_s32_fneg_vv
name: fptoui_s16_to_s32_fneg_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv
    ; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768

    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec

    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $exec
    ; GCN: [[V_CVT_F32_F16_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec

    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $exec
    ; GCN: [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_CVT_F32_F16_e32_]], implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]
    ; GCN: $vgpr0 = COPY [[V_CVT_U32_F32_e32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FNEG %1
    %2:vgpr(s16) = G_FNEG %1

    %3:vgpr(s32) = G_FPTOUI %2
    %3:vgpr(s32) = G_FPTOUI %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: frint_s32_vv
    ; GCN-LABEL: name: frint_s32_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]]
    ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FRINT %0
    %1:vgpr(s32) = G_FRINT %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: frint_s32_vs
name: frint_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; GCN-LABEL: name: frint_s32_vs
    ; GCN-LABEL: name: frint_s32_vs

    ; GCN: liveins: $sgpr0
    ; GCN: liveins: $sgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]]
    ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_FRINT %0
    %1:vgpr(s32) = G_FRINT %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: frint_fneg_s32_vv
name: frint_fneg_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: frint_fneg_s32_vv
    ; GCN-LABEL: name: frint_fneg_s32_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F32_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]]
    ; GCN: $vgpr0 = COPY [[V_RNDNE_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_FNEG %0
    %1:vgpr(s32) = G_FNEG %0

    %2:vgpr(s32) = G_FRINT %1
    %2:vgpr(s32) = G_FRINT %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: frint_s64_vv
name: frint_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; GCN-LABEL: name: frint_s64_vv
    ; GCN-LABEL: name: frint_s64_vv

    ; GCN: liveins: $vgpr0_vgpr1
    ; GCN: liveins: $vgpr0_vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]]
    ; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_FRINT %0
    %1:vgpr(s64) = G_FRINT %0

    $vgpr0_vgpr1 = COPY %1
    $vgpr0_vgpr1 = COPY %1

...
...




---
---

name: frint_s64_fneg_vv
name: frint_s64_fneg_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; GCN-LABEL: name: frint_s64_fneg_vv
    ; GCN-LABEL: name: frint_s64_fneg_vv

    ; GCN: liveins: $vgpr0_vgpr1
    ; GCN: liveins: $vgpr0_vgpr1

    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F64_e64_:%[0-9]+]]:vreg_64 = V_RNDNE_F64_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]]
    ; GCN: $vgpr0_vgpr1 = COPY [[V_RNDNE_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_FNEG %0
    %1:vgpr(s64) = G_FNEG %0

    %2:vgpr(s64) = G_FRINT %1
    %2:vgpr(s64) = G_FRINT %1

    $vgpr0_vgpr1 = COPY %2
    $vgpr0_vgpr1 = COPY %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frint.s16.mir
Show All 32 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: frint_s16_vv
    ; GCN-LABEL: name: frint_s16_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FRINT %1
    %2:vgpr(s16) = G_FRINT %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




---
---

name: frint_s16_vs
name: frint_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; GCN-LABEL: name: frint_s16_vs
    ; GCN-LABEL: name: frint_s16_vs

    ; GCN: liveins: $sgpr0
    ; GCN: liveins: $sgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FRINT %1
    %2:vgpr(s16) = G_FRINT %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




---
---

name: frint_fneg_s16_vv
name: frint_fneg_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: frint_fneg_s16_vv
    ; GCN-LABEL: name: frint_fneg_s16_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_RNDNE_F16_e64_:%[0-9]+]]:vgpr_32 = V_RNDNE_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_RNDNE_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FNEG %1
    %2:vgpr(s16) = G_FNEG %1

    %3:vgpr(s16) = G_FRINT %2
    %3:vgpr(s16) = G_FRINT %2

    %4:vgpr(s32) = G_ANYEXT %3
    %4:vgpr(s32) = G_ANYEXT %3

    $vgpr0 = COPY %4
    $vgpr0 = COPY %4

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s




---
---

name: intrinsic_trunc_s32_vv
name: intrinsic_trunc_s32_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; CHECK-LABEL: name: intrinsic_trunc_s32_vv
    ; CHECK-LABEL: name: intrinsic_trunc_s32_vv

    ; CHECK: liveins: $vgpr0
    ; CHECK: liveins: $vgpr0

    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; CHECK: [[V_TRUNC_F32_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_TRUNC_F32_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_TRUNC_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_TRUNC_F32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_INTRINSIC_TRUNC %0
    %1:vgpr(s32) = G_INTRINSIC_TRUNC %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: intrinsic_trunc_s32_vs
name: intrinsic_trunc_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; CHECK-LABEL: name: intrinsic_trunc_s32_vs
    ; CHECK-LABEL: name: intrinsic_trunc_s32_vs

    ; CHECK: liveins: $sgpr0
    ; CHECK: liveins: $sgpr0

    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; CHECK: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; CHECK: [[V_TRUNC_F32_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_TRUNC_F32_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0 = COPY [[V_TRUNC_F32_e64_]]
    ; CHECK: $vgpr0 = COPY [[V_TRUNC_F32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_INTRINSIC_TRUNC %0
    %1:vgpr(s32) = G_INTRINSIC_TRUNC %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: intrinsic_trunc_s64_sv
name: intrinsic_trunc_s64_sv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1




    ; CHECK-LABEL: name: intrinsic_trunc_s64_sv
    ; CHECK-LABEL: name: intrinsic_trunc_s64_sv

    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK: liveins: $sgpr0_sgpr1

    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; CHECK: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1

    ; CHECK: [[V_TRUNC_F64_e64_:%[0-9]+]]:vreg_64 = V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_TRUNC_F64_e64_:%[0-9]+]]:vreg_64 = V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0_vgpr1 = COPY [[V_TRUNC_F64_e64_]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[V_TRUNC_F64_e64_]]

    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %0:sgpr(s64) = COPY $sgpr0_sgpr1

    %1:vgpr(s64) = G_INTRINSIC_TRUNC %0
    %1:vgpr(s64) = G_INTRINSIC_TRUNC %0

    $vgpr0_vgpr1 = COPY %1
    $vgpr0_vgpr1 = COPY %1

...
...




---
---

name: intrinsic_trunc_s64_vv
name: intrinsic_trunc_s64_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1
    liveins: $vgpr0_vgpr1




    ; CHECK-LABEL: name: intrinsic_trunc_s64_vv
    ; CHECK-LABEL: name: intrinsic_trunc_s64_vv

    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK: liveins: $vgpr0_vgpr1

    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
    ; CHECK: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1

    ; CHECK: [[V_TRUNC_F64_e64_:%[0-9]+]]:vreg_64 = V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $exec
    ; CHECK: [[V_TRUNC_F64_e64_:%[0-9]+]]:vreg_64 = V_TRUNC_F64_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; CHECK: $vgpr0_vgpr1 = COPY [[V_TRUNC_F64_e64_]]
    ; CHECK: $vgpr0_vgpr1 = COPY [[V_TRUNC_F64_e64_]]

    %0:vgpr(s64) = COPY $vgpr0_vgpr1
    %0:vgpr(s64) = COPY $vgpr0_vgpr1

    %1:vgpr(s64) = G_INTRINSIC_TRUNC %0
    %1:vgpr(s64) = G_INTRINSIC_TRUNC %0

    $vgpr0_vgpr1 = COPY %1
    $vgpr0_vgpr1 = COPY %1

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s




---
---

name: intrinsic_trunc_s16_vv
name: intrinsic_trunc_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: intrinsic_trunc_s16_vv
    ; GCN-LABEL: name: intrinsic_trunc_s16_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC_TRUNC %1
    %2:vgpr(s16) = G_INTRINSIC_TRUNC %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




---
---

name: intrinsic_trunc_s16_vs
name: intrinsic_trunc_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; GCN-LABEL: name: intrinsic_trunc_s16_vs
    ; GCN-LABEL: name: intrinsic_trunc_s16_vs

    ; GCN: liveins: $sgpr0
    ; GCN: liveins: $sgpr0

    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:sgpr(s16) = G_TRUNC %0
    %1:sgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_INTRINSIC_TRUNC %1
    %2:vgpr(s16) = G_INTRINSIC_TRUNC %1

    %3:vgpr(s32) = G_ANYEXT %2
    %3:vgpr(s32) = G_ANYEXT %2

    $vgpr0 = COPY %3
    $vgpr0 = COPY %3

...
...




---
---

name: intrinsic_trunc_fneg_s16_vv
name: intrinsic_trunc_fneg_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; GCN-LABEL: name: intrinsic_trunc_fneg_s16_vv
    ; GCN-LABEL: name: intrinsic_trunc_fneg_s16_vv

    ; GCN: liveins: $vgpr0
    ; GCN: liveins: $vgpr0

    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 1, [[COPY]], 0, 0, implicit $exec
    ; GCN: [[V_TRUNC_F16_e64_:%[0-9]+]]:vgpr_32 = V_TRUNC_F16_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]]
    ; GCN: $vgpr0 = COPY [[V_TRUNC_F16_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_TRUNC %0
    %1:vgpr(s16) = G_TRUNC %0

    %2:vgpr(s16) = G_FNEG %1
    %2:vgpr(s16) = G_FNEG %1

    %3:vgpr(s16) = G_INTRINSIC_TRUNC %2
    %3:vgpr(s16) = G_INTRINSIC_TRUNC %2

    %4:vgpr(s32) = G_ANYEXT %3
    %4:vgpr(s32) = G_ANYEXT %3

    $vgpr0 = COPY %4
    $vgpr0 = COPY %4

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
Show All 10 Lines
body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
    liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4




    ; WAVE64-LABEL: name: sitofp
    ; WAVE64-LABEL: name: sitofp

    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; WAVE64: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; WAVE64: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
    ; WAVE64: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; WAVE64: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
    ; WAVE64: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
    ; WAVE64: FLAT_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)

    ; WAVE32-LABEL: name: sitofp
    ; WAVE32-LABEL: name: sitofp

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
    ; WAVE32: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4

    ; WAVE32: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $exec
    ; WAVE32: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; WAVE32: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $exec
    ; WAVE32: [[V_CVT_F32_I32_e64_1:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY1]], 0, 0, implicit $mode, implicit $exec

    ; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
    ; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)

    ; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
    ; WAVE32: GLOBAL_STORE_DWORD [[COPY2]], [[V_CVT_F32_I32_e64_1]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0




    %1:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr0




    %2:vgpr(p1) = COPY $vgpr3_vgpr4
    %2:vgpr(p1) = COPY $vgpr3_vgpr4




Show All 15 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; WAVE64-LABEL: name: sitofp_s32_to_s16_vv
    ; WAVE64-LABEL: name: sitofp_s32_to_s16_vv

    ; WAVE64: liveins: $vgpr0
    ; WAVE64: liveins: $vgpr0

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
    ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec

    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    ; WAVE32-LABEL: name: sitofp_s32_to_s16_vv
    ; WAVE32-LABEL: name: sitofp_s32_to_s16_vv

    ; WAVE32: liveins: $vgpr0
    ; WAVE32: liveins: $vgpr0

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
    ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec

    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_SITOFP %0
    %1:vgpr(s16) = G_SITOFP %0

    %2:vgpr(s32) = G_ANYEXT %1
    %2:vgpr(s32) = G_ANYEXT %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: sitofp_s32_to_s16_vs
name: sitofp_s32_to_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; WAVE64-LABEL: name: sitofp_s32_to_s16_vs
    ; WAVE64-LABEL: name: sitofp_s32_to_s16_vs

    ; WAVE64: liveins: $sgpr0
    ; WAVE64: liveins: $sgpr0

    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
    ; WAVE64: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec

    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    ; WAVE32-LABEL: name: sitofp_s32_to_s16_vs
    ; WAVE32-LABEL: name: sitofp_s32_to_s16_vs

    ; WAVE32: liveins: $sgpr0
    ; WAVE32: liveins: $sgpr0

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $exec
    ; WAVE32: [[V_CVT_F32_I32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $exec
    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_I32_e32_]], implicit $mode, implicit $exec

    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s16) = G_SITOFP %0
    %1:vgpr(s16) = G_SITOFP %0

    %2:vgpr(s32) = G_ANYEXT %1
    %2:vgpr(s32) = G_ANYEXT %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
Show All 9 Lines



body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; WAVE64-LABEL: name: uitofp_s32_to_s32_vv
    ; WAVE64-LABEL: name: uitofp_s32_to_s32_vv

    ; WAVE64: liveins: $vgpr0
    ; WAVE64: liveins: $vgpr0

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
    ; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
    ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]

    ; WAVE32-LABEL: name: uitofp_s32_to_s32_vv
    ; WAVE32-LABEL: name: uitofp_s32_to_s32_vv

    ; WAVE32: liveins: $vgpr0
    ; WAVE32: liveins: $vgpr0

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
    ; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
    ; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s32) = G_UITOFP %0
    %1:vgpr(s32) = G_UITOFP %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: uitofp_s32_to_s32_vs
name: uitofp_s32_to_s32_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; WAVE64-LABEL: name: uitofp_s32_to_s32_vs
    ; WAVE64-LABEL: name: uitofp_s32_to_s32_vs

    ; WAVE64: liveins: $sgpr0
    ; WAVE64: liveins: $sgpr0

    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
    ; WAVE64: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
    ; WAVE64: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]

    ; WAVE32-LABEL: name: uitofp_s32_to_s32_vs
    ; WAVE32-LABEL: name: uitofp_s32_to_s32_vs

    ; WAVE32: liveins: $sgpr0
    ; WAVE32: liveins: $sgpr0

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $exec
    ; WAVE32: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec

    ; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]
    ; WAVE32: $vgpr0 = COPY [[V_CVT_F32_U32_e64_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s32) = G_UITOFP %0
    %1:vgpr(s32) = G_UITOFP %0

    $vgpr0 = COPY %1
    $vgpr0 = COPY %1

...
...




---
---

name: uitofp_s32_to_s16_vv
name: uitofp_s32_to_s16_vv

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    ; WAVE64-LABEL: name: uitofp_s32_to_s16_vv
    ; WAVE64-LABEL: name: uitofp_s32_to_s16_vv

    ; WAVE64: liveins: $vgpr0
    ; WAVE64: liveins: $vgpr0

    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
    ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec

    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    ; WAVE32-LABEL: name: uitofp_s32_to_s16_vv
    ; WAVE32-LABEL: name: uitofp_s32_to_s16_vv

    ; WAVE32: liveins: $vgpr0
    ; WAVE32: liveins: $vgpr0

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0

    ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
    ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec

    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    %0:vgpr(s32) = COPY $vgpr0
    %0:vgpr(s32) = COPY $vgpr0

    %1:vgpr(s16) = G_UITOFP %0
    %1:vgpr(s16) = G_UITOFP %0

    %2:vgpr(s32) = G_ANYEXT %1
    %2:vgpr(s32) = G_ANYEXT %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...




---
---

name: uitofp_s32_to_s16_vs
name: uitofp_s32_to_s16_vs

legalized: true
legalized: true

regBankSelected: true
regBankSelected: true

tracksRegLiveness: true
tracksRegLiveness: true




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0
    liveins: $sgpr0




    ; WAVE64-LABEL: name: uitofp_s32_to_s16_vs
    ; WAVE64-LABEL: name: uitofp_s32_to_s16_vs

    ; WAVE64: liveins: $sgpr0
    ; WAVE64: liveins: $sgpr0

    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE64: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
    ; WAVE64: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
    ; WAVE64: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec

    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE64: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    ; WAVE32-LABEL: name: uitofp_s32_to_s16_vs
    ; WAVE32-LABEL: name: uitofp_s32_to_s16_vs

    ; WAVE32: liveins: $sgpr0
    ; WAVE32: liveins: $sgpr0

    ; WAVE32: $vcc_hi = IMPLICIT_DEF
    ; WAVE32: $vcc_hi = IMPLICIT_DEF

    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; WAVE32: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0

    ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $exec
    ; WAVE32: [[V_CVT_F32_U32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e32 [[COPY]], implicit $mode, implicit $exec

    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $exec
    ; WAVE32: [[V_CVT_F16_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_F16_F32_e32 [[V_CVT_F32_U32_e32_]], implicit $mode, implicit $exec

    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]
    ; WAVE32: $vgpr0 = COPY [[V_CVT_F16_F32_e32_]]

    %0:sgpr(s32) = COPY $sgpr0
    %0:sgpr(s32) = COPY $sgpr0

    %1:vgpr(s16) = G_UITOFP %0
    %1:vgpr(s16) = G_UITOFP %0

    %2:vgpr(s32) = G_ANYEXT %1
    %2:vgpr(s32) = G_ANYEXT %1

    $vgpr0 = COPY %2
    $vgpr0 = COPY %2

...
...

llvm/test/CodeGen/AMDGPU/bundle-latency.mir
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=post-RA-sched %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=post-RA-sched %s -o - | FileCheck -check-prefix=GCN %s




# Check that we move consumer further from producer, even if one of them is in a bundle.
# Check that we move consumer further from producer, even if one of them is in a bundle.




---
---

name:            src_bundle_latency
name:            src_bundle_latency

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    ; GCN-LABEL: name: src_bundle_latency
    ; GCN-LABEL: name: src_bundle_latency

    ; GCN: $vgpr0, $vgpr1 = BUNDLE undef $vgpr3_vgpr4, implicit $exec {
    ; GCN: $vgpr0, $vgpr1 = BUNDLE undef $vgpr3_vgpr4, implicit $exec {

    ; GCN:   $vgpr0 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec
    ; GCN:   $vgpr0 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec

    ; GCN:   $vgpr1 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 4, 0, 0, 0, implicit $exec
    ; GCN:   $vgpr1 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 4, 0, 0, 0, implicit $exec

    ; GCN: }
    ; GCN: }

    ; GCN: $vgpr6 = V_ADD_F32_e32 killed $vgpr0, $vgpr0, implicit $exec
    ; GCN: $vgpr6 = V_ADD_F32_e32 killed $vgpr0, $vgpr0, implicit $mode, implicit $exec

    ; GCN: $vgpr5 = V_ADD_F32_e32 killed $vgpr1, $vgpr1, implicit $exec
    ; GCN: $vgpr5 = V_ADD_F32_e32 killed $vgpr1, $vgpr1, implicit $mode, implicit $exec

    $vgpr0, $vgpr1 = BUNDLE undef $vgpr3_vgpr4, implicit $exec {
    $vgpr0, $vgpr1 = BUNDLE undef $vgpr3_vgpr4, implicit $exec {

      $vgpr0 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec
      $vgpr0 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 0, 0, 0, 0, implicit $exec

      $vgpr1 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 4, 0, 0, 0, implicit $exec
      $vgpr1 = GLOBAL_LOAD_DWORD undef $vgpr3_vgpr4, 4, 0, 0, 0, implicit $exec

    }
    }

    $vgpr5 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $exec
    $vgpr5 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec

    $vgpr6 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $exec
    $vgpr6 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec

...
...




---
---

name:            dst_bundle_latency
name:            dst_bundle_latency

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    ; GCN-LABEL: name: dst_bundle_latency
    ; GCN-LABEL: name: dst_bundle_latency

    ; GCN: $vgpr1 = V_ADD_F32_e32 undef $vgpr6, undef $vgpr6, implicit $exec
    ; GCN: $vgpr1 = V_ADD_F32_e32 undef $vgpr6, undef $vgpr6, implicit $mode, implicit $exec

    ; GCN: $vgpr0 = V_ADD_F32_e32 undef $vgpr5, undef $vgpr5, implicit $exec
    ; GCN: $vgpr0 = V_ADD_F32_e32 undef $vgpr5, undef $vgpr5, implicit $mode, implicit $exec

    ; GCN: BUNDLE killed $vgpr0, killed $vgpr1, undef $vgpr3_vgpr4, implicit $exec {
    ; GCN: BUNDLE killed $vgpr0, killed $vgpr1, undef $vgpr3_vgpr4, implicit $exec {

    ; GCN:   GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, killed $vgpr1, 0, 0, 0, 0, implicit $exec
    ; GCN:   GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, killed $vgpr1, 0, 0, 0, 0, implicit $exec

    ; GCN:   GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, killed $vgpr0, 4, 0, 0, 0, implicit $exec
    ; GCN:   GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, killed $vgpr0, 4, 0, 0, 0, implicit $exec

    ; GCN: }
    ; GCN: }

    $vgpr0 = V_ADD_F32_e32 undef $vgpr5, undef $vgpr5, implicit $exec
    $vgpr0 = V_ADD_F32_e32 undef $vgpr5, undef $vgpr5, implicit $mode, implicit $exec

    $vgpr1 = V_ADD_F32_e32 undef $vgpr6, undef $vgpr6, implicit $exec
    $vgpr1 = V_ADD_F32_e32 undef $vgpr6, undef $vgpr6, implicit $mode, implicit $exec

    BUNDLE $vgpr0, $vgpr1, undef $vgpr3_vgpr4, implicit $exec {
    BUNDLE $vgpr0, $vgpr1, undef $vgpr3_vgpr4, implicit $exec {

      GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, $vgpr1, 0, 0, 0, 0, implicit $exec
      GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, $vgpr1, 0, 0, 0, 0, implicit $exec

      GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, $vgpr0, 4, 0, 0, 0, implicit $exec
      GLOBAL_STORE_DWORD undef $vgpr3_vgpr4, $vgpr0, 4, 0, 0, 0, implicit $exec

    }
    }

...
...

llvm/test/CodeGen/AMDGPU/clamp-omod-special-case.mir
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands  %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands  %s -o - | FileCheck -check-prefix=GCN %s

---
---

# GCN-LABEL: name: v_max_self_clamp_not_set_f32
# GCN-LABEL: name: v_max_self_clamp_not_set_f32

# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit $exec
# GCN-NEXT: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit $mode, implicit $exec




name:            v_max_self_clamp_not_set_f32
name:            v_max_self_clamp_not_set_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

Show All 37 Lines  bb.0:

    %11 = S_MOV_B32 0
    %11 = S_MOV_B32 0

    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2

    %13 = REG_SEQUENCE killed %5, 17, %12, 18
    %13 = REG_SEQUENCE killed %5, 17, %12, 18

    %14 = S_MOV_B32 2
    %14 = S_MOV_B32 2

    %26 = V_LSHL_B64 killed %25, 2, implicit $exec
    %26 = V_LSHL_B64 killed %25, 2, implicit $exec

    %16 = REG_SEQUENCE killed %4, 17, %12, 18
    %16 = REG_SEQUENCE killed %4, 17, %12, 18

    %18 = COPY %26
    %18 = COPY %26

    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit $exec
    %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# GCN-LABEL: name: v_clamp_omod_already_set_f32
# GCN-LABEL: name: v_clamp_omod_already_set_f32

# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

# GCN: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec
# GCN: %21:vgpr_32 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $mode, implicit $exec

name:            v_clamp_omod_already_set_f32
name:            v_clamp_omod_already_set_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

  - { id: 4, class: sreg_64_xexec }
  - { id: 4, class: sreg_64_xexec }

Show All 36 Lines  bb.0:

    %11 = S_MOV_B32 0
    %11 = S_MOV_B32 0

    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2

    %13 = REG_SEQUENCE killed %5, 17, %12, 18
    %13 = REG_SEQUENCE killed %5, 17, %12, 18

    %14 = S_MOV_B32 2
    %14 = S_MOV_B32 2

    %26 = V_LSHL_B64 killed %25, 2, implicit $exec
    %26 = V_LSHL_B64 killed %25, 2, implicit $exec

    %16 = REG_SEQUENCE killed %4, 17, %12, 18
    %16 = REG_SEQUENCE killed %4, 17, %12, 18

    %18 = COPY %26
    %18 = COPY %26

    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $exec
    %21 = V_MAX_F32_e64 0, killed %20, 0, killed %20, 1, 3, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# Don't fold a mul that looks like an omod if itself has omod set
# Don't fold a mul that looks like an omod if itself has omod set




# GCN-LABEL: name: v_omod_mul_omod_already_set_f32
# GCN-LABEL: name: v_omod_mul_omod_already_set_f32

# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec
# GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $mode, implicit $exec

name:            v_omod_mul_omod_already_set_f32
name:            v_omod_mul_omod_already_set_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

  - { id: 4, class: sreg_64_xexec }
  - { id: 4, class: sreg_64_xexec }

Show All 36 Lines  bb.0:

    %11 = S_MOV_B32 0
    %11 = S_MOV_B32 0

    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2

    %13 = REG_SEQUENCE killed %5, 17, %12, 18
    %13 = REG_SEQUENCE killed %5, 17, %12, 18

    %14 = S_MOV_B32 2
    %14 = S_MOV_B32 2

    %26 = V_LSHL_B64 killed %25, 2, implicit $exec
    %26 = V_LSHL_B64 killed %25, 2, implicit $exec

    %16 = REG_SEQUENCE killed %4, 17, %12, 18
    %16 = REG_SEQUENCE killed %4, 17, %12, 18

    %18 = COPY %26
    %18 = COPY %26

    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $exec
    %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 0, 3, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# Don't fold a mul that looks like an omod if itself has clamp set
# Don't fold a mul that looks like an omod if itself has clamp set

# This might be OK, but would require folding the clamp at the same time.
# This might be OK, but would require folding the clamp at the same time.

# GCN-LABEL: name: v_omod_mul_clamp_already_set_f32
# GCN-LABEL: name: v_omod_mul_clamp_already_set_f32

# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $exec
# GCN-NEXT: %21:vgpr_32 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $mode, implicit $exec




name:            v_omod_mul_clamp_already_set_f32
name:            v_omod_mul_clamp_already_set_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

Show All 37 Lines  bb.0:

    %11 = S_MOV_B32 0
    %11 = S_MOV_B32 0

    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2

    %13 = REG_SEQUENCE killed %5, 17, %12, 18
    %13 = REG_SEQUENCE killed %5, 17, %12, 18

    %14 = S_MOV_B32 2
    %14 = S_MOV_B32 2

    %26 = V_LSHL_B64 killed %25, 2, implicit $exec
    %26 = V_LSHL_B64 killed %25, 2, implicit $exec

    %16 = REG_SEQUENCE killed %4, 17, %12, 18
    %16 = REG_SEQUENCE killed %4, 17, %12, 18

    %18 = COPY %26
    %18 = COPY %26

    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $exec
    %21 = V_MUL_F32_e64 0, killed %20, 0, 1056964608, 1, 0, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...








































---
---

# Don't fold a mul that looks like an omod if itself has omod set
# Don't fold a mul that looks like an omod if itself has omod set




# GCN-LABEL: name: v_omod_add_omod_already_set_f32
# GCN-LABEL: name: v_omod_add_omod_already_set_f32

# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit $exec
# GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit $mode, implicit $exec

name:            v_omod_add_omod_already_set_f32
name:            v_omod_add_omod_already_set_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

  - { id: 4, class: sreg_64_xexec }
  - { id: 4, class: sreg_64_xexec }

Show All 36 Lines  bb.0:

    %11 = S_MOV_B32 0
    %11 = S_MOV_B32 0

    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2

    %13 = REG_SEQUENCE killed %5, 17, %12, 18
    %13 = REG_SEQUENCE killed %5, 17, %12, 18

    %14 = S_MOV_B32 2
    %14 = S_MOV_B32 2

    %26 = V_LSHL_B64 killed %25, 2, implicit $exec
    %26 = V_LSHL_B64 killed %25, 2, implicit $exec

    %16 = REG_SEQUENCE killed %4, 17, %12, 18
    %16 = REG_SEQUENCE killed %4, 17, %12, 18

    %18 = COPY %26
    %18 = COPY %26

    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit $exec
    %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 0, 3, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# Don't fold a mul that looks like an omod if itself has clamp set
# Don't fold a mul that looks like an omod if itself has clamp set

# This might be OK, but would require folding the clamp at the same time.
# This might be OK, but would require folding the clamp at the same time.

# GCN-LABEL: name: v_omod_add_clamp_already_set_f32
# GCN-LABEL: name: v_omod_add_clamp_already_set_f32

# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
# GCN: %20:vgpr_32 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $exec
# GCN-NEXT: %21:vgpr_32 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $mode, implicit $exec




name:            v_omod_add_clamp_already_set_f32
name:            v_omod_add_clamp_already_set_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

Show All 37 Lines  bb.0:

    %11 = S_MOV_B32 0
    %11 = S_MOV_B32 0

    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2
    %12 = REG_SEQUENCE killed %11, 1, killed %10, 2

    %13 = REG_SEQUENCE killed %5, 17, %12, 18
    %13 = REG_SEQUENCE killed %5, 17, %12, 18

    %14 = S_MOV_B32 2
    %14 = S_MOV_B32 2

    %26 = V_LSHL_B64 killed %25, 2, implicit $exec
    %26 = V_LSHL_B64 killed %25, 2, implicit $exec

    %16 = REG_SEQUENCE killed %4, 17, %12, 18
    %16 = REG_SEQUENCE killed %4, 17, %12, 18

    %18 = COPY %26
    %18 = COPY %26

    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %17 = BUFFER_LOAD_DWORD_ADDR64 %26, killed %13, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $exec
    %20 = V_ADD_F32_e64 0, killed %17, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $exec
    %21 = V_ADD_F32_e64 0, killed %20, 0, killed %20, 1, 0, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %21, %26, killed %16, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---




# Pass used to crash with immediate second operand of max
# Pass used to crash with immediate second operand of max

name:            v_max_reg_imm_f32
name:            v_max_reg_imm_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vgpr_32 }
  - { id: 0, class: vgpr_32 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    %0 = COPY $vgpr0
    %0 = COPY $vgpr0

    %1 = V_MAX_F32_e64 0, killed %0, 0, 1056964608, 1, 0, implicit $exec
    %1 = V_MAX_F32_e64 0, killed %0, 0, 1056964608, 1, 0, implicit $mode, implicit $exec




...
...

llvm/test/CodeGen/AMDGPU/cluster-flat-loads.mir
Show All 9 Linesregisters:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:

    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)

    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec

    %3 = FLAT_LOAD_DWORD %0, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %3 = FLAT_LOAD_DWORD %0, 4, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)

...
...

llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-copymi-not-live.mir
Show All 16 Lines
...
...




---
---

name:            _amdgpu_cs_main
name:            _amdgpu_cs_main

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    successors: %bb.1(0x40000000), %bb.2(0x40000000)
    successors: %bb.1(0x40000000), %bb.2(0x40000000)

    %0:vgpr_32 = V_MUL_F32_e32 0, undef %1:vgpr_32, implicit $exec
    %0:vgpr_32 = nofpexcept V_MUL_F32_e32 0, undef %1:vgpr_32, implicit $mode, implicit $exec

    %2:vgpr_32 = V_CVT_U32_F32_e32 killed %0, implicit $exec
    %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %0, implicit $mode, implicit $exec

    %3:vgpr_32 = V_CVT_F32_I32_e32 killed %2, implicit $exec
    %3:vgpr_32 = nofpexcept V_CVT_F32_I32_e32 killed %2, implicit $mode, implicit $exec

    %4:vgpr_32 = V_CVT_U32_F32_e32 killed %3, implicit $exec
    %4:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %3, implicit $mode, implicit $exec

    %5:vgpr_32 = V_LSHRREV_B32_e32 4, killed %4, implicit $exec
    %5:vgpr_32 = V_LSHRREV_B32_e32 4, killed %4, implicit $exec

    S_CBRANCH_SCC0 %bb.2, implicit undef $scc
    S_CBRANCH_SCC0 %bb.2, implicit undef $scc




  bb.1:
  bb.1:

    successors: %bb.5(0x80000000)
    successors: %bb.5(0x80000000)

    undef %6.sub1:vreg_128 = COPY killed %5
    undef %6.sub1:vreg_128 = COPY killed %5

    %7:vreg_128 = COPY killed %6
    %7:vreg_128 = COPY killed %6

    S_BRANCH %bb.5
    S_BRANCH %bb.5

▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines  bb.15:

    %27.sub1:sgpr_256 = COPY %26
    %27.sub1:sgpr_256 = COPY %26

    %27.sub2:sgpr_256 = COPY %26
    %27.sub2:sgpr_256 = COPY %26

    %27.sub3:sgpr_256 = COPY %26
    %27.sub3:sgpr_256 = COPY %26

    %27.sub4:sgpr_256 = COPY %26
    %27.sub4:sgpr_256 = COPY %26

    %27.sub5:sgpr_256 = COPY %26
    %27.sub5:sgpr_256 = COPY %26

    %27.sub6:sgpr_256 = COPY %26
    %27.sub6:sgpr_256 = COPY %26

    %27.sub7:sgpr_256 = COPY killed %26
    %27.sub7:sgpr_256 = COPY killed %26

    %28:vgpr_32 = IMAGE_LOAD_V1_V4 killed %25, killed %27, 2, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
    %28:vgpr_32 = IMAGE_LOAD_V1_V4 killed %25, killed %27, 2, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)

    %29:vgpr_32 = V_ADD_F32_e32 0, killed %28, implicit $exec
    %29:vgpr_32 = nofpexcept V_ADD_F32_e32 0, killed %28, implicit $mode, implicit $exec

    $m0 = S_MOV_B32 -1
    $m0 = S_MOV_B32 -1

    DS_WRITE_B32 undef %30:vgpr_32, killed %29, 0, 0, implicit $m0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`, addrspace 3)
    DS_WRITE_B32 undef %30:vgpr_32, killed %29, 0, 0, implicit $m0, implicit $exec :: (store 4 into `i32 addrspace(3)* undef`, addrspace 3)

    S_ENDPGM 0
    S_ENDPGM 0

...
...

llvm/test/CodeGen/AMDGPU/coalescer-subranges-another-prune-error.mir
Show All 35 Lines  bb.1:

    successors: %bb.3(0x80000000)
    successors: %bb.3(0x80000000)

    %3:sgpr_128 = COPY killed %2
    %3:sgpr_128 = COPY killed %2

    %4:vreg_128 = COPY killed %3
    %4:vreg_128 = COPY killed %3

    %5:vreg_128 = COPY killed %4
    %5:vreg_128 = COPY killed %4

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.2:
  bb.2:

    successors: %bb.4(0x80000000)
    successors: %bb.4(0x80000000)

    %6:vgpr_32 = V_MUL_F32_e32 1031798784, undef %7:vgpr_32, implicit $exec
    %6:vgpr_32 = nofpexcept V_MUL_F32_e32 1031798784, undef %7:vgpr_32, implicit $mode, implicit $exec

    %8:vgpr_32 = V_FLOOR_F32_e32 killed %6, implicit $exec
    %8:vgpr_32 = nofpexcept V_FLOOR_F32_e32 killed %6, implicit $mode, implicit $exec

    %9:vgpr_32 = V_ADD_F32_e32 0, killed %8, implicit $exec
    %9:vgpr_32 = nofpexcept V_ADD_F32_e32 0, killed %8, implicit $mode, implicit $exec

    %10:vgpr_32 = V_CVT_U32_F32_e32 killed %9, implicit $exec
    %10:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %9, implicit $mode, implicit $exec

    %11:vgpr_32 = V_LSHLREV_B32_e32 1, killed %10, implicit $exec
    %11:vgpr_32 = V_LSHLREV_B32_e32 1, killed %10, implicit $exec

    %12:sreg_64 = S_MOV_B64 0
    %12:sreg_64 = S_MOV_B64 0

    %13:sgpr_128 = COPY killed %2
    %13:sgpr_128 = COPY killed %2

    %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %15:vreg_128 = COPY killed %13
    %15:vreg_128 = COPY killed %13

    %16:sreg_64 = COPY killed %12
    %16:sreg_64 = COPY killed %12

    %17:vreg_128 = IMPLICIT_DEF
    %17:vreg_128 = IMPLICIT_DEF

    %18:vgpr_32 = COPY killed %14
    %18:vgpr_32 = COPY killed %14

▲ Show 20 Lines • Show All 182 Lines • ▼ Show 20 Lines  bb.16:

    successors: %bb.3(0x80000000)
    successors: %bb.3(0x80000000)

    $exec = S_OR_B64 $exec, killed %95, implicit-def $scc
    $exec = S_OR_B64 $exec, killed %95, implicit-def $scc

    %103:vreg_128 = COPY killed %94
    %103:vreg_128 = COPY killed %94

    %104:vreg_128 = COPY killed %103
    %104:vreg_128 = COPY killed %103

    %5:vreg_128 = COPY killed %104
    %5:vreg_128 = COPY killed %104

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.17:
  bb.17:

    %105:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-rel32-lo) 0, %20.sub3, implicit $exec
    %105:vgpr_32 = nofpexcept V_ADD_F32_e32 target-flags(amdgpu-rel32-lo) 0, %20.sub3, implicit $mode, implicit $exec

    %106:vgpr_32 = V_ADD_F32_e32 target-flags(amdgpu-gotprel32-hi) 0, killed %20.sub2, implicit $exec
    %106:vgpr_32 = nofpexcept V_ADD_F32_e32 target-flags(amdgpu-gotprel32-hi) 0, killed %20.sub2, implicit $mode, implicit $exec

    undef %107.sub0:vreg_64 = COPY killed %106
    undef %107.sub0:vreg_64 = COPY killed %106

    %107.sub1:vreg_64 = COPY killed %105
    %107.sub1:vreg_64 = COPY killed %105

    $exec = S_AND_B64 $exec, killed %0, implicit-def dead $scc
    $exec = S_AND_B64 $exec, killed %0, implicit-def dead $scc

    %108:sreg_32_xm0 = S_MOV_B32 0
    %108:sreg_32_xm0 = S_MOV_B32 0

    undef %109.sub0:sgpr_256 = COPY %108
    undef %109.sub0:sgpr_256 = COPY %108

    %109.sub1:sgpr_256 = COPY %108
    %109.sub1:sgpr_256 = COPY %108

    %109.sub2:sgpr_256 = COPY %108
    %109.sub2:sgpr_256 = COPY %108

    %109.sub3:sgpr_256 = COPY %108
    %109.sub3:sgpr_256 = COPY %108

    %109.sub4:sgpr_256 = COPY %108
    %109.sub4:sgpr_256 = COPY %108

    %109.sub5:sgpr_256 = COPY %108
    %109.sub5:sgpr_256 = COPY %108

    %109.sub6:sgpr_256 = COPY %108
    %109.sub6:sgpr_256 = COPY %108

    %109.sub7:sgpr_256 = COPY killed %108
    %109.sub7:sgpr_256 = COPY killed %108

    %110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sgpr_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
    %110:vgpr_32 = IMAGE_SAMPLE_V1_V2 killed %107, killed %109, undef %111:sgpr_128, 8, 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)

    %112:vgpr_32 = V_MUL_F32_e32 0, killed %110, implicit $exec
    %112:vgpr_32 = nofpexcept V_MUL_F32_e32 0, killed %110, implicit $mode, implicit $exec

    %113:vgpr_32 = V_MUL_F32_e32 0, killed %112, implicit $exec
    %113:vgpr_32 = nofpexcept V_MUL_F32_e32 0, killed %112, implicit $mode, implicit $exec

    %114:vgpr_32 = V_MAD_F32 0, killed %113, 0, 0, 0, 0, 0, 0, implicit $exec
    %114:vgpr_32 = nofpexcept V_MAD_F32 0, killed %113, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %115:vgpr_32 = V_MAX_F32_e32 0, killed %114, implicit $exec
    %115:vgpr_32 = nofpexcept V_MAX_F32_e32 0, killed %114, implicit $mode, implicit $exec

    %116:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %115, 0, 1065353216, 0, 0, implicit $exec
    %116:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, killed %115, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    EXP 0, undef %117:vgpr_32, killed %116, undef %118:vgpr_32, undef %119:vgpr_32, -1, -1, 15, implicit $exec
    EXP 0, undef %117:vgpr_32, killed %116, undef %118:vgpr_32, undef %119:vgpr_32, -1, -1, 15, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

llvm/test/CodeGen/AMDGPU/coalescer-subregjoin-fullcopy.mir
Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Lines  bb.6:

    successors: %bb.7(0x40000000), %bb.18(0x40000000)
    successors: %bb.7(0x40000000), %bb.18(0x40000000)

    %9:vreg_128 = COPY killed %6
    %9:vreg_128 = COPY killed %6

    %10:sreg_64 = COPY killed %5
    %10:sreg_64 = COPY killed %5

    undef %11.sub2:sgpr_128 = COPY %4
    undef %11.sub2:sgpr_128 = COPY %4

    %11.sub3:sgpr_128 = COPY %3
    %11.sub3:sgpr_128 = COPY %3

    %12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %12:vreg_128 = BUFFER_LOAD_DWORDX4_OFFSET killed %11, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    undef %13.sub1:vreg_128 = COPY %9.sub1
    undef %13.sub1:vreg_128 = COPY %9.sub1

    %13.sub2:vreg_128 = COPY %9.sub2
    %13.sub2:vreg_128 = COPY %9.sub2

    %14:sreg_64 = V_CMP_GT_F32_e64 0, target-flags(amdgpu-rel32-lo) 0, 0, killed %12.sub3, 0, implicit $exec
    %14:sreg_64 = nofpexcept V_CMP_GT_F32_e64 0, target-flags(amdgpu-rel32-lo) 0, 0, killed %12.sub3, 0, implicit $mode, implicit $exec

    %15:vgpr_32 = V_ADD_F32_e32 1065353216, undef %16:vgpr_32, implicit $exec
    %15:vgpr_32 = nofpexcept V_ADD_F32_e32 1065353216, undef %16:vgpr_32, implicit $mode, implicit $exec

    %17:sreg_64 = V_CMP_GT_F32_e64 0, 0, 0, killed %15, 0, implicit $exec
    %17:sreg_64 = nofpexcept V_CMP_GT_F32_e64 0, 0, 0, killed %15, 0, implicit $mode, implicit $exec

    %18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc
    %18:sreg_64 = S_AND_B64 killed %17, killed %14, implicit-def dead $scc

    %19:sreg_64 = COPY %10
    %19:sreg_64 = COPY %10

    %20:vreg_128 = COPY %13
    %20:vreg_128 = COPY %13

    %21:vreg_128 = IMPLICIT_DEF
    %21:vreg_128 = IMPLICIT_DEF

    %22:sreg_64 = COPY $exec, implicit-def $exec
    %22:sreg_64 = COPY $exec, implicit-def $exec

    %23:sreg_64 = S_AND_B64 %22, %18, implicit-def dead $scc
    %23:sreg_64 = S_AND_B64 %22, %18, implicit-def dead $scc

    %24:sreg_64 = S_XOR_B64 %23, %22, implicit-def dead $scc
    %24:sreg_64 = S_XOR_B64 %23, %22, implicit-def dead $scc

    $exec = S_MOV_B64_term killed %23
    $exec = S_MOV_B64_term killed %23

Show All 36 Linesbody: |




  bb.12:
  bb.12:

    successors: %bb.13(0x80000000)
    successors: %bb.13(0x80000000)

    S_CBRANCH_SCC1 %bb.13, implicit undef $scc
    S_CBRANCH_SCC1 %bb.13, implicit undef $scc

    S_BRANCH %bb.13
    S_BRANCH %bb.13




  bb.13:
  bb.13:

    successors: %bb.14(0x80000000)
    successors: %bb.14(0x80000000)

    %32:vgpr_32 = V_MUL_F32_e32 undef %33:vgpr_32, killed %30.sub1, implicit $exec
    %32:vgpr_32 = nofpexcept V_MUL_F32_e32 undef %33:vgpr_32, killed %30.sub1, implicit $mode, implicit $exec

    %34:vgpr_32 = V_MUL_F32_e32 undef %35:vgpr_32, killed %32, implicit $exec
    %34:vgpr_32 = nofpexcept V_MUL_F32_e32 undef %35:vgpr_32, killed %32, implicit $mode, implicit $exec

    undef %36.sub0:vreg_128 = COPY %34
    undef %36.sub0:vreg_128 = COPY %34

    %31:vreg_128 = COPY killed %36
    %31:vreg_128 = COPY killed %36




  bb.14:
  bb.14:

    successors: %bb.16(0x40000000), %bb.15(0x40000000)
    successors: %bb.16(0x40000000), %bb.15(0x40000000)

    %37:vreg_128 = COPY killed %31
    %37:vreg_128 = COPY killed %31

    S_CBRANCH_SCC0 %bb.16, implicit undef $scc
    S_CBRANCH_SCC0 %bb.16, implicit undef $scc




  bb.15:
  bb.15:

    successors: %bb.17(0x80000000)
    successors: %bb.17(0x80000000)

    %38:vreg_128 = IMPLICIT_DEF
    %38:vreg_128 = IMPLICIT_DEF

    S_BRANCH %bb.17
    S_BRANCH %bb.17




  bb.16:
  bb.16:

    successors: %bb.17(0x80000000)
    successors: %bb.17(0x80000000)

    %39:vgpr_32 = V_FMA_F32 0, undef %40:vgpr_32, 0, killed %37.sub0, 0, undef %41:vgpr_32, 0, 0, implicit $exec
    %39:vgpr_32 = nofpexcept V_FMA_F32 0, undef %40:vgpr_32, 0, killed %37.sub0, 0, undef %41:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %42:vgpr_32 = V_FMA_F32 0, undef %43:vgpr_32, 0, undef %44:vgpr_32, 0, killed %39, 0, 0, implicit $exec
    %42:vgpr_32 = nofpexcept V_FMA_F32 0, undef %43:vgpr_32, 0, undef %44:vgpr_32, 0, killed %39, 0, 0, implicit $mode, implicit $exec

    %45:vgpr_32 = V_FMA_F32 0, undef %46:vgpr_32, 0, undef %47:vgpr_32, 0, killed %42, 0, 0, implicit $exec
    %45:vgpr_32 = nofpexcept V_FMA_F32 0, undef %46:vgpr_32, 0, undef %47:vgpr_32, 0, killed %42, 0, 0, implicit $mode, implicit $exec

    dead %48:vgpr_32 = V_MUL_F32_e32 undef %49:vgpr_32, killed %45, implicit $exec
    dead %48:vgpr_32 = nofpexcept V_MUL_F32_e32 undef %49:vgpr_32, killed %45, implicit $mode, implicit $exec

    %50:vgpr_32 = V_MUL_F32_e32 undef %51:vgpr_32, undef %52:vgpr_32, implicit $exec
    %50:vgpr_32 = nofpexcept V_MUL_F32_e32 undef %51:vgpr_32, undef %52:vgpr_32, implicit $mode, implicit $exec

    undef %53.sub1:vreg_128 = COPY %50
    undef %53.sub1:vreg_128 = COPY %50

    %38:vreg_128 = COPY killed %53
    %38:vreg_128 = COPY killed %53




  bb.17:
  bb.17:

    %54:vreg_128 = COPY killed %38
    %54:vreg_128 = COPY killed %38

    %55:vgpr_32 = V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $exec
    %55:vgpr_32 = nofpexcept V_FMA_F32 0, killed %54.sub1, 0, target-flags(amdgpu-gotprel32-lo) 1056964608, 0, 1056964608, 0, 0, implicit $mode, implicit $exec

    EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec
    EXP 1, undef %56:vgpr_32, killed %55, undef %57:vgpr_32, undef %58:vgpr_32, -1, 0, 15, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




  bb.18:
  bb.18:

    successors: %bb.7(0x80000000)
    successors: %bb.7(0x80000000)

    dead %59:vgpr_32 = V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $exec
    dead %59:vgpr_32 = nofpexcept V_FMA_F32 0, killed %9.sub2, 0, undef %60:vgpr_32, 0, undef %61:vgpr_32, 0, 0, implicit $mode, implicit $exec

    dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sgpr_128, undef %65:sreg_32, 0, 0, 0, 0, 0, 0, implicit $exec
    dead %62:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN undef %63:vgpr_32, undef %64:sgpr_128, undef %65:sreg_32, 0, 0, 0, 0, 0, 0, implicit $exec

    undef %66.sub1:vreg_128 = COPY %13.sub1
    undef %66.sub1:vreg_128 = COPY %13.sub1

    %66.sub2:vreg_128 = COPY %13.sub2
    %66.sub2:vreg_128 = COPY %13.sub2

    %67:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $exec
    %67:sreg_64 = nofpexcept V_CMP_NGT_F32_e64 0, 0, 0, undef %68:vgpr_32, 0, implicit $mode, implicit $exec

    %69:vgpr_32 = V_ADD_F32_e32 1065353216, undef %70:vgpr_32, implicit $exec
    %69:vgpr_32 = nofpexcept V_ADD_F32_e32 1065353216, undef %70:vgpr_32, implicit $mode, implicit $exec

    %71:vgpr_32 = V_ADD_F32_e32 1065353216, killed %69, implicit $exec
    %71:vgpr_32 = nofpexcept V_ADD_F32_e32 1065353216, killed %69, implicit $mode, implicit $exec

    %72:sreg_64 = V_CMP_NGT_F32_e64 0, 0, 0, killed %71, 0, implicit $exec
    %72:sreg_64 = nofpexcept V_CMP_NGT_F32_e64 0, 0, 0, killed %71, 0, implicit $mode, implicit $exec

    %73:sreg_64 = S_OR_B64 killed %72, killed %67, implicit-def dead $scc
    %73:sreg_64 = S_OR_B64 killed %72, killed %67, implicit-def dead $scc

    %74:sreg_64 = S_OR_B64 killed %73, killed %10, implicit-def dead $scc
    %74:sreg_64 = S_OR_B64 killed %73, killed %10, implicit-def dead $scc

    %19:sreg_64 = COPY killed %74
    %19:sreg_64 = COPY killed %74

    %20:vreg_128 = COPY %66
    %20:vreg_128 = COPY %66

    %21:vreg_128 = COPY killed %66
    %21:vreg_128 = COPY killed %66

    S_BRANCH %bb.7
    S_BRANCH %bb.7

...
...

llvm/test/CodeGen/AMDGPU/coalescer-with-subregs-bad-identical.mir
Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines  bb.2:

    %4.sub1:sgpr_256 = COPY %1
    %4.sub1:sgpr_256 = COPY %1

    %4.sub2:sgpr_256 = COPY %1
    %4.sub2:sgpr_256 = COPY %1

    %4.sub3:sgpr_256 = COPY %1
    %4.sub3:sgpr_256 = COPY %1

    %4.sub4:sgpr_256 = COPY %1
    %4.sub4:sgpr_256 = COPY %1

    %4.sub5:sgpr_256 = COPY %1
    %4.sub5:sgpr_256 = COPY %1

    %4.sub6:sgpr_256 = COPY %1
    %4.sub6:sgpr_256 = COPY %1

    %4.sub7:sgpr_256 = COPY killed %1
    %4.sub7:sgpr_256 = COPY killed %1

    %5:vgpr_32 = IMAGE_LOAD_V1_V4 killed %3, killed %4, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
    %5:vgpr_32 = IMAGE_LOAD_V1_V4 killed %3, killed %4, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)

    %6:vgpr_32 = V_MAD_F32 0, killed %5, 0, 0, 0, 0, 0, 0, implicit $exec
    %6:vgpr_32 = nofpexcept V_MAD_F32 0, killed %5, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %7:vgpr_32 = V_RCP_F32_e32 killed %6, implicit $exec
    %7:vgpr_32 = nofpexcept V_RCP_F32_e32 killed %6, implicit $mode, implicit $exec

    %8:vgpr_32 = V_MUL_F32_e32 0, killed %7, implicit $exec
    %8:vgpr_32 = nofpexcept V_MUL_F32_e32 0, killed %7, implicit $mode, implicit $exec

    %9:vgpr_32 = V_MAD_F32 0, killed %8, 0, 0, 0, 0, 0, 0, implicit $exec
    %9:vgpr_32 = nofpexcept V_MAD_F32 0, killed %8, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    dead %10:vgpr_32 = V_MAC_F32_e32 undef %11:vgpr_32, undef %12:vgpr_32, undef %10, implicit $exec
    dead %10:vgpr_32 = nofpexcept V_MAC_F32_e32 undef %11:vgpr_32, undef %12:vgpr_32, undef %10, implicit $mode, implicit $exec

    undef %13.sub0:vreg_128 = COPY %9
    undef %13.sub0:vreg_128 = COPY %9

    %14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
    %14:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec

    S_CBRANCH_SCC0 %bb.4, implicit undef $scc
    S_CBRANCH_SCC0 %bb.4, implicit undef $scc




  bb.3:
  bb.3:

    successors: %bb.6(0x80000000)
    successors: %bb.6(0x80000000)

    %15:vreg_128 = IMPLICIT_DEF
    %15:vreg_128 = IMPLICIT_DEF

    %16:vgpr_32 = COPY killed %14
    %16:vgpr_32 = COPY killed %14

    S_BRANCH %bb.6
    S_BRANCH %bb.6




  bb.4:
  bb.4:

    successors: %bb.5(0x40000000), %bb.7(0x40000000)
    successors: %bb.5(0x40000000), %bb.7(0x40000000)

    %17:vgpr_32 = V_MAD_F32 0, killed %9, 0, 0, 0, 0, 0, 0, implicit $exec
    %17:vgpr_32 = nofpexcept V_MAD_F32 0, killed %9, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %18:vgpr_32 = V_MIN_F32_e32 1065353216, killed %17, implicit $exec
    %18:vgpr_32 = nofpexcept V_MIN_F32_e32 1065353216, killed %17, implicit $mode, implicit $exec

    %19:sreg_64_xexec = V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %18, 0, implicit $exec
    %19:sreg_64_xexec = nofpexcept V_CMP_NEQ_F32_e64 0, 1065353216, 0, killed %18, 0, implicit $mode, implicit $exec

    %20:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
    %20:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec

    %21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, killed %20, killed %19, implicit $exec
    %21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, killed %20, killed %19, implicit $exec

    %22:sreg_64 = V_CMP_LT_F32_e64 0, 0, 0, killed %21, 0, implicit $exec
    %22:sreg_64 = nofpexcept V_CMP_LT_F32_e64 0, 0, 0, killed %21, 0, implicit $mode, implicit $exec

    %23:sreg_64 = COPY $exec, implicit-def $exec
    %23:sreg_64 = COPY $exec, implicit-def $exec

    %24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc
    %24:sreg_64 = S_AND_B64 %23, %22, implicit-def dead $scc

    $exec = S_MOV_B64_term killed %24
    $exec = S_MOV_B64_term killed %24

    SI_MASK_BRANCH %bb.7, implicit $exec
    SI_MASK_BRANCH %bb.7, implicit $exec

    S_BRANCH %bb.5
    S_BRANCH %bb.5




  bb.5:
  bb.5:

    successors: %bb.7(0x80000000)
    successors: %bb.7(0x80000000)

▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesbody: |




  bb.13:
  bb.13:

    successors: %bb.10(0x80000000)
    successors: %bb.10(0x80000000)

    %29:vreg_128 = COPY killed %37
    %29:vreg_128 = COPY killed %37

    S_BRANCH %bb.10
    S_BRANCH %bb.10




  bb.14:
  bb.14:

    successors: %bb.15(0x40000000), %bb.16(0x40000000)
    successors: %bb.15(0x40000000), %bb.16(0x40000000)

    %38:vgpr_32 = V_MAD_F32 0, killed %36.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
    %38:vgpr_32 = nofpexcept V_MAD_F32 0, killed %36.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %39:vgpr_32 = V_MAD_F32 0, killed %38, 0, 0, 0, 0, 0, 0, implicit $exec
    %39:vgpr_32 = nofpexcept V_MAD_F32 0, killed %38, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %40:vgpr_32 = V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $exec
    %40:vgpr_32 = nofpexcept V_MAD_F32 0, killed %39, 0, -1090519040, 0, 1056964608, 0, 0, implicit $mode, implicit $exec

    %41:vgpr_32 = V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $exec
    %41:vgpr_32 = nofpexcept V_MAD_F32 0, killed %40, 0, 0, 0, -1090519040, 0, 0, implicit $mode, implicit $exec

    %42:vgpr_32 = V_CVT_I32_F32_e32 killed %41, implicit $exec
    %42:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 killed %41, implicit $mode, implicit $exec

    %43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sgpr_128, 12, 0, 0 :: (dereferenceable invariant load 4)
    %43:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %44:sgpr_128, 12, 0, 0 :: (dereferenceable invariant load 4)

    %45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec
    %45:vgpr_32 = V_MUL_LO_I32 killed %42, killed %43, implicit $exec

    %46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec
    %46:vgpr_32 = V_LSHLREV_B32_e32 2, killed %45, implicit $exec

    %47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)
    %47:vgpr_32 = BUFFER_LOAD_FORMAT_X_IDXEN killed %46, undef %48:sgpr_128, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 4 from constant-pool, align 1, addrspace 4)

    %49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec
    %49:sreg_64 = V_CMP_NE_U32_e64 0, killed %47, implicit $exec

    %50:sreg_64 = COPY $exec, implicit-def $exec
    %50:sreg_64 = COPY $exec, implicit-def $exec

    %51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc
    %51:sreg_64 = S_AND_B64 %50, %49, implicit-def dead $scc

    $exec = S_MOV_B64_term killed %51
    $exec = S_MOV_B64_term killed %51

Show All 29 Lines
llvm/test/CodeGen/AMDGPU/couldnt-join-subrange-3.mir
Show All 11 Lines
machineFunctionInfo:
machineFunctionInfo:

  argumentInfo:
  argumentInfo:

    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }
    privateSegmentBuffer: { reg: '$sgpr0_sgpr1_sgpr2_sgpr3' }

    privateSegmentWaveByteOffset: { reg: '$sgpr33' }
    privateSegmentWaveByteOffset: { reg: '$sgpr33' }

body:             |
body:             |

  ; GCN-LABEL: name: _amdgpu_ps_main
  ; GCN-LABEL: name: _amdgpu_ps_main

  ; GCN: bb.0:
  ; GCN: bb.0:

  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   successors: %bb.1(0x80000000)

  ; GCN:   [[V_TRUNC_F32_e32_:%[0-9]+]]:vgpr_32 = V_TRUNC_F32_e32 undef %4:vgpr_32, implicit $exec
  ; GCN:   %3:vgpr_32 = nofpexcept V_TRUNC_F32_e32 undef %4:vgpr_32, implicit $mode, implicit $exec

  ; GCN:   [[V_CVT_U32_F32_e32_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e32 [[V_TRUNC_F32_e32_]], implicit $exec
  ; GCN:   %5:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec

  ; GCN:   [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 4, [[V_CVT_U32_F32_e32_]], implicit $exec
  ; GCN:   [[V_LSHRREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e32 4, %5, implicit $exec

  ; GCN:   undef %11.sub0:vreg_128 = V_MUL_LO_I32 [[V_LSHRREV_B32_e32_]], 3, implicit $exec
  ; GCN:   undef %11.sub0:vreg_128 = V_MUL_LO_I32 [[V_LSHRREV_B32_e32_]], 3, implicit $exec

  ; GCN:   %11.sub3:vreg_128 = COPY %11.sub0
  ; GCN:   %11.sub3:vreg_128 = COPY %11.sub0

  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
  ; GCN:   [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0

  ; GCN: bb.1:
  ; GCN: bb.1:

  ; GCN:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
  ; GCN:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)

  ; GCN:   [[COPY:%[0-9]+]]:vreg_128 = COPY %11
  ; GCN:   [[COPY:%[0-9]+]]:vreg_128 = COPY %11

  ; GCN:   %11.sub3:vreg_128 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, [[COPY]].sub3, implicit $exec
  ; GCN:   %11.sub3:vreg_128 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, [[COPY]].sub3, implicit $exec

  ; GCN:   [[S_ADD_I32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_I32 [[S_ADD_I32_]], 1, implicit-def dead $scc
  ; GCN:   [[S_ADD_I32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_I32 [[S_ADD_I32_]], 1, implicit-def dead $scc

Show All 11 Linesbody:             |

  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc
  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc

  ; GCN:   dead %20:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; GCN:   dead %20:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

  ; GCN: bb.4:
  ; GCN: bb.4:

  ; GCN:   successors: %bb.4(0x7c000000), %bb.6(0x04000000)
  ; GCN:   successors: %bb.4(0x7c000000), %bb.6(0x04000000)

  ; GCN:   $vcc = COPY [[S_AND_B64_]]
  ; GCN:   $vcc = COPY [[S_AND_B64_]]

  ; GCN:   S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
  ; GCN:   S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc

  ; GCN:   S_BRANCH %bb.6
  ; GCN:   S_BRANCH %bb.6

  ; GCN: bb.5:
  ; GCN: bb.5:

  ; GCN:   [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, %11.sub0, implicit $exec
  ; GCN:   %21:vgpr_32 = nofpexcept V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, %11.sub0, implicit $mode, implicit $exec

  ; GCN:   [[V_MIN_F32_e32_:%[0-9]+]]:vgpr_32 = V_MIN_F32_e32 1106771968, [[V_MUL_F32_e32_]], implicit $exec
  ; GCN:   %22:vgpr_32 = nofpexcept V_MIN_F32_e32 1106771968, %21, implicit $mode, implicit $exec

  ; GCN:   [[V_MAD_F32_:%[0-9]+]]:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, [[V_MIN_F32_e32_]], 0, 0, 0, 0, 0, 0, implicit $exec
  ; GCN:   %23:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, %22, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

  ; GCN:   [[V_MAD_F32_1:%[0-9]+]]:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, [[V_MAD_F32_]], 0, 0, 0, 0, 0, 0, implicit $exec
  ; GCN:   %24:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, %23, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

  ; GCN:   [[V_MAD_F32_2:%[0-9]+]]:vgpr_32 = V_MAD_F32 0, [[V_MAD_F32_1]], 0, 0, 0, 0, 0, 0, implicit $exec
  ; GCN:   %25:vgpr_32 = nofpexcept V_MAD_F32 0, %24, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

  ; GCN:   [[V_CVT_PKRTZ_F16_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, [[V_MAD_F32_2]], 0, undef %27:vgpr_32, 0, 0, implicit $exec
  ; GCN:   %26:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, %25, 0, undef %27:vgpr_32, 0, 0, implicit $mode, implicit $exec

  ; GCN:   EXP_DONE 0, [[V_CVT_PKRTZ_F16_F32_e64_]], undef %28:vgpr_32, undef %29:vgpr_32, undef %30:vgpr_32, -1, -1, 15, implicit $exec
  ; GCN:   EXP_DONE 0, %26, undef %28:vgpr_32, undef %29:vgpr_32, undef %30:vgpr_32, -1, -1, 15, implicit $exec

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  ; GCN: bb.6:
  ; GCN: bb.6:

  ; GCN:   S_ENDPGM 0
  ; GCN:   S_ENDPGM 0

  bb.0:
  bb.0:

    %10:vgpr_32 = V_TRUNC_F32_e32 undef %11:vgpr_32, implicit $exec
    %10:vgpr_32 = nofpexcept V_TRUNC_F32_e32 undef %11:vgpr_32, implicit $mode, implicit $exec

    %12:vgpr_32 = V_CVT_U32_F32_e32 killed %10, implicit $exec
    %12:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %10, implicit $mode, implicit $exec

    %50:vgpr_32 = V_LSHRREV_B32_e32 4, killed %12, implicit $exec
    %50:vgpr_32 = V_LSHRREV_B32_e32 4, killed %12, implicit $exec

    %51:vgpr_32 = V_MUL_LO_I32 killed %50, 3, implicit $exec
    %51:vgpr_32 = V_MUL_LO_I32 killed %50, 3, implicit $exec

    undef %52.sub0:vreg_128 = COPY %51
    undef %52.sub0:vreg_128 = COPY %51

    %52.sub3:vreg_128 = COPY %51
    %52.sub3:vreg_128 = COPY %51

    %9:sreg_32_xm0 = S_MOV_B32 0
    %9:sreg_32_xm0 = S_MOV_B32 0

    %70:sreg_32_xm0 = COPY killed %9
    %70:sreg_32_xm0 = COPY killed %9

    %71:vreg_128 = COPY killed %52
    %71:vreg_128 = COPY killed %52




Show All 26 Linesbody:             |

  bb.4:
  bb.4:

    successors: %bb.4(0x7c000000), %bb.6(0x04000000)
    successors: %bb.4(0x7c000000), %bb.6(0x04000000)




    $vcc = COPY %36
    $vcc = COPY %36

    S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
    S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc

    S_BRANCH %bb.6
    S_BRANCH %bb.6




  bb.5:
  bb.5:

    %39:vgpr_32 = V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, killed %55.sub0, implicit $exec
    %39:vgpr_32 = nofpexcept V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, killed %55.sub0, implicit $mode, implicit $exec

    %41:vgpr_32 = V_MIN_F32_e32 1106771968, killed %39, implicit $exec
    %41:vgpr_32 = nofpexcept V_MIN_F32_e32 1106771968, killed %39, implicit $mode, implicit $exec

    %42:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %41, 0, 0, 0, 0, 0, 0, implicit $exec
    %42:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %41, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %43:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %42, 0, 0, 0, 0, 0, 0, implicit $exec
    %43:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %42, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %44:vgpr_32 = V_MAD_F32 0, killed %43, 0, 0, 0, 0, 0, 0, implicit $exec
    %44:vgpr_32 = nofpexcept V_MAD_F32 0, killed %43, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %45:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %44, 0, undef %46:vgpr_32, 0, 0, implicit $exec
    %45:vgpr_32 = nofpexcept V_CVT_PKRTZ_F16_F32_e64 0, killed %44, 0, undef %46:vgpr_32, 0, 0, implicit $mode, implicit $exec

    EXP_DONE 0, killed %45, undef %47:vgpr_32, undef %48:vgpr_32, undef %49:vgpr_32, -1, -1, 15, implicit $exec
    EXP_DONE 0, killed %45, undef %47:vgpr_32, undef %48:vgpr_32, undef %49:vgpr_32, -1, -1, 15, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




  bb.6:
  bb.6:

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/dead-lane.mir
# RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=tonga %s -start-before detect-dead-lanes -stop-before machine-scheduler -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s




# GCN-LABEL: name: dead_lane
# GCN-LABEL: name: dead_lane

# GCN:      bb.0:
# GCN:      bb.0:

# GCN-NEXT: undef %3.sub0:vreg_64 = V_MAC_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, undef %3.sub0, implicit $exec
# GCN-NEXT: undef %3.sub0:vreg_64 = nofpexcept V_MAC_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, undef %3.sub0, implicit $mode, implicit $exec

# GCN-NEXT: FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0,
# GCN-NEXT: FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0,

---
---

name:            dead_lane
name:            dead_lane

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    %1:vgpr_32 = V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $exec
    %1:vgpr_32 = nofpexcept V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $mode, implicit $exec

    %2:vgpr_32 = V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $exec
    %2:vgpr_32 = nofpexcept V_MAC_F32_e32 undef %0:vgpr_32, undef %0:vgpr_32, undef %0:vgpr_32, implicit $mode, implicit $exec

    %3:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, %2:vgpr_32, %subreg.sub1
    %3:vreg_64 = REG_SEQUENCE %1:vgpr_32, %subreg.sub0, %2:vgpr_32, %subreg.sub1

    FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
    FLAT_STORE_DWORD undef %4:vreg_64, %3.sub0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/debug-value-scheduler-crash.mir
Show All 26 Linesbody:             |

  ; CHECK:   [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF3:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF6:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF7:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[V_MUL_F32_e32_:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 1082130432, [[DEF1]], implicit $exec
  ; CHECK:   %9:vgpr_32 = nofpexcept V_MUL_F32_e32 1082130432, [[DEF1]], implicit $mode, implicit $exec

  ; CHECK:   [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF9:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF10:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK: bb.1:
  ; CHECK: bb.1:

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   DBG_VALUE
  ; CHECK:   DBG_VALUE

  ; CHECK:   DBG_VALUE
  ; CHECK:   DBG_VALUE

  ; CHECK:   DBG_VALUE
  ; CHECK:   DBG_VALUE

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   successors: %bb.3(0x80000000)
  ; CHECK:   successors: %bb.3(0x80000000)

  ; CHECK:   S_BRANCH %bb.3
  ; CHECK:   S_BRANCH %bb.3

  ; CHECK: bb.3:
  ; CHECK: bb.3:

  ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

  ; CHECK:   [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF11:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF12:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]
  ; CHECK:   [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]

  ; CHECK:   [[V_MUL_F32_e32_1:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
  ; CHECK:   %16:vgpr_32 = nofpexcept V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $mode, implicit $exec

  ; CHECK:   [[V_MUL_F32_e32_2:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
  ; CHECK:   %17:vgpr_32 = nofpexcept V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $mode, implicit $exec

  ; CHECK:   [[V_MUL_F32_e32_3:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $exec
  ; CHECK:   %18:vgpr_32 = nofpexcept V_MUL_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $mode, implicit $exec

  ; CHECK:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
  ; CHECK:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

  ; CHECK:   [[DEF13:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF13:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[V_ADD_F32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $exec
  ; CHECK:   %21:vgpr_32 = nofpexcept V_ADD_F32_e32 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_]], implicit $mode, implicit $exec

  ; CHECK:   [[V_MUL_F32_e32_4:%[0-9]+]]:vgpr_32 = V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $exec
  ; CHECK:   %22:vgpr_32 = nofpexcept V_MUL_F32_e32 [[DEF7]], [[DEF7]], implicit $mode, implicit $exec

  ; CHECK:   dead %23:vgpr_32 = V_MUL_F32_e32 [[V_MUL_F32_e32_4]], [[DEF13]], implicit $exec
  ; CHECK:   dead %23:vgpr_32 = nofpexcept V_MUL_F32_e32 %22, [[DEF13]], implicit $mode, implicit $exec

  ; CHECK:   dead [[V_MOV_B32_e32_1]]:vgpr_32 = V_MAC_F32_e32 [[V_ADD_F32_e32_]], [[COPY]], [[V_MOV_B32_e32_1]], implicit $exec
  ; CHECK:   dead [[V_MOV_B32_e32_1]]:vgpr_32 = nofpexcept V_MAC_F32_e32 %21, [[COPY]], [[V_MOV_B32_e32_1]], implicit $mode, implicit $exec

  ; CHECK:   [[DEF14:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; CHECK:   [[DEF14:%[0-9]+]]:sreg_64 = IMPLICIT_DEF

  ; CHECK:   $sgpr4 = IMPLICIT_DEF
  ; CHECK:   $sgpr4 = IMPLICIT_DEF

  ; CHECK:   $vgpr0 = COPY [[DEF11]]
  ; CHECK:   $vgpr0 = COPY [[DEF11]]

  ; CHECK:   $vgpr0 = COPY [[V_MOV_B32_e32_]]
  ; CHECK:   $vgpr0 = COPY [[V_MOV_B32_e32_]]

  ; CHECK:   $vgpr1 = COPY [[DEF7]]
  ; CHECK:   $vgpr1 = COPY [[DEF7]]

  ; CHECK:   $vgpr0 = COPY [[V_MUL_F32_e32_1]]
  ; CHECK:   $vgpr0 = COPY %16

  ; CHECK:   $vgpr1 = COPY [[V_MUL_F32_e32_2]]
  ; CHECK:   $vgpr1 = COPY %17

  ; CHECK:   $vgpr2 = COPY [[V_MUL_F32_e32_3]]
  ; CHECK:   $vgpr2 = COPY %18

  ; CHECK:   dead $sgpr30_sgpr31 = SI_CALL [[DEF14]], @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit-def $vgpr0
  ; CHECK:   dead $sgpr30_sgpr31 = SI_CALL [[DEF14]], @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit-def $vgpr0

  ; CHECK:   [[V_ADD_F32_e32_1:%[0-9]+]]:vgpr_32 = V_ADD_F32_e32 [[V_MUL_F32_e32_]], [[DEF8]], implicit $exec
  ; CHECK:   %25:vgpr_32 = nofpexcept V_ADD_F32_e32 %9, [[DEF8]], implicit $mode, implicit $exec

  ; CHECK:   [[V_MAC_F32_e32_:%[0-9]+]]:vgpr_32 = V_MAC_F32_e32 [[DEF12]], [[DEF9]], [[V_MAC_F32_e32_]], implicit $exec
  ; CHECK:   %25:vgpr_32 = nofpexcept V_MAC_F32_e32 [[DEF12]], [[DEF9]], %25, implicit $mode, implicit $exec

  ; CHECK:   dead %26:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF4]], 0, [[DEF1]], 0, 0, implicit $exec
  ; CHECK:   dead %26:vgpr_32 = nofpexcept V_MAD_F32 0, %25, 0, [[DEF4]], 0, [[DEF1]], 0, 0, implicit $mode, implicit $exec

  ; CHECK:   dead %27:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF5]], 0, [[DEF2]], 0, 0, implicit $exec
  ; CHECK:   dead %27:vgpr_32 = nofpexcept V_MAD_F32 0, %25, 0, [[DEF5]], 0, [[DEF2]], 0, 0, implicit $mode, implicit $exec

  ; CHECK:   dead %28:vgpr_32 = V_MAD_F32 0, [[V_MAC_F32_e32_]], 0, [[DEF6]], 0, [[DEF3]], 0, 0, implicit $exec
  ; CHECK:   dead %28:vgpr_32 = nofpexcept V_MAD_F32 0, %25, 0, [[DEF6]], 0, [[DEF3]], 0, 0, implicit $mode, implicit $exec

  ; CHECK:   GLOBAL_STORE_DWORD [[DEF]], [[DEF10]], 0, 0, 0, 0, implicit $exec
  ; CHECK:   GLOBAL_STORE_DWORD [[DEF]], [[DEF10]], 0, 0, 0, 0, implicit $exec

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  bb.0:
  bb.0:

    successors: %bb.1
    successors: %bb.1




    %0:vreg_64 = IMPLICIT_DEF
    %0:vreg_64 = IMPLICIT_DEF

    %1:vgpr_32 = IMPLICIT_DEF
    %1:vgpr_32 = IMPLICIT_DEF

    %2:vgpr_32 = IMPLICIT_DEF
    %2:vgpr_32 = IMPLICIT_DEF

    %3:vgpr_32 = IMPLICIT_DEF
    %3:vgpr_32 = IMPLICIT_DEF

    %4:vgpr_32 = IMPLICIT_DEF
    %4:vgpr_32 = IMPLICIT_DEF

    %5:vgpr_32 = IMPLICIT_DEF
    %5:vgpr_32 = IMPLICIT_DEF

    %6:vgpr_32 = IMPLICIT_DEF
    %6:vgpr_32 = IMPLICIT_DEF

    %7:vgpr_32 = IMPLICIT_DEF
    %7:vgpr_32 = IMPLICIT_DEF

    %8:vgpr_32 = IMPLICIT_DEF
    %8:vgpr_32 = IMPLICIT_DEF

    %9:vgpr_32 = V_MUL_F32_e32 1082130432, %1, implicit $exec
    %9:vgpr_32 = nofpexcept V_MUL_F32_e32 1082130432, %1, implicit $mode, implicit $exec

    %10:vgpr_32 = IMPLICIT_DEF
    %10:vgpr_32 = IMPLICIT_DEF

    %11:vgpr_32 = IMPLICIT_DEF
    %11:vgpr_32 = IMPLICIT_DEF




  bb.1:
  bb.1:

    successors: %bb.2
    successors: %bb.2




    DBG_VALUE
    DBG_VALUE

    DBG_VALUE
    DBG_VALUE

    DBG_VALUE
    DBG_VALUE




  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3




    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    %12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %12:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %13:vgpr_32 = COPY %12
    %13:vgpr_32 = COPY %12

    %14:vgpr_32 = IMPLICIT_DEF
    %14:vgpr_32 = IMPLICIT_DEF

    %15:vgpr_32 = IMPLICIT_DEF
    %15:vgpr_32 = IMPLICIT_DEF

    %16:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
    %16:vgpr_32 = nofpexcept V_MUL_F32_e32 %7, %7, implicit $mode, implicit $exec

    %17:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
    %17:vgpr_32 = nofpexcept V_MUL_F32_e32 %7, %7, implicit $mode, implicit $exec

    %18:vgpr_32 = V_MUL_F32_e32 %12, %12, implicit $exec
    %18:vgpr_32 = nofpexcept V_MUL_F32_e32 %12, %12, implicit $mode, implicit $exec

    %19:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %19:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %20:vgpr_32 = IMPLICIT_DEF
    %20:vgpr_32 = IMPLICIT_DEF

    %21:vgpr_32 = V_ADD_F32_e32 %12, %12, implicit $exec
    %21:vgpr_32 = nofpexcept V_ADD_F32_e32 %12, %12, implicit $mode, implicit $exec

    %22:vgpr_32 = V_MUL_F32_e32 %7, %7, implicit $exec
    %22:vgpr_32 = nofpexcept V_MUL_F32_e32 %7, %7, implicit $mode, implicit $exec

    %23:vgpr_32 = V_MUL_F32_e32 %22, %20, implicit $exec
    %23:vgpr_32 = nofpexcept V_MUL_F32_e32 %22, %20, implicit $mode, implicit $exec

    %19:vgpr_32 = V_MAC_F32_e32 %21, %13, %19, implicit $exec
    %19:vgpr_32 = nofpexcept V_MAC_F32_e32 %21, %13, %19, implicit $mode, implicit $exec

    %24:sreg_64 = IMPLICIT_DEF
    %24:sreg_64 = IMPLICIT_DEF

    $vgpr0 = COPY %14
    $vgpr0 = COPY %14

    $vgpr0 = COPY %12
    $vgpr0 = COPY %12

    $vgpr1 = COPY %7
    $vgpr1 = COPY %7

    $vgpr0 = COPY %16
    $vgpr0 = COPY %16

    $vgpr1 = COPY %17
    $vgpr1 = COPY %17

    $vgpr2 = COPY %18
    $vgpr2 = COPY %18

    $sgpr4 = IMPLICIT_DEF
    $sgpr4 = IMPLICIT_DEF

    dead $sgpr30_sgpr31 = SI_CALL %24, @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit-def $vgpr0
    dead $sgpr30_sgpr31 = SI_CALL %24, @foo, csr_amdgpu_highregs, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0, implicit killed $vgpr1, implicit killed $vgpr2, implicit-def $vgpr0

    %25:vgpr_32 = V_ADD_F32_e32 %9, %8, implicit $exec
    %25:vgpr_32 = nofpexcept V_ADD_F32_e32 %9, %8, implicit $mode, implicit $exec

    %25:vgpr_32 = V_MAC_F32_e32 %15, %10, %25, implicit $exec
    %25:vgpr_32 = nofpexcept V_MAC_F32_e32 %15, %10, %25, implicit $mode, implicit $exec

    %26:vgpr_32 = V_MAD_F32 0, %25, 0, %4, 0, %1, 0, 0, implicit $exec
    %26:vgpr_32 = nofpexcept V_MAD_F32 0, %25, 0, %4, 0, %1, 0, 0, implicit $mode, implicit $exec

    %27:vgpr_32 = V_MAD_F32 0, %25, 0, %5, 0, %2, 0, 0, implicit $exec
    %27:vgpr_32 = nofpexcept V_MAD_F32 0, %25, 0, %5, 0, %2, 0, 0, implicit $mode, implicit $exec

    %28:vgpr_32 = V_MAD_F32 0, %25, 0, %6, 0, %3, 0, 0, implicit $exec
    %28:vgpr_32 = nofpexcept V_MAD_F32 0, %25, 0, %6, 0, %3, 0, 0, implicit $mode, implicit $exec

    GLOBAL_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec
    GLOBAL_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/dpp_combine.mir
Show First 20 Lines • Show All 290 Lines • ▼ Show 20 Lines  bb.0:

    %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %18:vgpr_32 = V_MOV_B32_dpp %17, %0, 1, 14, 15, 0, implicit $exec
    %18:vgpr_32 = V_MOV_B32_dpp %17, %0, 1, 14, 15, 0, implicit $exec

    %19:vgpr_32 = V_ADD_I32_e32 5, %18, implicit-def $vcc, implicit $exec
    %19:vgpr_32 = V_ADD_I32_e32 5, %18, implicit-def $vcc, implicit $exec

...
...




# check for floating point modifiers
# check for floating point modifiers

# GCN-LABEL: name: add_f32_e64
# GCN-LABEL: name: add_f32_e64

# GCN: %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
# GCN: %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec

# GCN: %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
# GCN: %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec

# GCN: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $exec
# GCN: %6:vgpr_32 = V_ADD_F32_dpp %2, 0, %1, 0, %0, 1, 15, 15, 1, implicit $mode, implicit $exec

# GCN: %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $exec
# GCN: %8:vgpr_32 = V_ADD_F32_dpp %2, 1, %1, 2, %0, 1, 15, 15, 1, implicit $mode, implicit $exec

# GCN: %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $exec
# GCN: %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec




name: add_f32_e64
name: add_f32_e64

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %1:vgpr_32 = COPY $vgpr1
    %1:vgpr_32 = COPY $vgpr1

    %2:vgpr_32 = IMPLICIT_DEF
    %2:vgpr_32 = IMPLICIT_DEF




    ; this shouldn't be combined as omod is set
    ; this shouldn't be combined as omod is set

    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
    %3:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec

    %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $exec
    %4:vgpr_32 = V_ADD_F32_e64 0, %3, 0, %0, 0, 1, implicit $mode, implicit $exec




    ; this should be combined as all modifiers are default
    ; this should be combined as all modifiers are default

    %5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
    %5:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec

    %6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $exec
    %6:vgpr_32 = V_ADD_F32_e64 0, %5, 0, %0, 0, 0, implicit $mode, implicit $exec




    ; this should be combined as modifiers other than abs|neg are default
    ; this should be combined as modifiers other than abs|neg are default

    %7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
    %7:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec

    %8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $exec
    %8:vgpr_32 = V_ADD_F32_e64 1, %7, 2, %0, 0, 0, implicit $mode, implicit $exec




    ; this shouldn't be combined as modifiers aren't abs|neg
    ; this shouldn't be combined as modifiers aren't abs|neg

    %9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec
    %9:vgpr_32 = V_MOV_B32_dpp undef %2, %1, 1, 15, 15, 1, implicit $exec

    %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $exec
    %10:vgpr_32 = V_ADD_F32_e64 4, %9, 8, %0, 0, 0, implicit $mode, implicit $exec

...
...




# check for e64 modifiers
# check for e64 modifiers

# GCN-LABEL: name: add_u32_e64
# GCN-LABEL: name: add_u32_e64

# GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec
# GCN: %4:vgpr_32 = V_ADD_U32_dpp %2, %0, %1, 1, 15, 15, 1, implicit $exec

# GCN: %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec
# GCN: %6:vgpr_32 = V_ADD_U32_e64 %5, %1, 1, implicit $exec




name: add_u32_e64
name: add_u32_e64

▲ Show 20 Lines • Show All 188 Lines • ▼ Show 20 Lines  bb.0:

    %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %2:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef
    %3:vreg_64 = REG_SEQUENCE %2, %subreg.sub0 ; %3.sub1 is undef

    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec
    %4:vgpr_32 = V_MOV_B32_dpp %3.sub1, %1, 1, 15, 15, 1, implicit $exec

    %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec
    %5:vgpr_32 = V_ADD_U32_e32 %4, %0.sub1, implicit $exec

...
...




# Test instruction which does not have modifiers in VOP1 form but does in DPP form.
# Test instruction which does not have modifiers in VOP1 form but does in DPP form.

# GCN-LABEL: name: dpp_vop1
# GCN-LABEL: name: dpp_vop1

# GCN: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec
# GCN: %3:vgpr_32 = V_CEIL_F32_dpp %0, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec

name: dpp_vop1
name: dpp_vop1

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    %1:vgpr_32 = IMPLICIT_DEF
    %1:vgpr_32 = IMPLICIT_DEF

    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec

    %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
    %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec

...
...




# Test instruction which does not have modifiers in VOP2 form but does in DPP form.
# Test instruction which does not have modifiers in VOP2 form but does in DPP form.

# GCN-LABEL: name: dpp_min
# GCN-LABEL: name: dpp_min

# GCN: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $exec
# GCN: %3:vgpr_32 = V_MIN_F32_dpp %0, 0, undef %2:vgpr_32, 0, undef %4:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec

name: dpp_min
name: dpp_min

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    %1:vgpr_32 = IMPLICIT_DEF
    %1:vgpr_32 = IMPLICIT_DEF

    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
    %2:vgpr_32 = V_MOV_B32_dpp %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec

    %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $exec
    %4:vgpr_32 = V_MIN_F32_e32 %2, undef %3:vgpr_32, implicit $mode, implicit $exec

...
...




# Test an undef old operand
# Test an undef old operand

# GCN-LABEL: name: dpp_undef_old
# GCN-LABEL: name: dpp_undef_old

# GCN: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $exec
# GCN: %3:vgpr_32 = V_CEIL_F32_dpp undef %1:vgpr_32, 0, undef %2:vgpr_32, 1, 15, 15, 1, implicit $mode, implicit $exec

name: dpp_undef_old
name: dpp_undef_old

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
    %2:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec

    %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
    %3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $mode, implicit $exec

...
...




# Do not combine a dpp mov which writes a physreg.
# Do not combine a dpp mov which writes a physreg.

# GCN-LABEL: name: phys_dpp_mov_dst
# GCN-LABEL: name: phys_dpp_mov_dst

# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec

# GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
# GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec

name: phys_dpp_mov_dst
name: phys_dpp_mov_dst

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
    $vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec

    %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
    %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $mode, implicit $exec

...
...




# Do not combine a dpp mov which reads a physreg.
# Do not combine a dpp mov which reads a physreg.

# GCN-LABEL: name: phys_dpp_mov_old_src
# GCN-LABEL: name: phys_dpp_mov_old_src

# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec

# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $exec
# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec

name: phys_dpp_mov_old_src
name: phys_dpp_mov_old_src

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
    %1:vgpr_32 = V_MOV_B32_dpp undef $vgpr0, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec

    %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $exec
    %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec

...
...




# Do not combine a dpp mov which reads a physreg.
# Do not combine a dpp mov which reads a physreg.

# GCN-LABEL: name: phys_dpp_mov_src
# GCN-LABEL: name: phys_dpp_mov_src

# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
# GCN: %0:vgpr_32 = V_MOV_B32_dpp undef %1:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec

# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $exec
# GCN: %2:vgpr_32 = V_CEIL_F32_e32 %0, implicit $mode, implicit $exec

name: phys_dpp_mov_src
name: phys_dpp_mov_src

tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec
    %1:vgpr_32 = V_MOV_B32_dpp undef %0:vgpr_32, undef $vgpr0, 1, 15, 15, 1, implicit $exec

    %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $exec
    %2:vgpr_32 = V_CEIL_F32_e32 %1, implicit $mode, implicit $exec

...
...




# GCN-LABEL: name: dpp_reg_sequence_both_combined
# GCN-LABEL: name: dpp_reg_sequence_both_combined

# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1

# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3
# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3

# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec
# GCN: %2:vgpr_32 = V_MOV_B32_e32 5, implicit $exec

# GCN: %9:vgpr_32 = IMPLICIT_DEF
# GCN: %9:vgpr_32 = IMPLICIT_DEF

# GCN: %8:vgpr_32 = IMPLICIT_DEF
# GCN: %8:vgpr_32 = IMPLICIT_DEF

▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
Show All 12 Linesregisters:

  - { id: 4, class: sgpr_32 }
  - { id: 4, class: sgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:

    $vcc = IMPLICIT_DEF
    $vcc = IMPLICIT_DEF

    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %3 = IMPLICIT_DEF
    %3 = IMPLICIT_DEF

    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc

    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)

    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec

    %4 = S_ADD_U32 %3, 1, implicit-def $scc
    %4 = S_ADD_U32 %3, 1, implicit-def $scc

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# GCN-LABEL: name: load_without_memoperand
# GCN-LABEL: name: load_without_memoperand

# GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc

# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr

# GCN-NEXT: S_ENDPGM 0
# GCN-NEXT: S_ENDPGM 0

name: load_without_memoperand
name: load_without_memoperand

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: sgpr_32 }
  - { id: 3, class: sgpr_32 }

  - { id: 4, class: sgpr_32 }
  - { id: 4, class: sgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:

    $vcc = IMPLICIT_DEF
    $vcc = IMPLICIT_DEF

    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %3 = IMPLICIT_DEF
    %3 = IMPLICIT_DEF

    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc

    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr

    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec

    %4 = S_ADD_U32 %3, 1, implicit-def $scc
    %4 = S_ADD_U32 %3, 1, implicit-def $scc

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# GCN-LABEL: name: load_volatile
# GCN-LABEL: name: load_volatile

# GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc

# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
# GCN-NEXT: dead %1:vgpr_32 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)

# GCN-NEXT: S_ENDPGM 0
# GCN-NEXT: S_ENDPGM 0

name: load_volatile
name: load_volatile

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: sgpr_32 }
  - { id: 3, class: sgpr_32 }

  - { id: 4, class: sgpr_32 }
  - { id: 4, class: sgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:

    $vcc = IMPLICIT_DEF
    $vcc = IMPLICIT_DEF

    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %3 = IMPLICIT_DEF
    %3 = IMPLICIT_DEF

    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc

    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)
    %1 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4)

    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $exec
    %2 = V_ADD_F32_e64 0, killed %1, 0, 1, 0, 0, implicit $mode, implicit $exec

    %4 = S_ADD_U32 %3, 1, implicit-def $scc
    %4 = S_ADD_U32 %3, 1, implicit-def $scc

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# GCN-LABEL: name: store
# GCN-LABEL: name: store

# GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
# GCN:      $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc

# GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
# GCN-NEXT: FLAT_STORE_DWORD %0, %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

# GCN-NEXT: S_ENDPGM 0
# GCN-NEXT: S_ENDPGM 0

▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
body:             |
body:             |

  bb.0:
  bb.0:

    $vcc = IMPLICIT_DEF
    $vcc = IMPLICIT_DEF

    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
    $sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc




  bb.1:
  bb.1:

    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %2 = IMPLICIT_DEF
    %2 = IMPLICIT_DEF

    %1 = V_ADD_F32_e64 0, killed %0, 0, 1, 0, 0, implicit $exec
    %1 = V_ADD_F32_e64 0, killed %0, 0, 1, 0, 0, implicit $mode, implicit $exec

    %3 = S_ADD_U32 %2, 1, implicit-def $scc
    %3 = S_ADD_U32 %2, 1, implicit-def $scc

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# GCN-LABEL: name: split_block_empty_block
# GCN-LABEL: name: split_block_empty_block

# GCN:      bb.0:
# GCN:      bb.0:

# GCN-NEXT:   successors: %bb.1
# GCN-NEXT:   successors: %bb.1

# GCN-NOT:  S_OR_B64
# GCN-NOT:  S_OR_B64

▲ Show 20 Lines • Show All 174 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/fix-sgpr-copies.mir
# RUN: llc -march=amdgcn -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GCN %s
# RUN: llc -march=amdgcn -run-pass=si-fix-sgpr-copies -o - %s | FileCheck --check-prefix=GCN %s




# GCN-LABEL: name: fix-sgpr-copies
# GCN-LABEL: name: fix-sgpr-copies

# GCN: V_ADD_I32_e32
# GCN: V_ADD_I32_e32

# GCN: V_ADDC_U32_e32
# GCN: V_ADDC_U32_e32

---
---

name: fix-sgpr-copies
name: fix-sgpr-copies

body:               |
body:               |

  bb.0:
  bb.0:

    %0:vgpr_32 = IMPLICIT_DEF
    %0:vgpr_32 = IMPLICIT_DEF

    %1:sreg_32 = IMPLICIT_DEF
    %1:sreg_32 = IMPLICIT_DEF

    %2:sreg_32 = IMPLICIT_DEF
    %2:sreg_32 = IMPLICIT_DEF

    %3:sreg_32 = IMPLICIT_DEF
    %3:sreg_32 = IMPLICIT_DEF

    %4:vgpr_32 = V_CVT_U32_F32_e64 0, %0:vgpr_32, 0, 0, implicit $exec
    %4:vgpr_32 = V_CVT_U32_F32_e64 0, %0:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %5:sreg_32 = COPY %4:vgpr_32
    %5:sreg_32 = COPY %4:vgpr_32

    %6:sreg_32 = S_ADD_I32 %2:sreg_32, %5:sreg_32, implicit-def $scc
    %6:sreg_32 = S_ADD_I32 %2:sreg_32, %5:sreg_32, implicit-def $scc

    %7:sreg_32 = S_ADDC_U32 %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $scc
    %7:sreg_32 = S_ADDC_U32 %3:sreg_32, %1:sreg_32, implicit-def $scc, implicit $scc

...
...




# Test to ensure i1 phi copies from scalar registers through another phi won't
# Test to ensure i1 phi copies from scalar registers through another phi won't

# be promoted into vector ones.
# be promoted into vector ones.

# GCN-LABEL: name: fix-sgpr-i1-phi-copies
# GCN-LABEL: name: fix-sgpr-i1-phi-copies

▲ Show 20 Lines • Show All 90 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir
Show First 20 Lines • Show All 105 Lines • ▼ Show 20 Lines



...
...

---
---




# f32 1.0 with a single use should be folded as the low 32-bits of a
# f32 1.0 with a single use should be folded as the low 32-bits of a

#  literal constant.
#  literal constant.




# CHECK-LABEL: name: add_f32_1.0_one_f16_use
# CHECK-LABEL: name: add_f32_1.0_one_f16_use

# CHECK: %13:vgpr_32 = V_ADD_F16_e32  1065353216, killed %11, implicit $exec
# CHECK: %13:vgpr_32 = V_ADD_F16_e32  1065353216, killed %11, implicit $mode, implicit $exec




name:            add_f32_1.0_one_f16_use
name:            add_f32_1.0_one_f16_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

Show All 32 Lines  bb.0 (%ir-block.0):

    %5 = COPY %4.sub1
    %5 = COPY %4.sub1

    %6 = IMPLICIT_DEF
    %6 = IMPLICIT_DEF

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %12 = V_MOV_B32_e32 1065353216, implicit $exec
    %12 = V_MOV_B32_e32 1065353216, implicit $exec

    %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit $exec
    %13 = V_ADD_F16_e64 0, killed %11, 0, %12, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %13, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# Materialized f32 inline immediate should not be folded into the f16
# Materialized f32 inline immediate should not be folded into the f16

# operands
# operands




# CHECK-LABEL: name: add_f32_1.0_multi_f16_use
# CHECK-LABEL: name: add_f32_1.0_multi_f16_use

# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec

# CHECK: %14:vgpr_32 = V_ADD_F16_e32 killed %11, %13, implicit $exec
# CHECK: %14:vgpr_32 = V_ADD_F16_e32 killed %11, %13, implicit $mode, implicit $exec

# CHECK: %15:vgpr_32 = V_ADD_F16_e32 killed %12, killed %13, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 killed %12, killed %13, implicit $mode, implicit $exec







name:            add_f32_1.0_multi_f16_use
name:            add_f32_1.0_multi_f16_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

Show All 36 Lines  bb.0 (%ir-block.0):

    %6 = IMPLICIT_DEF
    %6 = IMPLICIT_DEF

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %13 = V_MOV_B32_e32 1065353216, implicit $exec
    %13 = V_MOV_B32_e32 1065353216, implicit $exec

    %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec
    %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $mode, implicit $exec

    %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec
    %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---




# f32 1.0 should be folded into the single f32 use as an inline
# f32 1.0 should be folded into the single f32 use as an inline

#  immediate, and folded into the single f16 use as a literal constant
#  immediate, and folded into the single f16 use as a literal constant




# CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use
# CHECK-LABEL: name: add_f32_1.0_one_f32_use_one_f16_use

# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, %11, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1065353216, %11, implicit $mode, implicit $exec

# CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec
# CHECK: %16:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $mode, implicit $exec




name:            add_f32_1.0_one_f32_use_one_f16_use
name:            add_f32_1.0_one_f32_use_one_f16_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

Show All 37 Lines  bb.0 (%ir-block.0):

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %14 = V_MOV_B32_e32 1065353216, implicit $exec
    %14 = V_MOV_B32_e32 1065353216, implicit $exec

    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $mode, implicit $exec

    %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
    %16 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
    BUFFER_STORE_DWORD_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---




# f32 1.0 should be folded for the single f32 use as an inline
# f32 1.0 should be folded for the single f32 use as an inline

#  constant, and not folded as a multi-use literal for the f16 cases
#  constant, and not folded as a multi-use literal for the f16 cases




# CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use
# CHECK-LABEL: name: add_f32_1.0_one_f32_use_multi_f16_use

# CHECK: %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec
# CHECK: %14:vgpr_32 = V_MOV_B32_e32 1065353216, implicit $exec

# CHECK: %15:vgpr_32 = V_ADD_F16_e32  %11, %14, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32  %11, %14, implicit $mode, implicit $exec

# CHECK: %16:vgpr_32 = V_ADD_F16_e32 %12,  %14, implicit $exec
# CHECK: %16:vgpr_32 = V_ADD_F16_e32 %12,  %14, implicit $mode, implicit $exec

# CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $exec
# CHECK: %17:vgpr_32 = V_ADD_F32_e32 1065353216, killed %13, implicit $mode, implicit $exec




name:            add_f32_1.0_one_f32_use_multi_f16_use
name:            add_f32_1.0_one_f32_use_multi_f16_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

Show All 38 Lines  bb.0 (%ir-block.0):

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %14 = V_MOV_B32_e32 1065353216, implicit $exec
    %14 = V_MOV_B32_e32 1065353216, implicit $exec

    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $mode, implicit $exec

    %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec
    %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $mode, implicit $exec

    %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
    %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
    BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# CHECK-LABEL: name: add_i32_1_multi_f16_use
# CHECK-LABEL: name: add_i32_1_multi_f16_use

# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
# CHECK: %13:vgpr_32 = V_MOV_B32_e32 1, implicit $exec

# CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit $exec
# CHECK: %14:vgpr_32 = V_ADD_F16_e32 1, killed %11, implicit $mode, implicit $exec

# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 1, killed %12, implicit $mode, implicit $exec







name:            add_i32_1_multi_f16_use
name:            add_i32_1_multi_f16_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

Show All 36 Lines  bb.0 (%ir-block.0):

    %6 = IMPLICIT_DEF
    %6 = IMPLICIT_DEF

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %13 = V_MOV_B32_e32 1, implicit $exec
    %13 = V_MOV_B32_e32 1, implicit $exec

    %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $exec
    %14 = V_ADD_F16_e64 0, killed %11, 0, %13, 0, 0, implicit $mode, implicit $exec

    %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $exec
    %15 = V_ADD_F16_e64 0, killed %12, 0, killed %13, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---




# CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use
# CHECK-LABEL: name: add_i32_m2_one_f32_use_multi_f16_use

# CHECK: %14:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec
# CHECK: %14:vgpr_32 = V_MOV_B32_e32 -2, implicit $exec

# CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 -2, %11, implicit $mode, implicit $exec

# CHECK: %16:vgpr_32 = V_ADD_F16_e32 -2, %12, implicit $exec
# CHECK: %16:vgpr_32 = V_ADD_F16_e32 -2, %12, implicit $mode, implicit $exec

# CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit $exec
# CHECK: %17:vgpr_32 = V_ADD_F32_e32 -2, killed %13, implicit $mode, implicit $exec




name:            add_i32_m2_one_f32_use_multi_f16_use
name:            add_i32_m2_one_f32_use_multi_f16_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

Show All 38 Lines  bb.0 (%ir-block.0):

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %13 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %14 = V_MOV_B32_e32 -2, implicit $exec
    %14 = V_MOV_B32_e32 -2, implicit $exec

    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $exec
    %15 = V_ADD_F16_e64 0, %11, 0, %14, 0, 0, implicit $mode, implicit $exec

    %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $exec
    %16 = V_ADD_F16_e64 0, %12, 0, %14, 0, 0, implicit $mode, implicit $exec

    %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $exec
    %17 = V_ADD_F32_e64 0, killed %13, 0, killed %14, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %16, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
    BUFFER_STORE_DWORD_OFFSET killed %17, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---




# f32 1.0 should be folded for the single f32 use as an inline
# f32 1.0 should be folded for the single f32 use as an inline

#  constant, and not folded as a multi-use literal for the f16 cases
#  constant, and not folded as a multi-use literal for the f16 cases




# CHECK-LABEL: name: add_f16_1.0_multi_f32_use
# CHECK-LABEL: name: add_f16_1.0_multi_f32_use

# CHECK: %13:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec
# CHECK: %13:vgpr_32 = V_MOV_B32_e32 15360, implicit $exec

# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $exec
# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $mode, implicit $exec

# CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F32_e32 %12, %13, implicit $mode, implicit $exec




name:            add_f16_1.0_multi_f32_use
name:            add_f16_1.0_multi_f32_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

Show All 35 Lines  bb.0 (%ir-block.0):

    %6 = IMPLICIT_DEF
    %6 = IMPLICIT_DEF

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %12 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %13 = V_MOV_B32_e32 15360, implicit $exec
    %13 = V_MOV_B32_e32 15360, implicit $exec

    %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec
    %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $mode, implicit $exec

    %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit $exec
    %15 = V_ADD_F32_e64 0, %12, 0, %13, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
    BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)

    BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
    BUFFER_STORE_DWORD_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---




# The low 16-bits are an inline immediate, but the high bits are junk
# The low 16-bits are an inline immediate, but the high bits are junk

# FIXME: Should be able to fold this
# FIXME: Should be able to fold this




# CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use
# CHECK-LABEL: name: add_f16_1.0_other_high_bits_multi_f16_use

# CHECK: %13:vgpr_32 = V_MOV_B32_e32 80886784, implicit $exec
# CHECK: %13:vgpr_32 = V_MOV_B32_e32 80886784, implicit $exec

# CHECK: %14:vgpr_32 = V_ADD_F16_e32 %11, %13, implicit $exec
# CHECK: %14:vgpr_32 = V_ADD_F16_e32 %11, %13, implicit $mode, implicit $exec

# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $mode, implicit $exec




name:            add_f16_1.0_other_high_bits_multi_f16_use
name:            add_f16_1.0_other_high_bits_multi_f16_use

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

Show All 35 Lines  bb.0 (%ir-block.0):

    %6 = IMPLICIT_DEF
    %6 = IMPLICIT_DEF

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %11 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %13 = V_MOV_B32_e32 80886784, implicit $exec
    %13 = V_MOV_B32_e32 80886784, implicit $exec

    %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit $exec
    %14 = V_ADD_F16_e64 0, %11, 0, %13, 0, 0, implicit $mode, implicit $exec

    %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec
    %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---




# FIXME: Should fold inline immediate into f16 and literal use into
# FIXME: Should fold inline immediate into f16 and literal use into

# f32 instruction.
# f32 instruction.




# CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32
# CHECK-LABEL: name: add_f16_1.0_other_high_bits_use_f16_f32

# CHECK: %13:vgpr_32 = V_MOV_B32_e32 305413120, implicit $exec
# CHECK: %13:vgpr_32 = V_MOV_B32_e32 305413120, implicit $exec

# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $exec
# CHECK: %14:vgpr_32 = V_ADD_F32_e32 %11, %13, implicit $mode, implicit $exec

# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $exec
# CHECK: %15:vgpr_32 = V_ADD_F16_e32 %12, %13, implicit $mode, implicit $exec

name:            add_f16_1.0_other_high_bits_use_f16_f32
name:            add_f16_1.0_other_high_bits_use_f16_f32

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

Show All 34 Lines  bb.0 (%ir-block.0):

    %6 = IMPLICIT_DEF
    %6 = IMPLICIT_DEF

    %7 = COPY %6.sub0
    %7 = COPY %6.sub0

    %8 = S_MOV_B32 61440
    %8 = S_MOV_B32 61440

    %9 = S_MOV_B32 -1
    %9 = S_MOV_B32 -1

    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4
    %10 = REG_SEQUENCE killed %7, 1, killed %5, 2, killed %9, 3, killed %8, 4

    %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
    %11 = BUFFER_LOAD_DWORD_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)

    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)
    %12 = BUFFER_LOAD_USHORT_OFFSET %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 2 from `half addrspace(1)* undef`)

    %13 = V_MOV_B32_e32 305413120, implicit $exec
    %13 = V_MOV_B32_e32 305413120, implicit $exec

    %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $exec
    %14 = V_ADD_F32_e64 0, %11, 0, %13, 0, 0, implicit $mode, implicit $exec

    %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $exec
    %15 = V_ADD_F16_e64 0, %12, 0, %13, 0, 0, implicit $mode, implicit $exec

    BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)
    BUFFER_STORE_DWORD_OFFSET killed %14, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 4 into `float addrspace(1)* undef`)

    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)
    BUFFER_STORE_SHORT_OFFSET killed %15, %10, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (volatile store 2 into `half addrspace(1)* undef`)

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/fold-immediate-output-mods.mir
# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

...
...

# GCN-LABEL: name: no_fold_imm_madak_mac_clamp_f32
# GCN-LABEL: name: no_fold_imm_madak_mac_clamp_f32

# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec

# GCN-NEXT: %24:vgpr_32 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
# GCN-NEXT: %24:vgpr_32 = nofpexcept V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $mode, implicit $exec




name:            no_fold_imm_madak_mac_clamp_f32
name:            no_fold_imm_madak_mac_clamp_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines  bb.0:

    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec

    %17 = REG_SEQUENCE killed %6, 17, %13, 18
    %17 = REG_SEQUENCE killed %6, 17, %13, 18

    %18 = REG_SEQUENCE killed %4, 17, %13, 18
    %18 = REG_SEQUENCE killed %4, 17, %13, 18

    %20 = COPY %29
    %20 = COPY %29

    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %22 = COPY %29
    %22 = COPY %29

    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %23 = V_MOV_B32_e32 1090519040, implicit $exec
    %23 = V_MOV_B32_e32 1090519040, implicit $exec

    %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
    %24 = nofpexcept V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $mode, implicit $exec

    %26 = COPY %29
    %26 = COPY %29

    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# GCN-LABEL: name: no_fold_imm_madak_mac_omod_f32
# GCN-LABEL: name: no_fold_imm_madak_mac_omod_f32

# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec

# GCN: %24:vgpr_32 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec
# GCN: %24:vgpr_32 = nofpexcept V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $mode, implicit $exec




name:            no_fold_imm_madak_mac_omod_f32
name:            no_fold_imm_madak_mac_omod_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines  bb.0:

    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec

    %17 = REG_SEQUENCE killed %6, 17, %13, 18
    %17 = REG_SEQUENCE killed %6, 17, %13, 18

    %18 = REG_SEQUENCE killed %4, 17, %13, 18
    %18 = REG_SEQUENCE killed %4, 17, %13, 18

    %20 = COPY %29
    %20 = COPY %29

    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %22 = COPY %29
    %22 = COPY %29

    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %23 = V_MOV_B32_e32 1090519040, implicit $exec
    %23 = V_MOV_B32_e32 1090519040, implicit $exec

    %24 = V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $exec
    %24 = nofpexcept V_MAC_F32_e64 0, killed %19, 0, killed %21, 0, %23, 0, 2, implicit $mode, implicit $exec

    %26 = COPY %29
    %26 = COPY %29

    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# GCN: name: no_fold_imm_madak_mad_clamp_f32
# GCN: name: no_fold_imm_madak_mad_clamp_f32

# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec

# GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
# GCN: %24:vgpr_32 = nofpexcept V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $mode, implicit $exec




name:            no_fold_imm_madak_mad_clamp_f32
name:            no_fold_imm_madak_mad_clamp_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines  bb.0:

    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec

    %17 = REG_SEQUENCE killed %6, 17, %13, 18
    %17 = REG_SEQUENCE killed %6, 17, %13, 18

    %18 = REG_SEQUENCE killed %4, 17, %13, 18
    %18 = REG_SEQUENCE killed %4, 17, %13, 18

    %20 = COPY %29
    %20 = COPY %29

    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %22 = COPY %29
    %22 = COPY %29

    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %23 = V_MOV_B32_e32 1090519040, implicit $exec
    %23 = V_MOV_B32_e32 1090519040, implicit $exec

    %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $exec
    %24 = nofpexcept V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 1, 0, implicit $mode, implicit $exec

    %26 = COPY %29
    %26 = COPY %29

    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# GCN: name: no_fold_imm_madak_mad_omod_f32
# GCN: name: no_fold_imm_madak_mad_omod_f32

# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec
# GCN: %23:vgpr_32 = V_MOV_B32_e32 1090519040, implicit $exec

# GCN: %24:vgpr_32 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec
# GCN: %24:vgpr_32 = nofpexcept V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $mode, implicit $exec




name:            no_fold_imm_madak_mad_omod_f32
name:            no_fold_imm_madak_mad_omod_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: sgpr_64 }
  - { id: 0, class: sgpr_64 }

  - { id: 1, class: sreg_32_xm0 }
  - { id: 1, class: sreg_32_xm0 }

  - { id: 2, class: sgpr_32 }
  - { id: 2, class: sgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines  bb.0:

    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec
    %29 = V_LSHL_B64 killed %28, killed %15, implicit $exec

    %17 = REG_SEQUENCE killed %6, 17, %13, 18
    %17 = REG_SEQUENCE killed %6, 17, %13, 18

    %18 = REG_SEQUENCE killed %4, 17, %13, 18
    %18 = REG_SEQUENCE killed %4, 17, %13, 18

    %20 = COPY %29
    %20 = COPY %29

    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %19 = BUFFER_LOAD_DWORD_ADDR64 %20, killed %14, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %22 = COPY %29
    %22 = COPY %29

    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %21 = BUFFER_LOAD_DWORD_ADDR64 %22, killed %17, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    %23 = V_MOV_B32_e32 1090519040, implicit $exec
    %23 = V_MOV_B32_e32 1090519040, implicit $exec

    %24 = V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $exec
    %24 = nofpexcept V_MAD_F32 0, killed %19, 0, killed %21, 0, %23, 0, 1, implicit $mode, implicit $exec

    %26 = COPY %29
    %26 = COPY %29

    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_ADDR64 killed %24, %26, killed %18, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/fold-vgpr-copy.mir
Show All 33 Lines  bb.0:

    %3:vgpr_32 = IMPLICIT_DEF
    %3:vgpr_32 = IMPLICIT_DEF

    %1:sgpr_32 = COPY %0.sub0
    %1:sgpr_32 = COPY %0.sub0

    %2:vgpr_32 = COPY %1
    %2:vgpr_32 = COPY %1

    DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec
    DS_WRITE2_B32_gfx9 %2, killed %4, killed %3, 0, 1, 0, implicit $exec

...
...




# GCN-LABEL: name: fma_sgpr_use
# GCN-LABEL: name: fma_sgpr_use

# GCN:      %0:sreg_64_xexec = IMPLICIT_DEF
# GCN:      %0:sreg_64_xexec = IMPLICIT_DEF

# GCN-NEXT: %4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMA_F32 2, %0.sub0, 0, 1073741824, 0, %0.sub1, 0, 0, implicit $exec
# GCN-NEXT: %4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMA_F32 2, %0.sub0, 0, 1073741824, 0, %0.sub1, 0, 0, implicit $mode, implicit $exec

---
---

name:            fma_sgpr_use
name:            fma_sgpr_use

body:             |
body:             |

  bb.0:
  bb.0:

    %0:sreg_64_xexec = IMPLICIT_DEF
    %0:sreg_64_xexec = IMPLICIT_DEF

    %1:sgpr_32 = COPY %0.sub0
    %1:sgpr_32 = COPY %0.sub0

    %2:sgpr_32 = COPY %0.sub1
    %2:sgpr_32 = COPY %0.sub1

    %3:vgpr_32 = COPY %2
    %3:vgpr_32 = COPY %2

    %4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMAC_F32_e64 2, %1, 0, 1073741824, 0, %3, 0, 0, implicit $exec
    %4:vgpr_32 = nnan ninf nsz arcp contract afn reassoc V_FMAC_F32_e64 2, %1, 0, 1073741824, 0, %3, 0, 0, implicit $mode, implicit $exec

    DS_WRITE2_B32_gfx9 undef %5:vgpr_32, killed %4, undef %6:vgpr_32, 0, 1, 0, implicit $exec
    DS_WRITE2_B32_gfx9 undef %5:vgpr_32, killed %4, undef %6:vgpr_32, 0, 1, 0, implicit $exec

...
...

llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir
# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s




# GCN-LABEL: name: flat_atomic_fcmpswap_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fcmpswap_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FCMPSWAP
# GCN:      FLAT_ATOMIC_FCMPSWAP

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fcmpswap_to_s_denorm_mode
name:            flat_atomic_fcmpswap_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fcmpswap_x2_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fcmpswap_x2_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FCMPSWAP_X2
# GCN:      FLAT_ATOMIC_FCMPSWAP_X2

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fcmpswap_x2_to_s_denorm_mode
name:            flat_atomic_fcmpswap_x2_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmax_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmax_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMAX
# GCN:      FLAT_ATOMIC_FMAX

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmax_to_s_denorm_mode
name:            flat_atomic_fmax_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmax_x2_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmax_x2_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMAX_X2
# GCN:      FLAT_ATOMIC_FMAX_X2

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmax_x2_to_s_denorm_mode
name:            flat_atomic_fmax_x2_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmin_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmin_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMIN
# GCN:      FLAT_ATOMIC_FMIN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmin_to_s_denorm_mode
name:            flat_atomic_fmin_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmin_x2_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmin_x2_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMIN_X2
# GCN:      FLAT_ATOMIC_FMIN_X2

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmin_x2_to_s_denorm_mode
name:            flat_atomic_fmin_x2_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FCMPSWAP_X2_RTN
# GCN:      FLAT_ATOMIC_FCMPSWAP_X2_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
name:            flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = FLAT_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = FLAT_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmax_rtn_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmax_rtn_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMAX_RTN
# GCN:      FLAT_ATOMIC_FMAX_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmax_rtn_to_s_denorm_mode
name:            flat_atomic_fmax_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = FLAT_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = FLAT_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmax_x2_rtn_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmax_x2_rtn_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMAX_X2_RTN
# GCN:      FLAT_ATOMIC_FMAX_X2_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmax_x2_rtn_to_s_denorm_mode
name:            flat_atomic_fmax_x2_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = FLAT_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = FLAT_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmin_rtn_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmin_rtn_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMIN_RTN
# GCN:      FLAT_ATOMIC_FMIN_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmin_rtn_to_s_denorm_mode
name:            flat_atomic_fmin_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = FLAT_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = FLAT_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fmin_x2_rtn_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fmin_x2_rtn_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FMIN_X2_RTN
# GCN:      FLAT_ATOMIC_FMIN_X2_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fmin_x2_rtn_to_s_denorm_mode
name:            flat_atomic_fmin_x2_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = FLAT_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = FLAT_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_atomic_fcmpswap_rtn_to_s_denorm_mode
# GCN-LABEL: name: flat_atomic_fcmpswap_rtn_to_s_denorm_mode

# GCN:      FLAT_ATOMIC_FCMPSWAP_RTN
# GCN:      FLAT_ATOMIC_FCMPSWAP_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_atomic_fcmpswap_rtn_to_s_denorm_mode
name:            flat_atomic_fcmpswap_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = FLAT_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = FLAT_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fcmpswap_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fcmpswap_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FCMPSWAP
# GCN:      GLOBAL_ATOMIC_FCMPSWAP

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fcmpswap_to_s_denorm_mode
name:            global_atomic_fcmpswap_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    GLOBAL_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    GLOBAL_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fcmpswap_x2_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fcmpswap_x2_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2
# GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fcmpswap_x2_to_s_denorm_mode
name:            global_atomic_fcmpswap_x2_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    GLOBAL_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    GLOBAL_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmax_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmax_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMAX
# GCN:      GLOBAL_ATOMIC_FMAX

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmax_to_s_denorm_mode
name:            global_atomic_fmax_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    GLOBAL_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    GLOBAL_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmax_x2_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmax_x2_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMAX_X2
# GCN:      GLOBAL_ATOMIC_FMAX_X2

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmax_x2_to_s_denorm_mode
name:            global_atomic_fmax_x2_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    GLOBAL_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    GLOBAL_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmin_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmin_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMIN
# GCN:      GLOBAL_ATOMIC_FMIN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmin_to_s_denorm_mode
name:            global_atomic_fmin_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    GLOBAL_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    GLOBAL_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmin_x2_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmin_x2_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMIN_X2
# GCN:      GLOBAL_ATOMIC_FMIN_X2

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmin_x2_to_s_denorm_mode
name:            global_atomic_fmin_x2_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    GLOBAL_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    GLOBAL_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fcmpswap_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fcmpswap_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FCMPSWAP_RTN
# GCN:      GLOBAL_ATOMIC_FCMPSWAP_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fcmpswap_rtn_to_s_denorm_mode
name:            global_atomic_fcmpswap_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = GLOBAL_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = GLOBAL_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2_RTN
# GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
name:            global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmax_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmax_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMAX_RTN
# GCN:      GLOBAL_ATOMIC_FMAX_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmax_rtn_to_s_denorm_mode
name:            global_atomic_fmax_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = GLOBAL_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = GLOBAL_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmax_x2_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmax_x2_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMAX_X2_RTN
# GCN:      GLOBAL_ATOMIC_FMAX_X2_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmax_x2_rtn_to_s_denorm_mode
name:            global_atomic_fmax_x2_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmin_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmin_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMIN_RTN
# GCN:      GLOBAL_ATOMIC_FMIN_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmin_rtn_to_s_denorm_mode
name:            global_atomic_fmin_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = GLOBAL_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = GLOBAL_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmin_x2_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmin_x2_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMIN_X2_RTN
# GCN:      GLOBAL_ATOMIC_FMIN_X2_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmin_x2_rtn_to_s_denorm_mode
name:            global_atomic_fmin_x2_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fcmpswap_saddr_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fcmpswap_saddr_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FCMPSWAP_SADDR
# GCN:      GLOBAL_ATOMIC_FCMPSWAP_SADDR

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fcmpswap_saddr_to_s_denorm_mode
name:            global_atomic_fcmpswap_saddr_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    GLOBAL_ATOMIC_FCMPSWAP_SADDR undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    GLOBAL_ATOMIC_FCMPSWAP_SADDR undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN
# GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
name:            global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMAX_SADDR_RTN
# GCN:      GLOBAL_ATOMIC_FMAX_SADDR_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmax_saddr_rtn_to_s_denorm_mode
name:            global_atomic_fmax_saddr_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = GLOBAL_ATOMIC_FMAX_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = GLOBAL_ATOMIC_FMAX_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN
# GCN:      GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
name:            global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMIN_SADDR_RTN
# GCN:      GLOBAL_ATOMIC_FMIN_SADDR_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmin_saddr_rtn_to_s_denorm_mode
name:            global_atomic_fmin_saddr_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vgpr_32 = GLOBAL_ATOMIC_FMIN_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vgpr_32 = GLOBAL_ATOMIC_FMIN_SADDR_RTN undef %0:vreg_64, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
# GCN-LABEL: name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode

# GCN:      GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN
# GCN:      GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
name:            global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode

body:            |
body:            |

  bb.0:
  bb.0:

    %2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    %2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN undef %0:vreg_64, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_waitcnt
# GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_waitcnt

# GCN:      FLAT_ATOMIC_FMIN
# GCN:      FLAT_ATOMIC_FMIN

# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_WAITCNT

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_fp_atomic_to_s_denorm_mode_waitcnt
name:            flat_fp_atomic_to_s_denorm_mode_waitcnt

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    S_WAITCNT 0
    S_WAITCNT 0

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...




# GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_valu
# GCN-LABEL: name: flat_fp_atomic_to_s_denorm_mode_valu

# GCN:      FLAT_ATOMIC_FMIN
# GCN:      FLAT_ATOMIC_FMIN

# GCN-NEXT: V_ADD_F32_e32
# GCN-NEXT: V_ADD_F32_e32

# GCN-NEXT: S_DENORM_MODE
# GCN-NEXT: S_DENORM_MODE

---
---

name:            flat_fp_atomic_to_s_denorm_mode_valu
name:            flat_fp_atomic_to_s_denorm_mode_valu

body:            |
body:            |

  bb.0:
  bb.0:

    FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
    FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)

    %2:vgpr_32 = V_ADD_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, implicit $exec
    %2:vgpr_32 = V_ADD_F32_e32 undef %1:vgpr_32, undef %1:vgpr_32, implicit $mode, implicit $exec

    S_DENORM_MODE 0
    S_DENORM_MODE 0, implicit-def $mode, implicit $mode

...
...

llvm/test/CodeGen/AMDGPU/hazard-buffer-store-v-interp.mir
# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s
# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=VI %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s




# GCN-LABEL: name: hazard_buffer_store_v_interp
# GCN-LABEL: name: hazard_buffer_store_v_interp

# GCN:    bb.0.entry:
# GCN:    bb.0.entry:

# GCN-NEXT:    BUFFER_STORE_DWORDX4_OFFSET_exact
# GCN-NEXT:    BUFFER_STORE_DWORDX4_OFFSET_exact

# GCN-NEXT:    S_NOP
# GCN-NEXT:    S_NOP

# GCN-NEXT:    V_INTERP_P1_F32
# GCN-NEXT:    V_INTERP_P1_F32




name:            hazard_buffer_store_v_interp
name:            hazard_buffer_store_v_interp

body:             |
body:             |

  bb.0.entry:
  bb.0.entry:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr7, $vgpr8, $vgpr9, $vgpr10

  


    BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORDX4_OFFSET_exact killed $vgpr7_vgpr8_vgpr9_vgpr10, $sgpr4_sgpr5_sgpr6_sgpr7, 0, 96, 0, 0, 0, 0, 0, implicit $exec

    $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
    $vgpr7 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir
Show All 26 Lines
---
---

name: hazard_precedes_bundle
name: hazard_precedes_bundle

body: |
body: |

  bb.0:
  bb.0:

    $m0 = S_MOV_B32 $sgpr7
    $m0 = S_MOV_B32 $sgpr7

    S_SENDMSG 3, implicit $exec, implicit $m0
    S_SENDMSG 3, implicit $exec, implicit $m0

    $m0 = S_MOV_B32 $sgpr8
    $m0 = S_MOV_B32 $sgpr8

    BUNDLE implicit-def $vgpr0 {
    BUNDLE implicit-def $vgpr0 {

      $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $m0, implicit $exec
      $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec

    }
    }

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: vmem_vcc_hazard_ignore_bundle_instr
# GCN-LABEL: name: vmem_vcc_hazard_ignore_bundle_instr

# GCN:      S_LOAD_DWORDX2_IMM
# GCN:      S_LOAD_DWORDX2_IMM

# GCN-NEXT: }
# GCN-NEXT: }

# GCN-NEXT: S_NOP
# GCN-NEXT: S_NOP

▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/hazard-in-bundle.mir
Show All 32 Lines
# GFX10:      V_CMP_EQ_F32
# GFX10:      V_CMP_EQ_F32

---
---

name: hazard_smem_war_in_bundle
name: hazard_smem_war_in_bundle

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    BUNDLE implicit-def $sgpr0_sgpr1 {
    BUNDLE implicit-def $sgpr0_sgpr1 {

      $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
      $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

      $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
      $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    }
    }

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GFX9-LABEL: name: hazard_ignore_dbg_label_in_bundle
# GFX9-LABEL: name: hazard_ignore_dbg_label_in_bundle

# GFX9:      DBG_LABEL 6
# GFX9:      DBG_LABEL 6

# GFX9-NEXT: S_NOP 0
# GFX9-NEXT: S_NOP 0

# GFX9:      S_SENDMSG 3, implicit $exec, implicit $m0
# GFX9:      S_SENDMSG 3, implicit $exec, implicit $m0

Show All 17 Lines
llvm/test/CodeGen/AMDGPU/hazard-kill.mir
Show All 13 Lines
# GFX90-NEXT: KILL undef renamable $sgpr2
# GFX90-NEXT: KILL undef renamable $sgpr2

# GFX90-NEXT: S_MOV_B32 0
# GFX90-NEXT: S_MOV_B32 0

# GFX90-NEXT: V_INTERP_MOV_F32
# GFX90-NEXT: V_INTERP_MOV_F32

name:            _amdgpu_ps_main
name:            _amdgpu_ps_main

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $sgpr2, $sgpr3, $sgpr4
    liveins: $sgpr2, $sgpr3, $sgpr4

  


    $sgpr6 = S_MOV_B32 killed $sgpr3
    $sgpr6 = S_MOV_B32 killed $sgpr3

    renamable $sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 16, 0, 0
    renamable $sgpr8_sgpr9_sgpr10_sgpr11 = S_LOAD_DWORDX4_IMM renamable $sgpr6_sgpr7, 16, 0, 0

    $m0 = S_MOV_B32 killed renamable $sgpr4
    $m0 = S_MOV_B32 killed renamable $sgpr4

    dead renamable $sgpr0 = KILL undef renamable $sgpr2
    dead renamable $sgpr0 = KILL undef renamable $sgpr2

    renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $m0, implicit $exec
    renamable $vgpr0 = V_INTERP_MOV_F32 2, 0, 0, implicit $mode, implicit $m0, implicit $exec

    renamable $sgpr0 = S_MOV_B32 0
    renamable $sgpr0 = S_MOV_B32 0




    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/hazard.mir
Show All 21 Linesliveins:

  - { reg: '$sgpr7', virtual-reg: '' }
  - { reg: '$sgpr7', virtual-reg: '' }

  - { reg: '$vgpr4', virtual-reg: '' }
  - { reg: '$vgpr4', virtual-reg: '' }

body:             |
body:             |

  bb.0.entry:
  bb.0.entry:

    liveins: $sgpr7, $vgpr4
    liveins: $sgpr7, $vgpr4




    $m0 = S_MOV_B32 killed $sgpr7
    $m0 = S_MOV_B32 killed $sgpr7

    $vgpr5 = IMPLICIT_DEF
    $vgpr5 = IMPLICIT_DEF

    $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec

    SI_RETURN_TO_EPILOG killed $vgpr5, killed $vgpr0
    SI_RETURN_TO_EPILOG killed $vgpr5, killed $vgpr0




...
...




# GCN-LABEL: name: hazard_inlineasm
# GCN-LABEL: name: hazard_inlineasm

# GCN:    bb.0.entry:
# GCN:    bb.0.entry:

# GCN:      $m0 = S_MOV_B32
# GCN:      $m0 = S_MOV_B32

# GFX9:     S_NOP 0
# GFX9:     S_NOP 0

Show All 12 Linesliveins:

  - { reg: '$sgpr7', virtual-reg: '' }
  - { reg: '$sgpr7', virtual-reg: '' }

  - { reg: '$vgpr4', virtual-reg: '' }
  - { reg: '$vgpr4', virtual-reg: '' }

body:             |
body:             |

  bb.0.entry:
  bb.0.entry:

    liveins: $sgpr7, $vgpr4
    liveins: $sgpr7, $vgpr4




    $m0 = S_MOV_B32 killed $sgpr7
    $m0 = S_MOV_B32 killed $sgpr7

    INLINEASM &"; no-op", 1, 327690, def $vgpr5
    INLINEASM &"; no-op", 1, 327690, def $vgpr5

    $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec

    SI_RETURN_TO_EPILOG killed $vgpr5, killed $vgpr0
    SI_RETURN_TO_EPILOG killed $vgpr5, killed $vgpr0

...
...




# IMPLICIT_DEF/DBG_VALUE instructions should not prevent the hazard recognizer
# IMPLICIT_DEF/DBG_VALUE instructions should not prevent the hazard recognizer

# from adding s_nop instructions between m0 update and s_sendmsg.
# from adding s_nop instructions between m0 update and s_sendmsg.




# GCN-LABEL: name: hazard-lookahead-implicit-def
# GCN-LABEL: name: hazard-lookahead-implicit-def

# GCN: $vgpr6 = IMPLICIT_DEF
# GCN: $vgpr6 = IMPLICIT_DEF

▲ Show 20 Lines • Show All 60 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir
Show All 13 Lines
# CHECK-NEXT: S_SETPC_B64
# CHECK-NEXT: S_SETPC_B64

liveins:
liveins:

  - { reg: '$sgpr0_sgpr1' }
  - { reg: '$sgpr0_sgpr1' }

  - { reg: '$vgpr0' }
  - { reg: '$vgpr0' }




name: entry_callee_wait
name: entry_callee_wait

body:             |
body:             |

  bb.0:
  bb.0:

    $vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $exec
    $vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $mode, implicit $exec

    S_SETPC_B64 killed $sgpr0_sgpr1
    S_SETPC_B64 killed $sgpr0_sgpr1




...
...

llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
Show First 20 Lines • Show All 73 Lines • ▼ Show 20 Lines
# GCN: S_NOP
# GCN: S_NOP

# GCN: S_NOP
# GCN: S_NOP

# GCN: V_DIV_FMAS_F32
# GCN: V_DIV_FMAS_F32

name: div_fmas
name: div_fmas




body: |
body: |

  bb.0:
  bb.0:

    $vcc = S_MOV_B64 0
    $vcc = S_MOV_B64 0

    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec
    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    implicit $vcc = V_CMP_EQ_I32_e32 $vgpr1, $vgpr2, implicit $exec
    implicit $vcc = V_CMP_EQ_I32_e32 $vgpr1, $vgpr2, implicit $exec

    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec
    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    $vcc = V_CMP_EQ_I32_e64 $vgpr1, $vgpr2, implicit $exec
    $vcc = V_CMP_EQ_I32_e64 $vgpr1, $vgpr2, implicit $exec

    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec
    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    $vgpr4, $vcc = V_DIV_SCALE_F32 $vgpr1, $vgpr1, $vgpr3, implicit $exec
    $vgpr4, $vcc = V_DIV_SCALE_F32 $vgpr1, $vgpr1, $vgpr3, implicit $mode, implicit $exec

    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $vcc, implicit $exec
    $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...




...
...

---
---

# GCN-LABEL: name: s_getreg
# GCN-LABEL: name: s_getreg




Show All 17 Lines
# GCN-LABEL: bb.3:
# GCN-LABEL: bb.3:

# GCN: S_SETREG
# GCN: S_SETREG

# GCN-NEXT: S_GETREG
# GCN-NEXT: S_GETREG




name: s_getreg
name: s_getreg




body: |
body: |

  bb.0:
  bb.0:

    S_SETREG_B32 $sgpr0, 1
    S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode

    $sgpr1 = S_GETREG_B32 1
    $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    S_SETREG_IMM32_B32 0, 1
    S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode

    $sgpr1 = S_GETREG_B32 1
    $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    S_SETREG_B32 $sgpr0, 1
    S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode

    $sgpr1 = S_MOV_B32 0
    $sgpr1 = S_MOV_B32 0

    $sgpr2 = S_GETREG_B32 1
    $sgpr2 = S_GETREG_B32 1, implicit-def $mode, implicit $mode

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    S_SETREG_B32 $sgpr0, 0
    S_SETREG_B32 $sgpr0, 0, implicit-def $mode, implicit $mode

    $sgpr1 = S_GETREG_B32 1
    $sgpr1 = S_GETREG_B32 1, implicit-def $mode, implicit $mode

    S_ENDPGM 0
    S_ENDPGM 0

...
...




...
...

---
---

# GCN-LABEL: name: s_setreg
# GCN-LABEL: name: s_setreg




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

Show All 11 Lines
# GCN-LABEL: bb.2:
# GCN-LABEL: bb.2:

# GCN: S_SETREG
# GCN: S_SETREG

# GCN-NEXT: S_SETREG
# GCN-NEXT: S_SETREG




name: s_setreg
name: s_setreg




body: |
body: |

  bb.0:
  bb.0:

    S_SETREG_B32 $sgpr0, 1
    S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode

    S_SETREG_B32 $sgpr1, 1
    S_SETREG_B32 $sgpr1, 1, implicit-def $mode, implicit $mode

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    S_SETREG_B32 $sgpr0, 64
    S_SETREG_B32 $sgpr0, 64, implicit-def $mode, implicit $mode

    S_SETREG_B32 $sgpr1, 128
    S_SETREG_B32 $sgpr1, 128, implicit-def $mode, implicit $mode

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    S_SETREG_B32 $sgpr0, 1
    S_SETREG_B32 $sgpr0, 1, implicit-def $mode, implicit $mode

    S_SETREG_B32 $sgpr1, 0
    S_SETREG_B32 $sgpr1, 0, implicit-def $mode, implicit $mode

    S_ENDPGM 0
    S_ENDPGM 0

...
...




...
...

---
---

# GCN-LABEL: name: vmem_gt_8dw_store
# GCN-LABEL: name: vmem_gt_8dw_store




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
# GCN-LABEL: bb.1:
# GCN-LABEL: bb.1:

# GCN: S_SETREG
# GCN: S_SETREG

# GCN-NEXT: S_RFE_B64
# GCN-NEXT: S_RFE_B64




name: rfe
name: rfe




body: |
body: |

  bb.0:
  bb.0:

    S_SETREG_B32 $sgpr0, 3
    S_SETREG_B32 $sgpr0, 3, implicit-def $mode, implicit $mode

    S_RFE_B64 $sgpr2_sgpr3
    S_RFE_B64 $sgpr2_sgpr3

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    S_SETREG_B32 $sgpr0, 0
    S_SETREG_B32 $sgpr0, 0, implicit-def $mode, implicit $mode

    S_RFE_B64 $sgpr2_sgpr3
    S_RFE_B64 $sgpr2_sgpr3

    S_ENDPGM 0
    S_ENDPGM 0




...
...




...
...

---
---




▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
# GFX9-NEXT: S_NOP
# GFX9-NEXT: S_NOP

# GCN-NEXT: V_INTERP_MOV_F32
# GCN-NEXT: V_INTERP_MOV_F32




name: v_interp
name: v_interp




body: |
body: |

  bb.0:
  bb.0:

    $m0 = S_MOV_B32 0
    $m0 = S_MOV_B32 0

    $vgpr0 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1_F32 $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    $m0 = S_MOV_B32 0
    $m0 = S_MOV_B32 0

    $vgpr0 = V_INTERP_P2_F32 $vgpr0, $vgpr1, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P2_F32 $vgpr0, $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    $m0 = S_MOV_B32 0
    $m0 = S_MOV_B32 0

    $vgpr0 = V_INTERP_P1_F32_16bank $vgpr0, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1_F32_16bank $vgpr0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    $m0 = S_MOV_B32 0
    $m0 = S_MOV_B32 0

    $vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_MOV_F32 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




...
...

---
---




# GCN-LABEL: name: dpp
# GCN-LABEL: name: dpp




▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/madak-inline-constant.mir
# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -run-pass peephole-opt -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s







# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192
# GCN:  V_MOV_B32_e32 1092616192

# GCN:  S_MOV_B32 1082130432
# GCN:  S_MOV_B32 1082130432

# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $mode, implicit $exec




---
---

name:            test src1-inlined
name:            test src1-inlined

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1




    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %18:sreg_32 = S_MOV_B32 1082130432
    %18:sreg_32 = S_MOV_B32 1082130432

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %18, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %18, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...







# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192
# GCN:  V_MOV_B32_e32 1092616192

# GCN:  S_MOV_B32 1082130432
# GCN:  S_MOV_B32 1082130432

# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $mode, implicit $exec




---
---

name:            test src0-inlined
name:            test src0-inlined

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1




    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %18:sreg_32 = S_MOV_B32 1082130432
    %18:sreg_32 = S_MOV_B32 1082130432

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed %0, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed %0, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192
# GCN:  V_MOV_B32_e32 1092616192

# GCN:  S_MOV_B32 1082130432
# GCN:  S_MOV_B32 1082130432

# GCN:  %3:vgpr_32 = V_MADAK_F32 killed %0, killed %0, 1092616192, implicit $exec
# GCN:  %3:vgpr_32 = V_MADAK_F32 killed %0, killed %0, 1092616192, implicit $mode, implicit $exec




---
---

name:            test none-inlined
name:            test none-inlined

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1




    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %18:sreg_32 = S_MOV_B32 1082130432
    %18:sreg_32 = S_MOV_B32 1082130432

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %0, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %0, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192
# GCN:  V_MOV_B32_e32 1092616192

# GCN:  V_MOV_B32_e32 1082130432
# GCN:  V_MOV_B32_e32 1082130432

# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $mode, implicit $exec




---
---

name:            test src1-2vgprs-inlined
name:            test src1-2vgprs-inlined

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1




    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %18:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec
    %18:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %18, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed %18, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...







# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192
# GCN:  V_MOV_B32_e32 1092616192

# GCN:  V_MOV_B32_e32 1082130432
# GCN:  V_MOV_B32_e32 1082130432

# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
# GCN:  %3:vgpr_32 = V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $mode, implicit $exec




---
---

name:            test src0-2vgprs-inlined
name:            test src0-2vgprs-inlined

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1




    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %18:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec
    %18:vgpr_32 = V_MOV_B32_e32 1082130432, implicit $exec

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed %0, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed %0, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192, implicit $exec
# GCN:  V_MOV_B32_e32 1092616192, implicit $exec

# GCN:  S_MOV_B32 1082130432
# GCN:  S_MOV_B32 1082130432

# GCN:  V_MADAK_F32 1082130432, killed $vgpr1, 1092616192, implicit $exec
# GCN:  V_MADAK_F32 1082130432, killed $vgpr1, 1092616192, implicit $mode, implicit $exec




---
---

name:            test src0-phys-vgpr
name:            test src0-phys-vgpr

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1







    $vgpr1 = COPY $vgpr0
    $vgpr1 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %18:sgpr_32 = S_MOV_B32 1082130432
    %18:sgpr_32 = S_MOV_B32 1082130432

    %19:vgpr_32 = V_MAC_F32_e64 0, killed $vgpr1, 0, killed %18, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed $vgpr1, 0, killed %18, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192, implicit $exec
# GCN:  V_MOV_B32_e32 1092616192, implicit $exec

# GCN:  S_MOV_B32 1082130432
# GCN:  S_MOV_B32 1082130432

# GCN:  V_MADAK_F32 1082130432, killed $vgpr0, 1092616192, implicit $exec
# GCN:  V_MADAK_F32 1082130432, killed $vgpr0, 1092616192, implicit $mode, implicit $exec




---
---

name:            test src1-phys-vgpr
name:            test src1-phys-vgpr

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1







    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %18:sgpr_32 = S_MOV_B32 1082130432
    %18:sgpr_32 = S_MOV_B32 1082130432

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed $vgpr0, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %18, 0, killed $vgpr0, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192, implicit $exec
# GCN:  V_MOV_B32_e32 1092616192, implicit $exec

# GCN:  V_MAC_F32_e64 0, killed $sgpr2, 0, killed %0, 0, %1, 0, 0, implicit $exec
# GCN:  V_MAC_F32_e64 0, killed $sgpr2, 0, killed %0, 0, %1, 0, 0, implicit $mode, implicit $exec




---
---

name:            test src0-phys-sgpr
name:            test src0-phys-sgpr

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2
    liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2







    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %19:vgpr_32 = V_MAC_F32_e64 0, killed $sgpr2, 0, killed %0, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed $sgpr2, 0, killed %0, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192, implicit $exec
# GCN:  V_MOV_B32_e32 1092616192, implicit $exec

# GCN:  V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %1, 0, 0, implicit $exec
# GCN:  V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %1, 0, 0, implicit $mode, implicit $exec




---
---

name:            test src1-phys-sgpr
name:            test src1-phys-sgpr

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2
    liveins: $vgpr0, $sgpr0_sgpr1, $sgpr2







    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...




# GCN-LABEL: bb.0:
# GCN-LABEL: bb.0:

# GCN:  V_MOV_B32_e32 1092616192, implicit $exec
# GCN:  V_MOV_B32_e32 1092616192, implicit $exec

# GCN:  $sgpr2 = S_MOV_B32 1082130432
# GCN:  $sgpr2 = S_MOV_B32 1082130432

# GCN:  V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $exec
# GCN:  V_MADAK_F32 1082130432, killed %0, 1092616192, implicit $mode, implicit $exec




---
---

name:            test src1-phys-sgpr-move
name:            test src1-phys-sgpr-move

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $sgpr0_sgpr1
    liveins: $vgpr0, $sgpr0_sgpr1







    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 1092616192, implicit $exec

    $sgpr2 = S_MOV_B32 1082130432
    $sgpr2 = S_MOV_B32 1082130432

    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %17, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAC_F32_e64 0, killed %0, 0, killed $sgpr2, 0, %17, 0, 0, implicit $mode, implicit $exec




...
...

llvm/test/CodeGen/AMDGPU/mai-hazards.mir
# RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s




# GCN-LABEL: name: valu_write_vgpr_mfma_read
# GCN-LABEL: name: valu_write_vgpr_mfma_read

# GCN:      V_MOV_B32
# GCN:      V_MOV_B32

# GCN:      V_MOV_B32
# GCN:      V_MOV_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            valu_write_vgpr_mfma_read
name:            valu_write_vgpr_mfma_read

body:             |
body:             |

  bb.0:
  bb.0:

    $vgpr0 = V_MOV_B32_e32 1, implicit $exec
    $vgpr0 = V_MOV_B32_e32 1, implicit $exec

    $vgpr1 = V_MOV_B32_e32 1, implicit $exec
    $vgpr1 = V_MOV_B32_e32 1, implicit $exec

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: valu_write_vgpr_accvgpr_write_read
# GCN-LABEL: name: valu_write_vgpr_accvgpr_write_read

# GCN:      V_MOV_B32
# GCN:      V_MOV_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            valu_write_vgpr_accvgpr_write_read
name:            valu_write_vgpr_accvgpr_write_read

body:             |
body:             |

  bb.0:
  bb.0:

    $vgpr0 = V_MOV_B32_e32 1, implicit $exec
    $vgpr0 = V_MOV_B32_e32 1, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_write_agpr_mfma_read_same_agpr
# GCN-LABEL: name: mfma_write_agpr_mfma_read_same_agpr

# GCN:      V_MFMA
# GCN:      V_MFMA

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            mfma_write_agpr_mfma_read_same_agpr
name:            mfma_write_agpr_mfma_read_same_agpr

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_write_agpr_mfma_read_overlap
# GCN-LABEL: name: mfma_write_agpr_mfma_read_overlap

# GCN:      V_MFMA
# GCN:      V_MFMA

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            mfma_write_agpr_mfma_read_overlap
name:            mfma_write_agpr_mfma_read_overlap

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr1_agpr2_agpr3_agpr4 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr1_agpr2_agpr3_agpr4 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_write_agpr_mfma_read_partial
# GCN-LABEL: name: mfma_write_agpr_mfma_read_partial

# GCN:      V_MFMA
# GCN:      V_MFMA

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            mfma_write_agpr_mfma_read_partial
name:            mfma_write_agpr_mfma_read_partial

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_write_agpr_mfma_srca_read_overlap
# GCN-LABEL: name: mfma_write_agpr_mfma_srca_read_overlap

# GCN:      V_MFMA
# GCN:      V_MFMA

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            mfma_write_agpr_mfma_srca_read_overlap
name:            mfma_write_agpr_mfma_srca_read_overlap

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $agpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $agpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_write_agpr_mfma_srcb_read_overlap
# GCN-LABEL: name: mfma_write_agpr_mfma_srcb_read_overlap

# GCN:      V_MFMA
# GCN:      V_MFMA

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            mfma_write_agpr_mfma_srcb_read_overlap
name:            mfma_write_agpr_mfma_srcb_read_overlap

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $agpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $agpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_4x4_write_agpr_accvgpr_read
# GCN-LABEL: name: mfma_4x4_write_agpr_accvgpr_read

# GCN:      V_MFMA_F32_4X4X1F32
# GCN:      V_MFMA_F32_4X4X1F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_READ_B32
# GCN-NEXT: V_ACCVGPR_READ_B32

name:            mfma_4x4_write_agpr_accvgpr_read
name:            mfma_4x4_write_agpr_accvgpr_read

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_16x16_write_agpr_accvgpr_read
# GCN-LABEL: name: mfma_16x16_write_agpr_accvgpr_read

# GCN:      V_MFMA_F32_16X16X1F32
# GCN:      V_MFMA_F32_16X16X1F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_READ_B32
# GCN-NEXT: V_ACCVGPR_READ_B32

name:            mfma_16x16_write_agpr_accvgpr_read
name:            mfma_16x16_write_agpr_accvgpr_read

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec

    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_32x32_write_agpr_accvgpr_read
# GCN-LABEL: name: mfma_32x32_write_agpr_accvgpr_read

# GCN:      V_MFMA_F32_32X32X2F32
# GCN:      V_MFMA_F32_32X32X2F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

Show All 12 Lines
# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_READ_B32
# GCN-NEXT: V_ACCVGPR_READ_B32

name:            mfma_32x32_write_agpr_accvgpr_read
name:            mfma_32x32_write_agpr_accvgpr_read

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec

    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_4x4_write_agpr_accvgpr_write
# GCN-LABEL: name: mfma_4x4_write_agpr_accvgpr_write

# GCN:      V_MFMA_F32_4X4X1F32
# GCN:      V_MFMA_F32_4X4X1F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            mfma_4x4_write_agpr_accvgpr_write
name:            mfma_4x4_write_agpr_accvgpr_write

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_16x16_write_agpr_accvgpr_write
# GCN-LABEL: name: mfma_16x16_write_agpr_accvgpr_write

# GCN:      V_MFMA_F32_16X16X1F32
# GCN:      V_MFMA_F32_16X16X1F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            mfma_16x16_write_agpr_accvgpr_write
name:            mfma_16x16_write_agpr_accvgpr_write

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_32x32_write_agpr_accvgpr_write
# GCN-LABEL: name: mfma_32x32_write_agpr_accvgpr_write

# GCN:      V_MFMA_F32_32X32X2F32
# GCN:      V_MFMA_F32_32X32X2F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

Show All 9 Lines
# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            mfma_32x32_write_agpr_accvgpr_write
name:            mfma_32x32_write_agpr_accvgpr_write

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_4x4_read_srcc_accvgpr_write
# GCN-LABEL: name: mfma_4x4_read_srcc_accvgpr_write

# GCN:      V_MFMA_F32_4X4X1F32
# GCN:      V_MFMA_F32_4X4X1F32

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            mfma_4x4_read_srcc_accvgpr_write
name:            mfma_4x4_read_srcc_accvgpr_write

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_16x16_read_srcc_accvgpr_write
# GCN-LABEL: name: mfma_16x16_read_srcc_accvgpr_write

# GCN:      V_MFMA_F32_16X16X1F32
# GCN:      V_MFMA_F32_16X16X1F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            mfma_16x16_read_srcc_accvgpr_write
name:            mfma_16x16_read_srcc_accvgpr_write

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $exec
    $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec

...
...

---
---




# GCN-LABEL: name: mfma_32x32_read_srcc_accvgpr_write
# GCN-LABEL: name: mfma_32x32_read_srcc_accvgpr_write

# GCN:      V_MFMA_F32_32X32X2F32
# GCN:      V_MFMA_F32_32X32X2F32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            mfma_32x32_read_srcc_accvgpr_write
name:            mfma_32x32_read_srcc_accvgpr_write

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $exec
    $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec

...
...

---
---




# GCN-LABEL: name: accvgpr_read_write_vgpr_valu_read
# GCN-LABEL: name: accvgpr_read_write_vgpr_valu_read

# GCN:      V_ACCVGPR_READ_B32
# GCN:      V_ACCVGPR_READ_B32

# GCN-NEXT: V_ADD_F32
# GCN-NEXT: V_ADD_F32

name:            accvgpr_read_write_vgpr_valu_read
name:            accvgpr_read_write_vgpr_valu_read

body:             |
body:             |

  bb.0:
  bb.0:

    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr4, implicit $exec
    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr4, implicit $exec

    $vgpr1 = V_ADD_F32_e32 0, killed $vgpr0, implicit $exec
    $vgpr1 = V_ADD_F32_e32 0, killed $vgpr0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: accvgpr_read_write_vgpr_mfma_read
# GCN-LABEL: name: accvgpr_read_write_vgpr_mfma_read

# GCN:      V_ACCVGPR_READ_B32
# GCN:      V_ACCVGPR_READ_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            accvgpr_read_write_vgpr_mfma_read
name:            accvgpr_read_write_vgpr_mfma_read

body:             |
body:             |

  bb.0:
  bb.0:

    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr4, implicit $exec
    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr4, implicit $exec

    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr0, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr0, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: accvgpr_read_write_vgpr_accvgpr_write_read
# GCN-LABEL: name: accvgpr_read_write_vgpr_accvgpr_write_read

# GCN:      V_ACCVGPR_READ_B32
# GCN:      V_ACCVGPR_READ_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_ACCVGPR_WRITE_B32
# GCN-NEXT: V_ACCVGPR_WRITE_B32

name:            accvgpr_read_write_vgpr_accvgpr_write_read
name:            accvgpr_read_write_vgpr_accvgpr_write_read

body:             |
body:             |

  bb.0:
  bb.0:

    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr1, implicit $exec
    $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr1, implicit $exec

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

...
...

---
---




# GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srcc
# GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srcc

# GCN:      V_ACCVGPR_WRITE_B32
# GCN:      V_ACCVGPR_WRITE_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            accvgpr_write_agpr_mfma_read_srcc
name:            accvgpr_write_agpr_mfma_read_srcc

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr2, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr2, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srca
# GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srca

# GCN:      V_ACCVGPR_WRITE_B32
# GCN:      V_ACCVGPR_WRITE_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            accvgpr_write_agpr_mfma_read_srca
name:            accvgpr_write_agpr_mfma_read_srca

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr8 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr8 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $agpr8, killed $vgpr1, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $agpr8, killed $vgpr1, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srcb
# GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srcb

# GCN:      V_ACCVGPR_WRITE_B32
# GCN:      V_ACCVGPR_WRITE_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            accvgpr_write_agpr_mfma_read_srcb
name:            accvgpr_write_agpr_mfma_read_srcb

body:             |
body:             |

  bb.0:
  bb.0:

    $agpr8 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
    $agpr8 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec

    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $agpr8, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $agpr8, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: accvgpr_write_agpr_accvgpr_read
# GCN-LABEL: name: accvgpr_write_agpr_accvgpr_read

# GCN:      V_ACCVGPR_WRITE_B32
# GCN:      V_ACCVGPR_WRITE_B32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

Show All 12 Lines
# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: V_MFMA
# GCN-NEXT: V_MFMA

name:            vcmpx_write_exec_mfma
name:            vcmpx_write_exec_mfma

body:             |
body:             |

  bb.0:
  bb.0:

    implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
    implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec

    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $agpr8, killed $vgpr1, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $exec
    $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $agpr8, killed $vgpr1, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec

...
...

---
---




# GCN-LABEL: name: vcmpx_write_exec_accvgpr_write
# GCN-LABEL: name: vcmpx_write_exec_accvgpr_write

# GCN:      V_CMPX_EQ_I32_e32
# GCN:      V_CMPX_EQ_I32_e32

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

# GCN-NEXT: S_NOP 0
# GCN-NEXT: S_NOP 0

▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/merge-m0.mir
Show First 20 Lines • Show All 285 Lines • ▼ Show 20 Lines
name: move-m0-schedule-boundary
name: move-m0-schedule-boundary

registers:
registers:

  - { id: 0, class: vgpr_32 }
  - { id: 0, class: vgpr_32 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:

    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = IMPLICIT_DEF
    %1 = IMPLICIT_DEF

    S_SETREG_IMM32_B32 0, 1
    S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode

    SI_INIT_M0 -1, implicit-def $m0
    SI_INIT_M0 -1, implicit-def $m0

    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec

...
...

llvm/test/CodeGen/AMDGPU/mode-register.mir
Show All 11 Lines



name: interp_f16_default
name: interp_f16_default




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

    $m0 = S_MOV_B32 killed $sgpr2
    $m0 = S_MOV_B32 killed $sgpr2

    $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
    $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $exec
    $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec

    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $exec
    $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that the mode is not changed for interp f16 when the mode is already RTZ
# check that the mode is not changed for interp f16 when the mode is already RTZ

# CHECK-LABEL: name: interp_f16_explicit_rtz
# CHECK-LABEL: name: interp_f16_explicit_rtz

# CHECK-LABEL: bb.0:
# CHECK-LABEL: bb.0:

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK-NEXT: V_MOV_B32_e32
# CHECK-NEXT: V_MOV_B32_e32

# CHECK: S_SETREG_IMM32_B32 0, 2177
# CHECK: S_SETREG_IMM32_B32 0, 2177

# CHECK-NEXT: V_ADD_F16_e32
# CHECK-NEXT: V_ADD_F16_e32

# CHECK-NOT: S_SETREG_IMM32_B32
# CHECK-NOT: S_SETREG_IMM32_B32




name: interp_f16_explicit_rtz
name: interp_f16_explicit_rtz




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

    $m0 = S_MOV_B32 killed $sgpr2
    $m0 = S_MOV_B32 killed $sgpr2

    S_SETREG_IMM32_B32 3, 2177
    S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode

    $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
    $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $exec
    $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec

    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $exec
    $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that explicit RTN mode change is registered
# check that explicit RTN mode change is registered

# CHECK-LABEL: name: explicit_rtn
# CHECK-LABEL: name: explicit_rtn

# CHECK-LABEL: bb.0:
# CHECK-LABEL: bb.0:

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK-NEXT: V_INTERP_P1LL_F16
# CHECK-NEXT: V_INTERP_P1LL_F16

# CHECK: S_SETREG_IMM32_B32 0, 2177
# CHECK: S_SETREG_IMM32_B32 0, 2177

# CHECK-NEXT: V_ADD_F16_e32
# CHECK-NEXT: V_ADD_F16_e32

# CHECK-NOT: S_SETREG_IMM32_B32
# CHECK-NOT: S_SETREG_IMM32_B32




name: explicit_rtn
name: explicit_rtn




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2
    liveins: $sgpr0, $sgpr1, $sgpr2

    $m0 = S_MOV_B32 killed $sgpr2
    $m0 = S_MOV_B32 killed $sgpr2

    $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec
    $vgpr0 = V_MOV_B32_e32 killed $sgpr0, implicit $exec, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec, implicit $exec
    $vgpr2 = V_MOV_B32_e32 killed $sgpr1, implicit $exec

    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $mode, implicit $m0, implicit $exec

    S_SETREG_IMM32_B32 0, 2177
    S_SETREG_IMM32_B32 0, 2177, implicit-def $mode, implicit $mode

    $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $exec
    $vgpr0 = V_ADD_F16_e32 killed $vgpr1, killed $vgpr0, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that the mode is unchanged from RTN for F64 instruction
# check that the mode is unchanged from RTN for F64 instruction

# CHECK-LABEL: name: rtn_default
# CHECK-LABEL: name: rtn_default

# CHECK-LABEL: bb.0:
# CHECK-LABEL: bb.0:

# CHECK-NOT: S_SETREG_IMM32_B32
# CHECK-NOT: S_SETREG_IMM32_B32

# CHECK: V_FRACT_F64
# CHECK: V_FRACT_F64




name: rtn_default
name: rtn_default




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr1_vgpr2
    liveins: $vgpr1_vgpr2

    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $exec
    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that the mode is changed from RTZ to RTN for F64 instruction
# check that the mode is changed from RTZ to RTN for F64 instruction

# CHECK-LABEL: name: rtn_from_rtz
# CHECK-LABEL: name: rtn_from_rtz

# CHECK-LABEL: bb.0:
# CHECK-LABEL: bb.0:

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK-NEXT: S_SETREG_IMM32_B32 0, 2177
# CHECK-NEXT: S_SETREG_IMM32_B32 0, 2177

# CHECK-NEXT: V_FRACT_F64
# CHECK-NEXT: V_FRACT_F64

# CHECK-NOT: S_SETREG_IMM32_B32
# CHECK-NOT: S_SETREG_IMM32_B32




name: rtn_from_rtz
name: rtn_from_rtz




body: |
body: |

  bb.0:
  bb.0:

    liveins: $vgpr1_vgpr2
    liveins: $vgpr1_vgpr2

    S_SETREG_IMM32_B32 3, 2177
    S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode

    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $exec
    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# CHECK-LABEL: name: rtz_from_rtn
# CHECK-LABEL: name: rtz_from_rtn

# CHECK-LABEL: bb.1:
# CHECK-LABEL: bb.1:

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK-NOT: S_SETREG_IMM32_B32
# CHECK-NOT: S_SETREG_IMM32_B32




name: rtz_from_rtn
name: rtz_from_rtn




body: |
body: |

  bb.0:
  bb.0:

    successors: %bb.1
    successors: %bb.1

    liveins: $vgpr1_vgpr2
    liveins: $vgpr1_vgpr2

    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $exec
    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $mode, implicit $exec

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that the mode is changed from RTZ to RTN for F64 instruction
# check that the mode is changed from RTZ to RTN for F64 instruction

# and back again for remaining interp instruction
# and back again for remaining interp instruction

# CHECK-LABEL: name: interp_f16_plus_sqrt_f64
# CHECK-LABEL: name: interp_f16_plus_sqrt_f64

# CHECK-LABEL: bb.0:
# CHECK-LABEL: bb.0:

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK: V_INTERP_P1LL_F16
# CHECK: V_INTERP_P1LL_F16

# CHECK: V_INTERP_P1LL_F16
# CHECK: V_INTERP_P1LL_F16

# CHECK: V_INTERP_P2_F16
# CHECK: V_INTERP_P2_F16

# CHECK: S_SETREG_IMM32_B32 0, 2177
# CHECK: S_SETREG_IMM32_B32 0, 2177

# CHECK: V_FRACT_F64
# CHECK: V_FRACT_F64

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK: V_INTERP_P2_F16
# CHECK: V_INTERP_P2_F16




name: interp_f16_plus_sqrt_f64
name: interp_f16_plus_sqrt_f64




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr3, $vgpr4
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr3, $vgpr4

    $m0 = S_MOV_B32 killed $sgpr2
    $m0 = S_MOV_B32 killed $sgpr2

    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $exec
    $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $exec

    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $mode, implicit $exec

    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr0 = V_ADD_F16_e32 killed $sgpr0, killed $vgpr0, implicit $exec
    $vgpr0 = V_ADD_F16_e32 killed $sgpr0, killed $vgpr0, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that an explicit change to the single precision mode has no effect
# check that an explicit change to the single precision mode has no effect

# CHECK-LABEL: name: single_precision_mode_change
# CHECK-LABEL: name: single_precision_mode_change

# CHECK-LABEL: bb.0:
# CHECK-LABEL: bb.0:

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK: V_INTERP_P1LL_F16
# CHECK: V_INTERP_P1LL_F16

# CHECK: V_INTERP_P1LL_F16
# CHECK: V_INTERP_P1LL_F16

# CHECK: V_INTERP_P2_F16
# CHECK: V_INTERP_P2_F16

# CHECK: S_SETREG_IMM32_B32 0, 2177
# CHECK: S_SETREG_IMM32_B32 0, 2177

# CHECK: V_FRACT_F64
# CHECK: V_FRACT_F64

# CHECK: S_SETREG_IMM32_B32 3, 2177
# CHECK: S_SETREG_IMM32_B32 3, 2177

# CHECK: V_INTERP_P2_F16
# CHECK: V_INTERP_P2_F16




name: single_precision_mode_change
name: single_precision_mode_change




body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr3, $vgpr4
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr3, $vgpr4

    $m0 = S_MOV_B32 killed $sgpr2
    $m0 = S_MOV_B32 killed $sgpr2

    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_SETREG_IMM32_B32 2, 2049
    S_SETREG_IMM32_B32 2, 2049, implicit-def $mode, implicit $mode

    $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $exec
    $vgpr2 = V_MOV_B32_e32 $sgpr1, implicit $exec

    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P1LL_F16 0, killed $vgpr0, 2, 1, -1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P2_F16 0, $vgpr2, 2, 1, 0, killed $vgpr1, 0, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $mode, implicit $exec

    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $m0, implicit $exec
    $vgpr0 = V_INTERP_P2_F16 0, killed $vgpr2, 2, 1, 0, killed $vgpr0, -1, 0, implicit $mode, implicit $m0, implicit $exec

    $vgpr0 = V_ADD_F16_e32 killed $sgpr0, killed $vgpr0, implicit $exec
    $vgpr0 = V_ADD_F16_e32 killed $sgpr0, killed $vgpr0, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that mode is propagated back to start of loop - first instruction is RTN but needs
# check that mode is propagated back to start of loop - first instruction is RTN but needs

# setreg as RTZ is set in loop
# setreg as RTZ is set in loop

# CHECK-LABEL: name: loop
# CHECK-LABEL: name: loop

# CHECK-LABEL: bb.1:
# CHECK-LABEL: bb.1:

# CHECK: S_SETREG_IMM32_B32 0, 2177
# CHECK: S_SETREG_IMM32_B32 0, 2177

Show All 9 Linesbody: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr3, $vgpr4
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr3, $vgpr4

    successors: %bb.1
    successors: %bb.1

    $m0 = S_MOV_B32 killed $sgpr2
    $m0 = S_MOV_B32 killed $sgpr2

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    successors: %bb.2
    successors: %bb.2

    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $mode, implicit $exec

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    successors: %bb.1, %bb.3
    successors: %bb.1, %bb.3

    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_CBRANCH_VCCZ %bb.1, implicit $vcc
    S_CBRANCH_VCCZ %bb.1, implicit $vcc

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# two back-edges to same node with different modes
# two back-edges to same node with different modes

Show All 16 Linesbody: |




  bb.1:
  bb.1:

    successors: %bb.2
    successors: %bb.2

    S_NOP 1
    S_NOP 1

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    successors: %bb.1, %bb.3
    successors: %bb.1, %bb.3

    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $mode, implicit $exec

    S_CBRANCH_VCCZ %bb.1, implicit $vcc
    S_CBRANCH_VCCZ %bb.1, implicit $vcc

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    successors: %bb.4
    successors: %bb.4

    S_NOP 1
    S_NOP 1

    S_BRANCH %bb.4
    S_BRANCH %bb.4




  bb.4:
  bb.4:

    successors: %bb.5
    successors: %bb.5

    S_NOP 1
    S_NOP 1

    S_BRANCH %bb.5
    S_BRANCH %bb.5




  bb.5:
  bb.5:

    successors: %bb.1, %bb.6
    successors: %bb.1, %bb.6

    S_SETREG_IMM32_B32 3, 2177
    S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode

    S_CBRANCH_VCCZ %bb.1, implicit $vcc
    S_CBRANCH_VCCZ %bb.1, implicit $vcc

    S_BRANCH %bb.6
    S_BRANCH %bb.6




  bb.6:
  bb.6:

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that mode is propagated back to start of loop and through a block that
# check that mode is propagated back to start of loop and through a block that

Show All 22 Linesbody: |

  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3

    S_NOP 1
    S_NOP 1

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    successors: %bb.1, %bb.4
    successors: %bb.1, %bb.4

    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec
    $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_CBRANCH_VCCZ %bb.1, implicit $vcc
    S_CBRANCH_VCCZ %bb.1, implicit $vcc

    S_BRANCH %bb.4
    S_BRANCH %bb.4




  bb.4:
  bb.4:

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that multiple mode values are propagated to a block that uses the mode
# check that multiple mode values are propagated to a block that uses the mode

Show All 14 Linesbody: |




  bb.1:
  bb.1:

    successors: %bb.2, %bb.3
    successors: %bb.2, %bb.3

    S_CBRANCH_VCCZ %bb.2, implicit $vcc
    S_CBRANCH_VCCZ %bb.2, implicit $vcc

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3

    S_SETREG_IMM32_B32 3, 2177
    S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    successors: %bb.4
    successors: %bb.4

    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $mode, implicit $exec

    S_BRANCH %bb.4
    S_BRANCH %bb.4




  bb.4:
  bb.4:

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that multiple mode values are propagated through a block that neither
# check that multiple mode values are propagated through a block that neither

# sets or uses the mode.
# sets or uses the mode.

Show All 14 Linesbody: |




  bb.1:
  bb.1:

    successors: %bb.2, %bb.3
    successors: %bb.2, %bb.3

    S_CBRANCH_VCCZ %bb.2, implicit $vcc
    S_CBRANCH_VCCZ %bb.2, implicit $vcc

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3

    S_SETREG_IMM32_B32 3, 2177
    S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    successors: %bb.4
    successors: %bb.4

    S_NOP 1
    S_NOP 1

    S_BRANCH %bb.4
    S_BRANCH %bb.4




  bb.4:
  bb.4:

    successors: %bb.5
    successors: %bb.5

    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $mode, implicit $exec

    S_BRANCH %bb.5
    S_BRANCH %bb.5




  bb.5:
  bb.5:

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# CHECK-LABEL: name: pass_through_blocks
# CHECK-LABEL: name: pass_through_blocks

# CHECK-LABEL: bb.0:
# CHECK-LABEL: bb.0:

# CHECK: V_FRACT_F64_e32
# CHECK: V_FRACT_F64_e32

# CHECK-NEXT: S_SETREG_IMM32_B32 3, 2177
# CHECK-NEXT: S_SETREG_IMM32_B32 3, 2177

# CHECK-NOT: S_SETREG_IMM32_B32
# CHECK-NOT: S_SETREG_IMM32_B32




name: pass_through_blocks
name: pass_through_blocks




body: |
body: |

  bb.0:
  bb.0:

    successors: %bb.1
    successors: %bb.1

    liveins: $vgpr1_vgpr2
    liveins: $vgpr1_vgpr2

    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $exec
    $vgpr1_vgpr2 = V_FRACT_F64_e32 killed $vgpr1_vgpr2, implicit $mode, implicit $exec

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    successors: %bb.2
    successors: %bb.2

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    successors: %bb.4
    successors: %bb.4

    S_BRANCH %bb.4
    S_BRANCH %bb.4




  bb.4:
  bb.4:

    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $m0, implicit $exec
    $vgpr1 = V_INTERP_P1LL_F16 0, $vgpr0, 2, 1, 0, 0, 0, implicit $mode, implicit $m0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---

# check that multiple mode values are propagated
# check that multiple mode values are propagated

# CHECK-LABEL: name: if_then_else
# CHECK-LABEL: name: if_then_else

# CHECK-LABEL: bb.3:
# CHECK-LABEL: bb.3:

# CHECK: S_SETREG_IMM32_B32 0, 2177
# CHECK: S_SETREG_IMM32_B32 0, 2177

# CHECK: V_FRACT_F64_e32
# CHECK: V_FRACT_F64_e32

Show All 10 Linesbody: |




  bb.1:
  bb.1:

    successors: %bb.2, %bb.3
    successors: %bb.2, %bb.3

    S_CBRANCH_VCCZ %bb.3, implicit $vcc
    S_CBRANCH_VCCZ %bb.3, implicit $vcc

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3

    S_SETREG_IMM32_B32 3, 2177
    S_SETREG_IMM32_B32 3, 2177, implicit-def $mode, implicit $mode

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.3:
  bb.3:

    successors: %bb.4
    successors: %bb.4

    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $exec
    $vgpr3_vgpr4 = V_FRACT_F64_e32 killed $vgpr3_vgpr4, implicit $mode, implicit $exec

    S_BRANCH %bb.4
    S_BRANCH %bb.4




  bb.4:
  bb.4:

    S_ENDPGM 0
    S_ENDPGM 0

...
...

llvm/test/CodeGen/AMDGPU/movrels-bug.mir
Show All 18 Lines
name:            main
name:            main

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    $m0 = S_MOV_B32 undef $sgpr0
    $m0 = S_MOV_B32 undef $sgpr0

    V_MOVRELD_B32_e32 undef $vgpr2, 0, implicit $m0, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)
    V_MOVRELD_B32_e32 undef $vgpr2, 0, implicit $m0, implicit $exec, implicit-def $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8, implicit undef $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8(tied-def 4)

    $m0 = S_MOV_B32 undef $sgpr0
    $m0 = S_MOV_B32 undef $sgpr0

    $vgpr1 = V_MOVRELS_B32_e32 undef $vgpr1, implicit $m0, implicit $exec, implicit killed $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8
    $vgpr1 = V_MOVRELS_B32_e32 undef $vgpr1, implicit $m0, implicit $exec, implicit killed $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8

    $vgpr4 = V_MAC_F32_e32 undef $vgpr0, undef $vgpr0, undef $vgpr4, implicit $exec
    $vgpr4 = nofpexcept V_MAC_F32_e32 undef $vgpr0, undef $vgpr0, undef $vgpr4, implicit $mode, implicit $exec

    EXP_DONE 15, undef $vgpr0, killed $vgpr1, killed $vgpr4, undef $vgpr0, 0, 0, 12, implicit $exec
    EXP_DONE 15, undef $vgpr0, killed $vgpr1, killed $vgpr4, undef $vgpr0, 0, 0, 12, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/omod-nsz-flag.mir
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands  %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fold-operands  %s -o - | FileCheck -check-prefix=GCN %s




---
---




# FIXME: Is it OK to fold omod for this?
# FIXME: Is it OK to fold omod for this?

# GCN-LABEL: name: omod_inst_flag_nsz_src
# GCN-LABEL: name: omod_inst_flag_nsz_src

# GCN: %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
# GCN: %0:vgpr_32 = nsz nofpexcept V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: %1:vgpr_32 = V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
# GCN-NEXT: %1:vgpr_32 = nofpexcept V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: S_ENDPGM 0, implicit %1
# GCN-NEXT: S_ENDPGM 0, implicit %1

name: omod_inst_flag_nsz_src
name: omod_inst_flag_nsz_src

tracksRegLiveness: true
tracksRegLiveness: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    ieee: false
    ieee: false

    fp32-output-denormals: false
    fp32-output-denormals: false




body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




  %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
  %0:vgpr_32 = nsz nofpexcept V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec

  %1:vgpr_32 = V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
  %1:vgpr_32 = nofpexcept V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $mode, implicit $exec

  S_ENDPGM 0, implicit %1
  S_ENDPGM 0, implicit %1




...
...

---
---




# GCN-LABEL: name: omod_inst_flag_nsz_result
# GCN-LABEL: name: omod_inst_flag_nsz_result

# GCN: %0:vgpr_32 = V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $exec
# GCN: %0:vgpr_32 = nofpexcept V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $mode, implicit $exec

# GCN-NEXT: S_ENDPGM 0, implicit %0
# GCN-NEXT: S_ENDPGM 0, implicit %0




name: omod_inst_flag_nsz_result
name: omod_inst_flag_nsz_result

tracksRegLiveness: true
tracksRegLiveness: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    ieee: false
    ieee: false

    fp32-output-denormals: false
    fp32-output-denormals: false




body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




  %0:vgpr_32 = V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
  %0:vgpr_32 = nofpexcept V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec

  %1:vgpr_32 = nsz V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
  %1:vgpr_32 = nsz nofpexcept V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $mode, implicit $exec

  S_ENDPGM 0, implicit %1
  S_ENDPGM 0, implicit %1

...
...




---
---




# GCN-LABEL: name: omod_inst_flag_nsz_both
# GCN-LABEL: name: omod_inst_flag_nsz_both

# GCN: %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $exec
# GCN: %0:vgpr_32 = nsz nofpexcept V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 1, implicit $mode, implicit $exec

# GCN-NEXT: S_ENDPGM 0, implicit %0
# GCN-NEXT: S_ENDPGM 0, implicit %0




name: omod_inst_flag_nsz_both
name: omod_inst_flag_nsz_both

tracksRegLiveness: true
tracksRegLiveness: true

machineFunctionInfo:
machineFunctionInfo:

  mode:
  mode:

    ieee: false
    ieee: false

    fp32-output-denormals: false
    fp32-output-denormals: false




body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1
    liveins: $vgpr0, $vgpr1




  %0:vgpr_32 = nsz V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $exec
  %0:vgpr_32 = nsz nofpexcept V_ADD_F32_e64 0, $vgpr0, 0, $vgpr1, 0, 0, implicit $mode, implicit $exec

  %1:vgpr_32 = nsz V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $exec
  %1:vgpr_32 = nsz nofpexcept V_MUL_F32_e64 0, %0, 0, 1073741824, 0, 0, implicit $mode, implicit $exec

  S_ENDPGM 0, implicit %1
  S_ENDPGM 0, implicit %1

...
...

llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir
Show All 9 Lines
name:            test
name:            test

body:             |
body:             |

  bb.0.entry:
  bb.0.entry:




    $sgpr6 = S_MOV_B32 $sgpr5
    $sgpr6 = S_MOV_B32 $sgpr5

    $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr0_sgpr1_sgpr2_sgpr3
    $sgpr10_sgpr11 = S_MOV_B64 $sgpr2_sgpr3, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11, implicit $sgpr0_sgpr1_sgpr2_sgpr3

    $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3
    $sgpr8_sgpr9 = S_MOV_B64 $sgpr0_sgpr1, implicit killed $sgpr0_sgpr1_sgpr2_sgpr3

    S_BARRIER
    S_BARRIER

    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_32X32X1F32 undef $vgpr0, undef $vgpr0, 0, 0, 0, 2, implicit $exec
    $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_32X32X1F32 undef $vgpr0, undef $vgpr0, 0, 0, 0, 2, implicit $mode, implicit $exec

    $vgpr0 = V_ACCVGPR_READ_B32 $agpr31, implicit $exec
    $vgpr0 = V_ACCVGPR_READ_B32 $agpr31, implicit $exec

    BUFFER_STORE_DWORD_OFFEN killed $vgpr0, undef $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr6, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN killed $vgpr0, undef $vgpr0, $sgpr8_sgpr9_sgpr10_sgpr11, $sgpr6, 0, 0, 0, 0, 0, 0, implicit $exec




...
...

llvm/test/CodeGen/AMDGPU/regcoal-subrange-join-seg.mir
Show First 20 Lines • Show All 182 Lines • ▼ Show 20 Lines  bb.27:

    S_BRANCH %bb.28
    S_BRANCH %bb.28




  bb.28:
  bb.28:

    %9 = S_FF1_I32_B32 undef %10
    %9 = S_FF1_I32_B32 undef %10

    %13 = V_MAD_U32_U24 killed %9, 48, 32, 0, implicit $exec
    %13 = V_MAD_U32_U24 killed %9, 48, 32, 0, implicit $exec

    %45 = BUFFER_LOAD_DWORD_OFFEN killed %13, undef %15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)
    %45 = BUFFER_LOAD_DWORD_OFFEN killed %13, undef %15, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable invariant load 4)

    %46 = V_AND_B32_e32 1, killed %45, implicit $exec
    %46 = V_AND_B32_e32 1, killed %45, implicit $exec

    %21 = S_BUFFER_LOAD_DWORD_SGPR undef %22, undef %23, 0, 0 :: (dereferenceable invariant load 4)
    %21 = S_BUFFER_LOAD_DWORD_SGPR undef %22, undef %23, 0, 0 :: (dereferenceable invariant load 4)

    %25 = V_CMP_GE_F32_e64 0, 0, 0, killed %21, 0, implicit $exec
    %25 = nofpexcept V_CMP_GE_F32_e64 0, 0, 0, killed %21, 0, implicit $mode, implicit $exec

    %26 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %25, implicit $exec
    %26 = V_CNDMASK_B32_e64 0, 0, 0, -1, killed %25, implicit $exec

    %62 = IMPLICIT_DEF
    %62 = IMPLICIT_DEF




  bb.29:
  bb.29:

    successors: %bb.30(0x30000000), %bb.36(0x50000000)
    successors: %bb.30(0x30000000), %bb.36(0x50000000)




    %53 = COPY killed %62
    %53 = COPY killed %62

    %47 = V_ADD_I32_e32 -1, %46, implicit-def dead $vcc, implicit $exec
    %47 = V_ADD_I32_e32 -1, %46, implicit-def dead $vcc, implicit $exec

    %48 = V_OR_B32_e32 killed %47, %26, implicit $exec
    %48 = V_OR_B32_e32 killed %47, %26, implicit $exec

    %49 = COPY %53
    %49 = COPY %53

    %49.sub2 = COPY undef %48
    %49.sub2 = COPY undef %48

    %51 = COPY killed %49
    %51 = COPY killed %49

    %51.sub3 = COPY undef %26
    %51.sub3 = COPY undef %26

    V_CMP_NE_U32_e32 0, killed %48, implicit-def $vcc, implicit $exec
    V_CMP_NE_U32_e32 0, killed %48, implicit-def $vcc, implicit $exec

    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc

    S_CBRANCH_VCCZ %bb.30, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.30, implicit killed $vcc




  bb.36:
  bb.36:

    %63 = COPY killed %51
    %63 = COPY killed %51

    S_BRANCH %bb.31
    S_BRANCH %bb.31




  bb.30:
  bb.30:

    %33 = V_MAD_F32 1, killed %53.sub0, 0, undef %34, 0, 0, 0, 0, implicit $exec
    %33 = nofpexcept V_MAD_F32 1, killed %53.sub0, 0, undef %34, 0, 0, 0, 0, implicit $mode, implicit $exec

    %35 = V_MAC_F32_e32 killed %33, undef %36, undef %35, implicit $exec
    %35 = nofpexcept V_MAC_F32_e32 killed %33, undef %36, undef %35, implicit $mode, implicit $exec

    %38 = V_MAX_F32_e32 0, killed %35, implicit $exec
    %38 = nofpexcept V_MAX_F32_e32 0, killed %35, implicit $mode, implicit $exec

    %39 = V_LOG_F32_e32 killed %38, implicit $exec
    %39 = nofpexcept V_LOG_F32_e32 killed %38, implicit $mode, implicit $exec

    %40 = V_MUL_F32_e32 killed %39, undef %41, implicit $exec
    %40 = nofpexcept V_MUL_F32_e32 killed %39, undef %41, implicit $mode, implicit $exec

    %42 = V_EXP_F32_e32 killed %40, implicit $exec
    %42 = nofpexcept V_EXP_F32_e32 killed %40, implicit $mode, implicit $exec

    dead %43 = V_MUL_F32_e32 killed %42, undef %44, implicit $exec
    dead %43 = nofpexcept V_MUL_F32_e32 killed %42, undef %44, implicit $mode, implicit $exec

    %63 = COPY killed %51
    %63 = COPY killed %51




  bb.31:
  bb.31:

    %52 = COPY killed %63
    %52 = COPY killed %63

    %62 = COPY killed %52
    %62 = COPY killed %52

    S_BRANCH %bb.29
    S_BRANCH %bb.29




  bb.32:
  bb.32:

Show All 11 Lines
llvm/test/CodeGen/AMDGPU/regcoal-subrange-join.mir
Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Linesbody:             |




  bb.5:
  bb.5:

    %58 = COPY killed %1
    %58 = COPY killed %1

    %59 = COPY killed %17
    %59 = COPY killed %17

    S_BRANCH %bb.2
    S_BRANCH %bb.2




  bb.1:
  bb.1:

    %30 = V_MOV_B32_e32 1036831949, implicit $exec
    %30 = V_MOV_B32_e32 1036831949, implicit $exec

    %31 = V_ADD_F32_e32 %30, %1.sub3, implicit $exec
    %31 = nofpexcept V_ADD_F32_e32 %30, %1.sub3, implicit $mode, implicit $exec

    %33 = V_ADD_F32_e32 %30, %1.sub2, implicit $exec
    %33 = nofpexcept V_ADD_F32_e32 %30, %1.sub2, implicit $mode, implicit $exec

    %35 = V_ADD_F32_e32 %30, %1.sub1, implicit $exec
    %35 = nofpexcept V_ADD_F32_e32 %30, %1.sub1, implicit $mode, implicit $exec

    %37 = V_ADD_F32_e32 killed %30, killed %1.sub0, implicit $exec
    %37 = nofpexcept V_ADD_F32_e32 killed %30, killed %1.sub0, implicit $mode, implicit $exec

    undef %56.sub0 = COPY killed %37
    undef %56.sub0 = COPY killed %37

    %56.sub1 = COPY killed %35
    %56.sub1 = COPY killed %35

    %56.sub2 = COPY killed %33
    %56.sub2 = COPY killed %33

    %56.sub3 = COPY killed %31
    %56.sub3 = COPY killed %31

    %28 = S_MOV_B32 0
    %28 = S_MOV_B32 0

    %2 = COPY killed %56
    %2 = COPY killed %56

    %58 = COPY killed %2
    %58 = COPY killed %2

    %59 = COPY killed %28
    %59 = COPY killed %28




  bb.2:
  bb.2:

    %4 = COPY killed %59
    %4 = COPY killed %59

    %3 = COPY killed %58
    %3 = COPY killed %58

    %39 = S_LOAD_DWORDX2_IMM killed %0, 6, 0, 0
    %39 = S_LOAD_DWORDX2_IMM killed %0, 6, 0, 0

    %40 = S_LOAD_DWORD_IMM killed %39, 0, 0, 0
    %40 = S_LOAD_DWORD_IMM killed %39, 0, 0, 0

    %43 = V_MOV_B32_e32 -1102263091, implicit $exec
    %43 = V_MOV_B32_e32 -1102263091, implicit $exec

    %60 = COPY killed %4
    %60 = COPY killed %4

    %61 = COPY killed %3
    %61 = COPY killed %3




  bb.3:
  bb.3:

    successors: %bb.3, %bb.4
    successors: %bb.3, %bb.4




    %7 = COPY killed %61
    %7 = COPY killed %61

    %6 = COPY killed %60
    %6 = COPY killed %60

    %8 = S_ADD_I32 killed %6, 1, implicit-def dead $scc
    %8 = S_ADD_I32 killed %6, 1, implicit-def dead $scc

    %44 = V_ADD_F32_e32 %43, %7.sub3, implicit $exec
    %44 = nofpexcept V_ADD_F32_e32 %43, %7.sub3, implicit $mode, implicit $exec

    %46 = V_ADD_F32_e32 %43, %7.sub2, implicit $exec
    %46 = nofpexcept V_ADD_F32_e32 %43, %7.sub2, implicit $mode, implicit $exec

    %48 = V_ADD_F32_e32 %43, %7.sub1, implicit $exec
    %48 = nofpexcept V_ADD_F32_e32 %43, %7.sub1, implicit $mode, implicit $exec

    %50 = V_ADD_F32_e32 %43, killed %7.sub0, implicit $exec
    %50 = nofpexcept V_ADD_F32_e32 %43, killed %7.sub0, implicit $mode, implicit $exec

    undef %57.sub0 = COPY killed %50
    undef %57.sub0 = COPY killed %50

    %57.sub1 = COPY killed %48
    %57.sub1 = COPY killed %48

    %57.sub2 = COPY %46
    %57.sub2 = COPY %46

    %57.sub3 = COPY killed %44
    %57.sub3 = COPY killed %44

    S_CMP_LT_I32 %8, %40, implicit-def $scc
    S_CMP_LT_I32 %8, %40, implicit-def $scc

    %60 = COPY killed %8
    %60 = COPY killed %8

    %61 = COPY killed %57
    %61 = COPY killed %57

    S_CBRANCH_SCC1 %bb.3, implicit killed $scc
    S_CBRANCH_SCC1 %bb.3, implicit killed $scc

    S_BRANCH %bb.4
    S_BRANCH %bb.4




  bb.4:
  bb.4:

    EXP 32, undef %53, undef %54, killed %46, undef %55, 0, 0, 15, implicit $exec
    EXP 32, undef %53, undef %54, killed %46, undef %55, 0, 0, 15, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir
Show All 17 Lines  bb.1:

    %1 : sreg_32_xm0 = S_MOV_B32 0
    %1 : sreg_32_xm0 = S_MOV_B32 0

    undef %0.sub0 : sreg_64 = COPY %1
    undef %0.sub0 : sreg_64 = COPY %1

    %0.sub1 = COPY %1
    %0.sub1 = COPY %1

    %4 : vreg_64 = COPY killed %0
    %4 : vreg_64 = COPY killed %0

    %5 : vreg_64 = IMPLICIT_DEF
    %5 : vreg_64 = IMPLICIT_DEF

    %6 : vreg_64 = COPY killed %4
    %6 : vreg_64 = COPY killed %4




  bb.2:
  bb.2:

    %2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit $exec
    %2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit $mode, implicit $exec




  bb.3:
  bb.3:

    %3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit $exec
    %3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

llvm/test/CodeGen/AMDGPU/regcoalescing-remove-partial-redundancy-assert.mir
# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s

#
#

# This test gave "Use not jointly dominated by defs" when
# This test gave "Use not jointly dominated by defs" when

# removePartialRedundancy attempted to prune and then re-extend a subrange.
# removePartialRedundancy attempted to prune and then re-extend a subrange.

#
#

# GCN: {{^body}}
# GCN: {{^body}}




---
---

name:            _amdgpu_ps_main
name:            _amdgpu_ps_main

tracksRegLiveness: true
tracksRegLiveness: true

body:             |
body:             |

  bb.0:
  bb.0:

    successors: %bb.1, %bb.2
    successors: %bb.1, %bb.2

  


    %21:vgpr_32 = V_TRUNC_F32_e32 undef %22:vgpr_32, implicit $exec
    %21:vgpr_32 = nofpexcept V_TRUNC_F32_e32 undef %22:vgpr_32, implicit $mode, implicit $exec

    %23:vgpr_32 = V_CVT_U32_F32_e32 killed %21, implicit $exec
    %23:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %21, implicit $mode, implicit $exec

    %108:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec
    %108:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec

    undef %109.sub1:vreg_128 = COPY %108
    undef %109.sub1:vreg_128 = COPY %108

    %28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sgpr_128, 3044, 0, 0 :: (dereferenceable invariant load 4)
    %28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sgpr_128, 3044, 0, 0 :: (dereferenceable invariant load 4)

    S_CMP_EQ_U32 killed %28, 0, implicit-def $scc
    S_CMP_EQ_U32 killed %28, 0, implicit-def $scc

    S_CBRANCH_SCC0 %bb.2, implicit killed $scc
    S_CBRANCH_SCC0 %bb.2, implicit killed $scc

  


  bb.1:
  bb.1:

    %138:vreg_128 = COPY killed %109
    %138:vreg_128 = COPY killed %109

    S_BRANCH %bb.9
    S_BRANCH %bb.9

  


  bb.2:
  bb.2:

    successors: %bb.3, %bb.4
    successors: %bb.3, %bb.4

  


    S_CBRANCH_SCC0 %bb.4, implicit undef $scc
    S_CBRANCH_SCC0 %bb.4, implicit undef $scc

  


  bb.3:
  bb.3:

    %136:vreg_128 = COPY killed %109
    %136:vreg_128 = COPY killed %109

    S_BRANCH %bb.5
    S_BRANCH %bb.5

  


  bb.4:
  bb.4:

    %136:vreg_128 = COPY killed %109
    %136:vreg_128 = COPY killed %109

  


  bb.5:
  bb.5:

    successors: %bb.6, %bb.8
    successors: %bb.6, %bb.8

  


    %110:vreg_128 = COPY killed %136
    %110:vreg_128 = COPY killed %136

    dead %32:sreg_32_xm0 = S_MOV_B32 0
    dead %32:sreg_32_xm0 = S_MOV_B32 0

    %111:vreg_128 = COPY %110
    %111:vreg_128 = COPY %110

    %111.sub3:vreg_128 = COPY undef %32
    %111.sub3:vreg_128 = COPY undef %32

    S_CBRANCH_SCC1 %bb.8, implicit undef $scc
    S_CBRANCH_SCC1 %bb.8, implicit undef $scc

    S_BRANCH %bb.6
    S_BRANCH %bb.6

  


  bb.6:
  bb.6:

    %36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sgpr_128, 2708, 0, 0 :: (dereferenceable invariant load 4)
    %36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sgpr_128, 2708, 0, 0 :: (dereferenceable invariant load 4)

    %39:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %110.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec
    %39:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %110.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %40:vgpr_32 = V_MAD_F32 0, %111.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $exec
    %40:vgpr_32 = nofpexcept V_MAD_F32 0, %111.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %41:vgpr_32 = V_MUL_F32_e64 0, 0, 0, killed %40, 1, 0, implicit $exec
    %41:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 0, 0, killed %40, 1, 0, implicit $mode, implicit $exec

    %43:vgpr_32 = V_MUL_F32_e32 0, %39, implicit $exec
    %43:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %39, implicit $mode, implicit $exec

    %44:vgpr_32 = COPY killed %43
    %44:vgpr_32 = COPY killed %43

    %44:vgpr_32 = V_MAC_F32_e32 0, killed %41, %44, implicit $exec
    %44:vgpr_32 = nofpexcept V_MAC_F32_e32 0, killed %41, %44, implicit $mode, implicit $exec

    %47:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
    %47:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec

    %46:vgpr_32 = COPY killed %47
    %46:vgpr_32 = COPY killed %47

    %46:vgpr_32 = V_MAC_F32_e32 0, killed %39, %46, implicit $exec
    %46:vgpr_32 = nofpexcept V_MAC_F32_e32 0, killed %39, %46, implicit $mode, implicit $exec

    undef %115.sub0:vreg_128 = COPY %46
    undef %115.sub0:vreg_128 = COPY %46

    %115.sub1:vreg_128 = COPY killed %46
    %115.sub1:vreg_128 = COPY killed %46

    %115.sub2:vreg_128 = COPY killed %44
    %115.sub2:vreg_128 = COPY killed %44

    %50:sreg_64_xexec = V_CMP_NE_U32_e64 0, killed %36, implicit $exec
    %50:sreg_64_xexec = V_CMP_NE_U32_e64 0, killed %36, implicit $exec

    dead %118:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    dead %118:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %137:vreg_128 = IMPLICIT_DEF
    %137:vreg_128 = IMPLICIT_DEF

  


  bb.7:
  bb.7:

    successors: %bb.7, %bb.8
    successors: %bb.7, %bb.8

  


    %119:vreg_128 = COPY killed %137
    %119:vreg_128 = COPY killed %137

    %121:vreg_128 = COPY killed %119
    %121:vreg_128 = COPY killed %119

    %121.sub3:vreg_128 = COPY undef %32
    %121.sub3:vreg_128 = COPY undef %32

    %56:vgpr_32 = V_ADD_F32_e32 %115.sub2, %121.sub2, implicit $exec
    %56:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub2, %121.sub2, implicit $mode, implicit $exec

    %59:vgpr_32 = V_ADD_F32_e32 %115.sub1, %121.sub1, implicit $exec
    %59:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub1, %121.sub1, implicit $mode, implicit $exec

    %62:vgpr_32 = V_ADD_F32_e32 %115.sub0, killed %121.sub0, implicit $exec
    %62:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub0, killed %121.sub0, implicit $mode, implicit $exec

    undef %117.sub0:vreg_128 = COPY killed %62
    undef %117.sub0:vreg_128 = COPY killed %62

    %117.sub1:vreg_128 = COPY killed %59
    %117.sub1:vreg_128 = COPY killed %59

    %117.sub2:vreg_128 = COPY killed %56
    %117.sub2:vreg_128 = COPY killed %56

    %64:sreg_64 = S_AND_B64 $exec, %50, implicit-def dead $scc
    %64:sreg_64 = S_AND_B64 $exec, %50, implicit-def dead $scc

    $vcc = COPY killed %64
    $vcc = COPY killed %64

    %137:vreg_128 = COPY killed %117
    %137:vreg_128 = COPY killed %117

    S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
    S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc

    S_BRANCH %bb.8
    S_BRANCH %bb.8

  


  bb.8:
  bb.8:

    dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sgpr_128, 2704, 0, 0 :: (dereferenceable invariant load 4)
    dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sgpr_128, 2704, 0, 0 :: (dereferenceable invariant load 4)

    %138:vreg_128 = COPY killed %111
    %138:vreg_128 = COPY killed %111

  


  bb.9:
  bb.9:

    %113:vreg_128 = COPY killed %138
    %113:vreg_128 = COPY killed %138

    S_CBRANCH_SCC1 %bb.18, implicit undef $scc
    S_CBRANCH_SCC1 %bb.18, implicit undef $scc

    S_BRANCH %bb.10
    S_BRANCH %bb.10

  


  bb.10:
  bb.10:

    S_CBRANCH_SCC1 %bb.12, implicit undef $scc
    S_CBRANCH_SCC1 %bb.12, implicit undef $scc

    S_BRANCH %bb.11
    S_BRANCH %bb.11

  


  bb.11:
  bb.11:

  


  bb.12:
  bb.12:

    successors: %bb.13, %bb.18
    successors: %bb.13, %bb.18

  


    S_CBRANCH_SCC1 %bb.18, implicit undef $scc
    S_CBRANCH_SCC1 %bb.18, implicit undef $scc

    S_BRANCH %bb.13
    S_BRANCH %bb.13

  


  bb.13:
  bb.13:

    successors: %bb.14, %bb.17
    successors: %bb.14, %bb.17

  


    S_CBRANCH_SCC1 %bb.17, implicit undef $scc
    S_CBRANCH_SCC1 %bb.17, implicit undef $scc

    S_BRANCH %bb.14
    S_BRANCH %bb.14

  


  bb.14:
  bb.14:

    S_CBRANCH_SCC1 %bb.16, implicit undef $scc
    S_CBRANCH_SCC1 %bb.16, implicit undef $scc

    S_BRANCH %bb.15
    S_BRANCH %bb.15

  


  bb.15:
  bb.15:

  


  bb.16:
  bb.16:

  


  bb.17:
  bb.17:

  


  bb.18:
  bb.18:

    S_CBRANCH_SCC1 %bb.26, implicit undef $scc
    S_CBRANCH_SCC1 %bb.26, implicit undef $scc

    S_BRANCH %bb.19
    S_BRANCH %bb.19

  


  bb.19:
  bb.19:

    S_CBRANCH_SCC1 %bb.26, implicit undef $scc
    S_CBRANCH_SCC1 %bb.26, implicit undef $scc

    S_BRANCH %bb.20
    S_BRANCH %bb.20

  


  bb.20:
  bb.20:

    S_CBRANCH_SCC1 %bb.25, implicit undef $scc
    S_CBRANCH_SCC1 %bb.25, implicit undef $scc

    S_BRANCH %bb.21
    S_BRANCH %bb.21

  


  bb.21:
  bb.21:

    successors: %bb.22, %bb.24
    successors: %bb.22, %bb.24

  


    S_CBRANCH_SCC1 %bb.24, implicit undef $scc
    S_CBRANCH_SCC1 %bb.24, implicit undef $scc

    S_BRANCH %bb.22
    S_BRANCH %bb.22

  


  bb.22:
  bb.22:

    successors: %bb.23, %bb.24
    successors: %bb.23, %bb.24

  


    S_CBRANCH_SCC1 %bb.24, implicit undef $scc
    S_CBRANCH_SCC1 %bb.24, implicit undef $scc

    S_BRANCH %bb.23
    S_BRANCH %bb.23

  


  bb.23:
  bb.23:

  


  bb.24:
  bb.24:

  


  bb.25:
  bb.25:

  


  bb.26:
  bb.26:

    S_CBRANCH_SCC1 %bb.33, implicit undef $scc
    S_CBRANCH_SCC1 %bb.33, implicit undef $scc

    S_BRANCH %bb.27
    S_BRANCH %bb.27

  


  bb.27:
  bb.27:

    S_CBRANCH_SCC1 %bb.33, implicit undef $scc
    S_CBRANCH_SCC1 %bb.33, implicit undef $scc

    S_BRANCH %bb.28
    S_BRANCH %bb.28

  


  bb.28:
  bb.28:

    dead %77:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    dead %77:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %78:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %113.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 1065353216, 0, 0, implicit $exec
    %78:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %113.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 1065353216, 0, 0, implicit $mode, implicit $exec

    dead %80:sreg_32_xm0 = S_MOV_B32 0
    dead %80:sreg_32_xm0 = S_MOV_B32 0

    dead %82:vgpr_32 = V_MUL_F32_e32 killed %78, %78, implicit $exec
    dead %82:vgpr_32 = nofpexcept V_MUL_F32_e32 killed %78, %78, implicit $mode, implicit $exec

    dead %126:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
    dead %126:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec

    dead %125:vreg_128 = IMPLICIT_DEF
    dead %125:vreg_128 = IMPLICIT_DEF

    dead %91:sreg_32_xm0 = S_MOV_B32 2143289344
    dead %91:sreg_32_xm0 = S_MOV_B32 2143289344

    %96:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc
    %96:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc

    %139:vreg_128 = IMPLICIT_DEF
    %139:vreg_128 = IMPLICIT_DEF

  


  bb.29:
  bb.29:

    successors: %bb.30, %bb.31
    successors: %bb.30, %bb.31

  


    dead %127:vreg_128 = COPY killed %139
    dead %127:vreg_128 = COPY killed %139

    S_CBRANCH_SCC0 %bb.31, implicit undef $scc
    S_CBRANCH_SCC0 %bb.31, implicit undef $scc

  


  bb.30:
  bb.30:

    S_BRANCH %bb.32
    S_BRANCH %bb.32

  


  bb.31:
  bb.31:

    successors: %bb.32, %bb.34
    successors: %bb.32, %bb.34

  


    $vcc = COPY %96
    $vcc = COPY %96

    S_CBRANCH_VCCNZ %bb.34, implicit killed $vcc
    S_CBRANCH_VCCNZ %bb.34, implicit killed $vcc

    S_BRANCH %bb.32
    S_BRANCH %bb.32

  


  bb.32:
  bb.32:

    dead %130:vreg_128 = IMPLICIT_DEF
    dead %130:vreg_128 = IMPLICIT_DEF

    dead %128:vreg_128 = COPY undef %130
    dead %128:vreg_128 = COPY undef %130

    %139:vreg_128 = IMPLICIT_DEF
    %139:vreg_128 = IMPLICIT_DEF

    S_BRANCH %bb.29
    S_BRANCH %bb.29

  


  bb.33:
  bb.33:

    S_ENDPGM 0
    S_ENDPGM 0

  


  bb.34:
  bb.34:

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/rename-independent-subregs-mac-operands.mir
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s

---
---




# GCN-LABEL: name: mac_invalid_operands
# GCN-LABEL: name: mac_invalid_operands

# GCN: undef %18.sub0:vreg_128 = V_MAC_F32_e32 undef %3:vgpr_32, undef %9:vgpr_32, undef %18.sub0, implicit $exec
# GCN: undef %18.sub0:vreg_128 = nofpexcept V_MAC_F32_e32 undef %3:vgpr_32, undef %9:vgpr_32, undef %18.sub0, implicit $mode, implicit $exec




name:            mac_invalid_operands
name:            mac_invalid_operands

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

legalized:       false
legalized:       false

regBankSelected: false
regBankSelected: false

selected:        false
selected:        false

tracksRegLiveness: true
tracksRegLiveness: true

Show All 19 Linesregisters:

  - { id: 14, class: vgpr_32 }
  - { id: 14, class: vgpr_32 }

  - { id: 15, class: vreg_64 }
  - { id: 15, class: vreg_64 }

  - { id: 16, class: vgpr_32 }
  - { id: 16, class: vgpr_32 }

  - { id: 17, class: vreg_128 }
  - { id: 17, class: vreg_128 }

body:             |
body:             |

  bb.0:
  bb.0:

    successors: %bb.2, %bb.1
    successors: %bb.2, %bb.1




    %7 = V_CMP_NEQ_F32_e64 0, 0, 0, undef %3, 0, implicit $exec
    %7 = nofpexcept V_CMP_NEQ_F32_e64 0, 0, 0, undef %3, 0, implicit $mode, implicit $exec

    $vcc = COPY killed %7
    $vcc = COPY killed %7

    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc




  bb.1:
  bb.1:

    successors: %bb.3
    successors: %bb.3




    %4 = V_ADD_F32_e32 undef %6, undef %5, implicit $exec
    %4 = nofpexcept V_ADD_F32_e32 undef %6, undef %5, implicit $mode, implicit $exec

    undef %12.sub0 = COPY killed %4
    undef %12.sub0 = COPY killed %4

    %17 = COPY killed %12
    %17 = COPY killed %12

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3




    %8 = V_MAC_F32_e32 undef %3, undef %9, undef %8, implicit $exec
    %8 = nofpexcept V_MAC_F32_e32 undef %3, undef %9, undef %8, implicit $mode, implicit $exec

    undef %13.sub0 = COPY %8
    undef %13.sub0 = COPY %8

    %13.sub1 = COPY %8
    %13.sub1 = COPY %8

    %13.sub2 = COPY killed %8
    %13.sub2 = COPY killed %8

    %0 = COPY killed %13
    %0 = COPY killed %13

    %17 = COPY killed %0
    %17 = COPY killed %0




  bb.3:
  bb.3:

    %1 = COPY killed %17
    %1 = COPY killed %17

    FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
    FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr

    %14 = COPY %1.sub1
    %14 = COPY %1.sub1

    %16 = COPY killed %1.sub0
    %16 = COPY killed %1.sub0

    undef %15.sub0 = COPY killed %16
    undef %15.sub0 = COPY killed %16

    %15.sub1 = COPY killed %14
    %15.sub1 = COPY killed %14

    FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
    FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr

    S_ENDPGM 0
    S_ENDPGM 0




...
...

---
---

# Make sure others uses after the mac are properly handled and not
# Make sure others uses after the mac are properly handled and not

# left unreplaced due to iterator issues from substituteRegister.
# left unreplaced due to iterator issues from substituteRegister.




# GCN-LABEL: name: vreg_does_not_dominate
# GCN-LABEL: name: vreg_does_not_dominate




# GCN: undef %8.sub1:vreg_128 = V_MAC_F32_e32 undef %2:vgpr_32, undef %1:vgpr_32, undef %8.sub1, implicit $exec
# GCN: undef %8.sub1:vreg_128 = nofpexcept V_MAC_F32_e32 undef %2:vgpr_32, undef %1:vgpr_32, undef %8.sub1, implicit $mode, implicit $exec

# GCN: undef %7.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
# GCN: undef %7.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec

# GCN: undef %9.sub2:vreg_128 = COPY %7.sub0
# GCN: undef %9.sub2:vreg_128 = COPY %7.sub0




# GCN: undef %6.sub3:vreg_128 = V_ADD_F32_e32 undef %3:vgpr_32, undef %3:vgpr_32, implicit $exec
# GCN: undef %6.sub3:vreg_128 = nofpexcept V_ADD_F32_e32 undef %3:vgpr_32, undef %3:vgpr_32, implicit $mode, implicit $exec

# GCN: undef %7.sub0:vreg_128 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $exec
# GCN: undef %7.sub0:vreg_128 = nofpexcept V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

# GCN: %8.sub1:vreg_128 = V_ADD_F32_e32 %8.sub1, %8.sub1, implicit $exec
# GCN: %8.sub1:vreg_128 = nofpexcept V_ADD_F32_e32 %8.sub1, %8.sub1, implicit $mode, implicit $exec




# GCN: BUFFER_STORE_DWORD_OFFEN %6.sub3, %0,
# GCN: BUFFER_STORE_DWORD_OFFEN %6.sub3, %0,

# GCN: BUFFER_STORE_DWORD_OFFEN %9.sub2, %0,
# GCN: BUFFER_STORE_DWORD_OFFEN %9.sub2, %0,

# GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0,
# GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0,

# GCN: BUFFER_STORE_DWORD_OFFEN %7.sub0, %0,
# GCN: BUFFER_STORE_DWORD_OFFEN %7.sub0, %0,

name:            vreg_does_not_dominate
name:            vreg_does_not_dominate

alignment:       1
alignment:       1

exposesReturnsTwice: false
exposesReturnsTwice: false

Show All 17 Linesliveins:

  - { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
  - { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }

body:             |
body:             |

  bb.0:
  bb.0:

    successors: %bb.2, %bb.1
    successors: %bb.2, %bb.1

    liveins: $vgpr0, $sgpr30_sgpr31, $sgpr5
    liveins: $vgpr0, $sgpr30_sgpr31, $sgpr5




    %5 = COPY $sgpr30_sgpr31
    %5 = COPY $sgpr30_sgpr31

    %0 = COPY $vgpr0
    %0 = COPY $vgpr0

    undef %6.sub1 = V_MAC_F32_e32 undef %2, undef %1, undef %6.sub1, implicit $exec
    undef %6.sub1 = nofpexcept V_MAC_F32_e32 undef %2, undef %1, undef %6.sub1, implicit $mode, implicit $exec

    %6.sub0 = V_MOV_B32_e32 0, implicit $exec
    %6.sub0 = V_MOV_B32_e32 0, implicit $exec

    %6.sub2 = COPY %6.sub0
    %6.sub2 = COPY %6.sub0

    S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
    S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    successors: %bb.2
    successors: %bb.2




    %6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit $exec
    %6.sub3 = nofpexcept V_ADD_F32_e32 undef %3, undef %3, implicit $mode, implicit $exec

    %6.sub0 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $exec
    %6.sub0 = nofpexcept V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %6.sub1 = V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $exec
    %6.sub1 = nofpexcept V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $mode, implicit $exec

    %6.sub2 = COPY %6.sub0
    %6.sub2 = COPY %6.sub0




  bb.2:
  bb.2:

    BUFFER_STORE_DWORD_OFFEN %6.sub3, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %6.sub3, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, 0, 0, implicit $exec

    BUFFER_STORE_DWORD_OFFEN %6.sub2, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %6.sub2, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, 0, 0, implicit $exec

    BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, 0, 0, implicit $exec

    BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec

    $sgpr30_sgpr31 = COPY %5
    $sgpr30_sgpr31 = COPY %5

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31




...
...




# GCN-LABEL: name: inf_loop_tied_operand
# GCN-LABEL: name: inf_loop_tied_operand

# GCN: bb.0:
# GCN: bb.0:

# GCN-NEXT: undef %2.sub0:vreg_128 = V_MAC_F32_e32 1073741824, undef %0:vgpr_32, undef %2.sub0, implicit $exec
# GCN-NEXT: undef %2.sub0:vreg_128 = nofpexcept V_MAC_F32_e32 1073741824, undef %0:vgpr_32, undef %2.sub0, implicit $mode, implicit $exec

# GCN-NEXT: dead undef %3.sub1:vreg_128 = COPY %2.sub0
# GCN-NEXT: dead undef %3.sub1:vreg_128 = COPY %2.sub0




name:            inf_loop_tied_operand
name:            inf_loop_tied_operand

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vgpr_32, preferred-register: '' }
  - { id: 0, class: vgpr_32, preferred-register: '' }

  - { id: 1, class: vgpr_32, preferred-register: '' }
  - { id: 1, class: vgpr_32, preferred-register: '' }

  - { id: 2, class: vreg_128, preferred-register: '' }
  - { id: 2, class: vreg_128, preferred-register: '' }

body:             |
body:             |

  bb.0:
  bb.0:

    %1 = V_MAC_F32_e32 1073741824, undef %0, undef %1, implicit $exec
    %1 = nofpexcept V_MAC_F32_e32 1073741824, undef %0, undef %1, implicit $mode, implicit $exec

    undef %2.sub0 = COPY %1
    undef %2.sub0 = COPY %1

    %2.sub1 = COPY %1
    %2.sub1 = COPY %1




...
...

llvm/test/CodeGen/AMDGPU/sched-assert-onlydbg-value-empty-region.mir
Show All 27 Linesbody:             |

  ; CHECK:   undef %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
  ; CHECK:   undef %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec

  ; CHECK:   [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  ; CHECK:   [[DEF1:%[0-9]+]]:vreg_64 = IMPLICIT_DEF

  ; CHECK:   [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  ; CHECK:   [[DEF2:%[0-9]+]]:vreg_64 = IMPLICIT_DEF

  ; CHECK:   [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  ; CHECK:   [[DEF3:%[0-9]+]]:vreg_64 = IMPLICIT_DEF

  ; CHECK:   undef %11.sub1:vreg_64 = IMPLICIT_DEF
  ; CHECK:   undef %11.sub1:vreg_64 = IMPLICIT_DEF

  ; CHECK:   [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF4:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF5:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]
  ; CHECK:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[GLOBAL_LOAD_DWORDX2_]]

  ; CHECK:   undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $exec
  ; CHECK:   undef %6.sub0:vreg_64 = V_ADD_F32_e32 [[DEF]].sub0, [[COPY1]].sub0, implicit $mode, implicit $exec

  ; CHECK:   dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $exec
  ; CHECK:   dead undef %6.sub1:vreg_64 = V_ADD_F32_e32 [[DEF]].sub1, [[COPY1]].sub0, implicit $mode, implicit $exec

  ; CHECK:   [[DEF6:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  ; CHECK:   [[DEF6:%[0-9]+]]:vreg_64 = IMPLICIT_DEF

  ; CHECK:   [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, 0, implicit $exec
  ; CHECK:   [[GLOBAL_LOAD_DWORD1:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[COPY1]], 0, 0, 0, 0, implicit $exec

  ; CHECK:   undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $exec
  ; CHECK:   undef %19.sub0:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD1]], [[GLOBAL_LOAD_DWORDX2_]].sub0, implicit $mode, implicit $exec

  ; CHECK:   [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
  ; CHECK:   [[DEF7:%[0-9]+]]:vreg_64 = IMPLICIT_DEF

  ; CHECK:   %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $exec
  ; CHECK:   %19.sub1:vreg_64 = V_ADD_F32_e32 [[GLOBAL_LOAD_DWORD]], [[GLOBAL_LOAD_DWORD]], implicit $mode, implicit $exec

  ; CHECK:   [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; CHECK:   [[DEF8:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF

  ; CHECK:   %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec
  ; CHECK:   %4.sub1:vreg_64 = V_ADD_U32_e32 [[COPY]], [[COPY]], implicit $exec

  ; CHECK:   GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec
  ; CHECK:   GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec

  ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

  ; CHECK:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

  ; CHECK:   %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF2]], 0, 0, 0, 0, implicit $exec
  ; CHECK:   %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF2]], 0, 0, 0, 0, implicit $exec

  ; CHECK:   [[DEF1]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, 0, 0, implicit $exec
  ; CHECK:   [[DEF1]].sub0:vreg_64 = GLOBAL_LOAD_DWORD [[DEF3]], 0, 0, 0, 0, implicit $exec

  ; CHECK:   dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec
  ; CHECK:   dead %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec

  ; CHECK:   dead %21:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF6]], 0, 0, 0, 0, implicit $exec
  ; CHECK:   dead %21:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF6]], 0, 0, 0, 0, implicit $exec

  ; CHECK:   [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 2, [[DEF1]], implicit $exec
  ; CHECK:   [[V_LSHLREV_B64_:%[0-9]+]]:vreg_64 = V_LSHLREV_B64 2, [[DEF1]], implicit $exec

  ; CHECK:   dead %22:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF7]], 0, 0, 0, 0, implicit $exec
  ; CHECK:   dead %22:vgpr_32 = GLOBAL_LOAD_DWORD [[DEF7]], 0, 0, 0, 0, implicit $exec

  ; CHECK:   S_NOP 0, implicit [[DEF5]], implicit [[V_LSHLREV_B64_]].sub0, implicit [[DEF4]], implicit [[V_MOV_B32_e32_]]
  ; CHECK:   S_NOP 0, implicit [[DEF5]], implicit [[V_LSHLREV_B64_]].sub0, implicit [[DEF4]], implicit [[V_MOV_B32_e32_]]

  ; CHECK:   GLOBAL_STORE_DWORD [[DEF7]], [[V_MOV_B32_e32_1]], 0, 0, 0, 0, implicit $exec
  ; CHECK:   GLOBAL_STORE_DWORD [[DEF7]], [[V_MOV_B32_e32_1]], 0, 0, 0, 0, implicit $exec

  ; CHECK: bb.1:
  ; CHECK: bb.1:

  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   successors: %bb.2(0x80000000)

  ; CHECK:   S_SETREG_IMM32_B32 0, 1
  ; CHECK:   S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode

  ; CHECK:   DBG_VALUE
  ; CHECK:   DBG_VALUE

  ; CHECK:   DBG_VALUE
  ; CHECK:   DBG_VALUE

  ; CHECK:   DBG_VALUE
  ; CHECK:   DBG_VALUE

  ; CHECK:   S_SETREG_IMM32_B32 0, 1
  ; CHECK:   S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode

  ; CHECK: bb.2:
  ; CHECK: bb.2:

  ; CHECK:   S_NOP 0, implicit [[COPY]]
  ; CHECK:   S_NOP 0, implicit [[COPY]]

  ; CHECK:   S_NOP 0, implicit [[DEF8]]
  ; CHECK:   S_NOP 0, implicit [[DEF8]]

  ; CHECK:   S_ENDPGM 0
  ; CHECK:   S_ENDPGM 0

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0




    %0:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = COPY $vgpr0

    %1:vreg_64 = IMPLICIT_DEF
    %1:vreg_64 = IMPLICIT_DEF

    %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, 0, 0, implicit $exec
    %2:vreg_64 = GLOBAL_LOAD_DWORDX2 %1, 0, 0, 0, 0, implicit $exec

    %3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, 0, 0, implicit $exec
    %3:vgpr_32 = GLOBAL_LOAD_DWORD %1, 8, 0, 0, 0, implicit $exec

    undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec
    undef %4.sub1:vreg_64 = V_ADD_U32_e32 %0, %0, implicit $exec

    %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec
    %4.sub0:vreg_64 = V_MOV_B32_e32 111, implicit $exec

    %5:vreg_64 = COPY %2
    %5:vreg_64 = COPY %2

    undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $exec
    undef %6.sub0:vreg_64 = V_ADD_F32_e32 %1.sub0, %5.sub0, implicit $mode, implicit $exec

    %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $exec
    %6.sub1:vreg_64 = V_ADD_F32_e32 %1.sub1, %5.sub0, implicit $mode, implicit $exec

    %7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, 0, 0, implicit $exec
    %7:vgpr_32 = GLOBAL_LOAD_DWORD %5, 0, 0, 0, 0, implicit $exec

    %8:vreg_64 = IMPLICIT_DEF
    %8:vreg_64 = IMPLICIT_DEF

    %9:vreg_64 = IMPLICIT_DEF
    %9:vreg_64 = IMPLICIT_DEF

    %10:vreg_64 = IMPLICIT_DEF
    %10:vreg_64 = IMPLICIT_DEF

    undef %11.sub1:vreg_64 = IMPLICIT_DEF
    undef %11.sub1:vreg_64 = IMPLICIT_DEF

    %12:vgpr_32 = IMPLICIT_DEF
    %12:vgpr_32 = IMPLICIT_DEF

    %13:vgpr_32 = IMPLICIT_DEF
    %13:vgpr_32 = IMPLICIT_DEF

    %14:vreg_64 = IMPLICIT_DEF
    %14:vreg_64 = IMPLICIT_DEF

    %15:vreg_64 = IMPLICIT_DEF
    %15:vreg_64 = IMPLICIT_DEF

    %16:vgpr_32 = IMPLICIT_DEF
    %16:vgpr_32 = IMPLICIT_DEF

    %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %17:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %18:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $exec
    undef %19.sub0:vreg_64 = V_ADD_F32_e32 %7, %2.sub0, implicit $mode, implicit $exec

    %19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $exec
    %19.sub1:vreg_64 = V_ADD_F32_e32 %3, %3, implicit $mode, implicit $exec

    GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec
    GLOBAL_STORE_DWORDX2 %19, %4, 32, 0, 0, 0, implicit $exec

    %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, 0, 0, implicit $exec
    %11.sub0:vreg_64 = GLOBAL_LOAD_DWORD %9, 0, 0, 0, 0, implicit $exec

    %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, 0, 0, implicit $exec
    %8.sub0:vreg_64 = GLOBAL_LOAD_DWORD %10, 0, 0, 0, 0, implicit $exec

    %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec
    %20:vgpr_32 = GLOBAL_LOAD_DWORD %11, 0, 0, 0, 0, implicit $exec

    %21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, 0, 0, implicit $exec
    %21:vgpr_32 = GLOBAL_LOAD_DWORD %14, 0, 0, 0, 0, implicit $exec

    %22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, 0, 0, implicit $exec
    %22:vgpr_32 = GLOBAL_LOAD_DWORD %15, 0, 0, 0, 0, implicit $exec

    %23:vreg_64 = V_LSHLREV_B64 2, %8, implicit $exec
    %23:vreg_64 = V_LSHLREV_B64 2, %8, implicit $exec

    S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17
    S_NOP 0, implicit %13, implicit %23.sub0, implicit %12, implicit %17

    GLOBAL_STORE_DWORD %15, %18, 0, 0, 0, 0, implicit $exec
    GLOBAL_STORE_DWORD %15, %18, 0, 0, 0, 0, implicit $exec




  bb.1:
  bb.1:

    S_SETREG_IMM32_B32 0, 1
    S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode

    DBG_VALUE
    DBG_VALUE

    DBG_VALUE
    DBG_VALUE

    DBG_VALUE
    DBG_VALUE

    S_SETREG_IMM32_B32 0, 1
    S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode




  bb.2:
  bb.2:

    S_NOP 0, implicit %0
    S_NOP 0, implicit %0

    S_NOP 0, implicit %16
    S_NOP 0, implicit %16

    S_ENDPGM 0
    S_ENDPGM 0




...
...

llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
Show First 20 Lines • Show All 269 Lines • ▼ Show 20 Lines  bb.0.bb:

    %70.sub0:vreg_64 = IMPLICIT_DEF
    %70.sub0:vreg_64 = IMPLICIT_DEF

    %71:vreg_64 = IMPLICIT_DEF
    %71:vreg_64 = IMPLICIT_DEF

    undef %72.sub0:vreg_64, %73:sreg_64_xexec = V_ADD_I32_e64 %60, %71.sub0, 0, implicit $exec
    undef %72.sub0:vreg_64, %73:sreg_64_xexec = V_ADD_I32_e64 %60, %71.sub0, 0, implicit $exec

    %74:vgpr_32 = COPY %61
    %74:vgpr_32 = COPY %61

    %72.sub1:vreg_64, dead %75:sreg_64_xexec = V_ADDC_U32_e64 0, %71.sub1, %73, 0, implicit $exec
    %72.sub1:vreg_64, dead %75:sreg_64_xexec = V_ADDC_U32_e64 0, %71.sub1, %73, 0, implicit $exec

    %76:vreg_128 = GLOBAL_LOAD_DWORDX4 %72, 0, 0, 0, 0, implicit $exec
    %76:vreg_128 = GLOBAL_LOAD_DWORDX4 %72, 0, 0, 0, 0, implicit $exec

    %77:vgpr_32 = IMPLICIT_DEF
    %77:vgpr_32 = IMPLICIT_DEF

    %78:vgpr_32 = IMPLICIT_DEF
    %78:vgpr_32 = IMPLICIT_DEF

    %79:vgpr_32 = V_MUL_F32_e32 0, %77, implicit $exec
    %79:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %77, implicit $mode, implicit $exec

    %80:vgpr_32 = IMPLICIT_DEF
    %80:vgpr_32 = IMPLICIT_DEF

    %81:vgpr_32 = IMPLICIT_DEF
    %81:vgpr_32 = IMPLICIT_DEF

    %84:vgpr_32 = IMPLICIT_DEF
    %84:vgpr_32 = IMPLICIT_DEF

    BUFFER_STORE_DWORD_OFFEN %84, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 108, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %84, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 108, 0, 0, 0, 0, 0, implicit $exec

    BUFFER_STORE_DWORD_OFFEN %81, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 104, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %81, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 104, 0, 0, 0, 0, 0, implicit $exec

    BUFFER_STORE_DWORD_OFFEN %80, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 100, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %80, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 100, 0, 0, 0, 0, 0, implicit $exec

    BUFFER_STORE_DWORD_OFFEN %78, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 96, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFEN %78, %stack.0.tmp5, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr101, 96, 0, 0, 0, 0, 0, implicit $exec

    %85:vgpr_32 = IMPLICIT_DEF
    %85:vgpr_32 = IMPLICIT_DEF

    %86:vgpr_32 = IMPLICIT_DEF
    %86:vgpr_32 = IMPLICIT_DEF

    %87:vgpr_32 = IMPLICIT_DEF
    %87:vgpr_32 = IMPLICIT_DEF

    %88:vgpr_32 = IMPLICIT_DEF
    %88:vgpr_32 = IMPLICIT_DEF

    %90:vgpr_32 = IMPLICIT_DEF
    %90:vgpr_32 = IMPLICIT_DEF

    %91:vgpr_32, dead %92:sreg_64 = V_DIV_SCALE_F32 %90, %90, 1065353216, implicit $exec
    %91:vgpr_32, dead %92:sreg_64 = nofpexcept V_DIV_SCALE_F32 %90, %90, 1065353216, implicit $mode, implicit $exec

    %95:vgpr_32 = V_FMA_F32 0, 0, 0, 0, 0, undef %93:vgpr_32, 0, 0, implicit $exec
    %95:vgpr_32 = nofpexcept V_FMA_F32 0, 0, 0, 0, 0, undef %93:vgpr_32, 0, 0, implicit $mode, implicit $exec

    %96:vgpr_32, %97:sreg_64 = V_DIV_SCALE_F32 1065353216, %90, 1065353216, implicit $exec
    %96:vgpr_32, %97:sreg_64 = nofpexcept V_DIV_SCALE_F32 1065353216, %90, 1065353216, implicit $mode, implicit $exec

    %98:vgpr_32 = IMPLICIT_DEF
    %98:vgpr_32 = IMPLICIT_DEF

    %99:vgpr_32 = IMPLICIT_DEF
    %99:vgpr_32 = IMPLICIT_DEF

    %100:vgpr_32 = IMPLICIT_DEF
    %100:vgpr_32 = IMPLICIT_DEF

    %101:vgpr_32 = IMPLICIT_DEF
    %101:vgpr_32 = IMPLICIT_DEF

    %102:vgpr_32 = IMPLICIT_DEF
    %102:vgpr_32 = IMPLICIT_DEF

    %103:vgpr_32 = IMPLICIT_DEF
    %103:vgpr_32 = IMPLICIT_DEF

    %104:vgpr_32 = IMPLICIT_DEF
    %104:vgpr_32 = IMPLICIT_DEF

    %105:vgpr_32 = IMPLICIT_DEF
    %105:vgpr_32 = IMPLICIT_DEF

    %106:vgpr_32, dead %107:sreg_64 = V_DIV_SCALE_F32 %90, %90, %105, implicit $exec
    %106:vgpr_32, dead %107:sreg_64 = nofpexcept V_DIV_SCALE_F32 %90, %90, %105, implicit $mode, implicit $exec

    %108:vgpr_32 = V_RCP_F32_e32 0, implicit $exec
    %108:vgpr_32 = nofpexcept V_RCP_F32_e32 0, implicit $mode, implicit $exec

    %109:vgpr_32 = IMPLICIT_DEF
    %109:vgpr_32 = IMPLICIT_DEF

    %110:vgpr_32 = V_FMA_F32 0, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    %110:vgpr_32 = nofpexcept V_FMA_F32 0, 0, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %111:vgpr_32, %112:sreg_64 = V_DIV_SCALE_F32 0, 0, 0, implicit $exec
    %111:vgpr_32, %112:sreg_64 = nofpexcept V_DIV_SCALE_F32 0, 0, 0, implicit $mode, implicit $exec

    %113:vgpr_32 = V_MUL_F32_e32 0, %110, implicit $exec
    %113:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %110, implicit $mode, implicit $exec

    %114:vgpr_32 = IMPLICIT_DEF
    %114:vgpr_32 = IMPLICIT_DEF

    %115:vgpr_32 = IMPLICIT_DEF
    %115:vgpr_32 = IMPLICIT_DEF

    %116:vgpr_32 = IMPLICIT_DEF
    %116:vgpr_32 = IMPLICIT_DEF

    $vcc = IMPLICIT_DEF
    $vcc = IMPLICIT_DEF

    %117:vgpr_32 = V_DIV_FMAS_F32 0, %116, 0, %110, 0, %115, 0, 0, implicit killed $vcc, implicit $exec
    %117:vgpr_32 = nofpexcept V_DIV_FMAS_F32 0, %116, 0, %110, 0, %115, 0, 0, implicit killed $vcc, implicit $mode, implicit $exec

    %118:vgpr_32 = V_DIV_FIXUP_F32 0, %117, 0, %90, 0, %105, 0, 0, implicit $exec
    %118:vgpr_32 = nofpexcept V_DIV_FIXUP_F32 0, %117, 0, %90, 0, %105, 0, 0, implicit $mode, implicit $exec

    %119:vgpr_32 = IMPLICIT_DEF
    %119:vgpr_32 = IMPLICIT_DEF

    %120:vgpr_32 = IMPLICIT_DEF
    %120:vgpr_32 = IMPLICIT_DEF

    %121:vgpr_32 = IMPLICIT_DEF
    %121:vgpr_32 = IMPLICIT_DEF

    %122:vgpr_32 = IMPLICIT_DEF
    %122:vgpr_32 = IMPLICIT_DEF

    %123:vgpr_32 = IMPLICIT_DEF
    %123:vgpr_32 = IMPLICIT_DEF

    %124:vgpr_32 = IMPLICIT_DEF
    %124:vgpr_32 = IMPLICIT_DEF

    %125:vgpr_32 = IMPLICIT_DEF
    %125:vgpr_32 = IMPLICIT_DEF

    %126:vgpr_32 = IMPLICIT_DEF
    %126:vgpr_32 = IMPLICIT_DEF

Show All 13 Lines
llvm/test/CodeGen/AMDGPU/sdwa-gfx9.mir
Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines  bb.0:

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31




...
...




# GCN-LABEL: {{^}}name: trunc_shr_f32
# GCN-LABEL: {{^}}name: trunc_shr_f32




# CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
# CI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec

# CI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit-def $vcc, implicit $exec
# CI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit $mode, implicit $exec, implicit-def $vcc




# VI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec
# VI: [[SHIFT:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %{{[0-9]+}}, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit-def $vcc, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_e64 0, killed [[SHIFT]], 1, 2, implicit $mode, implicit $exec, implicit-def $vcc




#GFX9: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_sdwa 0, %{{[0-9]+}}, 1, 2, 6, 0, 5, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_TRUNC_F32_sdwa 0, %{{[0-9]+}}, 1, 2, 6, 0, 5, implicit $mode, implicit $exec




---
---

name:            trunc_shr_f32
name:            trunc_shr_f32

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vreg_64 }
  - { id: 1, class: vreg_64 }

  - { id: 2, class: sreg_64 }
  - { id: 2, class: sreg_64 }

Show All 10 Linesbody:             |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31




    %2 = COPY $sgpr30_sgpr31
    %2 = COPY $sgpr30_sgpr31

    %1 = COPY $vgpr2_vgpr3
    %1 = COPY $vgpr2_vgpr3

    %0 = COPY $vgpr0_vgpr1
    %0 = COPY $vgpr0_vgpr1

    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)

    %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
    %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec

    %11 = V_TRUNC_F32_e64 0, killed %10, 1, 2, implicit-def $vcc, implicit $exec
    %11 = V_TRUNC_F32_e64 0, killed %10, 1, 2, implicit $mode, implicit $exec, implicit-def $vcc

    FLAT_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
    FLAT_STORE_DWORD %0, %11, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31

llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr-gfx10.mir
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1010 -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX1010 -check-prefix=GCN %s




# GCN-LABEL: {{^}}name: vop1_instructions
# GCN-LABEL: {{^}}name: vop1_instructions




# GFX1010: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec




# GFX1010: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 6, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 6, 0, 5, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec




# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 1, 5, 0, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 1, 5, 0, 5, implicit $mode, implicit $exec




---
---

name:            vop1_instructions
name:            vop1_instructions

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vreg_64 }
  - { id: 1, class: vreg_64 }

  - { id: 2, class: sreg_64 }
  - { id: 2, class: sreg_64 }

▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines  bb.0:

    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)




    %5 = S_MOV_B32 65535
    %5 = S_MOV_B32 65535

    %6 = S_MOV_B32 65535
    %6 = S_MOV_B32 65535




    %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
    %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec

    %11 = V_MOV_B32_e32 %10, implicit $exec
    %11 = V_MOV_B32_e32 %10, implicit $exec

    %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec
    %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec

    %14 = V_FRACT_F32_e32 123, implicit $exec
    %14 = V_FRACT_F32_e32 123, implicit $mode, implicit $exec

    %15 = V_LSHLREV_B32_e64 16, %14, implicit $exec
    %15 = V_LSHLREV_B32_e64 16, %14, implicit $exec

    %16 = V_LSHRREV_B32_e64 16, %15, implicit $exec
    %16 = V_LSHRREV_B32_e64 16, %15, implicit $exec

    %17 = V_SIN_F32_e32 %16, implicit $exec
    %17 = V_SIN_F32_e32 %16, implicit $mode, implicit $exec

    %18 = V_LSHLREV_B32_e64 16, %17, implicit $exec
    %18 = V_LSHLREV_B32_e64 16, %17, implicit $exec

    %19 = V_LSHRREV_B32_e64 16, %18, implicit $exec
    %19 = V_LSHRREV_B32_e64 16, %18, implicit $exec

    %20 = V_CVT_U32_F32_e32 %19, implicit $exec
    %20 = V_CVT_U32_F32_e32 %19, implicit $mode, implicit $exec

    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec

    %23 = V_CVT_F32_I32_e32 123, implicit $exec
    %23 = V_CVT_F32_I32_e32 123, implicit $mode, implicit $exec

    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec




    %25 = V_LSHRREV_B32_e64 16, %3, implicit $exec
    %25 = V_LSHRREV_B32_e64 16, %3, implicit $exec

    %26 = V_MOV_B32_e64 %25, implicit $exec
    %26 = V_MOV_B32_e64 %25, implicit $exec

    %26 = V_LSHLREV_B32_e64 16, %26, implicit $exec
    %26 = V_LSHLREV_B32_e64 16, %26, implicit $exec

    %27 = V_FRACT_F32_e64 0, %6, 0, 0, implicit $exec
    %27 = V_FRACT_F32_e64 0, %6, 0, 0, implicit $mode, implicit $exec

    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec

    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec

    %30 = V_SIN_F32_e64 0, %29, 0, 0, implicit $exec
    %30 = V_SIN_F32_e64 0, %29, 0, 0, implicit $mode, implicit $exec

    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec

    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec

    %33 = V_CVT_U32_F32_e64 0, %32, 0, 0, implicit $exec
    %33 = V_CVT_U32_F32_e64 0, %32, 0, 0, implicit $mode, implicit $exec

    %34 = V_LSHLREV_B32_e64 16, %33, implicit $exec
    %34 = V_LSHLREV_B32_e64 16, %33, implicit $exec

    %35 = V_CVT_F32_I32_e64 %6, 0, 0, implicit $exec
    %35 = V_CVT_F32_I32_e64 %6, 0, 0, implicit $mode, implicit $exec

    %36 = V_LSHLREV_B32_e64 16, %35, implicit $exec
    %36 = V_LSHLREV_B32_e64 16, %35, implicit $exec







    %37 = V_LSHRREV_B32_e64 16, %36, implicit $exec
    %37 = V_LSHRREV_B32_e64 16, %36, implicit $exec

    %38 = V_FRACT_F32_e64 1, %37, 0, 0, implicit $exec
    %38 = V_FRACT_F32_e64 1, %37, 0, 0, implicit $mode, implicit $exec

    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec
    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec

    %40 = V_LSHRREV_B32_e64 16, %39, implicit $exec
    %40 = V_LSHRREV_B32_e64 16, %39, implicit $exec

    %41 = V_SIN_F32_e64 0, %40, 1, 0, implicit $exec
    %41 = V_SIN_F32_e64 0, %40, 1, 0, implicit $mode, implicit $exec

    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec
    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec

    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec
    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec

    %44 = V_CVT_U32_F32_e64 1, %43, 0, 0, implicit $exec
    %44 = V_CVT_U32_F32_e64 1, %43, 0, 0, implicit $mode, implicit $exec

    %45 = V_LSHLREV_B32_e64 16, %44, implicit $exec
    %45 = V_LSHLREV_B32_e64 16, %44, implicit $exec

    %46 = V_LSHRREV_B32_e64 16, %45, implicit $exec
    %46 = V_LSHRREV_B32_e64 16, %45, implicit $exec

    %47 = V_CVT_F32_I32_e64 %46, 0, 1, implicit $exec
    %47 = V_CVT_F32_I32_e64 %46, 0, 1, implicit $mode, implicit $exec

    %48 = V_LSHLREV_B32_e64 16, %47, implicit $exec
    %48 = V_LSHLREV_B32_e64 16, %47, implicit $exec







    %100 = V_MOV_B32_e32 %48, implicit $exec
    %100 = V_MOV_B32_e32 %48, implicit $exec




    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31




...
...

---
---

# GCN-LABEL: {{^}}name: vop2_instructions
# GCN-LABEL: {{^}}name: vop2_instructions




# GFX1010: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec




# GFX1010: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e64 0, 23, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e64 0, 23, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e64 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e64 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $mode, implicit $exec




# GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e64 1, 23, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 0, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F32_e64 1, 23, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 0, implicit $mode, implicit $exec

# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit $exec
# GFX1010: %{{[0-9]+}}:vgpr_32 = V_FMAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit $mode, implicit $exec




name:            vop2_instructions
name:            vop2_instructions

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vreg_64 }
  - { id: 1, class: vreg_64 }

  - { id: 2, class: sreg_64 }
  - { id: 2, class: sreg_64 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines  bb.0:

    %5 = S_MOV_B32 65535
    %5 = S_MOV_B32 65535

    %6 = S_MOV_B32 65535
    %6 = S_MOV_B32 65535




    %11 = V_LSHRREV_B32_e64 16, %3, implicit $exec
    %11 = V_LSHRREV_B32_e64 16, %3, implicit $exec

    %12 = V_AND_B32_e32 %6, %11, implicit $exec
    %12 = V_AND_B32_e32 %6, %11, implicit $exec

    %13 = V_LSHLREV_B32_e64 16, %12, implicit $exec
    %13 = V_LSHLREV_B32_e64 16, %12, implicit $exec

    %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec
    %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec

    %15 = V_BFE_U32 %13, 8, 8, implicit $exec
    %15 = V_BFE_U32 %13, 8, 8, implicit $exec

    %16 = V_ADD_F32_e32 %14, %15, implicit $exec
    %16 = V_ADD_F32_e32 %14, %15, implicit $mode, implicit $exec

    %17 = V_LSHLREV_B32_e64 16, %16, implicit $exec
    %17 = V_LSHLREV_B32_e64 16, %16, implicit $exec

    %18 = V_LSHRREV_B32_e64 16, %17, implicit $exec
    %18 = V_LSHRREV_B32_e64 16, %17, implicit $exec

    %19 = V_BFE_U32 %17, 8, 8, implicit $exec
    %19 = V_BFE_U32 %17, 8, 8, implicit $exec

    %20 = V_SUB_F16_e32 %18, %19, implicit $exec
    %20 = V_SUB_F16_e32 %18, %19, implicit $mode, implicit $exec

    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec

    %22 = V_BFE_U32 %20, 8, 8, implicit $exec
    %22 = V_BFE_U32 %20, 8, 8, implicit $exec

    %23 = V_FMAC_F32_e32 %21, %22, %22, implicit $exec
    %23 = V_FMAC_F32_e32 %21, %22, %22, implicit $mode, implicit $exec

    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec

    %25 = V_LSHRREV_B32_e64 16, %24, implicit $exec
    %25 = V_LSHRREV_B32_e64 16, %24, implicit $exec

    %26 = V_BFE_U32 %24, 8, 8, implicit $exec
    %26 = V_BFE_U32 %24, 8, 8, implicit $exec

    %27 = V_FMAC_F16_e32 %25, %26, %26, implicit $exec
    %27 = V_FMAC_F16_e32 %25, %26, %26, implicit $mode, implicit $exec

    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec




    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec

    %30 = V_AND_B32_e64 23, %29, implicit $exec
    %30 = V_AND_B32_e64 23, %29, implicit $exec

    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec

    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec

    %33 = V_BFE_U32 %31, 8, 8, implicit $exec
    %33 = V_BFE_U32 %31, 8, 8, implicit $exec

    %34 = V_ADD_F32_e64 0, %32, 0, %33, 0, 0, implicit $exec
    %34 = V_ADD_F32_e64 0, %32, 0, %33, 0, 0, implicit $mode, implicit $exec

    %35 = V_LSHLREV_B32_e64 16, %34, implicit $exec
    %35 = V_LSHLREV_B32_e64 16, %34, implicit $exec

    %37 = V_BFE_U32 %35, 8, 8, implicit $exec
    %37 = V_BFE_U32 %35, 8, 8, implicit $exec

    %38 = V_SUB_F16_e64 0, 23, 0, %37, 0, 0, implicit $exec
    %38 = V_SUB_F16_e64 0, 23, 0, %37, 0, 0, implicit $mode, implicit $exec

    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec
    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec

    %40 = V_BFE_U32 %39, 8, 8, implicit $exec
    %40 = V_BFE_U32 %39, 8, 8, implicit $exec

    %41 = V_FMAC_F32_e64 0, 23, 0, %40, 0, %40, 0, 0, implicit $exec
    %41 = V_FMAC_F32_e64 0, 23, 0, %40, 0, %40, 0, 0, implicit $mode, implicit $exec

    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec
    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec

    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec
    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec

    %44 = V_BFE_U32 %42, 8, 8, implicit $exec
    %44 = V_BFE_U32 %42, 8, 8, implicit $exec

    %45 = V_FMAC_F16_e64 0, %43, 0, %44, 0, %44, 0, 0, implicit $exec
    %45 = V_FMAC_F16_e64 0, %43, 0, %44, 0, %44, 0, 0, implicit $mode, implicit $exec

    %46 = V_LSHLREV_B32_e64 16, %45, implicit $exec
    %46 = V_LSHLREV_B32_e64 16, %45, implicit $exec




    %47 = V_LSHRREV_B32_e64 16, %46, implicit $exec
    %47 = V_LSHRREV_B32_e64 16, %46, implicit $exec

    %48 = V_BFE_U32 %46, 8, 8, implicit $exec
    %48 = V_BFE_U32 %46, 8, 8, implicit $exec

    %49 = V_ADD_F32_e64 0, %47, 1, %48, 0, 0, implicit $exec
    %49 = V_ADD_F32_e64 0, %47, 1, %48, 0, 0, implicit $mode, implicit $exec

    %50 = V_LSHLREV_B32_e64 16, %49, implicit $exec
    %50 = V_LSHLREV_B32_e64 16, %49, implicit $exec

    %51 = V_BFE_U32 %50, 8, 8, implicit $exec
    %51 = V_BFE_U32 %50, 8, 8, implicit $exec

    %52 = V_SUB_F16_e64 1, 23, 1, %51, 0, 0, implicit $exec
    %52 = V_SUB_F16_e64 1, 23, 1, %51, 0, 0, implicit $mode, implicit $exec

    %53 = V_LSHLREV_B32_e64 16, %52, implicit $exec
    %53 = V_LSHLREV_B32_e64 16, %52, implicit $exec

    %54 = V_BFE_U32 %53, 8, 8, implicit $exec
    %54 = V_BFE_U32 %53, 8, 8, implicit $exec

    %55 = V_FMAC_F32_e64 1, 23, 1, %54, 1, %54, 1, 0, implicit $exec
    %55 = V_FMAC_F32_e64 1, 23, 1, %54, 1, %54, 1, 0, implicit $mode, implicit $exec

    %56 = V_LSHLREV_B32_e64 16, %55, implicit $exec
    %56 = V_LSHLREV_B32_e64 16, %55, implicit $exec

    %57 = V_LSHRREV_B32_e64 16, %56, implicit $exec
    %57 = V_LSHRREV_B32_e64 16, %56, implicit $exec

    %58 = V_BFE_U32 %56, 8, 8, implicit $exec
    %58 = V_BFE_U32 %56, 8, 8, implicit $exec

    %59 = V_FMAC_F16_e64 1, %57, 1, %58, 1, %58, 0, 2, implicit $exec
    %59 = V_FMAC_F16_e64 1, %57, 1, %58, 1, %58, 0, 2, implicit $mode, implicit $exec

    %60 = V_LSHLREV_B32_e64 16, %59, implicit $exec
    %60 = V_LSHLREV_B32_e64 16, %59, implicit $exec




    %100 = V_MOV_B32_e32 %60, implicit $exec
    %100 = V_MOV_B32_e32 %60, implicit $exec




    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31




...
...

llvm/test/CodeGen/AMDGPU/sdwa-peephole-instr.mir
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=VI -check-prefix=GFX89 -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=VI -check-prefix=GFX89 -check-prefix=GCN %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 -check-prefix=GFX89 -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 -check-prefix=GFX89 -check-prefix=GCN %s




# GFX89-LABEL: {{^}}name: vop1_instructions
# GFX89-LABEL: {{^}}name: vop1_instructions




# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec







# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 6, 0, 5, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_sdwa 0, %{{[0-9]+}}, 0, 6, 0, 5, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 0, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, implicit $mode, implicit $exec







# VI: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_e64 %{{[0-9]+}}, 0, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_e64 %{{[0-9]+}}, 0, 1, implicit $mode, implicit $exec




# GFX9: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_FRACT_F32_sdwa 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_SIN_F32_sdwa 0, %{{[0-9]+}}, 1, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_CVT_U32_F32_sdwa 1, %{{[0-9]+}}, 0, 5, 0, 5, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 1, 5, 0, 5, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_CVT_F32_I32_sdwa 0, %{{[0-9]+}}, 0, 1, 5, 0, 5, implicit $mode, implicit $exec







---
---

name:            vop1_instructions
name:            vop1_instructions

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vreg_64 }
  - { id: 1, class: vreg_64 }

▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines  bb.0:

    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)




    %5 = S_MOV_B32 65535
    %5 = S_MOV_B32 65535

    %6 = S_MOV_B32 65535
    %6 = S_MOV_B32 65535




    %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec
    %10 = V_LSHRREV_B32_e64 16, %3, implicit $exec

    %11 = V_MOV_B32_e32 %10, implicit $exec
    %11 = V_MOV_B32_e32 %10, implicit $exec

    %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec
    %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec

    %14 = V_FRACT_F32_e32 123, implicit $exec
    %14 = V_FRACT_F32_e32 123, implicit $mode, implicit $exec

    %15 = V_LSHLREV_B32_e64 16, %14, implicit $exec
    %15 = V_LSHLREV_B32_e64 16, %14, implicit $exec

    %16 = V_LSHRREV_B32_e64 16, %15, implicit $exec
    %16 = V_LSHRREV_B32_e64 16, %15, implicit $exec

    %17 = V_SIN_F32_e32 %16, implicit $exec
    %17 = V_SIN_F32_e32 %16, implicit $mode, implicit $exec

    %18 = V_LSHLREV_B32_e64 16, %17, implicit $exec
    %18 = V_LSHLREV_B32_e64 16, %17, implicit $exec

    %19 = V_LSHRREV_B32_e64 16, %18, implicit $exec
    %19 = V_LSHRREV_B32_e64 16, %18, implicit $exec

    %20 = V_CVT_U32_F32_e32 %19, implicit $exec
    %20 = V_CVT_U32_F32_e32 %19, implicit $mode, implicit $exec

    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec

    %23 = V_CVT_F32_I32_e32 123, implicit $exec
    %23 = V_CVT_F32_I32_e32 123, implicit $mode, implicit $exec

    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec




    %25 = V_LSHRREV_B32_e64 16, %3, implicit $exec
    %25 = V_LSHRREV_B32_e64 16, %3, implicit $exec

    %26 = V_MOV_B32_e64 %25, implicit $exec
    %26 = V_MOV_B32_e64 %25, implicit $exec

    %26 = V_LSHLREV_B32_e64 16, %26, implicit $exec
    %26 = V_LSHLREV_B32_e64 16, %26, implicit $exec

    %27 = V_FRACT_F32_e64 0, %6, 0, 0, implicit $exec
    %27 = V_FRACT_F32_e64 0, %6, 0, 0, implicit $mode, implicit $exec

    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec

    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec

    %30 = V_SIN_F32_e64 0, %29, 0, 0, implicit $exec
    %30 = V_SIN_F32_e64 0, %29, 0, 0, implicit $mode, implicit $exec

    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec

    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec

    %33 = V_CVT_U32_F32_e64 0, %32, 0, 0, implicit $exec
    %33 = V_CVT_U32_F32_e64 0, %32, 0, 0, implicit $mode, implicit $exec

    %34 = V_LSHLREV_B32_e64 16, %33, implicit $exec
    %34 = V_LSHLREV_B32_e64 16, %33, implicit $exec

    %35 = V_CVT_F32_I32_e64 %6, 0, 0, implicit $exec
    %35 = V_CVT_F32_I32_e64 %6, 0, 0, implicit $mode, implicit $exec

    %36 = V_LSHLREV_B32_e64 16, %35, implicit $exec
    %36 = V_LSHLREV_B32_e64 16, %35, implicit $exec







    %37 = V_LSHRREV_B32_e64 16, %36, implicit $exec
    %37 = V_LSHRREV_B32_e64 16, %36, implicit $exec

    %38 = V_FRACT_F32_e64 1, %37, 0, 0, implicit $exec
    %38 = V_FRACT_F32_e64 1, %37, 0, 0, implicit $mode, implicit $exec

    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec
    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec

    %40 = V_LSHRREV_B32_e64 16, %39, implicit $exec
    %40 = V_LSHRREV_B32_e64 16, %39, implicit $exec

    %41 = V_SIN_F32_e64 0, %40, 1, 0, implicit $exec
    %41 = V_SIN_F32_e64 0, %40, 1, 0, implicit $mode, implicit $exec

    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec
    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec

    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec
    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec

    %44 = V_CVT_U32_F32_e64 1, %43, 0, 0, implicit $exec
    %44 = V_CVT_U32_F32_e64 1, %43, 0, 0, implicit $mode, implicit $exec

    %45 = V_LSHLREV_B32_e64 16, %44, implicit $exec
    %45 = V_LSHLREV_B32_e64 16, %44, implicit $exec

    %46 = V_LSHRREV_B32_e64 16, %45, implicit $exec
    %46 = V_LSHRREV_B32_e64 16, %45, implicit $exec

    %47 = V_CVT_F32_I32_e64 %46, 0, 1, implicit $exec
    %47 = V_CVT_F32_I32_e64 %46, 0, 1, implicit $mode, implicit $exec

    %48 = V_LSHLREV_B32_e64 16, %47, implicit $exec
    %48 = V_LSHLREV_B32_e64 16, %47, implicit $exec







    %100 = V_MOV_B32_e32 %48, implicit $exec
    %100 = V_MOV_B32_e32 %48, implicit $exec




    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31




...
...

---
---

# GCN-LABEL: {{^}}name: vop2_instructions
# GCN-LABEL: {{^}}name: vop2_instructions







# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $mode, implicit $exec




# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e32 %{{[0-9]+}}, %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec







# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 6, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, %{{[0-9]+}}, 0, 0, 6, 0, 5, 1, implicit $mode, implicit $exec




# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_AND_B32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 5, 0, 6, 5, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e64 0, 23, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e64 0, 23, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 0, implicit $mode, implicit $exec







# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, %{{[0-9]+}}, 1, 0, 6, 0, 6, 1, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, %{{[0-9]+}}, 1, 0, 6, 0, 6, 1, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit $exec
# VI: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit $mode, implicit $exec




# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 5, 1, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_SUB_F16_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 0, 5, 0, 6, 1, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e64 1, 23, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 0, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F32_e64 1, 23, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 0, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MAC_F16_e64 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 2, implicit $mode, implicit $exec




name:            vop2_instructions
name:            vop2_instructions

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vreg_64 }
  - { id: 1, class: vreg_64 }

  - { id: 2, class: sreg_64 }
  - { id: 2, class: sreg_64 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines  bb.0:

    %5 = S_MOV_B32 65535
    %5 = S_MOV_B32 65535

    %6 = S_MOV_B32 65535
    %6 = S_MOV_B32 65535




    %11 = V_LSHRREV_B32_e64 16, %3, implicit $exec
    %11 = V_LSHRREV_B32_e64 16, %3, implicit $exec

    %12 = V_AND_B32_e32 %6, %11, implicit $exec
    %12 = V_AND_B32_e32 %6, %11, implicit $exec

    %13 = V_LSHLREV_B32_e64 16, %12, implicit $exec
    %13 = V_LSHLREV_B32_e64 16, %12, implicit $exec

    %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec
    %14 = V_LSHRREV_B32_e64 16, %13, implicit $exec

    %15 = V_BFE_U32 %13, 8, 8, implicit $exec
    %15 = V_BFE_U32 %13, 8, 8, implicit $exec

    %16 = V_ADD_F32_e32 %14, %15, implicit $exec
    %16 = V_ADD_F32_e32 %14, %15, implicit $mode, implicit $exec

    %17 = V_LSHLREV_B32_e64 16, %16, implicit $exec
    %17 = V_LSHLREV_B32_e64 16, %16, implicit $exec

    %18 = V_LSHRREV_B32_e64 16, %17, implicit $exec
    %18 = V_LSHRREV_B32_e64 16, %17, implicit $exec

    %19 = V_BFE_U32 %17, 8, 8, implicit $exec
    %19 = V_BFE_U32 %17, 8, 8, implicit $exec

    %20 = V_SUB_F16_e32 %18, %19, implicit $exec
    %20 = V_SUB_F16_e32 %18, %19, implicit $mode, implicit $exec

    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec
    %21 = V_LSHLREV_B32_e64 16, %20, implicit $exec

    %22 = V_BFE_U32 %20, 8, 8, implicit $exec
    %22 = V_BFE_U32 %20, 8, 8, implicit $exec

    %23 = V_MAC_F32_e32 %21, %22, %22, implicit $exec
    %23 = V_MAC_F32_e32 %21, %22, %22, implicit $mode, implicit $exec

    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec
    %24 = V_LSHLREV_B32_e64 16, %23, implicit $exec

    %25 = V_LSHRREV_B32_e64 16, %24, implicit $exec
    %25 = V_LSHRREV_B32_e64 16, %24, implicit $exec

    %26 = V_BFE_U32 %24, 8, 8, implicit $exec
    %26 = V_BFE_U32 %24, 8, 8, implicit $exec

    %27 = V_MAC_F16_e32 %25, %26, %26, implicit $exec
    %27 = V_MAC_F16_e32 %25, %26, %26, implicit $mode, implicit $exec

    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec
    %28 = V_LSHLREV_B32_e64 16, %27, implicit $exec




    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec
    %29 = V_LSHRREV_B32_e64 16, %28, implicit $exec

    %30 = V_AND_B32_e64 23, %29, implicit $exec
    %30 = V_AND_B32_e64 23, %29, implicit $exec

    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec
    %31 = V_LSHLREV_B32_e64 16, %30, implicit $exec

    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec
    %32 = V_LSHRREV_B32_e64 16, %31, implicit $exec

    %33 = V_BFE_U32 %31, 8, 8, implicit $exec
    %33 = V_BFE_U32 %31, 8, 8, implicit $exec

    %34 = V_ADD_F32_e64 0, %32, 0, %33, 0, 0, implicit $exec
    %34 = V_ADD_F32_e64 0, %32, 0, %33, 0, 0, implicit $mode, implicit $exec

    %35 = V_LSHLREV_B32_e64 16, %34, implicit $exec
    %35 = V_LSHLREV_B32_e64 16, %34, implicit $exec

    %37 = V_BFE_U32 %35, 8, 8, implicit $exec
    %37 = V_BFE_U32 %35, 8, 8, implicit $exec

    %38 = V_SUB_F16_e64 0, 23, 0, %37, 0, 0, implicit $exec
    %38 = V_SUB_F16_e64 0, 23, 0, %37, 0, 0, implicit $mode, implicit $exec

    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec
    %39 = V_LSHLREV_B32_e64 16, %38, implicit $exec

    %40 = V_BFE_U32 %39, 8, 8, implicit $exec
    %40 = V_BFE_U32 %39, 8, 8, implicit $exec

    %41 = V_MAC_F32_e64 0, 23, 0, %40, 0, %40, 0, 0, implicit $exec
    %41 = V_MAC_F32_e64 0, 23, 0, %40, 0, %40, 0, 0, implicit $mode, implicit $exec

    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec
    %42 = V_LSHLREV_B32_e64 16, %41, implicit $exec

    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec
    %43 = V_LSHRREV_B32_e64 16, %42, implicit $exec

    %44 = V_BFE_U32 %42, 8, 8, implicit $exec
    %44 = V_BFE_U32 %42, 8, 8, implicit $exec

    %45 = V_MAC_F16_e64 0, %43, 0, %44, 0, %44, 0, 0, implicit $exec
    %45 = V_MAC_F16_e64 0, %43, 0, %44, 0, %44, 0, 0, implicit $mode, implicit $exec

    %46 = V_LSHLREV_B32_e64 16, %45, implicit $exec
    %46 = V_LSHLREV_B32_e64 16, %45, implicit $exec




    %47 = V_LSHRREV_B32_e64 16, %46, implicit $exec
    %47 = V_LSHRREV_B32_e64 16, %46, implicit $exec

    %48 = V_BFE_U32 %46, 8, 8, implicit $exec
    %48 = V_BFE_U32 %46, 8, 8, implicit $exec

    %49 = V_ADD_F32_e64 0, %47, 1, %48, 0, 0, implicit $exec
    %49 = V_ADD_F32_e64 0, %47, 1, %48, 0, 0, implicit $mode, implicit $exec

    %50 = V_LSHLREV_B32_e64 16, %49, implicit $exec
    %50 = V_LSHLREV_B32_e64 16, %49, implicit $exec

    %51 = V_BFE_U32 %50, 8, 8, implicit $exec
    %51 = V_BFE_U32 %50, 8, 8, implicit $exec

    %52 = V_SUB_F16_e64 1, 23, 1, %51, 0, 0, implicit $exec
    %52 = V_SUB_F16_e64 1, 23, 1, %51, 0, 0, implicit $mode, implicit $exec

    %53 = V_LSHLREV_B32_e64 16, %52, implicit $exec
    %53 = V_LSHLREV_B32_e64 16, %52, implicit $exec

    %54 = V_BFE_U32 %53, 8, 8, implicit $exec
    %54 = V_BFE_U32 %53, 8, 8, implicit $exec

    %55 = V_MAC_F32_e64 1, 23, 1, %54, 1, %54, 1, 0, implicit $exec
    %55 = V_MAC_F32_e64 1, 23, 1, %54, 1, %54, 1, 0, implicit $mode, implicit $exec

    %56 = V_LSHLREV_B32_e64 16, %55, implicit $exec
    %56 = V_LSHLREV_B32_e64 16, %55, implicit $exec

    %57 = V_LSHRREV_B32_e64 16, %56, implicit $exec
    %57 = V_LSHRREV_B32_e64 16, %56, implicit $exec

    %58 = V_BFE_U32 %56, 8, 8, implicit $exec
    %58 = V_BFE_U32 %56, 8, 8, implicit $exec

    %59 = V_MAC_F16_e64 1, %57, 1, %58, 1, %58, 0, 2, implicit $exec
    %59 = V_MAC_F16_e64 1, %57, 1, %58, 1, %58, 0, 2, implicit $mode, implicit $exec

    %60 = V_LSHLREV_B32_e64 16, %59, implicit $exec
    %60 = V_LSHLREV_B32_e64 16, %59, implicit $exec




    %100 = V_MOV_B32_e32 %60, implicit $exec
    %100 = V_MOV_B32_e32 %60, implicit $exec




    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31




...
...

---
---




# GCN-LABEL: {{^}}name: vopc_instructions
# GCN-LABEL: {{^}}name: vopc_instructions




# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 123, implicit $exec
# GFX89: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 123, implicit $exec

# GFX89: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $exec
# GFX89: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $mode, implicit $exec

# GFX89: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX89: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# GFX89: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $exec
# GFX89: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $exec

# GFX89: $vcc = V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX89: $vcc = V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec







# VI: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $exec
# VI: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $mode, implicit $exec

# VI: %{{[0-9]+}}:sreg_64 = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, implicit-def $exec, implicit $exec
# VI: %{{[0-9]+}}:sreg_64 = V_CMPX_GT_F32_e64 0, 23, 0, killed %{{[0-9]+}}, 0, implicit-def $exec, implicit $mode, implicit $exec

# VI: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %3, 0, 6, 4, implicit-def $vcc, implicit $exec
# VI: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %3, 0, 6, 4, implicit-def $vcc, implicit $exec

# VI: %{{[0-9]+}}:sreg_64 = V_CMPX_EQ_I32_e64 23, killed %{{[0-9]+}}, implicit-def $exec, implicit $exec
# VI: %{{[0-9]+}}:sreg_64 = V_CMPX_EQ_I32_e64 23, killed %{{[0-9]+}}, implicit-def $exec, implicit $exec




# GFX9: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $exec
# GFX9: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $mode, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 23, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 23, implicit $exec

# GFX9: %{{[0-9]+}}:sreg_64 = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX9: %{{[0-9]+}}:sreg_64 = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# GFX9: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $exec
# GFX9: $vcc = V_CMP_LT_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit $exec

# GFX9: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 23, implicit $exec
# GFX9: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 23, implicit $exec

# GFX9: %{{[0-9]+}}:sreg_64 = V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX9: %{{[0-9]+}}:sreg_64 = V_CMPX_EQ_I32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec







# VI: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 1, 6, 4, implicit-def $vcc, implicit $exec
# VI: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 1, 6, 4, implicit-def $vcc, implicit $mode, implicit $exec

# VI: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# VI: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# VI: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 1, 6, 4, implicit-def $vcc, implicit $exec
# VI: $vcc = V_CMP_EQ_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 1, 6, 4, implicit-def $vcc, implicit $mode, implicit $exec

# VI: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# VI: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# VI: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# VI: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# VI: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# VI: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# VI: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# VI: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 1, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec




# GFX9: $vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, implicit $exec
# GFX9: $vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, implicit $mode, implicit $exec

# GFX9: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX9: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# GFX9: $vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, implicit $exec
# GFX9: $vcc = V_CMP_EQ_F32_e64 0, %{{[0-9]+}}, 0, killed %{{[0-9]+}}, 1, implicit $mode, implicit $exec

# GFX9: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX9: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 0, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# GFX9: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX9: $vcc = V_CMPX_GT_F32_sdwa 0, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# GFX9: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $exec
# GFX9: $vcc = V_CMPX_GT_F32_sdwa 1, %{{[0-9]+}}, 1, %{{[0-9]+}}, 0, 6, 4, implicit-def $vcc, implicit-def $exec, implicit $mode, implicit $exec

# GFX9: $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %{{[0-9]+}}, 1, implicit-def $exec, implicit $exec
# GFX9: $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %{{[0-9]+}}, 1, implicit-def $exec, implicit $mode, implicit $exec










name:            vopc_instructions
name:            vopc_instructions

tracksRegLiveness: true
tracksRegLiveness: true

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vreg_64 }
  - { id: 1, class: vreg_64 }

Show All 32 Lines  bb.0:

    %1 = COPY $vgpr2_vgpr3
    %1 = COPY $vgpr2_vgpr3

    %0 = COPY $vgpr0_vgpr1
    %0 = COPY $vgpr0_vgpr1

    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %3 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)




    %5 = S_MOV_B32 65535
    %5 = S_MOV_B32 65535

    %6 = S_MOV_B32 65535
    %6 = S_MOV_B32 65535




    %10 = V_AND_B32_e64 %5, %3, implicit $exec
    %10 = V_AND_B32_e64 %5, %3, implicit $exec

    V_CMP_EQ_F32_e32 123, killed %10, implicit-def $vcc, implicit $exec
    V_CMP_EQ_F32_e32 123, killed %10, implicit-def $vcc, implicit $mode, implicit $exec

    %11 = V_AND_B32_e64 %5, %3, implicit $exec
    %11 = V_AND_B32_e64 %5, %3, implicit $exec

    V_CMPX_GT_F32_e32 123, killed %11, implicit-def $vcc, implicit-def $exec, implicit $exec
    V_CMPX_GT_F32_e32 123, killed %11, implicit-def $vcc, implicit $mode, implicit-def $exec, implicit $exec

    %12 = V_AND_B32_e64 %5, %3, implicit $exec
    %12 = V_AND_B32_e64 %5, %3, implicit $exec

    V_CMP_LT_I32_e32 123, killed %12, implicit-def $vcc, implicit $exec
    V_CMP_LT_I32_e32 123, killed %12, implicit-def $vcc, implicit $exec

    %13 = V_AND_B32_e64 %5, %3, implicit $exec
    %13 = V_AND_B32_e64 %5, %3, implicit $exec

    V_CMPX_EQ_I32_e32 123, killed %13, implicit-def $vcc, implicit-def $exec, implicit $exec
    V_CMPX_EQ_I32_e32 123, killed %13, implicit-def $vcc, implicit-def $exec, implicit $exec




    %14 = V_AND_B32_e64 %5, %3, implicit $exec
    %14 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %14, 0, implicit $exec
    $vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %14, 0, implicit $mode, implicit $exec

    %15 = V_AND_B32_e64 %5, %3, implicit $exec
    %15 = V_AND_B32_e64 %5, %3, implicit $exec

    %18 = V_CMPX_GT_F32_e64 0, 23, 0, killed %15, 0, implicit-def $exec, implicit $exec
    %18 = V_CMPX_GT_F32_e64 0, 23, 0, killed %15, 0, implicit-def $exec, implicit $mode, implicit $exec

    %16 = V_AND_B32_e64 %5, %3, implicit $exec
    %16 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMP_LT_I32_e64 %6, killed %16, implicit $exec
    $vcc = V_CMP_LT_I32_e64 %6, killed %16, implicit $exec

    %17 = V_AND_B32_e64 %5, %3, implicit $exec
    %17 = V_AND_B32_e64 %5, %3, implicit $exec

    %19 = V_CMPX_EQ_I32_e64 23, killed %17, implicit-def $exec, implicit $exec
    %19 = V_CMPX_EQ_I32_e64 23, killed %17, implicit-def $exec, implicit $exec




    %20 = V_AND_B32_e64 %5, %3, implicit $exec
    %20 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %20, 1, implicit $exec
    $vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %20, 1, implicit $mode, implicit $exec

    %21 = V_AND_B32_e64 %5, %3, implicit $exec
    %21 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMPX_GT_F32_e64 0, 23, 0, killed %21, 0, implicit-def $exec, implicit $exec
    $vcc = V_CMPX_GT_F32_e64 0, 23, 0, killed %21, 0, implicit-def $exec, implicit $mode, implicit $exec

    %23 = V_AND_B32_e64 %5, %3, implicit $exec
    %23 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %23, 1, implicit $exec
    $vcc = V_CMP_EQ_F32_e64 0, %6, 0, killed %23, 1, implicit $mode, implicit $exec

    %24 = V_AND_B32_e64 %5, %3, implicit $exec
    %24 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMPX_GT_F32_e64 1, 23, 0, killed %24, 0, implicit-def $exec, implicit $exec
    $vcc = V_CMPX_GT_F32_e64 1, 23, 0, killed %24, 0, implicit-def $exec, implicit $mode, implicit $exec

    %25 = V_AND_B32_e64 %5, %3, implicit $exec
    %25 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMPX_GT_F32_e64 0, 23, 1, killed %25, 0, implicit-def $exec, implicit $exec
    $vcc = V_CMPX_GT_F32_e64 0, 23, 1, killed %25, 0, implicit-def $exec, implicit $mode, implicit $exec

    %26 = V_AND_B32_e64 %5, %3, implicit $exec
    %26 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %26, 0, implicit-def $exec, implicit $exec
    $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %26, 0, implicit-def $exec, implicit $mode, implicit $exec

    %27 = V_AND_B32_e64 %5, %3, implicit $exec
    %27 = V_AND_B32_e64 %5, %3, implicit $exec

    $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %27, 1, implicit-def $exec, implicit $exec
    $vcc = V_CMPX_GT_F32_e64 1, 23, 1, killed %27, 1, implicit-def $exec, implicit $mode, implicit $exec







    %100 = V_MOV_B32_e32 $vcc_lo, implicit $exec
    %100 = V_MOV_B32_e32 $vcc_lo, implicit $exec




    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
    FLAT_STORE_DWORD %0, %100, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31

llvm/test/CodeGen/AMDGPU/sdwa-preserve.mir
# RUN: llc -march=amdgcn -mcpu=fiji -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s
# RUN: llc -march=amdgcn -mcpu=fiji -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s

# RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -start-before=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck -check-prefix=SDWA %s




# SDWA-LABEL: {{^}}add_f16_u32_preserve
# SDWA-LABEL: {{^}}add_f16_u32_preserve




# SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
# SDWA: flat_load_dword [[FIRST:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]

# SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]
# SDWA: flat_load_dword [[SECOND:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]




# SDWA: v_mul_f32_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_3
# SDWA: v_mul_f32_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_3

# SDWA: v_add_f16_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0 src1_sel:WORD_1
# SDWA: v_add_f16_sdwa [[RES:v[0-9]+]], [[FIRST]], [[SECOND]] dst_sel:BYTE_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0 src1_sel:WORD_1




# SDWA: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], [[RES]]
# SDWA: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], [[RES]]




---
---

name:            add_f16_u32_preserve
name:            add_f16_u32_preserve

tracksRegLiveness: true
tracksRegLiveness: true

registers:       
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vreg_64 }
  - { id: 1, class: vreg_64 }

  - { id: 2, class: sreg_64 }
  - { id: 2, class: sreg_64 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

  - { id: 4, class: vgpr_32 }
  - { id: 4, class: vgpr_32 }

  - { id: 5, class: vgpr_32 }
  - { id: 5, class: vgpr_32 }

  - { id: 6, class: vgpr_32 }
  - { id: 6, class: vgpr_32 }

  - { id: 7, class: vgpr_32 }
  - { id: 7, class: vgpr_32 }

  - { id: 8, class: vgpr_32 }
  - { id: 8, class: vgpr_32 }

  - { id: 9, class: vgpr_32 }
  - { id: 9, class: vgpr_32 }

  - { id: 10, class: vgpr_32 }
  - { id: 10, class: vgpr_32 }

  - { id: 11, class: vgpr_32 }
  - { id: 11, class: vgpr_32 }

  - { id: 12, class: vgpr_32 }
  - { id: 12, class: vgpr_32 }

  - { id: 13, class: vgpr_32 }
  - { id: 13, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31
    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $sgpr30_sgpr31

  


    %2 = COPY $sgpr30_sgpr31
    %2 = COPY $sgpr30_sgpr31

    %1 = COPY $vgpr2_vgpr3
    %1 = COPY $vgpr2_vgpr3

    %0 = COPY $vgpr0_vgpr1
    %0 = COPY $vgpr0_vgpr1

    %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %3 = FLAT_LOAD_DWORD %0, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)

    %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)
    %4 = FLAT_LOAD_DWORD %1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (load 4)




    %5 = V_AND_B32_e32 65535, %3, implicit $exec
    %5 = V_AND_B32_e32 65535, %3, implicit $exec

    %6 = V_LSHRREV_B32_e64 16, %4, implicit $exec
    %6 = V_LSHRREV_B32_e64 16, %4, implicit $exec

    %7 = V_BFE_U32 %3, 8, 8, implicit $exec
    %7 = V_BFE_U32 %3, 8, 8, implicit $exec

    %8 = V_LSHRREV_B32_e32 24, %4, implicit $exec
    %8 = V_LSHRREV_B32_e32 24, %4, implicit $exec




    %9 = V_ADD_F16_e64 0, %5, 0, %6, 0, 0, implicit $exec
    %9 = V_ADD_F16_e64 0, %5, 0, %6, 0, 0, implicit $mode, implicit $exec

    %10 = V_LSHLREV_B16_e64 8, %9, implicit $exec
    %10 = V_LSHLREV_B16_e64 8, %9, implicit $exec

    %11 = V_MUL_F32_e64 0, %7, 0, %8, 0, 0, implicit $exec
    %11 = V_MUL_F32_e64 0, %7, 0, %8, 0, 0, implicit $mode, implicit $exec

    %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec
    %12 = V_LSHLREV_B32_e64 16, %11, implicit $exec




    %13 = V_OR_B32_e64 %10, %12, implicit $exec
    %13 = V_OR_B32_e64 %10, %12, implicit $exec




    FLAT_STORE_DWORD %0, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)
    FLAT_STORE_DWORD %0, %13, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4)

    $sgpr30_sgpr31 = COPY %2
    $sgpr30_sgpr31 = COPY %2

    S_SETPC_B64_return $sgpr30_sgpr31
    S_SETPC_B64_return $sgpr30_sgpr31




▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s




# GCN-LABEL: name: hazard_smem_war
# GCN-LABEL: name: hazard_smem_war

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN:      $sgpr_null = S_MOV_B32 0
# GCN:      $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war
name: hazard_smem_war

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_no_hazard
# GCN-LABEL: name: hazard_smem_war_no_hazard

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_ADD_U32
# GCN-NEXT: S_ADD_U32

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_no_hazard
name: hazard_smem_war_no_hazard

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    $sgpr3 = S_ADD_U32 $sgpr4, $sgpr5, implicit-def $scc
    $sgpr3 = S_ADD_U32 $sgpr4, $sgpr5, implicit-def $scc

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_dependent_salu
# GCN-LABEL: name: hazard_smem_war_dependent_salu

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_WAITCNT

# GCN-NEXT: S_ADD_U32
# GCN-NEXT: S_ADD_U32

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_dependent_salu
name: hazard_smem_war_dependent_salu

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT 0
    S_WAITCNT 0

    $sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc
    $sgpr3 = S_ADD_U32 $sgpr2, $sgpr4, implicit-def $scc

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_independent_salu
# GCN-LABEL: name: hazard_smem_war_independent_salu

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_WAITCNT

# GCN-NEXT: S_ADD_U32
# GCN-NEXT: S_ADD_U32

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_independent_salu
name: hazard_smem_war_independent_salu

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT 0
    S_WAITCNT 0

    $sgpr3 = S_ADD_U32 $sgpr5, $sgpr4, implicit-def $scc
    $sgpr3 = S_ADD_U32 $sgpr5, $sgpr4, implicit-def $scc

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_only_smem
# GCN-LABEL: name: hazard_smem_war_only_smem

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_LOAD_DWORD_IMM
# GCN-NEXT: S_LOAD_DWORD_IMM

# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_only_smem
name: hazard_smem_war_only_smem

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr6, $sgpr7, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr6, $sgpr7, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    $sgpr5 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0, 0
    $sgpr5 = S_LOAD_DWORD_IMM $sgpr6_sgpr7, 0, 0, 0

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_only_waitcnt_0
# GCN-LABEL: name: hazard_smem_war_only_waitcnt_0

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_WAITCNT

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_only_waitcnt_0
name: hazard_smem_war_only_waitcnt_0

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT 0
    S_WAITCNT 0

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_only_vmcnt_0
# GCN-LABEL: name: hazard_smem_war_only_vmcnt_0

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT 3952{{$}}
# GCN-NEXT: S_WAITCNT 3952{{$}}

# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_only_vmcnt_0
name: hazard_smem_war_only_vmcnt_0

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT 3952
    S_WAITCNT 3952

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_only_expcnt_0
# GCN-LABEL: name: hazard_smem_war_only_expcnt_0

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT 53007{{$}}
# GCN-NEXT: S_WAITCNT 53007{{$}}

# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_only_expcnt_0
name: hazard_smem_war_only_expcnt_0

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT 53007
    S_WAITCNT 53007

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_only_lgkmcnt_0
# GCN-LABEL: name: hazard_smem_war_only_lgkmcnt_0

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT 49279{{$}}
# GCN-NEXT: S_WAITCNT 49279{{$}}

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_only_lgkmcnt_0
name: hazard_smem_war_only_lgkmcnt_0

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT 49279
    S_WAITCNT 49279

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_0
# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_0

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT_LGKMCNT
# GCN-NEXT: S_WAITCNT_LGKMCNT

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_only_waitcnt_lgkmcnt_0
name: hazard_smem_war_only_waitcnt_lgkmcnt_0

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT_LGKMCNT $sgpr_null, 0
    S_WAITCNT_LGKMCNT $sgpr_null, 0

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_1
# GCN-LABEL: name: hazard_smem_war_only_waitcnt_lgkmcnt_1

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN-NEXT: S_WAITCNT_LGKMCNT
# GCN-NEXT: S_WAITCNT_LGKMCNT

# GCN-NEXT: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_only_waitcnt_lgkmcnt_1
name: hazard_smem_war_only_waitcnt_lgkmcnt_1

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_WAITCNT_LGKMCNT $sgpr_null, 1
    S_WAITCNT_LGKMCNT $sgpr_null, 1

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_branch
# GCN-LABEL: name: hazard_smem_war_branch

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN:      $sgpr_null = S_MOV_B32 0
# GCN:      $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_branch
name: hazard_smem_war_branch

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr4, $vgpr0, $vgpr1

    successors: %bb.1
    successors: %bb.1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_cbranch
# GCN-LABEL: name: hazard_smem_war_cbranch

# GCN:      S_AND_B64
# GCN:      S_AND_B64

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN:      S_CBRANCH_VCCZ
# GCN:      S_CBRANCH_VCCZ

# GCN-NOT:  $sgpr_null = S_MOV_B32 0
# GCN-NOT:  $sgpr_null = S_MOV_B32 0

# GCN:      V_CMP_EQ_F32
# GCN:      V_CMP_EQ_F32

# GCN:      S_ENDPGM 0
# GCN:      S_ENDPGM 0

# GCN:      $sgpr_null = S_MOV_B32 0
# GCN:      $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_cbranch
name: hazard_smem_war_cbranch

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    successors: %bb.1, %bb.2
    successors: %bb.1, %bb.2

    $vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
    $vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc




  bb.1:
  bb.1:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




  bb.2:
  bb.2:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_cbranch_carry
# GCN-LABEL: name: hazard_smem_war_cbranch_carry

# GCN:      S_AND_B64
# GCN:      S_AND_B64

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN:      S_CBRANCH_VCCZ
# GCN:      S_CBRANCH_VCCZ

# GCN-NOT:  $sgpr_null = S_MOV_B32 0
# GCN-NOT:  $sgpr_null = S_MOV_B32 0

Show All 10 Lines  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    successors: %bb.1, %bb.2
    successors: %bb.1, %bb.2

    $vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc
    $vcc = S_AND_B64 $sgpr4_sgpr5, $sgpr4_sgpr5, implicit-def $scc

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.2, implicit killed $vcc




  bb.1:
  bb.1:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




  bb.2:
  bb.2:

    successors: %bb.3
    successors: %bb.3

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr4_sgpr5 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec




  bb.3:
  bb.3:

    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr4, $sgpr5, $vgpr0, $vgpr1

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_backedge
# GCN-LABEL: name: hazard_smem_war_backedge

# GCN:      $sgpr_null = S_MOV_B32 0
# GCN:      $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

---
---

name: hazard_smem_war_backedge
name: hazard_smem_war_backedge

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1

    successors: %bb.1
    successors: %bb.1

    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_F32_e64 0, $vgpr0, 0, $vgpr1, 1, implicit $mode, implicit $exec




  bb.1:
  bb.1:

    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1
    liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1

    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
    $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0

    S_BRANCH %bb.0
    S_BRANCH %bb.0

...
...




# GCN-LABEL: name: hazard_smem_war_impdef
# GCN-LABEL: name: hazard_smem_war_impdef

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN:      $sgpr_null = S_MOV_B32 0
# GCN:      $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_CMP_EQ_F32
# GCN-NEXT: V_CMP_EQ_F32

---
---

name: hazard_smem_war_impdef
name: hazard_smem_war_impdef

body: |
body: |

  bb.0:
  bb.0:

    liveins: $vcc, $vgpr0
    liveins: $vcc, $vgpr0

    $sgpr0 = S_LOAD_DWORD_IMM $vcc, 0, 0, 0
    $sgpr0 = S_LOAD_DWORD_IMM $vcc, 0, 0, 0

    V_CMP_EQ_F32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $exec
    V_CMP_EQ_F32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_smem_war_readlane
# GCN-LABEL: name: hazard_smem_war_readlane

# GCN:      S_LOAD_DWORD_IMM
# GCN:      S_LOAD_DWORD_IMM

# GCN:      $sgpr_null = S_MOV_B32 0
# GCN:      $sgpr_null = S_MOV_B32 0

# GCN-NEXT: V_READLANE_B32
# GCN-NEXT: V_READLANE_B32

---
---

Show All 37 Lines
llvm/test/CodeGen/AMDGPU/spill-empty-live-interval.mir
# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-dce-in-ra=0 -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-dce-in-ra=0 -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s

# https://bugs.llvm.org/show_bug.cgi?id=33620
# https://bugs.llvm.org/show_bug.cgi?id=33620




---
---

# This would assert due to the empty live interval created for %9
# This would assert due to the empty live interval created for %9

# on the last S_NOP with an undef subreg use.
# on the last S_NOP with an undef subreg use.




# CHECK-LABEL: name: expecting_non_empty_interval
# CHECK-LABEL: name: expecting_non_empty_interval




# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $exec
# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $mode, implicit $exec

# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)

# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec

# CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec
# CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $mode, implicit $exec




# CHECK: S_NOP 0, implicit %6.sub1
# CHECK: S_NOP 0, implicit %6.sub1

# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)

# CHECK-NEXT: S_NOP 0, implicit %8.sub1
# CHECK-NEXT: S_NOP 0, implicit %8.sub1

# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0




name: expecting_non_empty_interval
name: expecting_non_empty_interval

tracksRegLiveness: true
tracksRegLiveness: true

machineFunctionInfo:
machineFunctionInfo:

  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
  scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3

  stackPtrOffsetReg: $sgpr32
  stackPtrOffsetReg: $sgpr32

body:             |
body:             |

  bb.0:
  bb.0:

    successors: %bb.1
    successors: %bb.1




    undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $exec
    undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit $exec

    undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
    undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec

    dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $exec
    dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $mode, implicit $exec




  bb.1:
  bb.1:

    S_NOP 0, implicit %2.sub1
    S_NOP 0, implicit %2.sub1

    S_NOP 0, implicit %0.sub1
    S_NOP 0, implicit %0.sub1

    S_NOP 0, implicit undef %0.sub0
    S_NOP 0, implicit undef %0.sub0




...
...




Show All 31 Lines
llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines  bb.5:

    successors: %bb.6(0x40000000), %bb.22(0x40000000)
    successors: %bb.6(0x40000000), %bb.22(0x40000000)

    %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    S_CBRANCH_SCC1 %bb.22, implicit undef $scc
    S_CBRANCH_SCC1 %bb.22, implicit undef $scc

    S_BRANCH %bb.6
    S_BRANCH %bb.6




  bb.6:
  bb.6:

    successors: %bb.8(0x40000000), %bb.11(0x40000000)
    successors: %bb.8(0x40000000), %bb.11(0x40000000)

    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    dead %6:vgpr_32 = V_MUL_F32_e32 0, undef %7:vgpr_32, implicit $exec
    dead %6:vgpr_32 = V_MUL_F32_e32 0, undef %7:vgpr_32, implicit $mode, implicit $exec

    dead %8:vgpr_32 = V_MUL_F32_e32 0, %2, implicit $exec
    dead %8:vgpr_32 = V_MUL_F32_e32 0, %2, implicit $mode, implicit $exec

    undef %9.sub1:vreg_64 = V_MUL_F32_e32 0, %1, implicit $exec
    undef %9.sub1:vreg_64 = V_MUL_F32_e32 0, %1, implicit $mode, implicit $exec

    undef %10.sub0:vreg_128 = V_MUL_F32_e32 0, %0, implicit $exec
    undef %10.sub0:vreg_128 = V_MUL_F32_e32 0, %0, implicit $mode, implicit $exec

    undef %11.sub0:sgpr_256 = S_MOV_B32 0
    undef %11.sub0:sgpr_256 = S_MOV_B32 0

    %11.sub1:sgpr_256 = COPY %11.sub0
    %11.sub1:sgpr_256 = COPY %11.sub0

    %11.sub2:sgpr_256 = COPY %11.sub0
    %11.sub2:sgpr_256 = COPY %11.sub0

    %11.sub3:sgpr_256 = COPY %11.sub0
    %11.sub3:sgpr_256 = COPY %11.sub0

    %11.sub4:sgpr_256 = COPY %11.sub0
    %11.sub4:sgpr_256 = COPY %11.sub0

    %11.sub5:sgpr_256 = COPY %11.sub0
    %11.sub5:sgpr_256 = COPY %11.sub0

    %11.sub6:sgpr_256 = COPY %11.sub0
    %11.sub6:sgpr_256 = COPY %11.sub0

    %11.sub7:sgpr_256 = COPY %11.sub0
    %11.sub7:sgpr_256 = COPY %11.sub0

▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines  bb.12:

    successors: %bb.11(0x80000000)
    successors: %bb.11(0x80000000)

    %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %14:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %5:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
    %5:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec

    S_BRANCH %bb.11
    S_BRANCH %bb.11




  bb.13:
  bb.13:

    successors: %bb.15(0x40000000), %bb.14(0x40000000)
    successors: %bb.15(0x40000000), %bb.14(0x40000000)




    %18:vgpr_32 = V_MAD_F32 0, %10.sub0, 0, target-flags(amdgpu-gotprel) 1073741824, 0, -1082130432, 0, 0, implicit $exec
    %18:vgpr_32 = V_MAD_F32 0, %10.sub0, 0, target-flags(amdgpu-gotprel) 1073741824, 0, -1082130432, 0, 0, implicit $mode, implicit $exec

    %19:vgpr_32 = V_MAD_F32 0, %12.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $exec
    %19:vgpr_32 = V_MAD_F32 0, %12.sub0, 0, target-flags(amdgpu-gotprel) 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %20:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sgpr_128, 1040, 0, 0 :: (dereferenceable invariant load 16)
    %20:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %21:sgpr_128, 1040, 0, 0 :: (dereferenceable invariant load 16)

    %22:vgpr_32 = V_ADD_F32_e32 0, %19, implicit $exec
    %22:vgpr_32 = V_ADD_F32_e32 0, %19, implicit $mode, implicit $exec

    %23:vgpr_32 = V_MAD_F32 0, %18, 0, 0, 0, 0, 0, 0, implicit $exec
    %23:vgpr_32 = V_MAD_F32 0, %18, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %24:vgpr_32 = COPY %20.sub3
    %24:vgpr_32 = COPY %20.sub3

    %25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $exec
    %25:vgpr_32 = V_MUL_F32_e64 0, target-flags(amdgpu-gotprel32-lo) 0, 0, %20.sub1, 0, 0, implicit $mode, implicit $exec

    %26:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sgpr_128, 1056, 0, 0 :: (dereferenceable invariant load 16)
    %26:sgpr_128 = S_BUFFER_LOAD_DWORDX4_IMM undef %27:sgpr_128, 1056, 0, 0 :: (dereferenceable invariant load 16)

    %28:vgpr_32 = V_MAD_F32 0, %18, 0, %26.sub0, 0, 0, 0, 0, implicit $exec
    %28:vgpr_32 = V_MAD_F32 0, %18, 0, %26.sub0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %29:vgpr_32 = V_ADD_F32_e32 %28, %19, implicit $exec
    %29:vgpr_32 = V_ADD_F32_e32 %28, %19, implicit $mode, implicit $exec

    %30:vgpr_32 = V_RCP_F32_e32 %29, implicit $exec
    %30:vgpr_32 = V_RCP_F32_e32 %29, implicit $mode, implicit $exec

    %25:vgpr_32 = V_MAC_F32_e32 0, %18, %25, implicit $exec
    %25:vgpr_32 = V_MAC_F32_e32 0, %18, %25, implicit $mode, implicit $exec

    %31:vgpr_32 = V_MAD_F32 0, target-flags(amdgpu-gotprel) 0, 0, %12.sub0, 0, %24, 0, 0, implicit $exec
    %31:vgpr_32 = V_MAD_F32 0, target-flags(amdgpu-gotprel) 0, 0, %12.sub0, 0, %24, 0, 0, implicit $mode, implicit $exec

    %32:vgpr_32 = V_ADD_F32_e32 %25, %31, implicit $exec
    %32:vgpr_32 = V_ADD_F32_e32 %25, %31, implicit $mode, implicit $exec

    %33:vgpr_32 = V_MUL_F32_e32 %22, %30, implicit $exec
    %33:vgpr_32 = V_MUL_F32_e32 %22, %30, implicit $mode, implicit $exec

    %34:vgpr_32 = V_MUL_F32_e32 %23, %30, implicit $exec
    %34:vgpr_32 = V_MUL_F32_e32 %23, %30, implicit $mode, implicit $exec

    %35:vgpr_32 = V_MUL_F32_e32 %32, %30, implicit $exec
    %35:vgpr_32 = V_MUL_F32_e32 %32, %30, implicit $mode, implicit $exec

    %36:vgpr_32 = V_MUL_F32_e32 0, %34, implicit $exec
    %36:vgpr_32 = V_MUL_F32_e32 0, %34, implicit $mode, implicit $exec

    %36:vgpr_32 = V_MAC_F32_e32 0, %33, %36, implicit $exec
    %36:vgpr_32 = V_MAC_F32_e32 0, %33, %36, implicit $mode, implicit $exec

    %37:vgpr_32 = V_MAD_F32 0, %35, 0, 0, 0, 0, 0, 0, implicit $exec
    %37:vgpr_32 = V_MAD_F32 0, %35, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %38:sreg_64_xexec = V_CMP_NE_U32_e64 0, %5, implicit $exec
    %38:sreg_64_xexec = V_CMP_NE_U32_e64 0, %5, implicit $exec

    %39:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %38, implicit $exec
    %39:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %38, implicit $exec

    V_CMP_NE_U32_e32 1, %39, implicit-def $vcc, implicit $exec
    V_CMP_NE_U32_e32 1, %39, implicit-def $vcc, implicit $exec

    $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
    $vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc

    %40:vgpr_32 = V_ADD_F32_e32 %36, %37, implicit $exec
    %40:vgpr_32 = V_ADD_F32_e32 %36, %37, implicit $mode, implicit $exec

    S_CBRANCH_VCCZ %bb.15, implicit $vcc
    S_CBRANCH_VCCZ %bb.15, implicit $vcc




  bb.14:
  bb.14:

    successors: %bb.17(0x80000000)
    successors: %bb.17(0x80000000)

    S_BRANCH %bb.17
    S_BRANCH %bb.17




  bb.15:
  bb.15:

    successors: %bb.16(0x40000000), %bb.18(0x40000000)
    successors: %bb.16(0x40000000), %bb.18(0x40000000)

    %41:vgpr_32 = V_MAD_F32 0, %40, 0, 0, 0, 0, 0, 0, implicit $exec
    %41:vgpr_32 = V_MAD_F32 0, %40, 0, 0, 0, 0, 0, 0, implicit $mode, implicit $exec

    %42:sreg_64 = V_CMP_LE_F32_e64 0, 0, 0, %41, 0, implicit $exec
    %42:sreg_64 = V_CMP_LE_F32_e64 0, 0, 0, %41, 0, implicit $mode, implicit $exec

    %43:sreg_64 = V_CMP_GE_F32_e64 0, 1065353216, 0, %41, 0, implicit $exec
    %43:sreg_64 = V_CMP_GE_F32_e64 0, 1065353216, 0, %41, 0, implicit $mode, implicit $exec

    %44:sreg_64 = S_AND_B64 %43, %43, implicit-def dead $scc
    %44:sreg_64 = S_AND_B64 %43, %43, implicit-def dead $scc

    %45:sreg_64 = S_AND_B64 %42, %42, implicit-def dead $scc
    %45:sreg_64 = S_AND_B64 %42, %42, implicit-def dead $scc

    %46:sreg_64 = S_AND_B64 %45, %44, implicit-def dead $scc
    %46:sreg_64 = S_AND_B64 %45, %44, implicit-def dead $scc

    %47:sreg_64 = COPY $exec, implicit-def $exec
    %47:sreg_64 = COPY $exec, implicit-def $exec

    %48:sreg_64 = S_AND_B64 %47, %46, implicit-def dead $scc
    %48:sreg_64 = S_AND_B64 %47, %46, implicit-def dead $scc

    $exec = S_MOV_B64_term %48
    $exec = S_MOV_B64_term %48

    SI_MASK_BRANCH %bb.18, implicit $exec
    SI_MASK_BRANCH %bb.18, implicit $exec

    S_BRANCH %bb.16
    S_BRANCH %bb.16

Show All 9 Lines  bb.17:

    %51:vreg_128 = IMPLICIT_DEF
    %51:vreg_128 = IMPLICIT_DEF

    $vcc = COPY %50
    $vcc = COPY %50

    S_CBRANCH_VCCNZ %bb.21, implicit $vcc
    S_CBRANCH_VCCNZ %bb.21, implicit $vcc

    S_BRANCH %bb.23
    S_BRANCH %bb.23




  bb.18:
  bb.18:

    successors: %bb.20(0x40000000), %bb.19(0x40000000)
    successors: %bb.20(0x40000000), %bb.19(0x40000000)

    $exec = S_OR_B64 $exec, %47, implicit-def $scc
    $exec = S_OR_B64 $exec, %47, implicit-def $scc

    %52:vgpr_32 = V_MAD_F32 0, %3.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 1, %3.sub0, 0, 0, implicit $exec
    %52:vgpr_32 = V_MAD_F32 0, %3.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 1, %3.sub0, 0, 0, implicit $mode, implicit $exec

    %53:vgpr_32 = V_MUL_F32_e32 -2147483648, %3.sub1, implicit $exec
    %53:vgpr_32 = V_MUL_F32_e32 -2147483648, %3.sub1, implicit $mode, implicit $exec

    %53:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel32-hi) 1065353216, %3.sub2, %53, implicit $exec
    %53:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel32-hi) 1065353216, %3.sub2, %53, implicit $mode, implicit $exec

    %54:vgpr_32 = V_MUL_F32_e32 %53, %53, implicit $exec
    %54:vgpr_32 = V_MUL_F32_e32 %53, %53, implicit $mode, implicit $exec

    %54:vgpr_32 = V_MAC_F32_e32 %52, %52, %54, implicit $exec
    %54:vgpr_32 = V_MAC_F32_e32 %52, %52, %54, implicit $mode, implicit $exec

    %55:vgpr_32 = V_SQRT_F32_e32 %54, implicit $exec
    %55:vgpr_32 = V_SQRT_F32_e32 %54, implicit $mode, implicit $exec

    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %5:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %56:vgpr_32 = V_MOV_B32_e32 981668463, implicit $exec
    %56:vgpr_32 = V_MOV_B32_e32 981668463, implicit $exec

    %57:sreg_64 = V_CMP_NGT_F32_e64 0, %55, 0, %56, 0, implicit $exec
    %57:sreg_64 = V_CMP_NGT_F32_e64 0, %55, 0, %56, 0, implicit $mode, implicit $exec

    %58:sreg_64 = S_AND_B64 $exec, %57, implicit-def dead $scc
    %58:sreg_64 = S_AND_B64 $exec, %57, implicit-def dead $scc

    $vcc = COPY %58
    $vcc = COPY %58

    S_CBRANCH_VCCZ %bb.20, implicit $vcc
    S_CBRANCH_VCCZ %bb.20, implicit $vcc




  bb.19:
  bb.19:

    successors: %bb.17(0x80000000)
    successors: %bb.17(0x80000000)

    S_BRANCH %bb.17
    S_BRANCH %bb.17




  bb.20:
  bb.20:

    successors: %bb.17(0x80000000)
    successors: %bb.17(0x80000000)

    S_BRANCH %bb.17
    S_BRANCH %bb.17




  bb.21:
  bb.21:

    successors: %bb.23(0x80000000)
    successors: %bb.23(0x80000000)

    %59:sreg_32 = S_MOV_B32 0
    %59:sreg_32 = S_MOV_B32 0

    undef %51.sub0:vreg_128 = COPY %59
    undef %51.sub0:vreg_128 = COPY %59

    S_BRANCH %bb.23
    S_BRANCH %bb.23




  bb.22:
  bb.22:

    successors: %bb.24(0x80000000)
    successors: %bb.24(0x80000000)

    S_BRANCH %bb.24
    S_BRANCH %bb.24




  bb.23:
  bb.23:

    successors: %bb.22(0x80000000)
    successors: %bb.22(0x80000000)

    undef %60.sub1:vreg_64 = V_CVT_I32_F32_e32 %1, implicit $exec
    undef %60.sub1:vreg_64 = V_CVT_I32_F32_e32 %1, implicit $mode, implicit $exec

    %60.sub0:vreg_64 = V_CVT_I32_F32_e32 %0, implicit $exec
    %60.sub0:vreg_64 = V_CVT_I32_F32_e32 %0, implicit $mode, implicit $exec

    undef %61.sub0:sgpr_256 = S_MOV_B32 0
    undef %61.sub0:sgpr_256 = S_MOV_B32 0

    %61.sub1:sgpr_256 = COPY %61.sub0
    %61.sub1:sgpr_256 = COPY %61.sub0

    %61.sub2:sgpr_256 = COPY %61.sub0
    %61.sub2:sgpr_256 = COPY %61.sub0

    %61.sub3:sgpr_256 = COPY %61.sub0
    %61.sub3:sgpr_256 = COPY %61.sub0

    %61.sub4:sgpr_256 = COPY %61.sub0
    %61.sub4:sgpr_256 = COPY %61.sub0

    %61.sub5:sgpr_256 = COPY %61.sub0
    %61.sub5:sgpr_256 = COPY %61.sub0

    %61.sub6:sgpr_256 = COPY %61.sub0
    %61.sub6:sgpr_256 = COPY %61.sub0

    %61.sub7:sgpr_256 = COPY %61.sub0
    %61.sub7:sgpr_256 = COPY %61.sub0

    %62:vgpr_32 = V_MOV_B32_e32 1033100696, implicit $exec
    %62:vgpr_32 = V_MOV_B32_e32 1033100696, implicit $exec

    %63:vgpr_32 = V_MUL_F32_e32 1060575065, %15.sub1, implicit $exec
    %63:vgpr_32 = V_MUL_F32_e32 1060575065, %15.sub1, implicit $mode, implicit $exec

    %63:vgpr_32 = V_MAC_F32_e32 1046066128, %15.sub0, %63, implicit $exec
    %63:vgpr_32 = V_MAC_F32_e32 1046066128, %15.sub0, %63, implicit $mode, implicit $exec

    %64:vgpr_32 = IMAGE_LOAD_V1_V2 %60, %61, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)
    %64:vgpr_32 = IMAGE_LOAD_V1_V2 %60, %61, 1, -1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, addrspace 4)

    %64:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel) 0, %51.sub0, %64, implicit $exec
    %64:vgpr_32 = V_MAC_F32_e32 target-flags(amdgpu-gotprel) 0, %51.sub0, %64, implicit $mode, implicit $exec

    %65:vgpr_32 = V_MUL_F32_e32 0, %64, implicit $exec
    %65:vgpr_32 = V_MUL_F32_e32 0, %64, implicit $mode, implicit $exec

    %66:vgpr_32 = V_MUL_F32_e32 0, %65, implicit $exec
    %66:vgpr_32 = V_MUL_F32_e32 0, %65, implicit $mode, implicit $exec

    %67:vgpr_32 = V_MAD_F32 0, %66, 0, %62, 0, 0, 0, 0, implicit $exec
    %67:vgpr_32 = V_MAD_F32 0, %66, 0, %62, 0, 0, 0, 0, implicit $mode, implicit $exec

    %63:vgpr_32 = V_MAC_F32_e32 %15.sub2, %62, %63, implicit $exec
    %63:vgpr_32 = V_MAC_F32_e32 %15.sub2, %62, %63, implicit $mode, implicit $exec

    %4:vgpr_32 = V_ADD_F32_e32 %63, %67, implicit $exec
    %4:vgpr_32 = V_ADD_F32_e32 %63, %67, implicit $mode, implicit $exec

    S_BRANCH %bb.22
    S_BRANCH %bb.22




  bb.24:
  bb.24:

    %68:vgpr_32 = V_MUL_F32_e32 0, %4, implicit $exec
    %68:vgpr_32 = V_MUL_F32_e32 0, %4, implicit $mode, implicit $exec

    %69:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, undef %70:vgpr_32, 0, %68, 0, 0, implicit $exec
    %69:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, undef %70:vgpr_32, 0, %68, 0, 0, implicit $mode, implicit $exec

    EXP 0, undef %71:vgpr_32, %69, undef %72:vgpr_32, undef %73:vgpr_32, -1, -1, 15, implicit $exec
    EXP 0, undef %71:vgpr_32, %69, undef %72:vgpr_32, undef %73:vgpr_32, -1, -1, 15, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
# RUN: llc -march=amdgcn -mcpu=gfx1010 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s




# GCN-LABEL: name: test_fmamk_reg_imm_f32
# GCN-LABEL: name: test_fmamk_reg_imm_f32

# GCN: V_FMAMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_FMAMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_fmamk_reg_imm_f32
name:            test_fmamk_reg_imm_f32

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_FMAC_F32_e32 killed %0.sub0, %2, killed %1, implicit $exec
    %3 = V_FMAC_F32_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmamk_imm_reg_f32
# GCN-LABEL: name: test_fmamk_imm_reg_f32

# GCN: V_FMAMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_FMAMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_fmamk_imm_reg_f32
name:            test_fmamk_imm_reg_f32

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_FMAC_F32_e32 %2, killed %0.sub0, killed %1, implicit $exec
    %3 = V_FMAC_F32_e32 %2, killed %0.sub0, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmaak_f32
# GCN-LABEL: name: test_fmaak_f32

# GCN: V_FMAAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit $exec
# GCN: V_FMAAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit $mode, implicit $exec

---
---

name:            test_fmaak_f32
name:            test_fmaak_f32

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = V_MOV_B32_e32 1078523331, implicit $exec
    %1 = V_MOV_B32_e32 1078523331, implicit $exec

    %2 = V_FMAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit $exec
    %2 = V_FMAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmamk_reg_imm_f16
# GCN-LABEL: name: test_fmamk_reg_imm_f16

# GCN: V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_fmamk_reg_imm_f16
name:            test_fmamk_reg_imm_f16

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_FMAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $exec
    %3 = V_FMAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmamk_imm_reg_f16
# GCN-LABEL: name: test_fmamk_imm_reg_f16

# GCN: V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_FMAMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_fmamk_imm_reg_f16
name:            test_fmamk_imm_reg_f16

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_FMAC_F16_e32 %2, killed %0.sub0, killed %1, implicit $exec
    %3 = V_FMAC_F16_e32 %2, killed %0.sub0, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmaak_f16
# GCN-LABEL: name: test_fmaak_f16

# GCN: V_FMAAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit $exec
# GCN: V_FMAAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit $mode, implicit $exec

---
---

name:            test_fmaak_f16
name:            test_fmaak_f16

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = V_MOV_B32_e32 1078523331, implicit $exec
    %1 = V_MOV_B32_e32 1078523331, implicit $exec

    %2 = V_FMAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit $exec
    %2 = V_FMAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit $mode, implicit $exec

...
...




# GCN-LABEL: name: test_fmaak_sgpr_src0_f32
# GCN-LABEL: name: test_fmaak_sgpr_src0_f32

# GCN: %2:vgpr_32 = V_FMAMK_F32 killed %0, 1078523331, %3:vgpr_32, implicit $exec
# GCN: %2:vgpr_32 = V_FMAMK_F32 killed %0, 1078523331, %3:vgpr_32, implicit $mode, implicit $exec




---
---

name:            test_fmaak_sgpr_src0_f32
name:            test_fmaak_sgpr_src0_f32

registers:
registers:

  - { id: 0, class: sreg_32_xm0 }
  - { id: 0, class: sreg_32_xm0 }

  - { id: 1, class: vgpr_32}
  - { id: 1, class: vgpr_32}

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = V_MOV_B32_e32 1078523331, implicit $exec
    %1 = V_MOV_B32_e32 1078523331, implicit $exec

    %2 = V_FMAC_F32_e32 killed %0, %1, %3, implicit $exec
    %2 = V_FMAC_F32_e32 killed %0, %1, %3, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmaak_inlineimm_src0_f32
# GCN-LABEL: name: test_fmaak_inlineimm_src0_f32

# GCN: %1:vgpr_32 = V_FMAMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit $exec
# GCN: %1:vgpr_32 = V_FMAMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit $mode, implicit $exec




---
---

name:            test_fmaak_inlineimm_src0_f32
name:            test_fmaak_inlineimm_src0_f32

registers:
registers:

  - { id: 0, class: vgpr_32}
  - { id: 0, class: vgpr_32}

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = V_MOV_B32_e32 1078523331, implicit $exec
    %0 = V_MOV_B32_e32 1078523331, implicit $exec

    %1 = V_FMAC_F32_e32 1073741824, %0, %2, implicit $exec
    %1 = V_FMAC_F32_e32 1073741824, %0, %2, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmaak_otherimm_src0_f32
# GCN-LABEL: name: test_fmaak_otherimm_src0_f32

# GCN: %1:vgpr_32 = V_FMAC_F32_e32 1120403456, %0, %1, implicit $exec
# GCN: %1:vgpr_32 = V_FMAC_F32_e32 1120403456, %0, %1, implicit $mode, implicit $exec




---
---

name:            test_fmaak_otherimm_src0_f32
name:            test_fmaak_otherimm_src0_f32

registers:
registers:

  - { id: 0, class: vgpr_32}
  - { id: 0, class: vgpr_32}

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = V_MOV_B32_e32 1078523331, implicit $exec
    %0 = V_MOV_B32_e32 1078523331, implicit $exec

    %1 = V_FMAC_F32_e32 1120403456, %0, %2, implicit $exec
    %1 = V_FMAC_F32_e32 1120403456, %0, %2, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmaak_other_constantlike_src0_f32
# GCN-LABEL: name: test_fmaak_other_constantlike_src0_f32

# GCN: %1:vgpr_32 = V_FMAC_F32_e32 %stack.0, %0, %1, implicit $exec
# GCN: %1:vgpr_32 = V_FMAC_F32_e32 %stack.0, %0, %1, implicit $mode, implicit $exec

---
---

name:            test_fmaak_other_constantlike_src0_f32
name:            test_fmaak_other_constantlike_src0_f32

registers:
registers:

  - { id: 0, class: vgpr_32}
  - { id: 0, class: vgpr_32}

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

stack:
stack:

  - { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,
  - { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,

      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
      callee-saved-register: '', local-offset: 0, debug-info-variable: '',

      debug-info-expression: '', debug-info-location: '' }
      debug-info-expression: '', debug-info-location: '' }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = V_MOV_B32_e32 1078523331, implicit $exec
    %0 = V_MOV_B32_e32 1078523331, implicit $exec

    %1 = V_FMAC_F32_e32 %stack.0, %0, %2, implicit $exec
    %1 = V_FMAC_F32_e32 %stack.0, %0, %2, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_fmaak_inline_literal_f16
# GCN-LABEL: name: test_fmaak_inline_literal_f16

# GCN: %2:vgpr_32 = V_FMAAK_F16 16384, killed %0, 49664, implicit $exec
# GCN: %2:vgpr_32 = V_FMAAK_F16 16384, killed %0, 49664, implicit $mode, implicit $exec




---
---

name:            test_fmaak_inline_literal_f16
name:            test_fmaak_inline_literal_f16

liveins:
liveins:

  - { reg: '$vgpr0', virtual-reg: '%3' }
  - { reg: '$vgpr0', virtual-reg: '%3' }

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

  


    %3:vgpr_32 = COPY killed $vgpr0
    %3:vgpr_32 = COPY killed $vgpr0




    %26:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
    %26:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec

    %28:vgpr_32 = V_FMAC_F16_e32 16384, killed %3, %26, implicit $exec
    %28:vgpr_32 = V_FMAC_F16_e32 16384, killed %3, %26, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...




llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
# RUN: llc -march=amdgcn -mcpu=gfx900 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -march=amdgcn -mcpu=gfx900 %s -run-pass twoaddressinstruction -verify-machineinstrs -o - | FileCheck -check-prefix=GCN %s




# GCN-LABEL: name: test_madmk_reg_imm_f32
# GCN-LABEL: name: test_madmk_reg_imm_f32

# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_madmk_reg_imm_f32
name:            test_madmk_reg_imm_f32

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_MAC_F32_e32 killed %0.sub0, %2, killed %1, implicit $exec
    %3 = V_MAC_F32_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_madmk_imm_reg_f32
# GCN-LABEL: name: test_madmk_imm_reg_f32

# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_MADMK_F32 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_madmk_imm_reg_f32
name:            test_madmk_imm_reg_f32

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_MAC_F32_e32 %2, killed %0.sub0, killed %1, implicit $exec
    %3 = V_MAC_F32_e32 %2, killed %0.sub0, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_madak_f32
# GCN-LABEL: name: test_madak_f32

# GCN: V_MADAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit $exec
# GCN: V_MADAK_F32 killed %0.sub0, %0.sub1, 1078523331, implicit $mode, implicit $exec

---
---

name:            test_madak_f32
name:            test_madak_f32

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = V_MOV_B32_e32 1078523331, implicit $exec
    %1 = V_MOV_B32_e32 1078523331, implicit $exec

    %2 = V_MAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit $exec
    %2 = V_MAC_F32_e32 killed %0.sub0, %0.sub1, %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_madmk_reg_imm_f16
# GCN-LABEL: name: test_madmk_reg_imm_f16

# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_madmk_reg_imm_f16
name:            test_madmk_reg_imm_f16

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_MAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $exec
    %3 = V_MAC_F16_e32 killed %0.sub0, %2, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_madmk_imm_reg_f16
# GCN-LABEL: name: test_madmk_imm_reg_f16

# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $exec
# GCN: V_MADMK_F16 killed %0.sub0, 1078523331, killed %1, implicit $mode, implicit $exec

---
---

name:            test_madmk_imm_reg_f16
name:            test_madmk_imm_reg_f16

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = COPY %0.sub1
    %1 = COPY %0.sub1

    %2 = V_MOV_B32_e32 1078523331, implicit $exec
    %2 = V_MOV_B32_e32 1078523331, implicit $exec

    %3 = V_MAC_F16_e32 %2, killed %0.sub0, killed %1, implicit $exec
    %3 = V_MAC_F16_e32 %2, killed %0.sub0, killed %1, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_madak_f16
# GCN-LABEL: name: test_madak_f16

# GCN: V_MADAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit $exec
# GCN: V_MADAK_F16 killed %0.sub0, %0.sub1, 1078523331, implicit $mode, implicit $exec

---
---

name:            test_madak_f16
name:            test_madak_f16

registers:
registers:

  - { id: 0, class: vreg_64 }
  - { id: 0, class: vreg_64 }

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = V_MOV_B32_e32 1078523331, implicit $exec
    %1 = V_MOV_B32_e32 1078523331, implicit $exec

    %2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit $exec
    %2 = V_MAC_F16_e32 killed %0.sub0, %0.sub1, %1, implicit $mode, implicit $exec

...
...




# Make sure constant bus restriction isn't violated if src0 is an SGPR.
# Make sure constant bus restriction isn't violated if src0 is an SGPR.




# GCN-LABEL: name: test_madak_sgpr_src0_f32
# GCN-LABEL: name: test_madak_sgpr_src0_f32

# GCN: %1:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec
# GCN: %1:vgpr_32 = V_MOV_B32_e32 1078523331, implicit $exec

# GCN: %2:vgpr_32 = V_MAD_F32 0, killed %0, 0, %1, 0, %3:vgpr_32, 0, 0, implicit $exec
# GCN: %2:vgpr_32 = V_MAD_F32 0, killed %0, 0, %1, 0, %3:vgpr_32, 0, 0, implicit $mode, implicit $exec




---
---

name:            test_madak_sgpr_src0_f32
name:            test_madak_sgpr_src0_f32

registers:
registers:

  - { id: 0, class: sreg_32_xm0 }
  - { id: 0, class: sreg_32_xm0 }

  - { id: 1, class: vgpr_32}
  - { id: 1, class: vgpr_32}

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

  - { id: 3, class: vgpr_32 }
  - { id: 3, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = IMPLICIT_DEF
    %0 = IMPLICIT_DEF

    %1 = V_MOV_B32_e32 1078523331, implicit $exec
    %1 = V_MOV_B32_e32 1078523331, implicit $exec

    %2 = V_MAC_F32_e32 killed %0, %1, %3, implicit $exec
    %2 = V_MAC_F32_e32 killed %0, %1, %3, implicit $mode, implicit $exec




...
...




# This can still fold if this is an inline immediate.
# This can still fold if this is an inline immediate.




# GCN-LABEL: name: test_madak_inlineimm_src0_f32
# GCN-LABEL: name: test_madak_inlineimm_src0_f32

# GCN: %1:vgpr_32 = V_MADMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit $exec
# GCN: %1:vgpr_32 = V_MADMK_F32 1073741824, 1078523331, %2:vgpr_32, implicit $mode, implicit $exec




---
---

name:            test_madak_inlineimm_src0_f32
name:            test_madak_inlineimm_src0_f32

registers:
registers:

  - { id: 0, class: vgpr_32}
  - { id: 0, class: vgpr_32}

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = V_MOV_B32_e32 1078523331, implicit $exec
    %0 = V_MOV_B32_e32 1078523331, implicit $exec

    %1 = V_MAC_F32_e32 1073741824, %0, %2, implicit $exec
    %1 = V_MAC_F32_e32 1073741824, %0, %2, implicit $mode, implicit $exec




...
...

# Non-inline immediate uses constant bus already.
# Non-inline immediate uses constant bus already.




# GCN-LABEL: name: test_madak_otherimm_src0_f32
# GCN-LABEL: name: test_madak_otherimm_src0_f32

# GCN: %1:vgpr_32 = V_MAC_F32_e32 1120403456, %0, %1, implicit $exec
# GCN: %1:vgpr_32 = V_MAC_F32_e32 1120403456, %0, %1, implicit $mode, implicit $exec




---
---

name:            test_madak_otherimm_src0_f32
name:            test_madak_otherimm_src0_f32

registers:
registers:

  - { id: 0, class: vgpr_32}
  - { id: 0, class: vgpr_32}

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = V_MOV_B32_e32 1078523331, implicit $exec
    %0 = V_MOV_B32_e32 1078523331, implicit $exec

    %1 = V_MAC_F32_e32 1120403456, %0, %2, implicit $exec
    %1 = V_MAC_F32_e32 1120403456, %0, %2, implicit $mode, implicit $exec




...
...

# Non-inline immediate uses constant bus already.
# Non-inline immediate uses constant bus already.




# GCN-LABEL: name: test_madak_other_constantlike_src0_f32
# GCN-LABEL: name: test_madak_other_constantlike_src0_f32

# GCN: %1:vgpr_32 = V_MAC_F32_e32 %stack.0, %0, %1, implicit $exec
# GCN: %1:vgpr_32 = V_MAC_F32_e32 %stack.0, %0, %1, implicit $mode, implicit $exec

---
---

name:            test_madak_other_constantlike_src0_f32
name:            test_madak_other_constantlike_src0_f32

registers:
registers:

  - { id: 0, class: vgpr_32}
  - { id: 0, class: vgpr_32}

  - { id: 1, class: vgpr_32 }
  - { id: 1, class: vgpr_32 }

  - { id: 2, class: vgpr_32 }
  - { id: 2, class: vgpr_32 }

stack:
stack:

  - { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,
  - { id: 0, name: "", type: default, offset: 0, size: 128, alignment: 8,

      callee-saved-register: '', local-offset: 0, debug-info-variable: '',
      callee-saved-register: '', local-offset: 0, debug-info-variable: '',

      debug-info-expression: '', debug-info-location: '' }
      debug-info-expression: '', debug-info-location: '' }

body:             |
body:             |

  bb.0:
  bb.0:




    %0 = V_MOV_B32_e32 1078523331, implicit $exec
    %0 = V_MOV_B32_e32 1078523331, implicit $exec

    %1 = V_MAC_F32_e32 %stack.0, %0, %2, implicit $exec
    %1 = V_MAC_F32_e32 %stack.0, %0, %2, implicit $mode, implicit $exec




...
...




# GCN-LABEL: name: test_madak_inline_literal_f16
# GCN-LABEL: name: test_madak_inline_literal_f16

# GCN: %2:vgpr_32 = V_MADAK_F16 16384, killed %0, 49664, implicit $exec
# GCN: %2:vgpr_32 = V_MADAK_F16 16384, killed %0, 49664, implicit $mode, implicit $exec




---
---

name:            test_madak_inline_literal_f16
name:            test_madak_inline_literal_f16

liveins:
liveins:

  - { reg: '$vgpr0', virtual-reg: '%3' }
  - { reg: '$vgpr0', virtual-reg: '%3' }

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0
    liveins: $vgpr0

  


    %3:vgpr_32 = COPY killed $vgpr0
    %3:vgpr_32 = COPY killed $vgpr0




    %26:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec
    %26:vgpr_32 = V_MOV_B32_e32 49664, implicit $exec

    %28:vgpr_32 = V_MAC_F16_e32 16384, killed %3, %26, implicit $exec
    %28:vgpr_32 = V_MAC_F16_e32 16384, killed %3, %26, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0




...
...




llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines  bb.0:

    $vgpr4_vgpr5 = COPY killed $vgpr0_vgpr1
    $vgpr4_vgpr5 = COPY killed $vgpr0_vgpr1

    $vgpr0_vgpr1 = COPY killed $vgpr2_vgpr3
    $vgpr0_vgpr1 = COPY killed $vgpr2_vgpr3

    $vgpr2_vgpr3 = COPY killed $vgpr4_vgpr5
    $vgpr2_vgpr3 = COPY killed $vgpr4_vgpr5

...
...




# GCN-LABEL: name: swap_phys_overlap_x
# GCN-LABEL: name: swap_phys_overlap_x

# GCN: bb.0:
# GCN: bb.0:

# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec

# GCN-NEXT: $vgpr3_vgpr4 = V_ADD_F64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $exec
# GCN-NEXT: $vgpr3_vgpr4 = V_ADD_F64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $mode, implicit $exec

# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec

# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
# GCN-NEXT: $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec

---
---

name:            swap_phys_overlap_x
name:            swap_phys_overlap_x

body:             |
body:             |

  bb.0:
  bb.0:

    $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
    $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec

    $vgpr3_vgpr4 = V_ADD_F64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $exec
    $vgpr3_vgpr4 = V_ADD_F64 0, $vgpr0_vgpr1, 0, $vgpr3_vgpr4, 0, 0, implicit $mode, implicit $exec

    $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
    $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec

    $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec
    $vgpr1 = V_MOV_B32_e32 killed $vgpr2, implicit $exec

...
...




# GCN-LABEL: name: swap_phys_clobber_y
# GCN-LABEL: name: swap_phys_clobber_y

# GCN: bb.0:
# GCN: bb.0:

# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec
# GCN-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr0, implicit $exec

# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec
# GCN-NEXT: $vgpr0 = V_MOV_B32_e32 killed $vgpr1, implicit $exec

▲ Show 20 Lines • Show All 589 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
Show All 11 Lines
tracksRegLiveness: true
tracksRegLiveness: true

body: |
body: |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1
    liveins: $sgpr0_sgpr1




    $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0, 0
    $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed $sgpr0_sgpr1, 11, 0, 0

    $sgpr7 = S_MOV_B32 61440
    $sgpr7 = S_MOV_B32 61440

    $sgpr6 = S_MOV_B32 -1
    $sgpr6 = S_MOV_B32 -1

    $vcc = V_CMP_EQ_F32_e64 0, 0, 0, undef $sgpr2, 0, implicit $exec
    $vcc = V_CMP_EQ_F32_e64 0, 0, 0, undef $sgpr2, 0, implicit $mode, implicit $exec

    S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.1, implicit killed $vcc




  bb.2:
  bb.2:

    liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003
    liveins: $sgpr6, $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3:0x00000003




    $vgpr0 = V_MOV_B32_e32 9, implicit $exec
    $vgpr0 = V_MOV_B32_e32 9, implicit $exec

    BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, implicit $exec
    BUFFER_STORE_DWORD_OFFSET killed $vgpr0, killed $sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, 0, 0, implicit $exec

    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec

▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
Show First 20 Lines • Show All 111 Lines • ▼ Show 20 Lines  bb.0:

    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec

    SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec
    SI_KILL_F32_COND_IMM_TERMINATOR $vgpr0, 0, 3, implicit-def $exec, implicit-def $vcc, implicit-def $scc, implicit $exec

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.1:
  bb.1:

    $vgpr1 = IMPLICIT_DEF
    $vgpr1 = IMPLICIT_DEF

    $sgpr0 = IMPLICIT_DEF
    $sgpr0 = IMPLICIT_DEF

    $sgpr1 = IMPLICIT_DEF
    $sgpr1 = IMPLICIT_DEF

    $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1,  implicit $exec
    $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1,  implicit $mode, implicit $exec

    $vgpr1 = V_PERMLANE16_B32 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec
    $vgpr1 = V_PERMLANE16_B32 0, killed $vgpr1, 0, killed $sgpr1, 0, killed $sgpr0, $vgpr1, 0, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# GCN-LABEL: name: hazard_vcmpx_permlane16_undef_src
# GCN-LABEL: name: hazard_vcmpx_permlane16_undef_src

# GCN:      V_CMPX_LE_F32_nosdst_e32
# GCN:      V_CMPX_LE_F32_nosdst_e32

# GCN:      S_ADD_U32
# GCN:      S_ADD_U32

# GCN-NEXT: dead $vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec
# GCN-NEXT: dead $vgpr1 = V_MOV_B32_e32 undef $vgpr1, implicit $exec

Show All 17 Lines
llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
---
---

name:            vmem_valu_write_sgpr
name:            vmem_valu_write_sgpr

body:             |
body:             |

  bb.0:
  bb.0:

    $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
    $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF

    $sgpr4 = IMPLICIT_DEF
    $sgpr4 = IMPLICIT_DEF

    $vgpr0 = IMPLICIT_DEF
    $vgpr0 = IMPLICIT_DEF

    $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
    $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec

    $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $exec
    $vgpr2 = V_ADD_F32_e32 $vgpr1, $vgpr1, implicit $mode, implicit $exec

    $sgpr0 = S_MOV_B32 0
    $sgpr0 = S_MOV_B32 0

...
...

# GCN-LABEL: name: vmem_swait0_write_sgpr
# GCN-LABEL: name: vmem_swait0_write_sgpr

# GCN:      BUFFER_LOAD_DWORD_OFFEN
# GCN:      BUFFER_LOAD_DWORD_OFFEN

# GCN-NEXT: S_WAITCNT
# GCN-NEXT: S_WAITCNT

# GCN-NEXT: S_MOV_B32
# GCN-NEXT: S_MOV_B32

---
---

name:            vmem_swait0_write_sgpr
name:            vmem_swait0_write_sgpr

▲ Show 20 Lines • Show All 240 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
# RUN: llc -o - %s -march=amdgcn -mcpu=fiji -run-pass=si-insert-waitcnts -verify-machineinstrs | FileCheck -check-prefix=GCN %s
# RUN: llc -o - %s -march=amdgcn -mcpu=fiji -run-pass=si-insert-waitcnts -verify-machineinstrs | FileCheck -check-prefix=GCN %s




# GCN-LABEL: waitcnt-back-edge-loop
# GCN-LABEL: waitcnt-back-edge-loop

# GCN: bb.2
# GCN: bb.2

# GCN: S_WAITCNT 112
# GCN: S_WAITCNT 112

# GCN: $vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $exec
# GCN: $vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $mode, implicit $exec




---
---

name: waitcnt-back-edge-loop
name: waitcnt-back-edge-loop

body:             |
body:             |

  bb.0:
  bb.0:

    successors: %bb.1
    successors: %bb.1




    $vgpr1 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2
    $vgpr1 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2

    $vgpr2 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2
    $vgpr2 = V_MOV_B32_e32 0, implicit $exec, implicit-def $vgpr1_vgpr2

    $vgpr4 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
    $vgpr4 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)

    $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
    $vgpr0 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)

    $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 3, killed $sgpr4, implicit $exec
    $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 3, killed $sgpr4, implicit $exec

    $vgpr3 = V_CNDMASK_B32_e64 0, -1082130432, 0, 1065353216, killed $sgpr0_sgpr1, implicit $exec
    $vgpr3 = V_CNDMASK_B32_e64 0, -1082130432, 0, 1065353216, killed $sgpr0_sgpr1, implicit $exec

    $vgpr5 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $exec
    $vgpr5 = V_MOV_B32_e32 $vgpr0, implicit $exec, implicit $exec

    S_BRANCH %bb.1
    S_BRANCH %bb.1




  bb.3:
  bb.3:

    successors: %bb.1
    successors: %bb.1




    $vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
    $vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)




  bb.1:
  bb.1:

    successors: %bb.5, %bb.2
    successors: %bb.5, %bb.2




    $vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $exec
    $vgpr5 = V_CVT_I32_F32_e32 killed $vgpr5, implicit $mode, implicit $exec

    V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec
    V_CMP_NE_U32_e32 0, $vgpr5, implicit-def $vcc, implicit $exec

    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc

    S_CBRANCH_VCCZ %bb.5, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.5, implicit killed $vcc




  bb.2:
  bb.2:

    successors: %bb.4, %bb.3
    successors: %bb.4, %bb.3




    V_CMP_EQ_U32_e32 9, killed $vgpr5, implicit-def $vcc, implicit $exec
    V_CMP_EQ_U32_e32 9, killed $vgpr5, implicit-def $vcc, implicit $exec

    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc

    S_CBRANCH_VCCZ %bb.3, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.3, implicit killed $vcc




  bb.4:
  bb.4:

    successors: %bb.3, %bb.1
    successors: %bb.3, %bb.1




    $vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)
    $vgpr5 = FLAT_LOAD_DWORD $vgpr1_vgpr2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load 4 from `float addrspace(1)* null`, addrspace 1)

    $vgpr4 = V_CVT_I32_F32_e32 $vgpr5, implicit $exec
    $vgpr4 = V_CVT_I32_F32_e32 $vgpr5, implicit $mode, implicit $exec

    V_CMP_EQ_U32_e32 2, killed $vgpr4, implicit-def $vcc, implicit $exec
    V_CMP_EQ_U32_e32 2, killed $vgpr4, implicit-def $vcc, implicit $exec

    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc
    $vcc = S_AND_B64 $exec, killed $vcc, implicit-def dead $scc

    $vgpr4 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $exec
    $vgpr4 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $exec

    S_CBRANCH_VCCZ %bb.1, implicit killed $vcc
    S_CBRANCH_VCCZ %bb.1, implicit killed $vcc

    S_BRANCH %bb.3
    S_BRANCH %bb.3




  bb.5:
  bb.5:




    $vgpr4 = V_MAC_F32_e32 killed $vgpr0, killed $vgpr3, killed $vgpr4, implicit $exec
    $vgpr4 = V_MAC_F32_e32 killed $vgpr0, killed $vgpr3, killed $vgpr4, implicit $mode, implicit $exec

    EXP_DONE 12, killed $vgpr4, undef $vgpr0, undef $vgpr0, undef $vgpr0, 0, 0, 15, implicit $exec
    EXP_DONE 12, killed $vgpr4, undef $vgpr0, undef $vgpr0, undef $vgpr0, 0, 0, 15, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

---
---




# GCN-LABEL: name: waitcnt-multiple-back-edges{{$}}
# GCN-LABEL: name: waitcnt-multiple-back-edges{{$}}

# GCN: bb.0:
# GCN: bb.0:

# GCN: S_WAITCNT 0
# GCN: S_WAITCNT 0

Show All 29 Lines
llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
Show All 10 Linesbody:             |

  bb.0:
  bb.0:

    liveins: $vgpr99
    liveins: $vgpr99




    ; GFX9-LABEL: name: max-counter-lgkmcnt
    ; GFX9-LABEL: name: max-counter-lgkmcnt

    ; GFX9: S_WAITCNT 0
    ; GFX9: S_WAITCNT 0

    ; GFX9: $vgpr34_vgpr35 = DS_READ2_B32_gfx9 renamable $vgpr99, 34, 35, 0, implicit $exec
    ; GFX9: $vgpr34_vgpr35 = DS_READ2_B32_gfx9 renamable $vgpr99, 34, 35, 0, implicit $exec

    ; GFX9-NOT: S_WAITCNT 53119
    ; GFX9-NOT: S_WAITCNT 53119

    ; GFX9-NEXT: S_WAITCNT 52863
    ; GFX9-NEXT: S_WAITCNT 52863

    ; GFX9-NEXT: $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $exec
    ; GFX9-NEXT: $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $mode, implicit $exec

    ; GFX9-NEXT: $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $exec
    ; GFX9-NEXT: $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $mode, implicit $exec

    ; GFX9-NEXT: $vgpr4 = V_MAC_F32_e32 0, $vgpr5, $vgpr4, implicit $exec
    ; GFX9-NEXT: $vgpr4 = V_MAC_F32_e32 0, $vgpr5, $vgpr4, implicit $mode, implicit $exec

    ; GFX9-NEXT: $vgpr6 = V_MAC_F32_e32 0, $vgpr7, $vgpr6, implicit $exec
    ; GFX9-NEXT: $vgpr6 = V_MAC_F32_e32 0, $vgpr7, $vgpr6, implicit $mode, implicit $exec

    ; GFX9-NEXT: S_ENDPGM 0
    ; GFX9-NEXT: S_ENDPGM 0

    ; GFX10-LABEL: name: max-counter-lgkmcnt
    ; GFX10-LABEL: name: max-counter-lgkmcnt

    ; GFX10: $vgpr34_vgpr35 = DS_READ2_B32_gfx9 renamable $vgpr99, 34, 35, 0, implicit $exec
    ; GFX10: $vgpr34_vgpr35 = DS_READ2_B32_gfx9 renamable $vgpr99, 34, 35, 0, implicit $exec

    ; GFX10-NEXT: S_WAITCNT 53631
    ; GFX10-NEXT: S_WAITCNT 53631

    ; GFX10-NEXT: $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $exec
    ; GFX10-NEXT: $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $mode, implicit $exec

    ; GFX10-NEXT: S_WAITCNT 53375
    ; GFX10-NEXT: S_WAITCNT 53375

    ; GFX10-NEXT: $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $exec
    ; GFX10-NEXT: $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $mode, implicit $exec

    ; GFX10-NEXT: S_WAITCNT 53119
    ; GFX10-NEXT: S_WAITCNT 53119

    ; GFX10-NEXT: $vgpr4 = V_MAC_F32_e32 0, $vgpr5, $vgpr4, implicit $exec
    ; GFX10-NEXT: $vgpr4 = V_MAC_F32_e32 0, $vgpr5, $vgpr4, implicit $mode, implicit $exec

    ; GFX10-NEXT: S_WAITCNT 52863
    ; GFX10-NEXT: S_WAITCNT 52863

    ; GFX10-NEXT: $vgpr6 = V_MAC_F32_e32 0, $vgpr7, $vgpr6, implicit $exec
    ; GFX10-NEXT: $vgpr6 = V_MAC_F32_e32 0, $vgpr7, $vgpr6, implicit $mode, implicit $exec

    ; GFX10-NEXT: S_ENDPGM 0
    ; GFX10-NEXT: S_ENDPGM 0

    $vgpr0_vgpr1 = DS_READ2_B32_gfx9 renamable $vgpr99, 0, 1, 0, implicit $exec
    $vgpr0_vgpr1 = DS_READ2_B32_gfx9 renamable $vgpr99, 0, 1, 0, implicit $exec

    $vgpr2_vgpr3 = DS_READ2_B32_gfx9 renamable $vgpr99, 2, 3, 0, implicit $exec
    $vgpr2_vgpr3 = DS_READ2_B32_gfx9 renamable $vgpr99, 2, 3, 0, implicit $exec

    $vgpr4_vgpr5 = DS_READ2_B32_gfx9 renamable $vgpr99, 4, 5, 0, implicit $exec
    $vgpr4_vgpr5 = DS_READ2_B32_gfx9 renamable $vgpr99, 4, 5, 0, implicit $exec

    $vgpr6_vgpr7 = DS_READ2_B32_gfx9 renamable $vgpr99, 6, 7, 0, implicit $exec
    $vgpr6_vgpr7 = DS_READ2_B32_gfx9 renamable $vgpr99, 6, 7, 0, implicit $exec

    $vgpr8_vgpr9 = DS_READ2_B32_gfx9 renamable $vgpr99, 8, 9, 0, implicit $exec
    $vgpr8_vgpr9 = DS_READ2_B32_gfx9 renamable $vgpr99, 8, 9, 0, implicit $exec

    $vgpr10_vgpr11 = DS_READ2_B32_gfx9 renamable $vgpr99, 10, 11, 0, implicit $exec
    $vgpr10_vgpr11 = DS_READ2_B32_gfx9 renamable $vgpr99, 10, 11, 0, implicit $exec

    $vgpr12_vgpr13 = DS_READ2_B32_gfx9 renamable $vgpr99, 12, 13, 0, implicit $exec
    $vgpr12_vgpr13 = DS_READ2_B32_gfx9 renamable $vgpr99, 12, 13, 0, implicit $exec

    $vgpr14_vgpr15 = DS_READ2_B32_gfx9 renamable $vgpr99, 14, 15, 0, implicit $exec
    $vgpr14_vgpr15 = DS_READ2_B32_gfx9 renamable $vgpr99, 14, 15, 0, implicit $exec

    $vgpr16_vgpr17 = DS_READ2_B32_gfx9 renamable $vgpr99, 16, 17, 0, implicit $exec
    $vgpr16_vgpr17 = DS_READ2_B32_gfx9 renamable $vgpr99, 16, 17, 0, implicit $exec

    $vgpr18_vgpr19 = DS_READ2_B32_gfx9 renamable $vgpr99, 18, 19, 0, implicit $exec
    $vgpr18_vgpr19 = DS_READ2_B32_gfx9 renamable $vgpr99, 18, 19, 0, implicit $exec

    $vgpr20_vgpr21 = DS_READ2_B32_gfx9 renamable $vgpr99, 20, 21, 0, implicit $exec
    $vgpr20_vgpr21 = DS_READ2_B32_gfx9 renamable $vgpr99, 20, 21, 0, implicit $exec

    $vgpr22_vgpr23 = DS_READ2_B32_gfx9 renamable $vgpr99, 22, 23, 0, implicit $exec
    $vgpr22_vgpr23 = DS_READ2_B32_gfx9 renamable $vgpr99, 22, 23, 0, implicit $exec

    $vgpr24_vgpr25 = DS_READ2_B32_gfx9 renamable $vgpr99, 24, 25, 0, implicit $exec
    $vgpr24_vgpr25 = DS_READ2_B32_gfx9 renamable $vgpr99, 24, 25, 0, implicit $exec

    $vgpr26_vgpr27 = DS_READ2_B32_gfx9 renamable $vgpr99, 26, 27, 0, implicit $exec
    $vgpr26_vgpr27 = DS_READ2_B32_gfx9 renamable $vgpr99, 26, 27, 0, implicit $exec

    $vgpr28_vgpr29 = DS_READ2_B32_gfx9 renamable $vgpr99, 28, 29, 0, implicit $exec
    $vgpr28_vgpr29 = DS_READ2_B32_gfx9 renamable $vgpr99, 28, 29, 0, implicit $exec

    $vgpr30_vgpr31 = DS_READ2_B32_gfx9 renamable $vgpr99, 30, 31, 0, implicit $exec
    $vgpr30_vgpr31 = DS_READ2_B32_gfx9 renamable $vgpr99, 30, 31, 0, implicit $exec

    $vgpr32_vgpr33 = DS_READ2_B32_gfx9 renamable $vgpr99, 32, 33, 0, implicit $exec
    $vgpr32_vgpr33 = DS_READ2_B32_gfx9 renamable $vgpr99, 32, 33, 0, implicit $exec

    $vgpr34_vgpr35 = DS_READ2_B32_gfx9 renamable $vgpr99, 34, 35, 0, implicit $exec
    $vgpr34_vgpr35 = DS_READ2_B32_gfx9 renamable $vgpr99, 34, 35, 0, implicit $exec

    $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $exec
    $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $mode, implicit $exec

    $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $exec
    $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $mode, implicit $exec

    $vgpr4 = V_MAC_F32_e32 0, $vgpr5, $vgpr4, implicit $exec
    $vgpr4 = V_MAC_F32_e32 0, $vgpr5, $vgpr4, implicit $mode, implicit $exec

    $vgpr6 = V_MAC_F32_e32 0, $vgpr7, $vgpr6, implicit $exec
    $vgpr6 = V_MAC_F32_e32 0, $vgpr7, $vgpr6, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# Overflows vmcnt with gfx9 and gfx10.
# Overflows vmcnt with gfx9 and gfx10.

---
---

name:            max-counter-vmcnt
name:            max-counter-vmcnt

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4




    ; GFX9_10-LABEL: name: max-counter-vmcnt
    ; GFX9_10-LABEL: name: max-counter-vmcnt

    ; GFX9_10: $vgpr66 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 264, 0, 0, 0, 0, 0, implicit $exec
    ; GFX9_10: $vgpr66 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 264, 0, 0, 0, 0, 0, implicit $exec

    ; GFX9-NOT: S_WAITCNT 53119
    ; GFX9-NOT: S_WAITCNT 53119

    ; GFX10-NOT: S_WAITCNT 65407
    ; GFX10-NOT: S_WAITCNT 65407

    ; GFX9-NEXT: S_WAITCNT 53118
    ; GFX9-NEXT: S_WAITCNT 53118

    ; GFX10-NEXT: S_WAITCNT 65406
    ; GFX10-NEXT: S_WAITCNT 65406

    ; GFX9_10-NEXT: $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $exec
    ; GFX9_10-NEXT: $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $mode, implicit $exec

    ; GFX9_10-NEXT: $vgpr1 = V_MAC_F32_e32 0, $vgpr2, $vgpr1, implicit $exec
    ; GFX9_10-NEXT: $vgpr1 = V_MAC_F32_e32 0, $vgpr2, $vgpr1, implicit $mode, implicit $exec

    ; GFX9_10-NEXT: $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $exec
    ; GFX9_10-NEXT: $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $mode, implicit $exec

    ; GFX9_10-NEXT: $vgpr3 = V_MAC_F32_e32 0, $vgpr4, $vgpr3, implicit $exec
    ; GFX9_10-NEXT: $vgpr3 = V_MAC_F32_e32 0, $vgpr4, $vgpr3, implicit $mode, implicit $exec

    ; GFX9_10-NEXT: S_ENDPGM 0
    ; GFX9_10-NEXT: S_ENDPGM 0

    $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
    $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec

    $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, 0, 0, implicit $exec
    $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, 0, 0, implicit $exec

    $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, 0, 0, implicit $exec
    $vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, 0, 0, implicit $exec

    $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, 0, 0, implicit $exec
    $vgpr3 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, 0, 0, implicit $exec

    $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 16, 0, 0, 0, 0, 0, implicit $exec
    $vgpr4 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 16, 0, 0, 0, 0, 0, implicit $exec

    $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 20, 0, 0, 0, 0, 0, implicit $exec
    $vgpr5 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 20, 0, 0, 0, 0, 0, implicit $exec

    $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 24, 0, 0, 0, 0, 0, implicit $exec
    $vgpr6 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 24, 0, 0, 0, 0, 0, implicit $exec

▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines  bb.0:

    $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 236, 0, 0, 0, 0, 0, implicit $exec
    $vgpr59 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 236, 0, 0, 0, 0, 0, implicit $exec

    $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 240, 0, 0, 0, 0, 0, implicit $exec
    $vgpr60 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 240, 0, 0, 0, 0, 0, implicit $exec

    $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 244, 0, 0, 0, 0, 0, implicit $exec
    $vgpr61 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 244, 0, 0, 0, 0, 0, implicit $exec

    $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 248, 0, 0, 0, 0, 0, implicit $exec
    $vgpr62 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 248, 0, 0, 0, 0, 0, implicit $exec

    $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 252, 0, 0, 0, 0, 0, implicit $exec
    $vgpr63 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 252, 0, 0, 0, 0, 0, implicit $exec

    $vgpr64 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 256, 0, 0, 0, 0, 0, implicit $exec
    $vgpr64 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 256, 0, 0, 0, 0, 0, implicit $exec

    $vgpr65 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 260, 0, 0, 0, 0, 0, implicit $exec
    $vgpr65 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 260, 0, 0, 0, 0, 0, implicit $exec

    $vgpr66 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 264, 0, 0, 0, 0, 0, implicit $exec
    $vgpr66 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 264, 0, 0, 0, 0, 0, implicit $exec

    $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $exec
    $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $mode, implicit $exec

    $vgpr1 = V_MAC_F32_e32 0, $vgpr2, $vgpr1, implicit $exec
    $vgpr1 = V_MAC_F32_e32 0, $vgpr2, $vgpr1, implicit $mode, implicit $exec

    $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $exec
    $vgpr2 = V_MAC_F32_e32 0, $vgpr3, $vgpr2, implicit $mode, implicit $exec

    $vgpr3 = V_MAC_F32_e32 0, $vgpr4, $vgpr3, implicit $exec
    $vgpr3 = V_MAC_F32_e32 0, $vgpr4, $vgpr3, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...




# Should be no waitcnt if expcnt overflows.
# Should be no waitcnt if expcnt overflows.

---
---

name:            max-counter-expcnt
name:            max-counter-expcnt

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $vgpr0, $vgpr1
    liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $vgpr0, $vgpr1




    ; GFX9_10-LABEL: name: max-counter-expcnt
    ; GFX9_10-LABEL: name: max-counter-expcnt

    ; GFX9_10: EXP
    ; GFX9_10: EXP

    ; GFX9_10-NOT: S_WAITCNT
    ; GFX9_10-NOT: S_WAITCNT

    EXP 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec
    EXP 0, $vgpr0, $vgpr0, $vgpr0, $vgpr0, -1, -1, 15, implicit $exec

    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec

    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec

    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec

    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec

    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec

    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec

    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec
    EXP 0, $vgpr1, $vgpr1, $vgpr1, $vgpr1, -1, -1, 15, implicit $exec

    $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $exec
    $vgpr0 = V_MAC_F32_e32 0, $vgpr1, $vgpr0, implicit $mode, implicit $exec

    S_ENDPGM 0
    S_ENDPGM 0

...
...

llvm/test/CodeGen/AMDGPU/waitcnt-permute.mir
Show All 9 Linesliveins:

  - { reg: '$vgpr0' }
  - { reg: '$vgpr0' }

  - { reg: '$vgpr1' }
  - { reg: '$vgpr1' }

  - { reg: '$sgpr30_sgpr31' }
  - { reg: '$sgpr30_sgpr31' }

body:             |
body:             |

  bb.0:
  bb.0:

    liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
    liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31




    $vgpr0 = DS_BPERMUTE_B32 killed $vgpr0, killed $vgpr1, 0, implicit $exec
    $vgpr0 = DS_BPERMUTE_B32 killed $vgpr0, killed $vgpr1, 0, implicit $exec

    $vgpr0 = V_ADD_F32_e32 1065353216, killed $vgpr0, implicit $exec
    $vgpr0 = V_ADD_F32_e32 1065353216, killed $vgpr0, implicit $mode, implicit $exec

    S_SETPC_B64_return killed $sgpr30_sgpr31, implicit killed $vgpr0
    S_SETPC_B64_return killed $sgpr30_sgpr31, implicit killed $vgpr0




...
...

llvm/unittests/MI/LiveIntervalTest.cpp
Show First 20 Lines • Show All 426 Lines • ▼ Show 20 Lines  liveIntervalTest(R"MIR(

    %125.sub2:vreg_128 = COPY %125.sub0
    %125.sub2:vreg_128 = COPY %125.sub0

    undef %51.sub0:vreg_128 = V_MOV_B32_e32 898625526, implicit $exec
    undef %51.sub0:vreg_128 = V_MOV_B32_e32 898625526, implicit $exec

    %51.sub1:vreg_128 = COPY %51.sub0
    %51.sub1:vreg_128 = COPY %51.sub0

    %51.sub2:vreg_128 = COPY %51.sub0
    %51.sub2:vreg_128 = COPY %51.sub0

    %52:vgpr_32 = V_MOV_B32_e32 986714345, implicit $exec
    %52:vgpr_32 = V_MOV_B32_e32 986714345, implicit $exec

    %54:vgpr_32 = V_MOV_B32_e32 1742342378, implicit $exec
    %54:vgpr_32 = V_MOV_B32_e32 1742342378, implicit $exec

    %57:vgpr_32 = V_MOV_B32_e32 3168768712, implicit $exec
    %57:vgpr_32 = V_MOV_B32_e32 3168768712, implicit $exec

    %59:vgpr_32 = V_MOV_B32_e32 1039972644, implicit $exec
    %59:vgpr_32 = V_MOV_B32_e32 1039972644, implicit $exec

    %60:vgpr_32 = V_MAD_F32 0, %52, 0, undef %61:vgpr_32, 0, %59, 0, 0, implicit $exec
    %60:vgpr_32 = nofpexcept V_MAD_F32 0, %52, 0, undef %61:vgpr_32, 0, %59, 0, 0, implicit $mode, implicit $exec

    %63:vgpr_32 = V_ADD_F32_e32 %51.sub3, undef %64:vgpr_32, implicit $exec
    %63:vgpr_32 = nofpexcept V_ADD_F32_e32 %51.sub3, undef %64:vgpr_32, implicit $mode, implicit $exec

    dead %66:vgpr_32 = V_MAD_F32 0, %60, 0, undef %67:vgpr_32, 0, %125.sub2, 0, 0, implicit $exec
    dead %66:vgpr_32 = nofpexcept V_MAD_F32 0, %60, 0, undef %67:vgpr_32, 0, %125.sub2, 0, 0, implicit $mode, implicit $exec

    undef %124.sub1:vreg_128 = V_MAD_F32 0, %57, 0, undef %70:vgpr_32, 0, %125.sub1, 0, 0, implicit $exec
    undef %124.sub1:vreg_128 = nofpexcept V_MAD_F32 0, %57, 0, undef %70:vgpr_32, 0, %125.sub1, 0, 0, implicit $mode, implicit $exec

    %124.sub0:vreg_128 = V_MAD_F32 0, %54, 0, undef %73:vgpr_32, 0, %125.sub0, 0, 0, implicit $exec
    %124.sub0:vreg_128 = nofpexcept V_MAD_F32 0, %54, 0, undef %73:vgpr_32, 0, %125.sub0, 0, 0, implicit $mode, implicit $exec

    dead undef %125.sub3:vreg_128 = V_MAC_F32_e32 %63, undef %76:vgpr_32, %125.sub3, implicit $exec
    dead undef %125.sub3:vreg_128 = nofpexcept V_MAC_F32_e32 %63, undef %76:vgpr_32, %125.sub3, implicit $mode, implicit $exec

)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {
)MIR", [](MachineFunction &MF, LiveIntervals &LIS) {

    testHandleMove(MF, LIS, 15, 12);
    testHandleMove(MF, LIS, 15, 12);

  });
  });

}
}




TEST(LiveIntervalTest, TestMoveSubRegDefAcrossUseDef) {
TEST(LiveIntervalTest, TestMoveSubRegDefAcrossUseDef) {

  liveIntervalTest(R"MIR(
  liveIntervalTest(R"MIR(

    %1:vreg_64 = IMPLICIT_DEF
    %1:vreg_64 = IMPLICIT_DEF

▲ Show 20 Lines • Show All 132 Lines • Show Last 20 Lines