[NFC][AIX] Remove spaces after the comma for `.csect` directive

[Xiangling_L]

Summary

To be consistent with other directives like .comm, '.lcomm', we remove the spaces after the comma for .csect.

[jasonliu]

LGTM.
Although there are some other directives that has comma in them would have spaces, I'm fine if we want to take the position and say "as long as it's AIX specific directive, we will leave no space between commas". (llvm is already inconsistent, we will try to be somewhat consistent within ourselves.)
Thanks for the patch.

llvm/lib/MC/MCSectionXCOFF.cpp

 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 MCSectionXCOFF::~MCSectionXCOFF() = default;
 
 void MCSectionXCOFF::printCsectDirective(raw_ostream &OS) const {
-  OS << "\t.csect " << QualName->getName() << ", " << Log2_32(getAlignment())
+  OS << "\t.csect " << QualName->getName() << "," << Log2_32(getAlignment())
      << '\n';
 }
 
 void MCSectionXCOFF::PrintSwitchToSection(const MCAsmInfo &MAI, const Triple &T,
                                           raw_ostream &OS,
                                           const MCExpr *Subsection) const {
   if (getKind().isText()) {
     if (getMappingClass() != XCOFF::XMC_PR)

llvm/test/CodeGen/PowerPC/aix-func-align.ll

entry:
   ret i32 0
 }
 
 define i32 @bar()  align 64 {
 entry:
   ret i32 0
 }
 
-; CHECK:      .csect .text[PR], 6
+; CHECK:      .csect .text[PR],6
 ; CHECK-NEXT: .foo:
 
-; CHECK:      .csect .text[PR], 6
+; CHECK:      .csect .text[PR],6
 ; CHECK-NEXT: .bar:
 
 ; SYMS:       Symbol {{[{][[:space:]] *}}Index: [[#INDX:]]{{[[:space:]] *}}Name: .text
 ; SYMS-NEXT:    Value (RelocatableAddress): 0x0
 ; SYMS-NEXT:    Section: .text
 ; SYMS-NEXT:    Type: 0x0
 ; SYMS-NEXT:    StorageClass: C_HIDEXT (0x6B)
 ; SYMS-NEXT:    NumberOfAuxEntries: 1

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

 
 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocCPT %const.0, $x2 :: (load 8 from got)
 ; 64SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $x[[REG1]] :: (load 4 from constant-pool)
 
 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, %const.0
 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL %const.0, killed renamable $x[[REG1]], implicit $x2 :: (load 8 from got)
 ; 64LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $x[[REG2]] :: (load 4 from constant-pool)
 
-; 32SMALL-ASM:         .csect .rodata[RO], 2
+; 32SMALL-ASM:         .csect .rodata[RO],2
 ; 32SMALL-ASM:         .align  2
 ; 32SMALL-ASM: .LCPI0_0:
 ; 32SMALL-ASM:         .long  0x40b00000
 ; 32SMALL-ASM: .test_float:
 ; 32SMALL-ASM:         lwz [[REG1:[0-9]+]], LC0(2)
 ; 32SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 32SMALL-ASM:         blr
 
-; 32LARGE-ASM:         .csect .rodata[RO], 2
+; 32LARGE-ASM:         .csect .rodata[RO],2
 ; 32LARGE-ASM:         .align  2
 ; 32LARGE-ASM: .LCPI0_0:
 ; 32LARGE-ASM:         .long   0x40b00000
 ; 32LARGE-ASM: .test_float:
 ; 32LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 32LARGE-ASM:         lwz [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 32LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 32LARGE-ASM:         blr
 
-; 64SMALL-ASM:         .csect .rodata[RO], 2
+; 64SMALL-ASM:         .csect .rodata[RO],2
 ; 64SMALL-ASM:         .align  2
 ; 64SMALL-ASM: .LCPI0_0:
 ; 64SMALL-ASM:         .long   0x40b00000
 ; 64SMALL-ASM: .test_float:
 ; 64SMALL-ASM:         ld [[REG1:[0-9]+]], LC0(2)
 ; 64SMALL-ASM:         lfs 1, 0([[REG1]])
 ; 64SMALL-ASM:         blr
 
-; 64LARGE-ASM:         .csect .rodata[RO], 2
+; 64LARGE-ASM:         .csect .rodata[RO],2
 ; 64LARGE-ASM:         .align  2
 ; 64LARGE-ASM: .LCPI0_0:
 ; 64LARGE-ASM:         .long   0x40b00000
 ; 64LARGE-ASM: .test_float:
 ; 64LARGE-ASM:         addis [[REG1:[0-9]+]], LC0@u(2)
 ; 64LARGE-ASM:         ld [[REG2:[0-9]+]], LC0@l([[REG1]])
 ; 64LARGE-ASM:         lfs 1, 0([[REG2]])
 ; 64LARGE-ASM:         blr
 
 ; CHECK: .toc
 ; CHECK: .tc .LCPI0_0[TC],.LCPI0_0

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

 ; 32SMALL-ASM:      bctr
 ; 32SMALL-ASM: LBB0_2:
 ; 32SMALL-ASM: LBB0_3:
 ; 32SMALL-ASM: LBB0_4:
 ; 32SMALL-ASM: LBB0_5:
 ; 32SMALL-ASM: LBB0_6:
 ; 32SMALL-ASM:      li 3, 0
 ; 32SMALL-ASM:      blr
-; 32SMALL-ASM:      .csect .rodata[RO], 2
+; 32SMALL-ASM:      .csect .rodata[RO],2
 ; 32SMALL-ASM:      .align  2
 ; 32SMALL-ASM: .LJTI0_0:
 ; 32SMALL-ASM:      .long   LBB0_2-.LJTI0_0
 ; 32SMALL-ASM:      .long   LBB0_3-.LJTI0_0
 ; 32SMALL-ASM:      .long   LBB0_4-.LJTI0_0
 ; 32SMALL-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; 32LARGE-ASM-LABEL: jump_table

 ; 32LARGE-ASM:      bctr
 ; 32LARGE-ASM: LBB0_2:
 ; 32LARGE-ASM: LBB0_3:
 ; 32LARGE-ASM: LBB0_4:
 ; 32LARGE-ASM: LBB0_5:
 ; 32LARGE-ASM: LBB0_6:
 ; 32LARGE-ASM:      li 3, 0
 ; 32LARGE-ASM:      blr
-; 32LARGE-ASM:      .csect .rodata[RO], 2
+; 32LARGE-ASM:      .csect .rodata[RO],2
 ; 32LARGE-ASM:      .align  2
 ; 32LARGE-ASM: .LJTI0_0:
 ; 32LARGE-ASM:      .long   LBB0_2-.LJTI0_0
 ; 32LARGE-ASM:      .long   LBB0_3-.LJTI0_0
 ; 32LARGE-ASM:      .long   LBB0_4-.LJTI0_0
 ; 32LARGE-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; 64SMALL-ASM-LABEL: jump_table

 ; 64SMALL-ASM:      bctr
 ; 64SMALL-ASM: LBB0_2:
 ; 64SMALL-ASM: LBB0_3:
 ; 64SMALL-ASM: LBB0_4:
 ; 64SMALL-ASM: LBB0_5:
 ; 64SMALL-ASM: LBB0_6:
 ; 64SMALL-ASM:      li 3, 0
 ; 64SMALL-ASM:      blr
-; 64SMALL-ASM:      .csect .rodata[RO], 2
+; 64SMALL-ASM:      .csect .rodata[RO],2
 ; 64SMALL-ASM:      .align  2
 ; 64SMALL-ASM: .LJTI0_0:
 ; 64SMALL-ASM:      .long   LBB0_2-.LJTI0_0
 ; 64SMALL-ASM:      .long   LBB0_3-.LJTI0_0
 ; 64SMALL-ASM:      .long   LBB0_4-.LJTI0_0
 ; 64SMALL-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; 64LARGE-ASM-LABEL: jump_table

 ; 64LARGE-ASM:      bctr
 ; 64LARGE-ASM: LBB0_2:
 ; 64LARGE-ASM: LBB0_3:
 ; 64LARGE-ASM: LBB0_4:
 ; 64LARGE-ASM: LBB0_5:
 ; 64LARGE-ASM: LBB0_6:
 ; 64LARGE-ASM:      li 3, 0
 ; 64LARGE-ASM:      blr
-; 64LARGE-ASM:      .csect .rodata[RO], 2
+; 64LARGE-ASM:      .csect .rodata[RO],2
 ; 64LARGE-ASM:      .align  2
 ; 64LARGE-ASM: .LJTI0_0:
 ; 64LARGE-ASM:      .long   LBB0_2-.LJTI0_0
 ; 64LARGE-ASM:      .long   LBB0_3-.LJTI0_0
 ; 64LARGE-ASM:      .long   LBB0_4-.LJTI0_0
 ; 64LARGE-ASM:      .long   LBB0_5-.LJTI0_0
 
 ; CHECK: .toc
 ; CHECK: .tc .LJTI0_0[TC],.LJTI0_0

llvm/test/CodeGen/PowerPC/aix-readonly-with-relocation.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff --relocation-model=pic < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff --relocation-model=pic < %s | FileCheck --check-prefix=CHECK64 %s
 
 @a = common global i32 0
 @b = constant i32* @a
 
 ;CHECK:         .comm   a[RW],4,2
-;CHECK-NEXT:    .csect .data[RW], 2
+;CHECK-NEXT:    .csect .data[RW],2
 ;CHECK-NEXT:    .globl  b
 ;CHECK-NEXT:    .align  2
 ;CHECK-NEXT: b:
 ;CHECK-NEXT:    .long   a
 
 ;CHECK64:       .comm   a[RW],4,2
-;CHECK64-NEXT:  .csect .data[RW], 3
+;CHECK64-NEXT:  .csect .data[RW],3
 ;CHECK64-NEXT:  .globl  b
 ;CHECK64-NEXT:  .align  3
 ;CHECK64-NEXT: b:
 ;CHECK64-NEXT:  .llong  a

llvm/test/CodeGen/PowerPC/aix-reference-func-addr-const.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck --check-prefix=CHECK64 %s
 
 @foo_ptr = global void (...)* @foo
 declare void @foo(...)
 
 @bar_ptr1 = global void (...)* bitcast (void ()* @bar to void (...)*)
 define void @bar() {
 entry:
   ret void
 }
 
 
-;CHECK:          .csect .data[RW], 2
+;CHECK:          .csect .data[RW],2
 ;CHECK-NEXT:     .globl  foo_ptr
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     foo_ptr:
 ;CHECK-NEXT:     .long   foo[DS]
 ;CHECK-NEXT:     .globl  bar_ptr1
 ;CHECK-NEXT:     .align  2
 ;CHECK-NEXT:     bar_ptr1:
 ;CHECK-NEXT:     .long   bar[DS]
 ;CHECK-NEXT:     .extern foo[DS]
 
-;CHECK64:         .csect .data[RW], 3
+;CHECK64:         .csect .data[RW],3
 ;CHECK64-NEXT:         .globl  foo_ptr
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    foo_ptr:
 ;CHECK64-NEXT:         .llong  foo[DS]
 ;CHECK64-NEXT:         .globl  bar_ptr1
 ;CHECK64-NEXT:         .align  3
 ;CHECK64-NEXT:    bar_ptr1:
 ;CHECK64-NEXT:         .llong  bar[DS]
 ;CHECK64-NEXT:         .extern foo[DS]

llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll

 @f = common local_unnamed_addr global float 0.000000e+00, align 4
 
 @over_aligned_comm = common local_unnamed_addr global double 0.000000e+00, align 32
 
 @array = common local_unnamed_addr global [33 x i8] zeroinitializer, align 1
 
 ; CHECK-NOT: .toc
 
-; CHECK:      .csect .text[PR], 2
+; CHECK:      .csect .text[PR],2
 ; CHECK-NEXT:  .file
 
-; CHECK:      .csect .data[RW], 5
+; CHECK:      .csect .data[RW],5
 ; CHECK-NEXT: .globl  ivar
 ; CHECK-NEXT: .align  2
 ; CHECK-NEXT: ivar:
 ; CHECK-NEXT: .long   35
 
 ; CHECK:      .globl  llvar
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: llvar:

llvm/test/CodeGen/PowerPC/aix-xcoff-lower-comm.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,ASM32 %s
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck --check-prefixes=CHECK,ASM64 %s
 
 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
 ; RUN: llvm-readobj -r --expand-relocs -t %t.o | FileCheck --check-prefixes=RELOC,SYM %s
 
 ; RUN: not --crash llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -filetype=obj < %s 2>&1 | \
 ; RUN: FileCheck --check-prefix=XCOFF64 %s
 ; XCOFF64: LLVM ERROR: 64-bit XCOFF object files are not supported yet.
 
 @common = common global i32 0, align 4
 @pointer = global i32* @common, align 4
 
 
 ; CHECK:             .comm   common[RW],4,2
-; ASM32-NEXT:        .csect .data[RW], 2
-; ASM64-NEXT:        .csect .data[RW], 3
+; ASM32-NEXT:        .csect .data[RW],2
+; ASM64-NEXT:        .csect .data[RW],3
 ; CHECK-NEXT:        .globl  pointer
 ; ASM32-NEXT:        .align  2
 ; ASM64-NEXT:        .align  3
 ; CHECK-NEXT:pointer:
 ; ASM32-NEXT:        .long   common[RW]
 ; ASM64-NEXT:        .llong   common[RW]
 
 

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-const.ll

 @__const.main.cnst4 = private unnamed_addr constant %struct.Merge_cnst4 { i16 16392, i8 0 }
 
 ; Function Attrs: noinline nounwind optnone
 define i32 @main() #0 {
 entry:
   ret i32 0
 }
 
-;CHECK:         .csect .rodata[RO], 4
+;CHECK:         .csect .rodata[RO],4
 ;CHECK-NEXT:         .align  4
 ;CHECK-NEXT: .L__const.main.cnst32:
 ;CHECK-NEXT:         .llong  4611686018427387954
 ;CHECK-NEXT:         .long   0                       # 0x0
 ;CHECK-NEXT:         .space  4
 ;CHECK-NEXT:         .llong  0
 ;CHECK-NEXT:         .long   0                       # 0x0
 ;CHECK-NEXT:         .space  4

llvm/test/CodeGen/PowerPC/aix-xcoff-mergeable-str.ll

 ; Function Attrs: noinline nounwind optnone
 define i8 @foo() #0 {
 entry:
   %0 = load i8*, i8** @p, align 4
   %1 = load i8, i8* %0, align 1
   ret i8 %1
 }
 
-; CHECK:   .csect .rodata.str2.2[RO], 2
+; CHECK:   .csect .rodata.str2.2[RO],2
 ; CHECK-NEXT:   .align  1
 ; CHECK-NEXT: .Lmagic16:
 ; CHECK-NEXT:   .short  264                     # 0x108
 ; CHECK-NEXT:   .short  272                     # 0x110
 ; CHECK-NEXT:   .short  213                     # 0xd5
 ; CHECK-NEXT:   .short  0                       # 0x0
-; CHECK-NEXT:   .csect .rodata.str4.4[RO], 2
+; CHECK-NEXT:   .csect .rodata.str4.4[RO],2
 ; CHECK-NEXT:   .align  2
 ; CHECK-NEXT: .Lmagic32:
 ; CHECK-NEXT:   .long   464                     # 0x1d0
 ; CHECK-NEXT:   .long   472                     # 0x1d8
 ; CHECK-NEXT:   .long   413                     # 0x19d
 ; CHECK-NEXT:   .long   0                       # 0x0
-; CHECK-NEXT:   .csect .rodata.str1.1[RO], 2
+; CHECK-NEXT:   .csect .rodata.str1.1[RO],2
 ; CHECK-NEXT: .LstrA:
 ; CHECK-NEXT: .byte   104
 ; CHECK-NEXT: .byte   101
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   108
 ; CHECK-NEXT: .byte   111
 ; CHECK-NEXT: .byte   32
 ; CHECK-NEXT: .byte   119

llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll

 @const_llvar = constant i64 36, align 8
 @const_svar = constant i16 37, align 2
 @const_fvar = constant float 8.000000e+02, align 4
 @const_dvar = constant double 9.000000e+02, align 8
 @const_over_aligned = constant double 9.000000e+02, align 32
 @const_chrarray = constant [4 x i8] c"abcd", align 1
 @const_dblarr = constant [4 x double] [double 1.000000e+00, double 2.000000e+00, double 3.000000e+00, double 4.000000e+00], align 8
 
-; CHECK:               .csect .rodata[RO], 5
+; CHECK:               .csect .rodata[RO],5
 ; CHECK-NEXT:          .globl  const_ivar
 ; CHECK-NEXT:          .align  2
 ; CHECK-NEXT:  const_ivar:
 ; CHECK-NEXT:          .long   35
 ; CHECK-NEXT:          .globl  const_llvar
 ; CHECK-NEXT:          .align  3
 ; CHECK-NEXT:  const_llvar:
 ; CHECK-NEXT:          .llong  36

llvm/test/CodeGen/PowerPC/test_func_desc.ll

 
 define internal i32 @static_foo() {
 entry:
   ret i32 3
 }
 
 ; CHECK: .globl foo[DS]
 ; CHECK: .globl .foo
-; 32BIT: .csect foo[DS], 2
+; 32BIT: .csect foo[DS],2
 ; 32BIT-NEXT: .long .foo
 ; 32BIT-NEXT: .long TOC[TC0]
 ; 32BIT-NEXT: .long 0
-; 64BIT: .csect foo[DS], 3
+; 64BIT: .csect foo[DS],3
 ; 64BIT-NEXT: .llong .foo
 ; 64BIT-NEXT: .llong TOC[TC0]
 ; 64BIT-NEXT: .llong 0
-; CHECK-NEXT: .csect .text[PR], 2
+; CHECK-NEXT: .csect .text[PR],2
 ; CHECK-LABEL: .foo:
 
 ; CHECK: .globl main[DS]
 ; CHECK: .globl .main
-; 32BIT: .csect main[DS], 2
+; 32BIT: .csect main[DS],2
 ; 32BIT-NEXT: .long .main
 ; 32BIT-NEXT: .long TOC[TC0]
 ; 32BIT-NEXT: .long 0
-; 64BIT: .csect main[DS], 3
+; 64BIT: .csect main[DS],3
 ; 64BIT-NEXT: .llong .main
 ; 64BIT-NEXT: .llong TOC[TC0]
 ; 64BIT-NEXT: .llong 0
-; CHECK-NEXT: .csect .text[PR], 2
+; CHECK-NEXT: .csect .text[PR],2
 ; CHECK-LABEL: .main:
 ; CHECK: bl .foo
 ; CHECK: bl .extern_foo
 ; CHECK: bl .static_foo
 
 ; CHECK: .lglobl .static_foo
-; 32BIT: .csect static_foo[DS], 2
+; 32BIT: .csect static_foo[DS],2
 ; 32BIT-NEXT: .long .static_foo
 ; 32BIT-NEXT: .long TOC[TC0]
 ; 32BIT-NEXT: .long 0
-; 64BIT: .csect static_foo[DS], 3
+; 64BIT: .csect static_foo[DS],3
 ; 64BIT-NEXT: .llong .static_foo
 ; 64BIT-NEXT: .llong TOC[TC0]
 ; 64BIT-NEXT: .llong 0
-; CHECK-NEXT: .csect .text[PR], 2
+; CHECK-NEXT: .csect .text[PR],2
 ; CHECK-LABEL: .static_foo:
 
 ; CHECK-NOT: .csect extern_foo
 
 ; CHECK: .toc
 ; CHECK-NOT: .tc