[AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO.

[alex-t]

Summary

This fixes the 5b898bddff51 bug when the carry-in and carry-out registers became lost in lowering S_ADD/SUB_CO_PSEUDO.

[arsenm]

Needs test

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

5183

I'm pretty sure there's a constrain to regclass helper that will do this for you

[arsenm]

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

5183

This should try MRI.constrainRegClass rather than enforcing class equality

[alex-t]

Explicit register class comparison changed to constrain reg class. Test added.

[arsenm]

llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir

5 ↗

(On Diff #265395)

Doesn't test for the copy? I would also probably just use update_mir_test_checks here

8 ↗

(On Diff #265395)

Better test name?

10 ↗

(On Diff #265395)

Should be able to drop the register section

[alex-t]

test reworked.

[alex-t]

ping

[alex-t]

Ping again. Could you please take a look?

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

while (!Worklist.empty()) {
     // S_ADD/SUB_CO_PSEUDO as well as S_UADDO/USUBO_PSEUDO
     // can only be selected from the uniform SDNode.
     case AMDGPU::S_ADD_CO_PSEUDO:
     case AMDGPU::S_SUB_CO_PSEUDO: {
       unsigned Opc = (Inst.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO)
                          ? AMDGPU::V_ADDC_U32_e64
                          : AMDGPU::V_SUBB_U32_e64;
       const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
-      Register DummyCReg = MRI.createVirtualRegister(CarryRC);
-      Register CarryReg = MRI.createVirtualRegister(CarryRC);
+
+      Register CarryInReg = Inst.getOperand(4).getReg();
+      const TargetRegisterClass *CarryInRC = MRI.getRegClass(CarryInReg);
+      if (CarryInRC != CarryRC) {
+        Register NewCarryReg = MRI.createVirtualRegister(CarryRC);
+        BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY), NewCarryReg)
+            .addReg(CarryInReg);
+      }
+
+      Register CarryOutReg = Inst.getOperand(1).getReg();
+
       Register DestReg = MRI.createVirtualRegister(RI.getEquivalentVGPRClass(
           MRI.getRegClass(Inst.getOperand(0).getReg())));
-      BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY), CarryReg)
-          .addReg(Inst.getOperand(4).getReg());
       MachineInstr *CarryOp =
           BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(Opc), DestReg)
-              .addReg(DummyCReg, RegState::Define | RegState::Dead)
+              .addReg(CarryOutReg, RegState::Define)
               .add(Inst.getOperand(2))
               .add(Inst.getOperand(3))
-              .addReg(CarryReg, RegState::Kill)
+              .addReg(CarryInReg)
               .addImm(0);
       legalizeOperands(*CarryOp);
       MRI.replaceRegWith(Inst.getOperand(0).getReg(), DestReg);
       addUsersToMoveToVALUWorklist(DestReg, MRI, Worklist);
       Inst.eraseFromParent();
     }
       continue;
     case AMDGPU::S_UADDO_PSEUDO: