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[X86] Fix a regression caused by moving combineLoopMAddPattern to IR

Authored by craig.topper on Wed, May 13, 2:31 PM.



When I moved combineLoopMAddPattern to an IR pass. I didn't match the behavior of canReduceVMulWidth that was used in the SelectionDAG version. canReduceVMulWidth just calls computeSignBits and assumes a truncate is always profitable. The version I put in IR just looks for constants and zext/sext. Though I neglected to check the number of bits in input of the zext/sext.

This patch adds a check for the number of input bits to the sext/zext. And it adds a special case for add/sub with zext/sext inputs which can be handled by combineTruncatedArithmetic. Match the original SelectionDAG behavior appears to be a regression in some cases if the truncate isn't removed and becomes pack and permq. So enabled only this specific case is the conservative approach.

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craig.topper created this revision.Wed, May 13, 2:31 PM
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RKSimon accepted this revision.Thu, May 14, 4:06 AM

LGTM - cheers

This revision is now accepted and ready to land.Thu, May 14, 4:06 AM
This revision was automatically updated to reflect the committed changes.