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Differential D79402

[ARM] Correct the type on a predicate cast
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Authored by dmgreen on May 5 2020, 2:09 AM.

Details

Reviewers
simon_tatham
SjoerdMeijer
samparker
ostannard
Commits
rGf85acb19158b: [ARM] Correct the type on a predicate cast
Summary

A PREDICATE_CAST(PREDICATE_CAST(X)) can be converted to a PREDICATE_CAST(X) as the operation can convert between any forms of predicates (v4i1/v8i1/v16i1/i32). Unfortunately I got the type wrong on one of the rarer converts, which would lead to invalid nodes during isel. This fixes it up to the correct type.

Diff Detail

Event Timeline

dmgreen created this revision.May 5 2020, 2:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 5 2020, 2:09 AM
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
dmgreen added reviewers: SjoerdMeijer, samparker, ostannard.May 5 2020, 2:09 AM
simon_tatham accepted this revision.May 5 2020, 2:54 AM
This revision is now accepted and ready to land.May 5 2020, 2:54 AM
Closed by commit rGf85acb19158b: [ARM] Correct the type on a predicate cast (authored by dmgreen). · Explain WhyMay 5 2020, 5:21 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
3 lines
test/
CodeGen/
Thumb2/
26 lines

Diff 262075

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 13,220 Lines • ▼ Show 20 LinesPerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
SDValue Op = N->getOperand(0); SDValue Op = N->getOperand(0);
SDLoc dl(N); SDLoc dl(N);
// PREDICATE_CAST(PREDICATE_CAST(x)) == PREDICATE_CAST(x) // PREDICATE_CAST(PREDICATE_CAST(x)) == PREDICATE_CAST(x)
if (Op->getOpcode() == ARMISD::PREDICATE_CAST) { if (Op->getOpcode() == ARMISD::PREDICATE_CAST) {
// If the valuetypes are the same, we can remove the cast entirely. // If the valuetypes are the same, we can remove the cast entirely.
if (Op->getOperand(0).getValueType() == VT) if (Op->getOperand(0).getValueType() == VT)
return Op->getOperand(0); return Op->getOperand(0);
return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
Op->getOperand(0).getValueType(), Op->getOperand(0));
} }
return SDValue(); return SDValue();
} }
static SDValue static SDValue
PerformVECTOR_REG_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, PerformVECTOR_REG_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
const ARMSubtarget *ST) { const ARMSubtarget *ST) {
▲ Show 20 Lines • Show All 4,992 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-pred-convert.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
define void @g(i8* %v) {
; CHECK-LABEL: g:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r0, #63
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vstrbt.8 q0, [r0]
; CHECK-NEXT: bx lr
entry:
%0 = load i8, i8* %v, align 1
%conv = zext i8 %0 to i32
%broadcast.splatinsert = insertelement <16 x i32> undef, i32 %conv, i32 0
%broadcast.splat = shufflevector <16 x i32> %broadcast.splatinsert, <16 x i32> undef, <16 x i32> zeroinitializer
%1 = and <16 x i32> %broadcast.splat, <i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64, i32 128, i32 256, i32 512, i32 1024, i32 2048, i32 4096, i32 8192, i32 16384, i32 32768>
%2 = icmp eq <16 x i32> %1, zeroinitializer
%3 = select <16 x i1> %2, <16 x i8> zeroinitializer, <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>
call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %3, <16 x i8>* undef, i32 1, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>)
ret void
}
; Function Attrs: argmemonly nounwind willreturn
declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>) #1