[PowerPC][AIX] Spill CSRs to the ABI specified stack offsets.

[sfertile]

Summary

Extend the CSR save/restore insertion code to AIX.

[sfertile]

Updated aix-calleesaved.ll test.

[sfertile]

ping.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

230

Is the extra CSR only applicable to 32BIT AIX? Eg. is X13 not a CSR in 64BIT AIX?

llvm/test/CodeGen/PowerPC/aix-csr.ll

177–183

What are the other tests in this file showing that this one doesn't? It seems to me this test makes at least the gprs_only test redundant.

[cebowleratibm]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

233–234

nit: remove blank line.

1835

Since we're enabling this path for AIX is there a LIT test that we should add an AIX variant for to validate this shrink-wrap functionality?

1999–2000

const or fold it into the use. This change is NFC and could be committed independently.

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

206

Why do we expect this change to bump the stack adj? I thought the cc tests don't touch non-volatile regs.

[cebowleratibm]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

230

https://www.ibm.com/support/knowledgecenter/en/ssw_aix_72/assembler/idalangref_reg_use_conv.html

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

230

Thanks, I was using Table 1 here as a reference: https://www.ibm.com/support/knowledgecenter/ssw_aix_72/assembler/idalangref_prologs_epilogs.html but I suppose the information there is for 32BIT only. Even though it's not specified.

[sfertile]

• Removed extra whitespace.
• Removed redundant testing (of fprs saves)

[sfertile]

rebased to pick up NFC commit.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

1835

Shrink-wrapping is only enabled for 64-bit ELF for now. I intend to enable it eventually, but not in this patch,

bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
  if (MF.getInfo<PPCFunctionInfo>()->shrinkWrapDisabled())
    return false;
  return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
          MF.getSubtarget<PPCSubtarget>().isPPC64());
}

I can add atest where we shrink wrap for ELF 64-bit and then check we don't shrink wrap for AIX if you want, but I didn't think it was necessary.

1999–2000

Good point, will update and commit separately.

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

206

Some of them do: For example in this test, we load the address of the global before the call to memcpy. This means the compiler has to use a non-volatile (r30) to keep the value live across the call. By saving r30 to its ABI specified offset, we increase the stack frame size by 4, and to keep the stack aligned the size has to grow by 16. It's similar case for the other tests that change.

llvm/test/CodeGen/PowerPC/aix-csr.ll

177–183

The gprs_only test shows that we calculate the offsets to gprs when he fpr save area is non-existent. The fpr only test is redundant though, I'll remove it.

[ZarkoCA]

LGMT, I will give some time for other reviewers to have a look before I approve.

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

231

nit: From what I've seen the TODO format is to do use a colon TODO:

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

: TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
       FramePointerSaveOffset(computeFramePointerSaveOffset(Subtarget)),
       LinkageSize(computeLinkageSize(Subtarget)),
       BasePointerSaveOffset(computeBasePointerSaveOffset(Subtarget)),
       CRSaveOffset(computeCRSaveOffset(Subtarget)) {}
 
 // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
 const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
     unsigned &NumEntries) const {
-  // Early exit if not using the SVR4 ABI.
-  if (!Subtarget.isSVR4ABI()) {
-    NumEntries = 0;
-    return nullptr;
-  }
 
 // Floating-point register save area offsets.
 #define CALLEE_SAVED_FPRS \
       {PPC::F31, -8},     \
       {PPC::F30, -16},    \
       {PPC::F29, -24},    \
       {PPC::F28, -32},    \
       {PPC::F27, -40},    \
       {PPC::F26, -48},    \
       {PPC::F25, -56},    \
       {PPC::F24, -64},    \
       {PPC::F23, -72},    \
       {PPC::F22, -80},    \
       {PPC::F21, -88},    \
       {PPC::F20, -96},    \
       {PPC::F19, -104},   \
       {PPC::F18, -112},   \
       {PPC::F17, -120},   \
       {PPC::F16, -128},   \
       {PPC::F15, -136},   \
       {PPC::F14, -144}
 
-// 32-bit general purpose register save area offsets.
+// 32-bit general purpose register save area offsets shared by ELF and
+// AIX. AIX has an extra CSR with r13.
 #define CALLEE_SAVED_GPRS32 \
       {PPC::R31, -4},       \
       {PPC::R30, -8},       \
       {PPC::R29, -12},      \
       {PPC::R28, -16},      \
       {PPC::R27, -20},      \
       {PPC::R26, -24},      \
       {PPC::R25, -28},      \
#define CALLEE_SAVED_VRS \
       {PPC::V23, -144},  \
       {PPC::V22, -160},  \
       {PPC::V21, -176},  \
       {PPC::V20, -192}
 
   // Note that the offsets here overlap, but this is fixed up in
   // processFunctionBeforeFrameFinalized.
 
-  static const SpillSlot Offsets[] = {
+  static const SpillSlot ELFOffsets32[] = {
       CALLEE_SAVED_FPRS,
       CALLEE_SAVED_GPRS32,
 
       // CR save area offset.  We map each of the nonvolatile CR fields
       // to the slot for CR2, which is the first of the nonvolatile CR
       // fields to be assigned, so that we only allocate one save slot.
       // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
       {PPC::CR2, -4},
static const SpillSlot ELFOffsets32[] = {
       {PPC::S20, -96},
       {PPC::S19, -104},
       {PPC::S18, -112},
       {PPC::S17, -120},
       {PPC::S16, -128},
       {PPC::S15, -136},
       {PPC::S14, -144}};
 
-  static const SpillSlot Offsets64[] = {
+  static const SpillSlot ELFOffsets64[] = {
       CALLEE_SAVED_FPRS,
       CALLEE_SAVED_GPRS64,
 
       // VRSAVE save area offset.
       {PPC::VRSAVE, -4},
-
       CALLEE_SAVED_VRS
   };
 
-  if (Subtarget.isPPC64()) {
-    NumEntries = array_lengthof(Offsets64);
+  static const SpillSlot AIXOffsets32[] = {
+    CALLEE_SAVED_FPRS,
+    CALLEE_SAVED_GPRS32,
+    // Add AIX's extra CSR.
+    {PPC::R13, -76},
+    // TODO Update when we add vector support for AIX.
+  };
 
-    return Offsets64;
-  } else {
-    NumEntries = array_lengthof(Offsets);
+  static const SpillSlot AIXOffsets64[] = {
+    CALLEE_SAVED_FPRS,
+    CALLEE_SAVED_GPRS64,
+    // TODO Update when we add vector support for AIX.
+  };
+
+  if (Subtarget.is64BitELFABI()) {
+    NumEntries = array_lengthof(ELFOffsets64);
+    return ELFOffsets64;
+  }
 
-    return Offsets;
+  if (Subtarget.is32BitELFABI()) {
+    NumEntries = array_lengthof(ELFOffsets32);
+    return ELFOffsets32;
   }
+
+  assert(Subtarget.isAIXABI() && "Unexpected ABI.");
+
+  if (Subtarget.isPPC64()) {
+    NumEntries = array_lengthof(AIXOffsets64);
+    return AIXOffsets64;
+  }
+
+  NumEntries = array_lengthof(AIXOffsets32);
+  return AIXOffsets32;
 }
 
 /// RemoveVRSaveCode - We have found that this function does not need any code
 /// to manipulate the VRSAVE register, even though it uses vector registers.
 /// This can happen when the only registers used are known to be live in or out
 /// of the function.  Remove all of the VRSAVE related code from the function.
 /// FIXME: The removal of the code results in a compile failure at -O0 when the
 /// function contains a function call, as the GPR containing original VRSAVE
int FrameIdx =
         MFI.CreateFixedObject(SpillSize, SpillOffset,
                               /* IsImmutable */ true, /* IsAliased */ false);
     FI->setCRSpillFrameIndex(FrameIdx);
   }
 }
 
 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
                                                        RegScavenger *RS) const {
-  // Early exit if not using the SVR4 ABI.
-  if (!Subtarget.isSVR4ABI()) {
-    addScavengingSpillSlot(MF, RS);
-    return;
-  }
-
   // Get callee saved register information.
   MachineFrameInfo &MFI = MF.getFrameInfo();
   const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
 
   // If the function is shrink-wrapped, and if the function has a tail call, the
   // tail call might not be in the new RestoreBlock, so real branch instruction
   // won't be generated by emitEpilogue(), because shrink-wrap has chosen new
   // RestoreBlock. So we handle this case here.
   if (MFI.getSavePoint() && MFI.hasTailCall()) {
     MachineBasicBlock *RestoreBlock = MFI.getRestorePoint();
     for (MachineBasicBlock &MBB : MF) {
       if (MBB.isReturnBlock() && (&MBB) != RestoreBlock)
         createTailCallBranchInstr(MBB);
     }
   }
 
   // Early exit if no callee saved registers are modified!
for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
         MFI.setObjectOffset(FI, LowerBound + MFI.getObjectOffset(FI));
       }
     }
 
     unsigned MinReg =
       std::min<unsigned>(TRI->getEncodingValue(MinGPR),
                          TRI->getEncodingValue(MinG8R));
 
-    if (Subtarget.isPPC64()) {
-      LowerBound -= (31 - MinReg + 1) * 8;
-    } else {
-      LowerBound -= (31 - MinReg + 1) * 4;
-    }
+    unsigned GPRegSize = Subtarget.isPPC64() ? 8 : 4;
+    LowerBound -= (31 - MinReg + 1) * GPRegSize;
   }
 
   // For 32-bit only, the CR save area is below the general register
   // save area.  For 64-bit SVR4, the CR save area is addressed relative
   // to the stack pointer and hence does not need an adjustment here.
   // Only CR2 (the first nonvolatile spilled) has an associated frame
   // index so that we have a single uniform save area.
   if (spillsCR(MF) && Subtarget.is32BitELFABI()) {

llvm/test/CodeGen/PowerPC/aix-calleesavedregs.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \
 ; RUN:  -mtriple powerpc-ibm-aix-xcoff -O0 < %s | \
 ; RUN: FileCheck --check-prefixes=CHECK %s
 
 define void @usethirteen() {
     call void asm "nop", "~{r13}"()
     ret void
 }
 
-; CHECK: stw 13, -4(1)
-; CHECK: lwz 13, -4(1)
+; CHECK: stw 13, -76(1)
+; CHECK: lwz 13, -76(1)

llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 152(1)
 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 156(1)
 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 160(1)
 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 164(1)
 ; ASM32PWR4:       bl .mix_floats
 
 ; ASM64PWR4:      mflr 0
 ; ASM64PWR4-DAG:  std 0, 16(1)
-; ASM64PWR4-DAG:  stdu 1, -240(1)
+; ASM64PWR4-DAG:  stdu 1, -256(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 112(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 120(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 128(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 136(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 144(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 152(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 160(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 168(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 176(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 184(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 192(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 200(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 208(1)
 ; ASM64PWR4-DAG:  std [[REG:[0-9]+]], 216(1)
 ; ASM64PWR4:      bl .mix_floats

llvm/test/CodeGen/PowerPC/aix-cc-byval-mem.ll

 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem3>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $f1, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 92, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_byval_mem3:
 
-; ASM32BIT:       stwu 1, -96(1)
+; ASM32BIT:       stwu 1, -112(1)
 ; ASM32BIT-DAG:   lwz [[REG:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   addi 3, 1, 56
 ; ASM32BIT-DAG:   addi 4, [[REG]], 24
 ; ASM32BIT-DAG:   li 5, 33
 ; ASM32BIT-NEXT:  bl .memcpy
 ; ASM32BIT-DAG:   lwz 5, 0([[REG]])
 ; ASM32BIT-DAG:   lwz 6, 4([[REG]])
 ; ASM32BIT-DAG:   lwz 7, 8([[REG]])
 ; ASM32BIT-DAG:   lwz 8, 12([[REG]])
 ; ASM32BIT-DAG:   lwz 9, 16([[REG]])
 ; ASM32BIT-DAG:   lwz 10, 20([[REG]])
 ; ASM32BIT:       bl .test_byval_mem3
-; ASM32BIT:       addi 1, 1, 96
+; ASM32BIT:       addi 1, 1, 112
 
 ; The memcpy call was inlined in 64-bit so MIR test is redundant and omitted.
 ; ASM64BIT:       stdu 1, -128(1)
 ; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], 48([[REG1]])
 ; ASM64BIT-DAG:   std [[REG2]], 112(1)
 ; ASM64BIT-DAG:   lbz [[REG3:[0-9]+]], 56([[REG1]])
 ; ASM64BIT-DAG:   stb [[REG3]], 120(1)

 ; 32BIT-DAG:      $r6 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r7 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r8 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r9 = COPY %{{[0-9]+}}
 ; 32BIT-DAG:      $r10 = COPY %{{[0-9]+}}
 ; 32BIT-NEXT:     BL_NOP <mcsymbol .test_byval_mem4>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r4, implicit $r5, implicit $r6, implicit $r7, implicit $r8, implicit $r9, implicit $r10, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT:     ADJCALLSTACKUP 316, 0, implicit-def dead $r1, implicit $r1
 
-; ASM32BIT:       stwu 1, -320(1)
+; ASM32BIT:       stwu 1, -336(1)
 ; ASM32BIT-NEXT:  stw [[REG1:[0-9]+]], {{[0-9]+}}(1)
 ; ASM32BIT:       lwz [[REG1]], LC{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   lhz [[REG2:[0-9]+]], 28([[REG1]])
 ; ASM32BIT-DAG:   sth [[REG2]], 56(1)
 ; ASM32BIT-DAG:   lbz [[REG3:[0-9]+]], 30([[REG1]])
 ; ASM32BIT-DAG:   stb [[REG3]], 58(1)
 ; ASM32BIT-DAG:   addi 3, 1, 60
 ; ASM32BIT-DAG:   lwz 4, LC{{[0-9]+}}(2)
 ; ASM32BIT-DAG:   li 5, 256
 ; ASM32BIT-NEXT:  bl .memcpy
 ; ASM32BIT-DAG:   lwz 4, 0([[REG1]])
 ; ASM32BIT-DAG:   lwz 5, 4([[REG1]])
 ; ASM32BIT-DAG:   lwz 6, 8([[REG1]])
 ; ASM32BIT-DAG:   lwz 7, 12([[REG1]])
 ; ASM32BIT-DAG:   lwz 8, 16([[REG1]])
 ; ASM32BIT-DAG:   lwz 9, 20([[REG1]])
 ; ASM32BIT-DAG:   lwz 10, 24([[REG1]])
 ; ASM32BIT:       bl .test_byval_mem4
-; ASM32BIT:       addi 1, 1, 320
+; ASM32BIT:       addi 1, 1, 336
 
 ; Confirm the expected memcpy call is independent of the call to test_byval_mem4.
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:     %0:g8rc_and_g8rc_nox0 = LDtoc @gS256, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:     %1:g8rc = nuw ADDI8 %0, 24
 ; 64BIT-NEXT:     %2:g8rc = nuw ADDI8 $x1, 112
 ; 64BIT-NEXT:     %3:g8rc = LI8 232
 ; 64BIT-DAG:      $x3 = COPY %2
 ; 64BIT-DAG:      $x4 = COPY %1
 ; 64BIT-DAG:      $x5 = COPY %3
 ; 64BIT-NEXT:     BL8_NOP <mcsymbol .memcpy>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT-NEXT:     ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT:          ADJCALLSTACKDOWN 344, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:      $x3 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x4 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x5 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x6 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x7 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x8 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x9 = COPY %{{[0-9]+}}
 ; 64BIT-DAG:      $x10 = COPY %{{[0-9]+}}
 ; 64BIT-NEXT:     BL8_NOP <mcsymbol .test_byval_mem4>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:     ADJCALLSTACKUP 344, 0, implicit-def dead $r1, implicit $r1
 
-; ASM64BIT:       stdu 1, -352(1)
+; ASM64BIT:       stdu 1, -368(1)
 ; ASM64BIT-DAG:   ld [[REG1:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   addi 3, 1, 112
 ; ASM64BIT-DAG:   addi 4, [[REG1]], 24
 ; ASM64BIT-DAG:   li 5, 232
 ; ASM64BIT-NEXT:  bl .memcpy
 ; ASM64BIT-DAG:   ld [[REG2:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64BIT-DAG:   ld 4, 0([[REG2]])
 ; ASM64BIT-DAG:   ld 5, 8([[REG2]])
 ; ASM64BIT-DAG:   ld 6, 16([[REG2]])
 ; ASM64BIT-DAG:   lwz [[REG3:[0-9]+]], 24([[REG2]])
 ; ASM64BIT-DAG:   lhz [[REG4:[0-9]+]], 28([[REG2]])
 ; ASM64BIT-DAG:   lbz 7, 30([[REG2]])
 ; ASM64BIT-DAG:   rlwinm 7, 7, 8, 16, 23
 ; ASM64BIT-DAG:   rlwimi 7, [[REG4]], 16, 0, 15
 ; ASM64BIT-DAG:   rldimi 7, [[REG3]], 32, 0
 ; ASM64BIT-DAG:   ld 8, 0([[REG1]])
 ; ASM64BIT-DAG:   ld 9, 8([[REG1]])
 ; ASM64BIT-DAG:   ld 10, 16([[REG1]])
 ; ASM64BIT:       bl .test_byval_mem4
-; ASM64BIT:       addi 1, 1, 352
+; ASM64BIT:       addi 1, 1, 368
 
 define void @test_byval_mem4(i32, %struct_S31* byval(%struct_S31) align 1, %struct_S256* byval(%struct_S256) align 1 %s) {
 entry:
   ret void
 }
 
 ; CHECK-LABEL:    name:            test_byval_mem4
 

llvm/test/CodeGen/PowerPC/aix-csr.ll

+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: FileCheck --check-prefix=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec < %s | FileCheck --check-prefix=ASM64 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec -stop-after=prologepilog < %s | \
+; RUN: FileCheck --check-prefix=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr4 -mattr=-altivec < %s | FileCheck --check-prefix=ASM32 %s
+
+define dso_local signext i32 @gprs_only(i32 signext %i) {
+entry:
+  call void asm sideeffect "", "~{r16},~{r22},~{r30}"()
+  ret i32 %i
+}
+
+; MIR64:       name:            gprs_only
+; MIR64-LABEL: fixedStack:
+; MIR64-NEXT:   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:       callee-saved-register: '$x30', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:       debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:   - { id: 1, type: spill-slot, offset: -80, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:       callee-saved-register: '$x22', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:       debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:   - { id: 2, type: spill-slot, offset: -128, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:       callee-saved-register: '$x16', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:       debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:  stack:           []
+
+; MIR32:       name:            gprs_only
+; MIR32-LABEL: fixedStack:
+; MIR32:        - { id: 0, type: spill-slot, offset: -8, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT:       callee-saved-register: '$r30', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:       debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:   - { id: 1, type: spill-slot, offset: -40, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT:       callee-saved-register: '$r22', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:       debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:   - { id: 2, type: spill-slot, offset: -64, size: 4, alignment: 16, stack-id: default,
+; MIR32-NEXT:       callee-saved-register: '$r16', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:       debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:  stack:           []
+
+
+; MIR64: liveins: $x3, $x16, $x22, $x30
+
+; MIR64-DAG: STD killed $x16, -128, $x1 :: (store 8 into %fixed-stack.2, align 16)
+; MIR64-DAG: STD killed $x22, -80, $x1 :: (store 8 into %fixed-stack.1, align 16)
+; MIR64-DAG: STD killed $x30, -16, $x1 :: (store 8 into %fixed-stack.0, align 16)
+
+; MIR64:     INLINEASM
+
+; MIR64-DAG: $x30 = LD -16, $x1 :: (load 8 from %fixed-stack.0, align 16)
+; MIR64-DAG: $x22 = LD -80, $x1 :: (load 8 from %fixed-stack.1, align 16)
+; MIR64-DAG: $x16 = LD -128, $x1 :: (load 8 from %fixed-stack.2, align 16)
+; MIR64:     BLR8 implicit $lr8, implicit $rm, implicit $x3
+
+
+; MIR32: liveins: $r3, $r16, $r22, $r30
+
+; MIR32-DAG: STW killed $r16, -64, $r1 :: (store 4 into %fixed-stack.2, align 16)
+; MIR32-DAG: STW killed $r22, -40, $r1 :: (store 4 into %fixed-stack.1, align 8)
+; MIR32-DAG: STW killed $r30, -8, $r1 :: (store 4 into %fixed-stack.0, align 8)
+
+; MIR32:     INLINEASM
+
+; MIR32-DAG: $r30 = LWZ -8, $r1 :: (load 4 from %fixed-stack.0, align 8)
+; MIR32-DAG: $r22 = LWZ -40, $r1 :: (load 4 from %fixed-stack.1, align 8)
+; MIR32-DAG: $r16 = LWZ -64, $r1 :: (load 4 from %fixed-stack.2, align 16)
+; MIR32:     BLR implicit $lr, implicit $rm, implicit $r3
+
+
+; ASM64-LABEL: .gprs_only:
+; ASM64-DAG:      std 16, -128(1)                 # 8-byte Folded Spill
+; ASM64-DAG:      std 22, -80(1)                  # 8-byte Folded Spill
+; ASM64-DAG:      std 30, -16(1)                  # 8-byte Folded Spill
+; ASM64:          #APP
+; ASM64-DAG:      ld 30, -16(1)                   # 8-byte Folded Reload
+; ASM64-DAG:      ld 22, -80(1)                   # 8-byte Folded Reload
+; ASM64-DAG:      ld 16, -128(1)                  # 8-byte Folded Reload
+; ASM64:          blr
+
+; ASM32-LABEl: .gprs_only:
+; ASM32-DAG:     stw 16, -64(1)                  # 4-byte Folded Spill
+; ASM32-DAG:     stw 22, -40(1)                  # 4-byte Folded Spill
+; ASM32-DAG:     stw 30, -8(1)                   # 4-byte Folded Spill
+; ASM32:         #APP
+; ASM32-DAG:     lwz 30, -8(1)                   # 4-byte Folded Reload
+; ASM32-DAG:     lwz 22, -40(1)                  # 4-byte Folded Reload
+; ASM32-DAG:     lwz 16, -64(1)                  # 4-byte Folded Reload
+; ASM32-DAG:     blr
+
+
+declare double @dummy(i32 signext);
+
+define dso_local double @fprs_and_gprs(i32 signext %i) {
+  call void asm sideeffect "", "~{r13},~{r14},~{r25},~{r31},~{f14},~{f19},~{f21},~{f31}"()
+  %result = call double @dummy(i32 signext %i)
+  ret double %result
+}
+
+; MIR64:       name:            fprs_and_gprs
+; MIR64-LABEL: fixedStack:
+; MIR64-NEXT:    - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 1, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 2, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 3, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 4, type: spill-slot, offset: -152, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x31', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 5, type: spill-slot, offset: -200, size: 8, alignment: 8, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x25', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:    - { id: 6, type: spill-slot, offset: -288, size: 8, alignment: 16, stack-id: default,
+; MIR64-NEXT:        callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
+; MIR64-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR64-NEXT:  stack:           []
+
+; MIR32:       name:            fprs_and_gprs
+; MIR32-LABEL: fixedStack:
+; MIR32-NEXT:    - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 1, type: spill-slot, offset: -88, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f21', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 2, type: spill-slot, offset: -104, size: 8, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f19', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 3, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$f14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 4, type: spill-slot, offset: -148, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r31', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 5, type: spill-slot, offset: -172, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r25', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 6, type: spill-slot, offset: -216, size: 4, alignment: 8, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:    - { id: 7, type: spill-slot, offset: -220, size: 4, alignment: 4, stack-id: default,
+; MIR32-NEXT:        callee-saved-register: '$r13', callee-saved-restored: true, debug-info-variable: '',
+; MIR32-NEXT:        debug-info-expression: '', debug-info-location: '' }
+; MIR32-NEXT:  stack:           []
+
+
+; MIR64: liveins: $x3, $x14, $x25, $x31, $f14, $f19, $f21, $f31
+
+; MIR64:       $x0 = MFLR8 implicit $lr8
+; MIR64-NEXT:  STD killed $x0, 16, $x1
+; MIR64-NEXT:  $x1 = STDU $x1, -400, $x1
+; MIR64-DAG:   STD killed $x14, 112, $x1 :: (store 8 into %fixed-stack.6, align 16)
+; MIR64-DAG:   STD killed $x25, 200, $x1 :: (store 8 into %fixed-stack.5)
+; MIR64-DAG:   STD killed $x31, 248, $x1 :: (store 8 into %fixed-stack.4)
+; MIR64-DAG:   STFD killed $f14, 256, $x1 :: (store 8 into %fixed-stack.3, align 16)
+; MIR64-DAG:   STFD killed $f19, 296, $x1 :: (store 8 into %fixed-stack.2)
+; MIR64-DAG:   STFD killed $f21, 312, $x1 :: (store 8 into %fixed-stack.1)
+; MIR64-DAG:   STFD killed $f31, 392, $x1 :: (store 8 into %fixed-stack.0)
+
+; MIR64:       INLINEASM
+; MIR64-NEXT:  BL8_NOP
+
+; MIR64-DAG:   $f31 = LFD 392, $x1 :: (load 8 from %fixed-stack.0)
+; MIR64-DAG:   $f21 = LFD 312, $x1 :: (load 8 from %fixed-stack.1)
+; MIR64-DAG:   $f19 = LFD 296, $x1 :: (load 8 from %fixed-stack.2)
+; MIR64-DAG:   $f14 = LFD 256, $x1 :: (load 8 from %fixed-stack.3, align 16)
+; MIR64-DAG:   $x31 = LD 248, $x1 :: (load 8 from %fixed-stack.4)
+; MIR64-DAG:   $x25 = LD 200, $x1 :: (load 8 from %fixed-stack.5)
+; MIR64-DAG:   $x14 = LD 112, $x1 :: (load 8 from %fixed-stack.6, align 16)
+; MIR64:       $x1 = ADDI8 $x1, 400
+; MIR64-NEXT:  $x0 = LD 16, $x1
+; MIR64-NEXT:  MTLR8 $x0, implicit-def $lr8
+; MIR64-NEXT:  BLR8 implicit $lr8, implicit $rm, implicit $f1
+
+
+; MIR32: liveins: $r3, $r13, $r14, $r25, $r31, $f14, $f19, $f21, $f31
+
+; MIR32:      $r0 = MFLR implicit $lr
+; MIR32-NEXT: STW killed $r0, 8, $r1
+; MIR32-NEXT: $r1 = STWU $r1, -288, $r1
+; MIR32-DAG:  STW killed $r13, 68, $r1 :: (store 4 into %fixed-stack.7)
+; MIR32-DAG:  STW killed $r14, 72, $r1 :: (store 4 into %fixed-stack.6, align 8)
+; MIR32-DAG:  STW killed $r25, 116, $r1 :: (store 4 into %fixed-stack.5)
+; MIR32-DAG:  STW killed $r31, 140, $r1 :: (store 4 into %fixed-stack.4)
+; MIR32-DAG:  STFD killed $f14, 144, $r1 :: (store 8 into %fixed-stack.3, align 16)
+; MIR32-DAG:  STFD killed $f19, 184, $r1 :: (store 8 into %fixed-stack.2)
+; MIR32-DAG:  STFD killed $f21, 200, $r1 :: (store 8 into %fixed-stack.1)
+; MIR32-DAG:  STFD killed $f31, 280, $r1 :: (store 8 into %fixed-stack.0)
+
+; MIR32:      INLINEASM
+; MIR32:      BL_NOP
+
+; MIR32-DAG:  $f31 = LFD 280, $r1 :: (load 8 from %fixed-stack.0)
+; MIR32-DAG:  $f21 = LFD 200, $r1 :: (load 8 from %fixed-stack.1)
+; MIR32-DAG:  $f19 = LFD 184, $r1 :: (load 8 from %fixed-stack.2)
+; MIR32-DAG:  $f14 = LFD 144, $r1 :: (load 8 from %fixed-stack.3, align 16)
+; MIR32-DAG:  $r31 = LWZ 140, $r1 :: (load 4 from %fixed-stack.4)
+; MIR32-DAG:  $r25 = LWZ 116, $r1 :: (load 4 from %fixed-stack.5)
+; MIR32-DAG:  $r14 = LWZ 72, $r1 :: (load 4 from %fixed-stack.6, align 8)
+; MIR32-DAG:  $r13 = LWZ 68, $r1 :: (load 4 from %fixed-stack.7)
+; MIR32:      $r1 = ADDI $r1, 288
+; MIR32-NEXT: $r0 = LWZ 8, $r1
+; MIR32-NEXT: MTLR $r0, implicit-def $lr
+; MIR32-NEXT: BLR implicit $lr, implicit $rm, implicit $f1
+
+; ASM64-LABEL: .fprs_and_gprs:
+; ASM64:         mflr 0
+; ASM64-NEXT:    std 0, 16(1)
+; ASM64-NEXT:    stdu 1, -400(1)
+; ASM64-DAG:     std 14, 112(1)                  # 8-byte Folded Spill
+; ASM64-DAG:     std 25, 200(1)                  # 8-byte Folded Spill
+; ASM64-DAG:     std 31, 248(1)                  # 8-byte Folded Spill
+; ASM64-DAG:     stfd 14, 256(1)                 # 8-byte Folded Spill
+; ASM64-DAG:     stfd 19, 296(1)                 # 8-byte Folded Spill
+; ASM64-DAG:     stfd 21, 312(1)                 # 8-byte Folded Spill
+; ASM64-DAG:     stfd 31, 392(1)                 # 8-byte Folded Spill
+
+; ASM64:         bl .dummy
+
+; ASM64-DAG:     lfd 31, 392(1)                  # 8-byte Folded Reload
+; ASM64-DAG:     lfd 21, 312(1)                  # 8-byte Folded Reload
+; ASM64-DAG:     lfd 19, 296(1)                  # 8-byte Folded Reload
+; ASM64-DAG:     lfd 14, 256(1)                  # 8-byte Folded Reload
+; ASM64-DAG:     ld 31, 248(1)                   # 8-byte Folded Reload
+; ASM64-DAG:     ld 25, 200(1)                   # 8-byte Folded Reload
+; ASM64-DAG:     ld 14, 112(1)                   # 8-byte Folded Reload
+; ASM64:         addi 1, 1, 400
+; ASM64-NEXT:    ld 0, 16(1)
+; ASM64-NEXT:    mtlr 0
+; ASM64-NEXT:    blr
+
+; ASM32-LABEL: .fprs_and_gprs:
+; ASM32:         mflr 0
+; ASM32-NEXT:    stw 0, 8(1)
+; ASM32-NEXT:    stwu 1, -288(1)
+; ASM32-DAG:     stw 13, 68(1)                   # 4-byte Folded Spill
+; ASM32-DAG:     stw 14, 72(1)                   # 4-byte Folded Spill
+; ASM32-DAG:     stw 25, 116(1)                  # 4-byte Folded Spill
+; ASM32-DAG:     stw 31, 140(1)                  # 4-byte Folded Spill
+; ASM32-DAG:     stfd 14, 144(1)                 # 8-byte Folded Spill
+; ASM32-DAG:     stfd 19, 184(1)                 # 8-byte Folded Spill
+; ASM32-DAG:     stfd 21, 200(1)                 # 8-byte Folded Spill
+; ASM32-DAG:     stfd 31, 280(1)                 # 8-byte Folded Spill
+
+; ASM32-DAG:     bl .dummy
+
+; ASM32-DAG:     lfd 31, 280(1)                  # 8-byte Folded Reload
+; ASM32-DAG:     lfd 21, 200(1)                  # 8-byte Folded Reload
+; ASM32-DAG:     lfd 19, 184(1)                  # 8-byte Folded Reload
+; ASM32-DAG:     lfd 14, 144(1)                  # 8-byte Folded Reload
+; ASM32-DAG:     lwz 31, 140(1)                  # 4-byte Folded Reload
+; ASM32-DAG:     lwz 25, 116(1)                  # 4-byte Folded Reload
+; ASM32-DAG:     lwz 14, 72(1)                   # 4-byte Folded Reload
+; ASM32-DAG:     lwz 13, 68(1)                   # 4-byte Folded Reload
+; ASM32:         addi 1, 1, 288
+; ASM32-NEXT:    lwz 0, 8(1)
+; ASM32-NEXT:    mtlr 0
+; ASM32-NEXT:    blr

llvm/test/CodeGen/PowerPC/aix32-crsave.mir

body:             |
   bb.0.entry:
     liveins: $r3
     renamable $r29 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
     renamable $cr2lt = COPY $cr0gt
     renamable $cr4lt = COPY $cr0gt
     renamable $r3 = COPY $r29
     BLR implicit $lr, implicit $rm, implicit $r3
 
-    ; CHECK-LABEL: fixedStack:
-    ; CHECK:       - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
-    ; CHECK-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
-    ; CHECK-NEXT:      callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
-    ; CHECK-NEXT:      debug-info-location: '' }
-    ; CHECK-LABEL: stack:
+    ; CHECK-LABEL:  fixedStack:
+    ; CHECK-NEXT:   - { id: 0, type: spill-slot, offset: -12, size: 4, alignment: 4, stack-id: default,
+    ; CHECK-NEXT:       callee-saved-register: '$r29', callee-saved-restored: true, debug-info-variable: '',
+    ; CHECK-NEXT:       debug-info-expression: '', debug-info-location: '' }
+    ; CHECK-NEXT:   - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
+    ; CHECK-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
+    ; CHECK-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+    ; CHECK-NEXT:       debug-info-location: '' }
+    ; CHECK-LABEL:  stack:
 
     ; CHECK:      bb.0.entry:
     ; CHECK-NEXT:  liveins: $r3, $r29, $cr2, $cr4
 
     ; CHECK:      $r12 = MFCR implicit killed $cr2, implicit killed $cr4
     ; CHECK-NEXT: STW killed $r12, 4, $r1
+    ; CHECK-NEXT: STW killed $r29, -12, $r1 :: (store 4 into %fixed-stack.0)
 
-    ; CHECK:      $r12 = LWZ 4, $r1
+    ; CHECK:      $r29 = LWZ -12, $r1 :: (load 4 from %fixed-stack.0)
+    ; CHECK-NEXT: $r12 = LWZ 4, $r1
     ; CHECK-NEXT: $cr2 = MTOCRF $r12
     ; CHECK-NEXT: $cr4 = MTOCRF killed $r12
 
 ...
 ---
 name:            CR3Save
 alignment:       16
 tracksRegLiveness: true
 liveins:
   - { reg: '$r3', virtual-reg: '' }
 body:             |
   bb.0.entry:
     liveins: $r3
     renamable $r14 = ANDI_rec killed renamable $r3, 1, implicit-def dead $cr0, implicit-def $cr0gt
     renamable $cr3lt = COPY $cr0gt
     renamable $r3 = COPY $r14
     BLR implicit $lr, implicit $rm, implicit $r3
 
     ; CHECK-LABEL: fixedStack:
-    ; CHECK:       - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
+    ; CHECK-NEXT:  - { id: 0, type: spill-slot, offset: -72, size: 4, alignment: 8, stack-id: default,
+    ; CHECK-NEXT:      callee-saved-register: '$r14', callee-saved-restored: true, debug-info-variable: '',
+    ; CHECK-NEXT:      debug-info-expression: '', debug-info-location: '' }
+    ; CHECK-NEXT:  - { id: 1, type: default, offset: 4, size: 4, alignment: 4, stack-id: default,
     ; CHECK-NEXT:      isImmutable: true, isAliased: false, callee-saved-register: '$cr3',
     ; CHECK-NEXT:      callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
     ; CHECK-NEXT:      debug-info-location: '' }
     ; CHECK-LABEL: stack:
 
     ; CHECK:      bb.0.entry:
     ; CHECK-NEXT:   liveins: $r3, $r14, $cr3
 
     ; CHECK:      $r12 = MFCR implicit killed $cr3
     ; CHECK-NEXT: STW killed $r12, 4, $r1
+    ; CHECK-NEXT: STW killed $r14, -72, $r1 :: (store 4 into %fixed-stack.0, align 8)
 
-    ; CHECK:      $r12 = LWZ 4, $r1
+    ; CHECK:      $r14 = LWZ -72, $r1 :: (load 4 from %fixed-stack.0, align 8)
+    ; CHECK-NEXT: $r12 = LWZ 4, $r1
     ; CHECK-NEXT: $cr3 = MTOCRF killed $r12

llvm/test/CodeGen/PowerPC/ppc64-crsave.mir

 # RUN: llc -mtriple powerpc64le-unknown-linux-gnu -x mir -mcpu=pwr8 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE,ELF
+# RUN: FileCheck %s --check-prefixes=CHECK,SAVEONE
 
 # RUN: llc -mtriple powerpc64-unknown-linux-gnu -x mir -mcpu=pwr7 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
-# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL,ELF
+# RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
 
 # RUN: llc -mtriple powerpc64-unknown-aix-xcoff -x mir -mcpu=pwr4 \
 # RUN: -run-pass=prologepilog --verify-machineinstrs < %s | \
 # RUN: FileCheck %s --check-prefixes=CHECK,SAVEALL
 
-# TODO FIXME: We only check the save and restores of the callee saved gpr for
-# ELF becuase AIX callee saved registers haven't been properly implemented yet.
-
 ---
 name:            CRAllSave
 alignment:       16
 tracksRegLiveness: true
 liveins:
   - { reg: '$x3', virtual-reg: '' }
 body:             |
   bb.0.entry:
     liveins: $x3
     renamable $x29 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
     renamable $cr2lt = COPY $cr0gt
     renamable $cr4lt = COPY $cr0gt
     renamable $x3 = COPY $x29
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
     ; CHECK-LABEL: fixedStack:
-    ; ELF:          - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
-    ; AIX:          - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
-    ; CHECK:            isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
-    ; CHECK-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
-    ; CHECK-NEXT:       debug-info-location: '' }
+    ; CHECK-NEXT:     - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: default,
+    ; CHECK-NEXT:         callee-saved-register: '$x29', callee-saved-restored: true, debug-info-variable: '',
+    ; CHECK-NEXT:         debug-info-expression: '', debug-info-location: '' }
+    ; CHECK-NEXT:     - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+    ; CHECK-NEXT:         isImmutable: true, isAliased: false, callee-saved-register: '$cr4',
+    ; CHECK-NEXT:         callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
+    ; CHECK-NEXT:         debug-info-location: '' }
     ; CHECK-LABEL:  stack:
 
     ; Verify the proper live-ins have been added in the prologue.
     ; CHECK:    liveins: $x3, $x29, $cr2, $cr4
 
     ; CHECK:     $x12 = MFCR8 implicit killed $cr2, implicit killed $cr4
-    ; ELF-DAG:   STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.0)
+    ; CHECK-DAG: STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.0)
     ; CHECK-DAG: STW8 killed $x12, 8, $x1
 
-    ; ELF:       $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.0)
+    ; CHECK:     $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.0)
     ; CHECK:     $x12 = LWZ8 8, $x1
     ; CHECK:     $cr2 = MTOCRF8 $x12
     ; CHECK:     $cr4 = MTOCRF8 killed $x12
 
 ...
 ---
 name:            CR2Save
 alignment:       16
 tracksRegLiveness: true
 liveins:
   - { reg: '$x3', virtual-reg: '' }
 body:             |
   bb.0.entry:
     liveins: $x3
     renamable $x14 = ANDI8_rec killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt
     renamable $cr2lt = COPY $cr0gt
     renamable $x3 = COPY $x14
     BLR8 implicit $lr8, implicit $rm, implicit $x3
 
     ; CHECK-LABEL: CR2Save
 
     ; CHECK-LABEL: fixedStack:
-    ; ELF:          - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
-    ; AIX:          - { id: 0, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
-    ; CHECK:            isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
+    ; CHECK-NEXT:   - { id: 0, type: spill-slot, offset: -144, size: 8, alignment: 16, stack-id: default,
+    ; CHECK-NEXT:       callee-saved-register: '$x14', callee-saved-restored: true, debug-info-variable: '',
+    ; CHECK-NEXT:       debug-info-expression: '', debug-info-location: '' }
+    ; CHECK-NEXT:   - { id: 1, type: default, offset: 8, size: 4, alignment: 8, stack-id: default,
+    ; CHECK-NEXT:       isImmutable: true, isAliased: false, callee-saved-register: '$cr2',
     ; CHECK-NEXT:       callee-saved-restored: true, debug-info-variable: '', debug-info-expression: '',
     ; CHECK-NEXT:       debug-info-location: '' }
     ; CHECK-LABEL:  stack:
 
     ; Verify the proper live-ins have been added in the prologue.
     ; CHECK:    liveins: $x3, $x14, $cr2
 
     ; ELF V2 ABI allows saving only the clobbered cr fields,
     ; whereas the other ABIs do not.
     ; SAVEONE:     $x12 = MFOCRF8 killed $cr2
     ; SAVEALL:     $x12 = MFCR8 implicit killed $cr2
 
-    ; ELF-DAG:   STD killed $x14, -144, $x1 :: (store 8 into %fixed-stack.0, align 16)
+    ; CHECK-DAG: STD killed $x14, -144, $x1 :: (store 8 into %fixed-stack.0, align 16)
     ; CHECK-DAG: STW8 killed $x12, 8, $x1
 
-    ; ELF:       $x14 = LD -144, $x1 :: (load 8 from %fixed-stack.0, align 16)
+    ; CHECK:     $x14 = LD -144, $x1 :: (load 8 from %fixed-stack.0, align 16)
     ; CHECK:     $x12 = LWZ8 8, $x1
     ; CHECK:     $cr2 = MTOCRF8 killed $x12
 
 
 ...