[RISCV] Add patterns for checking isnan

[lenary]

Summary

This patch addresses some weird assembly sequences we were seeing during
comparing floats. In particular, comparing a float to itself tells you whether
it is NaN or not, which we were doing correctly, but with an extra unneeded
and instruction.

This patch specialises the existing patterns to remove the and instruction
when both their operands are the same.

[asb]

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

316

I think this pattern and the matching one in RISCVInstrInfoF.td is left untested?

[lenary]

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

316

This pattern is what is tested by fcmp uno {float,double} %0, 0.000000e+00. The sltiu is shown in the assembly output as seqz.

[asb]

LGTM, thanks!

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

316

Doh - thanks!

[luismarques]

LGTM

[lenary]

Updates based on test changes (to use hardfloat ABIs).

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

 
 // Define pattern expansions for setcc operations which aren't directly
 // handled by a RISC-V instruction and aren't expanded in the SelectionDAG
 // Legalizer.
 
 def : Pat<(seto FPR64:$rs1, FPR64:$rs2),
           (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
                (FEQ_D FPR64:$rs2, FPR64:$rs2))>;
+def : Pat<(seto FPR64:$rs1, FPR64:$rs1),
+          (FEQ_D $rs1, $rs1)>;
 
 def : Pat<(setuo FPR64:$rs1, FPR64:$rs2),
           (SLTIU (AND (FEQ_D FPR64:$rs1, FPR64:$rs1),
                       (FEQ_D FPR64:$rs2, FPR64:$rs2)),
                  1)>;
+def : Pat<(setuo FPR64:$rs1, FPR64:$rs1),
+          (SLTIU (FEQ_D $rs1, $rs1), 1)>;
 
 def Select_FPR64_Using_CC_GPR : SelectCC_rrirr<FPR64, GPR>;
 
 /// Loads
 
 defm : LdPat<load, FLD>;
 
 /// Stores

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

 
 // Define pattern expansions for setcc operations which aren't directly
 // handled by a RISC-V instruction and aren't expanded in the SelectionDAG
 // Legalizer.
 
 def : Pat<(seto FPR32:$rs1, FPR32:$rs2),
           (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
                (FEQ_S FPR32:$rs2, FPR32:$rs2))>;
+def : Pat<(seto FPR32:$rs1, FPR32:$rs1),
+          (FEQ_S $rs1, $rs1)>;
 
 def : Pat<(setuo FPR32:$rs1, FPR32:$rs2),
           (SLTIU (AND (FEQ_S FPR32:$rs1, FPR32:$rs1),
                       (FEQ_S FPR32:$rs2, FPR32:$rs2)),
                  1)>;
+def : Pat<(setuo FPR32:$rs1, FPR32:$rs1),
+          (SLTIU (FEQ_S $rs1, $rs1), 1)>;
 
 def Select_FPR32_Using_CC_GPR : SelectCC_rrirr<FPR32, GPR>;
 
 /// Loads
 
 defm : LdPat<load, FLW>;
 
 /// Stores

llvm/test/CodeGen/RISCV/double-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64IFD %s
 
 define zeroext i1 @double_is_nan(double %a) nounwind {
 ; RV32IFD-LABEL: double_is_nan:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    and a0, a0, a0
 ; RV32IFD-NEXT:    seqz a0, a0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: double_is_nan:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    and a0, a0, a0
 ; RV64IFD-NEXT:    seqz a0, a0
 ; RV64IFD-NEXT:    ret
   %1 = fcmp uno double %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @double_not_nan(double %a) nounwind {
 ; RV32IFD-LABEL: double_not_nan:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    feq.d a0, fa0, fa0
-; RV32IFD-NEXT:    and a0, a0, a0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: double_not_nan:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    feq.d a0, fa0, fa0
-; RV64IFD-NEXT:    and a0, a0, a0
 ; RV64IFD-NEXT:    ret
   %1 = fcmp ord double %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/float-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64IF %s
 
 define zeroext i1 @float_is_nan(float %a) nounwind {
 ; RV32IF-LABEL: float_is_nan:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    and a0, a0, a0
 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_is_nan:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    and a0, a0, a0
 ; RV64IF-NEXT:    seqz a0, a0
 ; RV64IF-NEXT:    ret
   %1 = fcmp uno float %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @float_not_nan(float %a) nounwind {
 ; RV32IF-LABEL: float_not_nan:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    feq.s a0, fa0, fa0
-; RV32IF-NEXT:    and a0, a0, a0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: float_not_nan:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    feq.s a0, fa0, fa0
-; RV64IF-NEXT:    and a0, a0, a0
 ; RV64IF-NEXT:    ret
   %1 = fcmp ord float %a, 0.000000e+00
   ret i1 %1
 }