[RISCV][NFC] Add tests for checking isnan patterns

[lenary]

Summary

I worked on adding some SelectionDag patterns to address code generated by these
examples, which came out of some differential testing against GCC. The pattern
additions will be in a follow-up patch.

[asb]

LGTM. Minor nit: using %0 and %2 as the only two named values seems odd though? Most other tests in test/CodeGen/RISCV use a/b/... for arguments and %0/%1/%2/... in the body.

[lenary]

In D78907#2012344, @asb wrote:

LGTM. Minor nit: using %0 and %2 as the only two named values seems odd though? Most other tests in test/CodeGen/RISCV use a/b/... for arguments and %0/%1/%2/... in the body.

I generated the testcases in Clang (actually using godbolt, but it's doing the same IR lowering as clang HEAD is), which is why the arguments don't have names. I can re-introduce them if that's easier.

[asb]

In D78907#2012362, @lenary wrote:

In D78907#2012344, @asb wrote:

LGTM. Minor nit: using %0 and %2 as the only two named values seems odd though? Most other tests in test/CodeGen/RISCV use a/b/... for arguments and %0/%1/%2/... in the body.

I generated the testcases in Clang (actually using godbolt, but it's doing the same IR lowering as clang HEAD is), which is why the arguments don't have names. I can re-introduce them if that's easier.

It's not the biggest deal in the world, but the following would better match conventions elsewhere in the dir (whether those conventions are sensible or not is another discussion of course!):

define zeroext i1 @float_not_nan(float %a) nounwind {
  %1 = fcmp ord float %a, 0.000000e+00
  ret i1 %1
}

[lenary]

Address feedback on test contents.

[luismarques]

LGTM. I would prefer a hardfloat ABI to make the test slightly cleaner.

[lenary]

Update tests to use hard float ABIs

llvm/test/CodeGen/RISCV/double-isnan.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV32IFD %s
+; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi lp64d -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV64IFD %s
+
+define zeroext i1 @double_is_nan(double %a) nounwind {
+; RV32IFD-LABEL: double_is_nan:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    feq.d a0, fa0, fa0
+; RV32IFD-NEXT:    and a0, a0, a0
+; RV32IFD-NEXT:    seqz a0, a0
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: double_is_nan:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    feq.d a0, fa0, fa0
+; RV64IFD-NEXT:    and a0, a0, a0
+; RV64IFD-NEXT:    seqz a0, a0
+; RV64IFD-NEXT:    ret
+  %1 = fcmp uno double %a, 0.000000e+00
+  ret i1 %1
+}
+
+define zeroext i1 @double_not_nan(double %a) nounwind {
+; RV32IFD-LABEL: double_not_nan:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    feq.d a0, fa0, fa0
+; RV32IFD-NEXT:    and a0, a0, a0
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: double_not_nan:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    feq.d a0, fa0, fa0
+; RV64IFD-NEXT:    and a0, a0, a0
+; RV64IFD-NEXT:    ret
+  %1 = fcmp ord double %a, 0.000000e+00
+  ret i1 %1
+}

llvm/test/CodeGen/RISCV/float-isnan.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV64IF %s
+
+define zeroext i1 @float_is_nan(float %a) nounwind {
+; RV32IF-LABEL: float_is_nan:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    feq.s a0, fa0, fa0
+; RV32IF-NEXT:    and a0, a0, a0
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: float_is_nan:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    feq.s a0, fa0, fa0
+; RV64IF-NEXT:    and a0, a0, a0
+; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    ret
+  %1 = fcmp uno float %a, 0.000000e+00
+  ret i1 %1
+}
+
+define zeroext i1 @float_not_nan(float %a) nounwind {
+; RV32IF-LABEL: float_not_nan:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    feq.s a0, fa0, fa0
+; RV32IF-NEXT:    and a0, a0, a0
+; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: float_not_nan:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    feq.s a0, fa0, fa0
+; RV64IF-NEXT:    and a0, a0, a0
+; RV64IF-NEXT:    ret
+  %1 = fcmp ord float %a, 0.000000e+00
+  ret i1 %1
+}