[RISCV] Add patterns for indirect float conversions

[lenary]

Summary

This addresses some weird assembly sequences seen during float conversion
involving casts via double. In particular, the fcvt instructions should, if
GCC and I are not mistaken, compose together based on suffix/prefix, as shown in
the test.

The patterns are added for the F extension because they only need F-extension
instructions, but the tests only apply if you have enabled the D extension
because without it, the legaliser will turn the conversions into libcalls which
cannot be matched on in the same way. Maybe this is really a job for the
DAGCombiner?

[lenary]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

397–404

These patterns were duplicated in this file, which seems incorrect.

[asb]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

397–404

Looks like a likely holdover of some rebasing. I agree, these patterns can be deleted. Please do land that NFC change directly.

[lenary]

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

397–404

Landed directly in rG09f6b9792bc.

[lenary]

Rebased onto rG09f6b9792bcdaa057d23caa62eb38265a3f1a668 and changes in D78905.

llvm/lib/Target/RISCV/RISCVInstrInfoF.td

 let Predicates = [HasStdExtF, IsRV32] in {
 // float->[u]int. Round-to-zero must be used.
 def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
 
 // [u]int->float. Match GCC and default to using dynamic rounding mode.
 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
-} // Predicates = [HasStdExtF, IsRV32]
-
-let Predicates = [HasStdExtF, IsRV32] in {
-// FP->[u]int. Round-to-zero must be used
-def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
-def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
 
-// [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
-def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_WU $rs1, 0b111)>;
+// [u]int->double->float
+def : Pat<(fpround (f64 (sint_to_fp GPR:$rs1))),
+          (FCVT_S_W GPR:$rs1, 0b111)>;
+def : Pat<(fpround (f64 (uint_to_fp GPR:$rs1))),
+          (FCVT_S_WU GPR:$rs1, 0b111)>;
 } // Predicates = [HasStdExtF, IsRV32]
 
 let Predicates = [HasStdExtF, IsRV64] in {
 def : Pat<(riscv_fmv_w_x_rv64 GPR:$src), (FMV_W_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyextw_rv64 FPR32:$src), (FMV_X_W FPR32:$src)>;
 def : Pat<(sexti32 (riscv_fmv_x_anyextw_rv64 FPR32:$src)),
           (FMV_X_W FPR32:$src)>;
 
 // FP->[u]int32 is mostly handled by the FP->[u]int64 patterns. This is safe
 // because fpto[u|s]i produces poison if the value can't fit into the target.
 // We match the single case below because fcvt.wu.s sign-extends its result so
 // is cheaper than fcvt.lu.s+sext.w.
 def : Pat<(sext_inreg (assertzexti32 (fp_to_uint FPR32:$rs1)), i32),
           (FCVT_WU_S $rs1, 0b001)>;
 
 // FP->[u]int64
 def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_L_S $rs1, 0b001)>;
 def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_LU_S $rs1, 0b001)>;
 
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
 def : Pat<(sint_to_fp (sext_inreg GPR:$rs1, i32)), (FCVT_S_W $rs1, 0b111)>;
 def : Pat<(uint_to_fp (zexti32 GPR:$rs1)), (FCVT_S_WU $rs1, 0b111)>;
 def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_L $rs1, 0b111)>;
 def : Pat<(uint_to_fp GPR:$rs1), (FCVT_S_LU $rs1, 0b111)>;
+
+// [u]int->double->float
+def : Pat<(fpround (f64 (sint_to_fp (sext_inreg GPR:$rs1, i32)))),
+          (FCVT_S_W GPR:$rs1, 0b111)>;
+def : Pat<(fpround (f64 (uint_to_fp (zexti32 GPR:$rs1)))),
+          (FCVT_S_WU GPR:$rs1, 0b111)>;
+
 } // Predicates = [HasStdExtF, IsRV64]

llvm/test/CodeGen/RISCV/double-convert-indirect.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IFD %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IFD %s
 
 ;; These testcases check that we merge sequences of `fcvt.d.wu; fcvt.s.d` into
 ;; `fcvt.s.wu`.
 ;;
 ;; TODO: Unfortunately, though this only uses 32-bit FP instructions, we cannot
 ;; do this optimisation without the D extension as we need 64-bit FP values to
 ;; be legal to get the right operands to match.
 
 define float @fcvt_s_w_via_d(i32 %0) nounwind {
 ; RV32IFD-LABEL: fcvt_s_w_via_d:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.w ft0, a0
-; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV32IFD-NEXT:    fcvt.s.w ft0, a0
 ; RV32IFD-NEXT:    fmv.x.w a0, ft0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_s_w_via_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.w ft0, a0
-; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV64IFD-NEXT:    fcvt.s.w ft0, a0
 ; RV64IFD-NEXT:    fmv.x.w a0, ft0
 ; RV64IFD-NEXT:    ret
   %2 = sitofp i32 %0 to double
   %3 = fptrunc double %2 to float
   ret float %3
 }
 
 define float @fcvt_s_wu_via_d(i32 %0) nounwind {
 ; RV32IFD-LABEL: fcvt_s_wu_via_d:
 ; RV32IFD:       # %bb.0:
-; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
-; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV32IFD-NEXT:    fcvt.s.wu ft0, a0
 ; RV32IFD-NEXT:    fmv.x.w a0, ft0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_s_wu_via_d:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
-; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV64IFD-NEXT:    fcvt.s.wu ft0, a0
 ; RV64IFD-NEXT:    fmv.x.w a0, ft0
 ; RV64IFD-NEXT:    ret
   %2 = uitofp i32 %0 to double
   %3 = fptrunc double %2 to float
   ret float %3
 }