[RISCV][NFC] Tests for indirect float conversion

[lenary]

Summary

I worked on some patterns to address the code generated by these
examples, which came out of some differential testing against GCC. The patterns
will be in a follow-up patch.

[asb]

llvm/test/CodeGen/RISCV/double-convert-indirect.ll

10

If I'm interpreting this comment correctly, you're neglecting to test rv32if/rv64if because your planned optimisation won't improve things (but feel in principle it should be possible to optimise)? If so, I think it would be better to include the rv32if/rv64if cases here too, even if we don't have a solution on the horizon.

[lenary]

llvm/test/CodeGen/RISCV/double-convert-indirect.ll

10

You are interpreting correctly.

It might be possible to optimise, but not with normal SelectionDAG patterns, because on RV32IF the legaliser has already turned the two operations we want to match on into libcalls.

I can look at doing a follow-up DAGCombiner patch (which would run before the legaliser), but it's not clear to me that this is valid on every architecture, because I'm not super familiar with floats. I can post a draft DAGCombiner patch and seek feedback?

[asb]

llvm/test/CodeGen/RISCV/double-convert-indirect.ll

10

A DAGCombiner patch might be interesting, but actually I was just suggesting that this test case contain check lines for RV32IF and RV64IF so that we'll be sure to pick it up if some other change means codegen for those cases improves too.

[lenary]

llvm/test/CodeGen/RISCV/double-convert-indirect.ll

10

Ok, sure. I'll add those lines and also rename it so it's clear it's for all FP extensions, not just the D extension.

[lenary]

Address @asb's feedback

• Renamed the test
• Added lines for F-extension only runs, showing libcalls.

llvm/test/CodeGen/RISCV/double-convert-indirect.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IFD %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IFD %s
+
+;; These testcases check that we merge sequences of `fcvt.d.wu; fcvt.s.d` into
+;; `fcvt.s.wu`.
+;;
+;; TODO: Unfortunately, though this only uses 32-bit FP instructions, we cannot
+;; do this optimisation without the D extension as we need 64-bit FP values to
+;; be legal to get the right operands to match.
+
+define float @fcvt_s_w_via_d(i32 %0) nounwind {
+; RV32IFD-LABEL: fcvt_s_w_via_d:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    fcvt.d.w ft0, a0
+; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV32IFD-NEXT:    fmv.x.w a0, ft0
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_s_w_via_d:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.d.w ft0, a0
+; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV64IFD-NEXT:    fmv.x.w a0, ft0
+; RV64IFD-NEXT:    ret
+  %2 = sitofp i32 %0 to double
+  %3 = fptrunc double %2 to float
+  ret float %3
+}
+
+define float @fcvt_s_wu_via_d(i32 %0) nounwind {
+; RV32IFD-LABEL: fcvt_s_wu_via_d:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
+; RV32IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV32IFD-NEXT:    fmv.x.w a0, ft0
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: fcvt_s_wu_via_d:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
+; RV64IFD-NEXT:    fcvt.s.d ft0, ft0
+; RV64IFD-NEXT:    fmv.x.w a0, ft0
+; RV64IFD-NEXT:    ret
+  %2 = uitofp i32 %0 to double
+  %3 = fptrunc double %2 to float
+  ret float %3
+}