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Differential D78860

[AMDGPU] Fixed incorrect PAL metadata register naming
ClosedPublic

Authored by tpr on Apr 25 2020, 4:17 AM.

Details

Reviewers
dstuttard
rampitec
piotr
Commits
rGd13a50882006: [AMDGPU] Fixed incorrect PAL metadata register naming
Summary

This only affects assembly and -filetype=asm codegen of PAL metadata.

Change-Id: I7b822e1917bf7b403486820d31afc483be207652

Diff Detail

Event Timeline

tpr created this revision.Apr 25 2020, 4:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 25 2020, 4:17 AM
Herald added subscribers: llvm-commits, kerbowa, hiraditya and 8 others. · View Herald Transcript
tpr added reviewers: dstuttard, rampitec.Apr 25 2020, 4:19 AM
Harbormaster completed remote builds in B54674: Diff 260081.Apr 25 2020, 5:16 AM
arsenm added a comment.Apr 25 2020, 8:04 AM

Testcase?

tpr updated this revision to Diff 261448.May 1 2020, 2:57 AM

V2: Also fixed GS regs. Added test.

Harbormaster completed remote builds in B55422: Diff 261448.May 1 2020, 3:09 AM
tpr added a comment.May 10 2020, 2:33 AM

Ping.

tpr added a comment.May 18 2020, 12:43 AM

Ping

piotr accepted this revision.May 18 2020, 7:11 AM
piotr added a subscriber: piotr.

LGTM

This revision is now accepted and ready to land.May 18 2020, 7:11 AM
Closed by commit rGd13a50882006: [AMDGPU] Fixed incorrect PAL metadata register naming (authored by tpr). · Explain WhyMay 21 2020, 2:39 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
Utils/
114 lines
test/
CodeGen/
AMDGPU/
16 lines

Diff 265610

llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

Show First 20 Lines • Show All 391 Lines • ▼ Show 20 Lines const char *Name;
{0x2c65, "SPI_SHADER_USER_DATA_VS_25"}, {0x2c65, "SPI_SHADER_USER_DATA_VS_25"},
{0x2c66, "SPI_SHADER_USER_DATA_VS_26"}, {0x2c66, "SPI_SHADER_USER_DATA_VS_26"},
{0x2c67, "SPI_SHADER_USER_DATA_VS_27"}, {0x2c67, "SPI_SHADER_USER_DATA_VS_27"},
{0x2c68, "SPI_SHADER_USER_DATA_VS_28"}, {0x2c68, "SPI_SHADER_USER_DATA_VS_28"},
{0x2c69, "SPI_SHADER_USER_DATA_VS_29"}, {0x2c69, "SPI_SHADER_USER_DATA_VS_29"},
{0x2c6a, "SPI_SHADER_USER_DATA_VS_30"}, {0x2c6a, "SPI_SHADER_USER_DATA_VS_30"},
{0x2c6b, "SPI_SHADER_USER_DATA_VS_31"}, {0x2c6b, "SPI_SHADER_USER_DATA_VS_31"},
{0x2c8c, "SPI_SHADER_USER_DATA_GS_0"},
{0x2c8d, "SPI_SHADER_USER_DATA_GS_1"},
{0x2c8e, "SPI_SHADER_USER_DATA_GS_2"},
{0x2c8f, "SPI_SHADER_USER_DATA_GS_3"},
{0x2c90, "SPI_SHADER_USER_DATA_GS_4"},
{0x2c91, "SPI_SHADER_USER_DATA_GS_5"},
{0x2c92, "SPI_SHADER_USER_DATA_GS_6"},
{0x2c93, "SPI_SHADER_USER_DATA_GS_7"},
{0x2c94, "SPI_SHADER_USER_DATA_GS_8"},
{0x2c95, "SPI_SHADER_USER_DATA_GS_9"},
{0x2c96, "SPI_SHADER_USER_DATA_GS_10"},
{0x2c97, "SPI_SHADER_USER_DATA_GS_11"},
{0x2c98, "SPI_SHADER_USER_DATA_GS_12"},
{0x2c99, "SPI_SHADER_USER_DATA_GS_13"},
{0x2c9a, "SPI_SHADER_USER_DATA_GS_14"},
{0x2c9b, "SPI_SHADER_USER_DATA_GS_15"},
{0x2c9c, "SPI_SHADER_USER_DATA_GS_16"},
{0x2c9d, "SPI_SHADER_USER_DATA_GS_17"},
{0x2c9e, "SPI_SHADER_USER_DATA_GS_18"},
{0x2c9f, "SPI_SHADER_USER_DATA_GS_19"},
{0x2ca0, "SPI_SHADER_USER_DATA_GS_20"},
{0x2ca1, "SPI_SHADER_USER_DATA_GS_21"},
{0x2ca2, "SPI_SHADER_USER_DATA_GS_22"},
{0x2ca3, "SPI_SHADER_USER_DATA_GS_23"},
{0x2ca4, "SPI_SHADER_USER_DATA_GS_24"},
{0x2ca5, "SPI_SHADER_USER_DATA_GS_25"},
{0x2ca6, "SPI_SHADER_USER_DATA_GS_26"},
{0x2ca7, "SPI_SHADER_USER_DATA_GS_27"},
{0x2ca8, "SPI_SHADER_USER_DATA_GS_28"},
{0x2ca9, "SPI_SHADER_USER_DATA_GS_29"},
{0x2caa, "SPI_SHADER_USER_DATA_GS_30"},
{0x2cab, "SPI_SHADER_USER_DATA_GS_31"},
{0x2ccc, "SPI_SHADER_USER_DATA_ES_0"}, {0x2ccc, "SPI_SHADER_USER_DATA_ES_0"},
{0x2ccd, "SPI_SHADER_USER_DATA_ES_1"}, {0x2ccd, "SPI_SHADER_USER_DATA_ES_1"},
{0x2cce, "SPI_SHADER_USER_DATA_ES_2"}, {0x2cce, "SPI_SHADER_USER_DATA_ES_2"},
{0x2ccf, "SPI_SHADER_USER_DATA_ES_3"}, {0x2ccf, "SPI_SHADER_USER_DATA_ES_3"},
{0x2cd0, "SPI_SHADER_USER_DATA_ES_4"}, {0x2cd0, "SPI_SHADER_USER_DATA_ES_4"},
{0x2cd1, "SPI_SHADER_USER_DATA_ES_5"}, {0x2cd1, "SPI_SHADER_USER_DATA_ES_5"},
{0x2cd2, "SPI_SHADER_USER_DATA_ES_6"}, {0x2cd2, "SPI_SHADER_USER_DATA_ES_6"},
{0x2cd3, "SPI_SHADER_USER_DATA_ES_7"}, {0x2cd3, "SPI_SHADER_USER_DATA_ES_7"},
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines const char *Name;
{0xa2db, "VGT_TF_PARAM"}, {0xa2db, "VGT_TF_PARAM"},
{0xa2d6, "VGT_LS_HS_CONFIG"}, {0xa2d6, "VGT_LS_HS_CONFIG"},
{0xa287, "VGT_HOS_MIN_TESS_LEVEL"}, {0xa287, "VGT_HOS_MIN_TESS_LEVEL"},
{0xa286, "VGT_HOS_MAX_TESS_LEVEL"}, {0xa286, "VGT_HOS_MAX_TESS_LEVEL"},
{0xa2f8, "PA_SC_AA_CONFIG"}, {0xa2f8, "PA_SC_AA_CONFIG"},
{0xa310, "PA_SC_SHADER_CONTROL"}, {0xa310, "PA_SC_SHADER_CONTROL"},
{0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"}, {0xa313, "PA_SC_CONSERVATIVE_RASTERIZATION_CNTL"},
{0x2d0c, "SPI_SHADER_USER_DATA_LS_0"}, {0x2d0c, "SPI_SHADER_USER_DATA_HS_0"},
{0x2d0d, "SPI_SHADER_USER_DATA_LS_1"}, {0x2d0d, "SPI_SHADER_USER_DATA_HS_1"},
{0x2d0e, "SPI_SHADER_USER_DATA_LS_2"}, {0x2d0e, "SPI_SHADER_USER_DATA_HS_2"},
{0x2d0f, "SPI_SHADER_USER_DATA_LS_3"}, {0x2d0f, "SPI_SHADER_USER_DATA_HS_3"},
{0x2d10, "SPI_SHADER_USER_DATA_LS_4"}, {0x2d10, "SPI_SHADER_USER_DATA_HS_4"},
{0x2d11, "SPI_SHADER_USER_DATA_LS_5"}, {0x2d11, "SPI_SHADER_USER_DATA_HS_5"},
{0x2d12, "SPI_SHADER_USER_DATA_LS_6"}, {0x2d12, "SPI_SHADER_USER_DATA_HS_6"},
{0x2d13, "SPI_SHADER_USER_DATA_LS_7"}, {0x2d13, "SPI_SHADER_USER_DATA_HS_7"},
{0x2d14, "SPI_SHADER_USER_DATA_LS_8"}, {0x2d14, "SPI_SHADER_USER_DATA_HS_8"},
{0x2d15, "SPI_SHADER_USER_DATA_LS_9"}, {0x2d15, "SPI_SHADER_USER_DATA_HS_9"},
{0x2d16, "SPI_SHADER_USER_DATA_LS_10"}, {0x2d16, "SPI_SHADER_USER_DATA_HS_10"},
{0x2d17, "SPI_SHADER_USER_DATA_LS_11"}, {0x2d17, "SPI_SHADER_USER_DATA_HS_11"},
{0x2d18, "SPI_SHADER_USER_DATA_LS_12"}, {0x2d18, "SPI_SHADER_USER_DATA_HS_12"},
{0x2d19, "SPI_SHADER_USER_DATA_LS_13"}, {0x2d19, "SPI_SHADER_USER_DATA_HS_13"},
{0x2d1a, "SPI_SHADER_USER_DATA_LS_14"}, {0x2d1a, "SPI_SHADER_USER_DATA_HS_14"},
{0x2d1b, "SPI_SHADER_USER_DATA_LS_15"}, {0x2d1b, "SPI_SHADER_USER_DATA_HS_15"},
{0x2d1c, "SPI_SHADER_USER_DATA_LS_16"}, {0x2d1c, "SPI_SHADER_USER_DATA_HS_16"},
{0x2d1d, "SPI_SHADER_USER_DATA_LS_17"}, {0x2d1d, "SPI_SHADER_USER_DATA_HS_17"},
{0x2d1e, "SPI_SHADER_USER_DATA_LS_18"}, {0x2d1e, "SPI_SHADER_USER_DATA_HS_18"},
{0x2d1f, "SPI_SHADER_USER_DATA_LS_19"}, {0x2d1f, "SPI_SHADER_USER_DATA_HS_19"},
{0x2d20, "SPI_SHADER_USER_DATA_LS_20"}, {0x2d20, "SPI_SHADER_USER_DATA_HS_20"},
{0x2d21, "SPI_SHADER_USER_DATA_LS_21"}, {0x2d21, "SPI_SHADER_USER_DATA_HS_21"},
{0x2d22, "SPI_SHADER_USER_DATA_LS_22"}, {0x2d22, "SPI_SHADER_USER_DATA_HS_22"},
{0x2d23, "SPI_SHADER_USER_DATA_LS_23"}, {0x2d23, "SPI_SHADER_USER_DATA_HS_23"},
{0x2d24, "SPI_SHADER_USER_DATA_LS_24"}, {0x2d24, "SPI_SHADER_USER_DATA_HS_24"},
{0x2d25, "SPI_SHADER_USER_DATA_LS_25"}, {0x2d25, "SPI_SHADER_USER_DATA_HS_25"},
{0x2d26, "SPI_SHADER_USER_DATA_LS_26"}, {0x2d26, "SPI_SHADER_USER_DATA_HS_26"},
{0x2d27, "SPI_SHADER_USER_DATA_LS_27"}, {0x2d27, "SPI_SHADER_USER_DATA_HS_27"},
{0x2d28, "SPI_SHADER_USER_DATA_LS_28"}, {0x2d28, "SPI_SHADER_USER_DATA_HS_28"},
{0x2d29, "SPI_SHADER_USER_DATA_LS_29"}, {0x2d29, "SPI_SHADER_USER_DATA_HS_29"},
{0x2d2a, "SPI_SHADER_USER_DATA_LS_30"}, {0x2d2a, "SPI_SHADER_USER_DATA_HS_30"},
{0x2d2b, "SPI_SHADER_USER_DATA_LS_31"}, {0x2d2b, "SPI_SHADER_USER_DATA_HS_31"},
{0x2d4c, "SPI_SHADER_USER_DATA_LS_0"},
{0x2d4d, "SPI_SHADER_USER_DATA_LS_1"},
{0x2d4e, "SPI_SHADER_USER_DATA_LS_2"},
{0x2d4f, "SPI_SHADER_USER_DATA_LS_3"},
{0x2d50, "SPI_SHADER_USER_DATA_LS_4"},
{0x2d51, "SPI_SHADER_USER_DATA_LS_5"},
{0x2d52, "SPI_SHADER_USER_DATA_LS_6"},
{0x2d53, "SPI_SHADER_USER_DATA_LS_7"},
{0x2d54, "SPI_SHADER_USER_DATA_LS_8"},
{0x2d55, "SPI_SHADER_USER_DATA_LS_9"},
{0x2d56, "SPI_SHADER_USER_DATA_LS_10"},
{0x2d57, "SPI_SHADER_USER_DATA_LS_11"},
{0x2d58, "SPI_SHADER_USER_DATA_LS_12"},
{0x2d59, "SPI_SHADER_USER_DATA_LS_13"},
{0x2d5a, "SPI_SHADER_USER_DATA_LS_14"},
{0x2d5b, "SPI_SHADER_USER_DATA_LS_15"},
{0xa2aa, "IA_MULTI_VGT_PARAM"}, {0xa2aa, "IA_MULTI_VGT_PARAM"},
{0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"}, {0xa2a5, "VGT_GS_MAX_PRIMS_PER_SUBGROUP"},
{0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"}, {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
{0xa2e5, "VGT_STRMOUT_CONFIG"}, {0xa2e5, "VGT_STRMOUT_CONFIG"},
{0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"}, {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
{0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"}, {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
{0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"}, {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
▲ Show 20 Lines • Show All 192 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll

  • This file was added.
; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx802 <%s | FileCheck %s
; Test that the mnemonic names for PAL metadata user data registers work in a
; full tessellation-and-geometry pipeline, compiled on gfx8 so it uses all six
; hardware shader types.
; CHECK-DAG: 0x2c0c (SPI_SHADER_USER_DATA_PS_0): 0x10000000
; CHECK-DAG: 0x2c4c (SPI_SHADER_USER_DATA_VS_0): 0x10000000
; CHECK-DAG: 0x2c8c (SPI_SHADER_USER_DATA_GS_0): 0x10000000
; CHECK-DAG: 0x2ccc (SPI_SHADER_USER_DATA_ES_0): 0x10000000
; CHECK-DAG: 0x2d0c (SPI_SHADER_USER_DATA_HS_0): 0x10000000
; CHECK-DAG: 0x2d4c (SPI_SHADER_USER_DATA_LS_0): 0x10000000
!amdgpu.pal.metadata.msgpack = !{!0}
!0 = !{!"\82\B0amdpal.pipelines\91\88\A4.api\A6Vulkan\B0.hardware_stages\86\A3.es\82\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\A3.gs\82\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\A3.hs\82\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\A3.ls\83\A9.lds_size\CD\03\00\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\A3.ps\82\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\A3.vs\82\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\B7.internal_pipeline_hash\92\CF\0BE\F2u\8CK\FA\BC\CF\E5\A2\84o\83\86\1C\F8\AA.registers\DE\00I\CD,\0A\CE\00,\00\00\CD,\0B\04\CD,\0C\CE\10\00\00\00\CD,J\CE\00,\00\00\CD,K\08\CD,L\CE\10\00\00\00\CD,\8A\CE\00,\00\00\CD,\8B\06\CD,\8C\CE\10\00\00\00\CD,\8E\01\CD,\CA\CE\03,\00\00\CD,\CB\06\CD,\CC\CE\10\00\00\00\CD,\CE\01\CD-\0A\CE\00,\00\00\CD-\0B\06\CD-\0C\CE\10\00\00\00\CD-\0E\01\CD-J\CE\01,\00\00\CD-K\CD\01\0A\CD-L\CE\10\00\00\00\CD-N\01\CD-O\CE\10\00\00\03\CD-P\CE\10\00\00\04\CD\A0\8F\01\CD\A1\91\00\CD\A1\B1\00\CD\A1\B3\00\CD\A1\B4\00\CD\A1\B5\00\CD\A1\B6\00\CD\A1\B8\CE\01\00\00\00\CD\A1\C3\04\CD\A1\C4\00\CD\A1\C5\01\CD\A2\03\10\CD\A2\04\CE\01\08\00\00\CD\A2\06\CD\04?\CD\A2\07\00\CD\A2\86\CEB\80\00\00\CD\A2\87\CE?\80\00\00\CD\A2\90\CE\00\18\003\CD\A2\91\00\CD\A2\93\CE\06\02\01\8C\CD\A2\95\CD\01\00\CD\A2\96\CC\80\CD\A2\97\02\CD\A2\98\04\CD\A2\99\04\CD\A2\9A\04\CD\A2\9B\00\CD\A2\A1\01\CD\A2\AA\CE\00\0C\00\00\CD\A2\AB\04\CD\A2\AC\04\CD\A2\AD\00\CD\A2\B5\00\CD\A2\B9\00\CD\A2\BD\00\CD\A2\C1\00\CD\A2\CE\01\CD\A2\D5\CC\AD\CD\A2\D6\CDA\10\CD\A2\D7\04\CD\A2\D8\00\CD\A2\D9\00\CD\A2\DA\00\CD\A2\DB \CD\A2\E4\00\CD\A2\E5\00\CD\A2\E6\00\CD\A2\F9-\CD\A3\16\0E\A8.shaders\85\A7.domain\82\B0.api_shader_hash\92\CF\B6\08\8De\FF\A1`\85\00\B1.hardware_mapping\91\A3.es\A9.geometry\82\B0.api_shader_hash\92\CF\B0Hn\E7\C1\9Etq\00\B1.hardware_mapping\92\A3.gs\A3.vs\A5.hull\82\B0.api_shader_hash\92\CF}\F2\C7\CF\AB\DB,B\00\B1.hardware_mapping\91\A3.hs\A6.pixel\82\B0.api_shader_hash\92\CF\A9\C3\05H\E3(Ay\00\B1.hardware_mapping\91\A3.ps\A7.vertex\82\B0.api_shader_hash\92\CF\A8\A3\C7x\DB\C5\88\84\00\B1.hardware_mapping\91\A3.ls\B0.spill_threshold\CE\FF\FF\FF\FF\A5.type\A6GsTess\B0.user_data_limit\02\AEamdpal.version\92\02\03"}