If a 16-bit thumb STM with writeback stores the base register but it isn't the first register in the list, then an unknown value is stored. The load/store optimizer knows this and generates a 32-bit STM without writeback instead, but thumb2 size reduction converts it into a 16-bit STM. Fix this by having thumb2 size reduction notice such STMs and leave them as they are.
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llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | ||
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525 | It's probably worth reorganizing the comments here to clarify: tSTMIA_UPD the only 16-bit STM. So the Thumb2 instruction is fine, but the rewritten one would be unpredictable. |
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Adjust comments. Also, after double-checking the 8-A and 8-M ARMARMs it's OK if the base register being stored is the lowest one so adjusted to allow that.
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LGTM
The ARMv7 ARM claims the form with writeback of the lowest register is deprecated, but it looks like ARMv8 un-deprecated it, so we probably don't care about that.
It's probably worth reorganizing the comments here to clarify: tSTMIA_UPD the only 16-bit STM. So the Thumb2 instruction is fine, but the rewritten one would be unpredictable.