[AArch64LoadStoreOptimizer] Skip debug insts during pattern matching

[vsk]

Summary

Do not count the presence of debug insts against the limit set by
LdStLimit, and allow the optimizer to find matching insts by skipping
over debug insts.

[vsk]

Apologies, this was uploaded too early. This patch still needs cleanup before it's ready to be reviewed.

[vsk]

Backed out some unrelated changes.

[fhahn]

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

751

could use range based iterator?

1013

nit: Not sure if it is worth to introduce a variable for a single use, as it also increases the number of variables to keep track in the function.

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir

1

I think it would be slightly better to have the version with DBG_VALUE as separate test, as it unnecessarily clutters the test with respect to the core functionality.

[fhahn]

LGTM with the nits addressed, thanks!

[vsk]

Address review feedback:

• Use range based iterator, split out a second test with debug info, drop extra variable

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir

1

I see; let's add a -mir-debugify run line to the original test so that extensions to the pass get tested with debug info, and then copy the test to have coverage for the case where there are multiple DBG_VALUEs between instruction pairs?

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

 
 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
                                            MachineBasicBlock::iterator MergeMI,
                                            const LdStPairFlags &Flags) {
   assert(isPromotableZeroStoreInst(*I) && isPromotableZeroStoreInst(*MergeMI) &&
          "Expected promotable zero stores.");
 
-  MachineBasicBlock::iterator NextI = I;
-  ++NextI;
+  MachineBasicBlock::iterator E = I->getParent()->end();
+  MachineBasicBlock::iterator NextI = next_nodbg(I, E);
   // If NextI is the second of the two instructions to be merged, we need
   // to skip one further. Either way we merge will invalidate the iterator,
   // and we don't need to scan the new instruction, as it's a pairwise
   // instruction, which we're not considering for further action anyway.
   if (NextI == MergeMI)
-    ++NextI;
+    NextI = next_nodbg(NextI, E);
 
   unsigned Opc = I->getOpcode();
   bool IsScaled = !TII->isUnscaledLdSt(Opc);
   int OffsetStride = IsScaled ? 1 : TII->getMemScale(*I);
 
   bool MergeForward = Flags.getMergeForward();
   // Insert our new paired instruction after whichever of the paired
   // instructions MergeForward indicates.

 
 // Apply Fn to all instructions between MI and the beginning of the block, until
 // a def for DefReg is reached. Returns true, iff Fn returns true for all
 // visited instructions. Stop after visiting Limit iterations.
 static bool forAllMIsUntilDef(MachineInstr &MI, MCPhysReg DefReg,
                               const TargetRegisterInfo *TRI, unsigned Limit,
                               std::function<bool(MachineInstr &, bool)> &Fn) {
   auto MBB = MI.getParent();
   for (MachineBasicBlock::reverse_iterator I = MI.getReverseIterator(),
                                            E = MBB->rend();
-       I != E; I++) {
+       I != E; I = next_nodbg(I, E)) {
     if (!Limit)
       return false;
     --Limit;
 
     bool isDef = any_of(I->operands(), [DefReg, TRI](MachineOperand &MOP) {
       return MOP.isReg() && MOP.isDef() && !MOP.isDebug() && MOP.getReg() &&
              TRI->regsOverlap(MOP.getReg(), DefReg);
     });
for (const MachineOperand &MOP : phys_regs_and_masks(MI))
     if (MOP.isReg() && !MOP.isKill())
       Units.addReg(MOP.getReg());
 }
 
 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
                                       MachineBasicBlock::iterator Paired,
                                       const LdStPairFlags &Flags) {
-  MachineBasicBlock::iterator NextI = I;
-  ++NextI;
+  MachineBasicBlock::iterator E = I->getParent()->end();
+  MachineBasicBlock::iterator NextI = next_nodbg(I, E);
   // If NextI is the second of the two instructions to be merged, we need
   // to skip one further. Either way we merge will invalidate the iterator,
   // and we don't need to scan the new instruction, as it's a pairwise
   // instruction, which we're not considering for further action anyway.
   if (NextI == Paired)
-    ++NextI;
+    NextI = next_nodbg(NextI, E);
 
   int SExtIdx = Flags.getSExtIdx();
   unsigned Opc =
       SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
   bool IsUnscaled = TII->isUnscaledLdSt(Opc);
   int OffsetStride = IsUnscaled ? TII->getMemScale(*I) : 1;
 
   bool MergeForward = Flags.getMergeForward();
#endif
   Paired->eraseFromParent();
 
   return NextI;
 }
 
 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
                                           MachineBasicBlock::iterator StoreI) {
-  MachineBasicBlock::iterator NextI = LoadI;
-  ++NextI;
+  MachineBasicBlock::iterator E = LoadI->getParent()->end();
+  MachineBasicBlock::iterator NextI = next_nodbg(LoadI, E);
 
   int LoadSize = TII->getMemScale(*LoadI);
   int StoreSize = TII->getMemScale(*StoreI);
   Register LdRt = getLdStRegOp(*LoadI).getReg();
   const MachineOperand &StMO = getLdStRegOp(*StoreI);
   Register StRt = getLdStRegOp(*StoreI).getReg();
   bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
 
bool AArch64LoadStoreOpt::findMatchingStore(
 
   // Track which register units have been modified and used between the first
   // insn and the second insn.
   ModifiedRegUnits.clear();
   UsedRegUnits.clear();
 
   unsigned Count = 0;
   do {
-    --MBBI;
+    MBBI = prev_nodbg(MBBI, B);
     MachineInstr &MI = *MBBI;
 
     // Don't count transient instructions towards the search limit since there
     // may be different numbers of them if e.g. debug information is present.
     if (!MI.isTransient())
       ++Count;
 
     // If the load instruction reads directly from the address to which the

 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
                                       LdStPairFlags &Flags, unsigned Limit,
                                       bool FindNarrowMerge) {
   MachineBasicBlock::iterator E = I->getParent()->end();
   MachineBasicBlock::iterator MBBI = I;
   MachineBasicBlock::iterator MBBIWithRenameReg;
   MachineInstr &FirstMI = *I;
-  ++MBBI;
+  MBBI = next_nodbg(MBBI, E);
 
   bool MayLoad = FirstMI.mayLoad();
   bool IsUnscaled = TII->isUnscaledLdSt(FirstMI);
   Register Reg = getLdStRegOp(FirstMI).getReg();
   Register BaseReg = getLdStBaseOp(FirstMI).getReg();
   int Offset = getLdStOffsetOp(FirstMI).getImm();
   int OffsetStride = IsUnscaled ? TII->getMemScale(FirstMI) : 1;
   bool IsPromotableZeroStore = isPromotableZeroStoreInst(FirstMI);
AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
   // Track which register units have been modified and used between the first
   // insn (inclusive) and the second insn.
   ModifiedRegUnits.clear();
   UsedRegUnits.clear();
 
   // Remember any instructions that read/write memory between FirstMI and MI.
   SmallVector<MachineInstr *, 4> MemInsns;
 
-  for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
+  for (unsigned Count = 0; MBBI != E && Count < Limit;
+       MBBI = next_nodbg(MBBI, E)) {
     MachineInstr &MI = *MBBI;
 
     UsedInBetween.accumulate(MI);
 
     // Don't count transient instructions towards the search limit since there
     // may be different numbers of them if e.g. debug information is present.
     if (!MI.isTransient())
       ++Count;

 
 MachineBasicBlock::iterator
 AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
                                      MachineBasicBlock::iterator Update,
                                      bool IsPreIdx) {
   assert((Update->getOpcode() == AArch64::ADDXri ||
           Update->getOpcode() == AArch64::SUBXri) &&
          "Unexpected base register update instruction to merge!");
-  MachineBasicBlock::iterator NextI = I;
+  MachineBasicBlock::iterator E = I->getParent()->end();
+  MachineBasicBlock::iterator NextI = next_nodbg(I, E);
   // Return the instruction following the merged instruction, which is
   // the instruction following our unmerged load. Unless that's the add/sub
   // instruction we're merging, in which case it's the one after that.
-  if (++NextI == Update)
-    ++NextI;
+  if (NextI == Update)
+    NextI = next_nodbg(NextI, E);
 
   int Value = Update->getOperand(2).getImm();
   assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
          "Can't merge 1 << 12 offset into pre-/post-indexed load / store");
   if (Update->getOpcode() == AArch64::SUBXri)
     Value = -Value;
 
   unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
         return E;
     }
   }
 
   // Track which register units have been modified and used between the first
   // insn (inclusive) and the second insn.
   ModifiedRegUnits.clear();
   UsedRegUnits.clear();
-  ++MBBI;
+  MBBI = next_nodbg(MBBI, E);
 
   // We can't post-increment the stack pointer if any instruction between
   // the memory access (I) and the increment (MBBI) can access the memory
   // region defined by [SP, MBBI].
   const bool BaseRegSP = BaseReg == AArch64::SP;
   if (BaseRegSP) {
     // FIXME: For now, we always block the optimization over SP in windows
     // targets as it requires to adjust the unwind/debug info, messing up
     // the unwind info can actually cause a miscompile.
     const MCAsmInfo *MAI = I->getMF()->getTarget().getMCAsmInfo();
     if (MAI->usesWindowsCFI() &&
         I->getMF()->getFunction().needsUnwindTableEntry())
       return E;
   }
 
-  for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
+  for (unsigned Count = 0; MBBI != E && Count < Limit;
+       MBBI = next_nodbg(MBBI, E)) {
     MachineInstr &MI = *MBBI;
 
     // Don't count transient instructions towards the search limit since there
     // may be different numbers of them if e.g. debug information is present.
     if (!MI.isTransient())
       ++Count;
 
     // If we found a match, return it.
MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
   }
 
   // Track which register units have been modified and used between the first
   // insn (inclusive) and the second insn.
   ModifiedRegUnits.clear();
   UsedRegUnits.clear();
   unsigned Count = 0;
   do {
-    --MBBI;
+    MBBI = prev_nodbg(MBBI, B);
     MachineInstr &MI = *MBBI;
 
     // Don't count transient instructions towards the search limit since there
     // may be different numbers of them if e.g. debug information is present.
     if (!MI.isTransient())
       ++Count;
 
     // If we found a match, return it.

llvm/test/CodeGen/AArch64/ldst-opt-mte.mir

-# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt  -verify-machineinstrs  -o - %s | FileCheck %s
+# Strip out debug info, then run ldst-opt with limit=1.
+# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -run-pass mir-strip-debug,aarch64-ldst-opt -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
+#
+# Run ldst-opt with limit=1, then strip out debug info.
+# RUN: llc -aarch64-load-store-scan-limit=1 -mtriple=aarch64-none-linux-gnu -run-pass aarch64-ldst-opt,mir-strip-debug -mir-strip-debugify-only=0 -verify-machineinstrs  -o - %s | FileCheck %s
 ---
 
 ### STG and its offset limits
 
 # CHECK-LABEL: name: test_STG_post
 # CHECK: STGPostIndex $x0, $x0, 7
 name: test_STG_post
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post_same_reg
 # CHECK: STGPostIndex $x1, $x0, 7
 name: test_STG_post_same_reg
 body: |
   bb.0.entry:
     liveins: $x0, $x1
 
     STGOffset $x1, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post_unaligned
 # CHECK:      STGOffset $x0, $x0, 0
 # CHECK-NEXT: ADDXri $x0, 8, 0
 name: test_STG_post_unaligned
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 8, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post2
 # CHECK: STGPostIndex $x0, $x0, -256
 name: test_STG_post2
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = SUBXri $x0, 4096, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post3
 # CHECK:      STGOffset $x0, $x0, 0
 # CHECK-NEXT: SUBXri $x0, 4112, 0
 name: test_STG_post3
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = SUBXri $x0, 4112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post4
 # CHECK: STGPostIndex $x0, $x0, 255
 name: test_STG_post4
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 4080, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STG_post5
 # CHECK:      STGOffset $x0, $x0, 0
 # CHECK-NEXT: ADDXri $x0, 4096, 0
 name: test_STG_post5
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 4096, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### The rest of ST*G variants.
 
 # CHECK-LABEL: name: test_STZG_post
 # CHECK: STZGPostIndex $x0, $x0, 7
 name: test_STZG_post
 body: |
   bb.0.entry:
     liveins: $x0
 
     STZGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_ST2G_post
 # CHECK: ST2GPostIndex $x0, $x0, 7
 name: test_ST2G_post
 body: |
   bb.0.entry:
     liveins: $x0
 
     ST2GOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STZ2G_post
 # CHECK: STZ2GPostIndex $x0, $x0, 7
 name: test_STZ2G_post
 body: |
   bb.0.entry:
     liveins: $x0
 
     STZ2GOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### STGP and its offset limits
 
 # CHECK-LABEL: name: test_STGP_post
 # CHECK: STGPpost $x1, $x2, $x0, 7
 name: test_STGP_post
 body: |
   bb.0.entry:
     liveins: $x0, $x1, $x2
 
     STGPi $x1, $x2, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_post2
 # CHECK: STGPpost $x1, $x2, $x0, -64
 name: test_STGP_post2
 body: |
   bb.0.entry:
     liveins: $x0, $x1, $x2
 
     STGPi $x1, $x2, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = SUBXri $x0, 1024, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_post3
 # CHECK:      STGPi $x1, $x2, $x0, 0
 # CHECK-NEXT: SUBXri $x0, 1040, 0
 name: test_STGP_post3
 body: |
   bb.0.entry:
     liveins: $x0, $x1, $x2
 
     STGPi $x1, $x2, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = SUBXri $x0, 1040, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_post4
 # CHECK: STGPpost $x1, $x2, $x0, 63
 name: test_STGP_post4
 body: |
   bb.0.entry:
     liveins: $x0, $x1, $x2
 
     STGPi $x1, $x2, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 1008, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_post5
 # CHECK:      STGPi $x1, $x2, $x0, 0
 # CHECK-NEXT: ADDXri $x0, 1024, 0
 name: test_STGP_post5
 body: |
   bb.0.entry:
     liveins: $x0, $x1, $x2
 
     STGPi $x1, $x2, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 1024, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### Pre-indexed forms
 
 # CHECK-LABEL: name: test_STG_pre
 # CHECK: STGPreIndex $x0, $x0, 10
 name: test_STG_pre
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGOffset $x0, $x0, 10
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 160, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_pre
 # CHECK: STGPpre $x1, $x2, $x0, 10
 name: test_STGP_pre
 body: |
   bb.0.entry:
     liveins: $x0, $x1, $x2
 
     STGPi $x1, $x2, $x0, 10
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 160, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### Pre-indexed forms with add/sub coming before the store.
 
 # CHECK-LABEL: name: test_STG_pre_back
 # CHECK: STGPreIndex $x0, $x0, 2
 name: test_STG_pre_back
 body: |
   bb.0.entry:
     liveins: $x0
 
     $x0 = ADDXri $x0, 32, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     STGOffset $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_pre_back
 # CHECK: STGPpre $x1, $x2, $x0, -3
 name: test_STGP_pre_back
 body: |
   bb.0.entry:
     liveins: $x0, $x1, $x2
 
     $x0 = SUBXri $x0, 48, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     STGPi $x1, $x2, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 ### STGP with source register == address register
 
 # CHECK-LABEL: name: test_STGP_post_same_reg
 # CHECK: STGPpost $x0, $x0, $x0, 7
 name: test_STGP_post_same_reg
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGPi $x0, $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # CHECK-LABEL: name: test_STGP_pre_same_reg
 # CHECK: STGPpre $x0, $x0, $x0, 7
 name: test_STGP_pre_same_reg
 body: |
   bb.0.entry:
     liveins: $x0
 
     STGPi $x0, $x0, $x0, 7
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     $x0 = ADDXri $x0, 112, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...
 
 # This case can not be merged because the source register is always read before writeback.
 # CHECK-LABEL: name: test_STGP_pre_back_same_reg
 # CHECK:      SUBXri $x0, 48, 0
 # CHECK-NEXT: STGPi $x0, $x0, $x0, 0
 name: test_STGP_pre_back_same_reg
 body: |
   bb.0.entry:
     liveins: $x0
 
     $x0 = SUBXri $x0, 48, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     STGPi $x0, $x0, $x0, 0
+    DBG_VALUE $x0, 0
+    DBG_VALUE $x0, 0
     RET_ReallyLR implicit $x0
 ...