[PowerPC] Use add instead of addReg in ppc-early-ret pass

[ZhangKang]

Summary

The ppc-early-ret pass use the addReg() to add operand to the new instruction.

106               BuildMI(
107                   **PI, J, J->getDebugLoc(),
108                   TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn))
109                   .addReg(J->getOperand(0).getReg())
110                   .copyImplicitOps(*I);

For example:

BC undef renamable $cr5lt, %bb.4
BLR implicit $lr, implicit $rm

Above case will be converted to:

BCLR $cr5lt, implicit $lr, implicit $rm

It;s obvious that the BCLR $cr5lt, implicit $lr, implicit $rm should be BCLR undef renamable $cr5lt, implicit $lr, implicit $rm.

[ZhangKang]

Rebase.

[steven.zhang]

LGTM.

[steven.zhang]

I notice that this revision has dependency with D76042. Can we break the dependency ?

[ZhangKang]

Break the dependency for D76042.

[ZhangKang]

In D77997#2033003, @steven.zhang wrote:

I notice that this revision has dependency with D76042. Can we break the dependency ?

Have broken the dependency for D76042 and updated the patch.

llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp

bool processBlock(MachineBasicBlock &ReturnMBB) {
             }
           } else if (J->getOpcode() == PPC::BCC) {
             if (J->getOperand(2).getMBB() == &ReturnMBB) {
               // This is a conditional branch to the return. Replace the branch
               // with a bclr.
               MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
               MI->setDesc(TII->get(PPC::BCCLR));
               MachineInstrBuilder(*ReturnMBB.getParent(), MI)
-                  .addImm(J->getOperand(0).getImm())
-                  .addReg(J->getOperand(1).getReg());
+                  .add(J->getOperand(0))
+                  .add(J->getOperand(1));
               (*PI)->insert(J, MI);
 
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();
               BlockChanged = true;
               ++NumBCLR;
               continue;
             }
           } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) {
             if (J->getOperand(1).getMBB() == &ReturnMBB) {
               // This is a conditional branch to the return. Replace the branch
               // with a bclr.
               MachineInstr *MI = ReturnMBB.getParent()->CloneMachineInstr(&*I);
               MI->setDesc(
                   TII->get(J->getOpcode() == PPC::BC ? PPC::BCLR : PPC::BCLRn));
               MachineInstrBuilder(*ReturnMBB.getParent(), MI)
-                  .addReg(J->getOperand(0).getReg());
+                  .add(J->getOperand(0));
               (*PI)->insert(J, MI);
 
               MachineBasicBlock::iterator K = J--;
               K->eraseFromParent();
               BlockChanged = true;
               ++NumBCLR;
               continue;
             }

llvm/test/CodeGen/PowerPC/early-ret-verify.mir

 # RUN: llc -mtriple powerpc64le-unknown-linux-gnu -run-pass=ppc-early-ret -o \
-# RUN:   - %s | FileCheck %s
+# RUN:   - %s -verify-machineinstrs | FileCheck %s
 
 ---
 name:            testEarlyRet
 body:             |
   bb.0.entry:
     successors: %bb.4(0x40000000), %bb.1(0x40000000)
   
     BC undef renamable $cr5lt, %bb.4
bb.3:
     renamable $cr5lt = CRAND killed renamable $cr0eq, killed renamable $cr1lt, implicit $cr1, implicit $cr0
     BCn killed renamable $cr5lt, %bb.2
   
   bb.4:
     BLR implicit $lr, implicit $rm
 
   ; CHECK-LABEL: testEarlyRet
   ; CHECK: bb.0.entry:
-  ; CHECK:   BCLR $cr5lt, implicit $lr, implicit $rm
+  ; CHECK:   BCLR undef renamable $cr5lt, implicit $lr, implicit $rm
   ; CHECK: bb.1:
   ; CHECK:   renamable $r3 = IMPLICIT_DEF
   ; CHECK:   renamable $r4 = IMPLICIT_DEF
   ; CHECK: bb.2:
   ; CHECK:   $r5 = OR $r4, $r4
   ; CHECK:   renamable $r4 = ADDIC killed $r4, 1, implicit-def $carry
   ; CHECK:   $r6 = OR $r3, $r3
   ; CHECK:   renamable $r3 = ADDZE killed $r3, implicit-def dead $carry, implicit killed $carry

llvm/test/CodeGen/PowerPC/early-ret.mir

body:             |
   bb.3:
     liveins: $v2
 
     BLR implicit $lr, implicit $rm, implicit killed $v2
 
   ; CHECK-LABEL: name: testBCLRn
   ; CHECK: bb.0.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f3, killed renamable $f4
-  ; CHECK:   BCLRn $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
+  ; CHECK:   BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.1.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
   ; CHECK:   BCLR killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.2:
   ; CHECK:   $v2 = VOR killed $v3, $v3
   ; CHECK:   BLR implicit $lr, implicit $rm, implicit killed $v2
 ...
 
body:             |
   bb.3:
     liveins: $v2
 
     BLR implicit $lr, implicit $rm, implicit killed $v2
 
   ; CHECK-LABEL: name: testBCLR
   ; CHECK: bb.0.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f3, killed renamable $f4
-  ; CHECK:   BCLR $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
+  ; CHECK:   BCLR killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.1.entry:
   ; CHECK:   renamable $cr0 = FCMPUS killed renamable $f1, killed renamable $f2
   ; CHECK:   BCLRn killed renamable $cr0eq, implicit $lr, implicit $rm, implicit killed $v2
   ; CHECK: bb.2:
   ; CHECK:   $v2 = VOR killed $v3, $v3
   ; CHECK:   BLR implicit $lr, implicit $rm, implicit killed $v2
 ...
 
body:             |
 
   bb.2:
     BLR implicit $lr, implicit $rm
 
   ; CHECK-LABEL: name: testBCCLR
   ; CHECK: bb.0.entry:
   ; CHECK: renamable $r4 = LI 0
   ; CHECK: renamable $cr0 = CMPLWI killed renamable $r4, 0
-  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm
+  ; CHECK: BCCLR 68, renamable $cr0, implicit $lr, implicit $rm
   ; CHECK: bb.1:
-  ; CHECK: BCCLR 68, $cr0, implicit $lr, implicit $rm
+  ; CHECK: BCCLR 68, killed renamable $cr0, implicit $lr, implicit $rm
   ; CHECK: BLR implicit $lr, implicit $rm
 ...