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Differential D77720

[ARM] Patterns for VQSHRN
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Authored by dmgreen on Apr 8 2020, 5:00 AM.

Details

Reviewers
SjoerdMeijer
samparker
ostannard
simon_tatham
Commits
rG2123bb843e4b: [ARM] Patterns for VQSHRN
Summary

Given a VQMOVN(VSHR), we can fold that into a VQSHRN simply enough using a few tablegen patterns.

Diff Detail

Event Timeline

dmgreen created this revision.Apr 8 2020, 5:00 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald TranscriptApr 8 2020, 5:00 AM
samparker added a comment.Apr 14 2020, 2:44 AM

Are you missing top-half tests?

dmgreen added a parent revision: D77590: [ARM] MVE saturating truncates.Apr 16 2020, 11:25 PM
Herald added a subscriber: danielkiss. · View Herald TranscriptApr 16 2020, 11:25 PM
dmgreen added a child revision: D77718: [ARM] Combines for VMOVN.Apr 16 2020, 11:26 PM
dmgreen updated this revision to Diff 260588.Apr 28 2020, 4:20 AM

I originally had these in the other order, having these patterns before the transforms that would create vqmovt's. I've switched the order, so the tests should now show it folding into vqshrnt.

Herald added a project: Restricted Project. · View Herald TranscriptApr 28 2020, 4:20 AM
dmgreen added a comment.May 14 2020, 3:12 AM

ping

samparker accepted this revision.May 14 2020, 6:19 AM

Cheers.

This revision is now accepted and ready to land.May 14 2020, 6:19 AM
Closed by commit rG2123bb843e4b: [ARM] Patterns for VQSHRN (authored by dmgreen). · Explain WhyMay 16 2020, 10:01 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
18 lines
test/
CodeGen/
Thumb2/
78 lines
24 lines

Diff 264446

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,731 Lines • ▼ Show 20 Lineslet Predicates = [HasMVEInt] in {
def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 0))), def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 0))),
(v8i16 (MVE_VQMOVNu32bh (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>; (v8i16 (MVE_VQMOVNu32bh (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>;
def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 1))), def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), (i32 1))),
(v8i16 (MVE_VQMOVNu32th (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>; (v8i16 (MVE_VQMOVNu32th (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm)))>;
def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 0))), def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 0))),
(v16i8 (MVE_VQMOVNu16bh (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>; (v16i8 (MVE_VQMOVNu16bh (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 1))), def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), (i32 1))),
(v16i8 (MVE_VQMOVNu16th (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>; (v16i8 (MVE_VQMOVNu16th (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm)))>;
def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
(v8i16 (MVE_VQSHRNbhs32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
(v16i8 (MVE_VQSHRNbhs16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
def : Pat<(v8i16 (MVEvqmovns (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshrsImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
(v8i16 (MVE_VQSHRNths32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
def : Pat<(v16i8 (MVEvqmovns (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshrsImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
(v16i8 (MVE_VQSHRNths16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 0))),
(v8i16 (MVE_VQSHRNbhu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 0))),
(v16i8 (MVE_VQSHRNbhu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
def : Pat<(v8i16 (MVEvqmovnu (v8i16 MQPR:$Qd_src), (v4i32 (ARMvshruImm (v4i32 MQPR:$Qm), imm0_31:$imm)), (i32 1))),
(v8i16 (MVE_VQSHRNthu32 (v8i16 MQPR:$Qd_src), (v4i32 MQPR:$Qm), imm0_31:$imm))>;
def : Pat<(v16i8 (MVEvqmovnu (v16i8 MQPR:$Qd_src), (v8i16 (ARMvshruImm (v8i16 MQPR:$Qm), imm0_15:$imm)), (i32 1))),
(v16i8 (MVE_VQSHRNthu16 (v16i8 MQPR:$Qd_src), (v8i16 MQPR:$Qm), imm0_15:$imm))>;
} }
class MVE_VCVT_ff<string iname, string suffix, bit op, bit T, class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
dag iops_extra, vpred_ops vpred, string cstr> dag iops_extra, vpred_ops vpred, string cstr>
: MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
!con(iops_extra, (ins MQPR:$Qm)), "$Qd, $Qm", !con(iops_extra, (ins MQPR:$Qm)), "$Qd, $Qm",
vpred, cstr, []> { vpred, cstr, []> {
let Inst{28} = op; let Inst{28} = op;
▲ Show 20 Lines • Show All 2,438 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

Show First 20 Lines • Show All 1,129 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1
; CHECK-NEXT: add.w r6, r1, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB5_4: @ %vector.body ; CHECK-NEXT: .LBB5_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.s32 q0, [r0], #8 ; CHECK-NEXT: vldrh.s32 q0, [r0], #8
; CHECK-NEXT: vldrh.s32 q1, [r1], #8 ; CHECK-NEXT: vldrh.s32 q1, [r1], #8
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vshr.s32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vstrh.32 q0, [r2], #8 ; CHECK-NEXT: vstrh.32 q0, [r2], #8
; CHECK-NEXT: le lr, .LBB5_4 ; CHECK-NEXT: le lr, .LBB5_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB5_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB5_6: @ %for.body.preheader21
; CHECK-NEXT: movw r0, #32768 ; CHECK-NEXT: movw r0, #32768
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; CHECK-NEXT: add.w r6, r1, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB6_4: @ %vector.body ; CHECK-NEXT: .LBB6_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.s32 q0, [r0, #8] ; CHECK-NEXT: vldrh.s32 q0, [r0, #8]
; CHECK-NEXT: vldrh.s32 q1, [r1, #8] ; CHECK-NEXT: vldrh.s32 q1, [r1, #8]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r1], #16 ; CHECK-NEXT: vldrh.s32 q1, [r1], #16
; CHECK-NEXT: vshr.s32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vstrh.32 q0, [r2, #8] ; CHECK-NEXT: vstrh.32 q0, [r2, #8]
; CHECK-NEXT: vldrh.s32 q0, [r0], #16 ; CHECK-NEXT: vldrh.s32 q0, [r0], #16
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vshr.s32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vstrh.32 q0, [r2], #16 ; CHECK-NEXT: vstrh.32 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB6_4 ; CHECK-NEXT: le lr, .LBB6_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21
; CHECK-NEXT: movw r0, #32768 ; CHECK-NEXT: movw r0, #32768
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add.w r6, r1, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB7_4: @ %vector.body ; CHECK-NEXT: .LBB7_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q0, [r0], #16 ; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.u16 q1, [r1], #16 ; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vmullt.s16 q2, q1, q0 ; CHECK-NEXT: vmullt.s16 q2, q1, q0
; CHECK-NEXT: vmullb.s16 q0, q1, q0 ; CHECK-NEXT: vmullb.s16 q0, q1, q0
; CHECK-NEXT: vshr.s32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vshr.s32 q2, q2, #15
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vqmovnt.s32 q0, q2 ; CHECK-NEXT: vqshrnt.s32 q0, q2, #15
; CHECK-NEXT: vstrb.8 q0, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB7_4 ; CHECK-NEXT: le lr, .LBB7_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB7_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB7_6: @ %for.body.preheader21
; CHECK-NEXT: movw r0, #32768 ; CHECK-NEXT: movw r0, #32768
▲ Show 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vdup.32 q2, r3 ; CHECK-NEXT: vdup.32 q2, r3
; CHECK-NEXT: adds r3, #4 ; CHECK-NEXT: adds r3, #4
; CHECK-NEXT: vorr q2, q2, q0 ; CHECK-NEXT: vorr q2, q2, q0
; CHECK-NEXT: vptt.u32 cs, q1, q2 ; CHECK-NEXT: vptt.u32 cs, q1, q2
; CHECK-NEXT: vldrht.s32 q2, [r0], #8 ; CHECK-NEXT: vldrht.s32 q2, [r0], #8
; CHECK-NEXT: vldrht.s32 q3, [r1], #8 ; CHECK-NEXT: vldrht.s32 q3, [r1], #8
; CHECK-NEXT: vmul.i32 q2, q3, q2 ; CHECK-NEXT: vmul.i32 q2, q3, q2
; CHECK-NEXT: vshr.s32 q2, q2, #15 ; CHECK-NEXT: vqshrnb.s32 q2, q2, #15
; CHECK-NEXT: vqmovnb.s32 q2, q2
; CHECK-NEXT: vmovlb.s16 q2, q2 ; CHECK-NEXT: vmovlb.s16 q2, q2
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.32 q2, [r2], #8 ; CHECK-NEXT: vstrht.32 q2, [r2], #8
; CHECK-NEXT: le lr, .LBB8_1 ; CHECK-NEXT: le lr, .LBB8_1
; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup ; CHECK-NEXT: @ %bb.2: @ %for.cond.cleanup
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov.32 q0[0], r4 ; CHECK-NEXT: vmov.32 q0[0], r4
; CHECK-NEXT: vmov.u16 r4, q7[1] ; CHECK-NEXT: vmov.u16 r4, q7[1]
; CHECK-NEXT: vmov.32 q0[1], r4 ; CHECK-NEXT: vmov.32 q0[1], r4
; CHECK-NEXT: vmov.u16 r4, q7[2] ; CHECK-NEXT: vmov.u16 r4, q7[2]
; CHECK-NEXT: vmov.32 q0[2], r4 ; CHECK-NEXT: vmov.32 q0[2], r4
; CHECK-NEXT: vmov.u16 r4, q7[3] ; CHECK-NEXT: vmov.u16 r4, q7[3]
; CHECK-NEXT: vmov.32 q0[3], r4 ; CHECK-NEXT: vmov.32 q0[3], r4
; CHECK-NEXT: vmullb.s16 q0, q0, q5 ; CHECK-NEXT: vmullb.s16 q0, q0, q5
; CHECK-NEXT: vshr.s32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vmov r4, s0 ; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vmov.16 q5[0], r4
; CHECK-NEXT: vmov r4, s1 ; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vmov.16 q5[1], r4 ; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vmov r4, s2 ; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: vmov.16 q5[2], r4 ; CHECK-NEXT: vmov.16 q5[2], r4
; CHECK-NEXT: vmov r4, s3 ; CHECK-NEXT: vmov r4, s3
Show All 10 Lines
; CHECK-NEXT: vmov.32 q6[0], r4 ; CHECK-NEXT: vmov.32 q6[0], r4
; CHECK-NEXT: vmov.u16 r4, q7[5] ; CHECK-NEXT: vmov.u16 r4, q7[5]
; CHECK-NEXT: vmov.32 q6[1], r4 ; CHECK-NEXT: vmov.32 q6[1], r4
; CHECK-NEXT: vmov.u16 r4, q7[6] ; CHECK-NEXT: vmov.u16 r4, q7[6]
; CHECK-NEXT: vmov.32 q6[2], r4 ; CHECK-NEXT: vmov.32 q6[2], r4
; CHECK-NEXT: vmov.u16 r4, q7[7] ; CHECK-NEXT: vmov.u16 r4, q7[7]
; CHECK-NEXT: vmov.32 q6[3], r4 ; CHECK-NEXT: vmov.32 q6[3], r4
; CHECK-NEXT: vmullb.s16 q0, q6, q0 ; CHECK-NEXT: vmullb.s16 q0, q6, q0
; CHECK-NEXT: vshr.s32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vmov r4, s0 ; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov.16 q5[4], r4 ; CHECK-NEXT: vmov.16 q5[4], r4
; CHECK-NEXT: vmov r4, s1 ; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vmov.16 q5[5], r4 ; CHECK-NEXT: vmov.16 q5[5], r4
; CHECK-NEXT: vmov r4, s2 ; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: vmov.16 q5[6], r4 ; CHECK-NEXT: vmov.16 q5[6], r4
; CHECK-NEXT: vmov r4, s3 ; CHECK-NEXT: vmov r4, s3
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; CHECK-NEXT: vmov.16 q5[6], r4 ; CHECK-NEXT: vmov.16 q5[6], r4
; CHECK-NEXT: vmov r4, s27 ; CHECK-NEXT: vmov r4, s27
; CHECK-NEXT: vmov.16 q5[7], r4 ; CHECK-NEXT: vmov.16 q5[7], r4
; CHECK-NEXT: vptt.i16 ne, q5, zr ; CHECK-NEXT: vptt.i16 ne, q5, zr
; CHECK-NEXT: vldrht.u16 q5, [r0], #16 ; CHECK-NEXT: vldrht.u16 q5, [r0], #16
; CHECK-NEXT: vldrht.u16 q6, [r1], #16 ; CHECK-NEXT: vldrht.u16 q6, [r1], #16
; CHECK-NEXT: vmullt.s16 q7, q6, q5 ; CHECK-NEXT: vmullt.s16 q7, q6, q5
; CHECK-NEXT: vmullb.s16 q5, q6, q5 ; CHECK-NEXT: vmullb.s16 q5, q6, q5
; CHECK-NEXT: vshr.s32 q7, q7, #15 ; CHECK-NEXT: vqshrnb.s32 q5, q5, #15
; CHECK-NEXT: vshr.s32 q5, q5, #15
; CHECK-NEXT: vqmovnb.s32 q5, q5
; CHECK-NEXT: vmovlb.s16 q5, q5 ; CHECK-NEXT: vmovlb.s16 q5, q5
; CHECK-NEXT: vqmovnt.s32 q5, q7 ; CHECK-NEXT: vqshrnt.s32 q5, q7, #15
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.16 q5, [r2], #16 ; CHECK-NEXT: vstrht.16 q5, [r2], #16
; CHECK-NEXT: le lr, .LBB10_2 ; CHECK-NEXT: le lr, .LBB10_2
; CHECK-NEXT: .LBB10_3: @ %for.cond.cleanup ; CHECK-NEXT: .LBB10_3: @ %for.cond.cleanup
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.4: ; CHECK-NEXT: @ %bb.4:
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; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1
; CHECK-NEXT: add.w r6, r1, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB11_4: @ %vector.body ; CHECK-NEXT: .LBB11_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u32 q0, [r0], #8 ; CHECK-NEXT: vldrh.u32 q0, [r0], #8
; CHECK-NEXT: vldrh.u32 q1, [r1], #8 ; CHECK-NEXT: vldrh.u32 q1, [r1], #8
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vshr.u32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.u32 q0, q0, #15
; CHECK-NEXT: vqmovnb.u32 q0, q0
; CHECK-NEXT: vstrh.32 q0, [r2], #8 ; CHECK-NEXT: vstrh.32 q0, [r2], #8
; CHECK-NEXT: le lr, .LBB11_4 ; CHECK-NEXT: le lr, .LBB11_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB11_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB11_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
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; CHECK-NEXT: add.w r6, r1, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB12_4: @ %vector.body ; CHECK-NEXT: .LBB12_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u32 q0, [r0, #8] ; CHECK-NEXT: vldrh.u32 q0, [r0, #8]
; CHECK-NEXT: vldrh.u32 q1, [r1, #8] ; CHECK-NEXT: vldrh.u32 q1, [r1, #8]
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vldrh.u32 q1, [r1], #16 ; CHECK-NEXT: vldrh.u32 q1, [r1], #16
; CHECK-NEXT: vshr.u32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.u32 q0, q0, #15
; CHECK-NEXT: vqmovnb.u32 q0, q0
; CHECK-NEXT: vstrh.32 q0, [r2, #8] ; CHECK-NEXT: vstrh.32 q0, [r2, #8]
; CHECK-NEXT: vldrh.u32 q0, [r0], #16 ; CHECK-NEXT: vldrh.u32 q0, [r0], #16
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vshr.u32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.u32 q0, q0, #15
; CHECK-NEXT: vqmovnb.u32 q0, q0
; CHECK-NEXT: vstrh.32 q0, [r2], #16 ; CHECK-NEXT: vstrh.32 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB12_4 ; CHECK-NEXT: le lr, .LBB12_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB12_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB12_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
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; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r4, r2, r5
; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB14_4: @ %vector.body ; CHECK-NEXT: .LBB14_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.s16 q0, [r0], #8 ; CHECK-NEXT: vldrb.s16 q0, [r0], #8
; CHECK-NEXT: vldrb.s16 q1, [r1], #8 ; CHECK-NEXT: vldrb.s16 q1, [r1], #8
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vshr.s16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2], #8 ; CHECK-NEXT: vstrb.16 q0, [r2], #8
; CHECK-NEXT: le lr, .LBB14_4 ; CHECK-NEXT: le lr, .LBB14_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB14_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB14_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
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; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB15_4: @ %vector.body ; CHECK-NEXT: .LBB15_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.s16 q0, [r0, #8] ; CHECK-NEXT: vldrb.s16 q0, [r0, #8]
; CHECK-NEXT: vldrb.s16 q1, [r1, #8] ; CHECK-NEXT: vldrb.s16 q1, [r1, #8]
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vldrb.s16 q1, [r1], #16 ; CHECK-NEXT: vldrb.s16 q1, [r1], #16
; CHECK-NEXT: vshr.s16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2, #8] ; CHECK-NEXT: vstrb.16 q0, [r2, #8]
; CHECK-NEXT: vldrb.s16 q0, [r0], #16 ; CHECK-NEXT: vldrb.s16 q0, [r0], #16
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vshr.s16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2], #16 ; CHECK-NEXT: vstrb.16 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB15_4 ; CHECK-NEXT: le lr, .LBB15_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
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; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB16_4: @ %vector.body ; CHECK-NEXT: .LBB16_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.u8 q0, [r0], #16 ; CHECK-NEXT: vldrb.u8 q0, [r0], #16
; CHECK-NEXT: vldrb.u8 q1, [r1], #16 ; CHECK-NEXT: vldrb.u8 q1, [r1], #16
; CHECK-NEXT: vmullt.s8 q2, q1, q0 ; CHECK-NEXT: vmullt.s8 q2, q1, q0
; CHECK-NEXT: vmullb.s8 q0, q1, q0 ; CHECK-NEXT: vmullb.s8 q0, q1, q0
; CHECK-NEXT: vshr.s16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vshr.s16 q2, q2, #7
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vqmovnt.s16 q0, q2 ; CHECK-NEXT: vqshrnt.s16 q0, q2, #7
; CHECK-NEXT: vstrb.8 q0, [r2], #16 ; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB16_4 ; CHECK-NEXT: le lr, .LBB16_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB16_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB16_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
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; CHECK-NEXT: vmov r4, s26 ; CHECK-NEXT: vmov r4, s26
; CHECK-NEXT: vmov.16 q5[6], r4 ; CHECK-NEXT: vmov.16 q5[6], r4
; CHECK-NEXT: vmov r4, s27 ; CHECK-NEXT: vmov r4, s27
; CHECK-NEXT: vmov.16 q5[7], r4 ; CHECK-NEXT: vmov.16 q5[7], r4
; CHECK-NEXT: vptt.i16 ne, q5, zr ; CHECK-NEXT: vptt.i16 ne, q5, zr
; CHECK-NEXT: vldrbt.s16 q5, [r0], #8 ; CHECK-NEXT: vldrbt.s16 q5, [r0], #8
; CHECK-NEXT: vldrbt.s16 q6, [r1], #8 ; CHECK-NEXT: vldrbt.s16 q6, [r1], #8
; CHECK-NEXT: vmul.i16 q5, q6, q5 ; CHECK-NEXT: vmul.i16 q5, q6, q5
; CHECK-NEXT: vshr.s16 q5, q5, #7 ; CHECK-NEXT: vqshrnb.s16 q5, q5, #7
; CHECK-NEXT: vqmovnb.s16 q5, q5
; CHECK-NEXT: vmovlb.s8 q5, q5 ; CHECK-NEXT: vmovlb.s8 q5, q5
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrbt.16 q5, [r2], #8 ; CHECK-NEXT: vstrbt.16 q5, [r2], #8
; CHECK-NEXT: le lr, .LBB17_2 ; CHECK-NEXT: le lr, .LBB17_2
; CHECK-NEXT: .LBB17_3: @ %for.cond.cleanup ; CHECK-NEXT: .LBB17_3: @ %for.cond.cleanup
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: vmov.16 q5[4], r4 ; CHECK-NEXT: vmov.16 q5[4], r4
; CHECK-NEXT: vmov.u8 r4, q4[5] ; CHECK-NEXT: vmov.u8 r4, q4[5]
; CHECK-NEXT: vmov.16 q5[5], r4 ; CHECK-NEXT: vmov.16 q5[5], r4
; CHECK-NEXT: vmov.u8 r4, q4[6] ; CHECK-NEXT: vmov.u8 r4, q4[6]
; CHECK-NEXT: vmov.16 q5[6], r4 ; CHECK-NEXT: vmov.16 q5[6], r4
; CHECK-NEXT: vmov.u8 r4, q4[7] ; CHECK-NEXT: vmov.u8 r4, q4[7]
; CHECK-NEXT: vmov.16 q5[7], r4 ; CHECK-NEXT: vmov.16 q5[7], r4
; CHECK-NEXT: vmullb.s8 q5, q5, q7 ; CHECK-NEXT: vmullb.s8 q5, q5, q7
; CHECK-NEXT: vshr.s16 q5, q5, #7 ; CHECK-NEXT: vqshrnb.s16 q5, q5, #7
; CHECK-NEXT: vqmovnb.s16 q5, q5
; CHECK-NEXT: vmovlb.s8 q5, q5 ; CHECK-NEXT: vmovlb.s8 q5, q5
; CHECK-NEXT: vmov.u16 r4, q5[0] ; CHECK-NEXT: vmov.u16 r4, q5[0]
; CHECK-NEXT: vmov.8 q7[0], r4 ; CHECK-NEXT: vmov.8 q7[0], r4
; CHECK-NEXT: vmov.u16 r4, q5[1] ; CHECK-NEXT: vmov.u16 r4, q5[1]
; CHECK-NEXT: vmov.8 q7[1], r4 ; CHECK-NEXT: vmov.8 q7[1], r4
; CHECK-NEXT: vmov.u16 r4, q5[2] ; CHECK-NEXT: vmov.u16 r4, q5[2]
; CHECK-NEXT: vmov.8 q7[2], r4 ; CHECK-NEXT: vmov.8 q7[2], r4
; CHECK-NEXT: vmov.u16 r4, q5[3] ; CHECK-NEXT: vmov.u16 r4, q5[3]
Show All 34 Lines
; CHECK-NEXT: vmov.16 q0[4], r4 ; CHECK-NEXT: vmov.16 q0[4], r4
; CHECK-NEXT: vmov.u8 r4, q4[13] ; CHECK-NEXT: vmov.u8 r4, q4[13]
; CHECK-NEXT: vmov.16 q0[5], r4 ; CHECK-NEXT: vmov.16 q0[5], r4
; CHECK-NEXT: vmov.u8 r4, q4[14] ; CHECK-NEXT: vmov.u8 r4, q4[14]
; CHECK-NEXT: vmov.16 q0[6], r4 ; CHECK-NEXT: vmov.16 q0[6], r4
; CHECK-NEXT: vmov.u8 r4, q4[15] ; CHECK-NEXT: vmov.u8 r4, q4[15]
; CHECK-NEXT: vmov.16 q0[7], r4 ; CHECK-NEXT: vmov.16 q0[7], r4
; CHECK-NEXT: vmullb.s8 q0, q0, q5 ; CHECK-NEXT: vmullb.s8 q0, q0, q5
; CHECK-NEXT: vshr.s16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmov.u16 r4, q0[0] ; CHECK-NEXT: vmov.u16 r4, q0[0]
; CHECK-NEXT: vmov.8 q7[8], r4 ; CHECK-NEXT: vmov.8 q7[8], r4
; CHECK-NEXT: vmov.u16 r4, q0[1] ; CHECK-NEXT: vmov.u16 r4, q0[1]
; CHECK-NEXT: vmov.8 q7[9], r4 ; CHECK-NEXT: vmov.8 q7[9], r4
; CHECK-NEXT: vmov.u16 r4, q0[2] ; CHECK-NEXT: vmov.u16 r4, q0[2]
; CHECK-NEXT: vmov.8 q7[10], r4 ; CHECK-NEXT: vmov.8 q7[10], r4
; CHECK-NEXT: vmov.u16 r4, q0[3] ; CHECK-NEXT: vmov.u16 r4, q0[3]
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; CHECK-NEXT: vmov.8 q7[14], r4 ; CHECK-NEXT: vmov.8 q7[14], r4
; CHECK-NEXT: vmov.u16 r4, q0[7] ; CHECK-NEXT: vmov.u16 r4, q0[7]
; CHECK-NEXT: vmov.8 q7[15], r4 ; CHECK-NEXT: vmov.8 q7[15], r4
; CHECK-NEXT: vptt.i8 ne, q7, zr ; CHECK-NEXT: vptt.i8 ne, q7, zr
; CHECK-NEXT: vldrbt.u8 q0, [r0], #16 ; CHECK-NEXT: vldrbt.u8 q0, [r0], #16
; CHECK-NEXT: vldrbt.u8 q4, [r1], #16 ; CHECK-NEXT: vldrbt.u8 q4, [r1], #16
; CHECK-NEXT: vmullt.s8 q5, q4, q0 ; CHECK-NEXT: vmullt.s8 q5, q4, q0
; CHECK-NEXT: vmullb.s8 q0, q4, q0 ; CHECK-NEXT: vmullb.s8 q0, q4, q0
; CHECK-NEXT: vshr.s16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vshr.s16 q5, q5, #7
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vqmovnt.s16 q0, q5 ; CHECK-NEXT: vqshrnt.s16 q0, q5, #7
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrbt.8 q0, [r2], #16 ; CHECK-NEXT: vstrbt.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB19_2 ; CHECK-NEXT: le lr, .LBB19_2
; CHECK-NEXT: .LBB19_3: @ %for.cond.cleanup ; CHECK-NEXT: .LBB19_3: @ %for.cond.cleanup
; CHECK-NEXT: add sp, #56 ; CHECK-NEXT: add sp, #56
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r4, r2, r5
; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB20_4: @ %vector.body ; CHECK-NEXT: .LBB20_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.u16 q0, [r0], #8 ; CHECK-NEXT: vldrb.u16 q0, [r0], #8
; CHECK-NEXT: vldrb.u16 q1, [r1], #8 ; CHECK-NEXT: vldrb.u16 q1, [r1], #8
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vshr.u16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
; CHECK-NEXT: vqmovnb.u16 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2], #8 ; CHECK-NEXT: vstrb.16 q0, [r2], #8
; CHECK-NEXT: le lr, .LBB20_4 ; CHECK-NEXT: le lr, .LBB20_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB20_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB20_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
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; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: dls lr, lr ; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB21_4: @ %vector.body ; CHECK-NEXT: .LBB21_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.u16 q0, [r0, #8] ; CHECK-NEXT: vldrb.u16 q0, [r0, #8]
; CHECK-NEXT: vldrb.u16 q1, [r1, #8] ; CHECK-NEXT: vldrb.u16 q1, [r1, #8]
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vldrb.u16 q1, [r1], #16 ; CHECK-NEXT: vldrb.u16 q1, [r1], #16
; CHECK-NEXT: vshr.u16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
; CHECK-NEXT: vqmovnb.u16 q0, q0
; CHECK-NEXT: vmovlb.u8 q0, q0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2, #8] ; CHECK-NEXT: vstrb.16 q0, [r2, #8]
; CHECK-NEXT: vldrb.u16 q0, [r0], #16 ; CHECK-NEXT: vldrb.u16 q0, [r0], #16
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vshr.u16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
; CHECK-NEXT: vqmovnb.u16 q0, q0
; CHECK-NEXT: vmovlb.u8 q0, q0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2], #16 ; CHECK-NEXT: vstrb.16 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB21_4 ; CHECK-NEXT: le lr, .LBB21_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB21_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB21_6: @ %for.body.preheader23
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llvm/test/CodeGen/Thumb2/mve-vqshrn.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_smaxmin(<4 x i32> %so) { define arm_aapcs_vfpcc <4 x i32> @vqshrni32_smaxmin(<4 x i32> %so) {
; CHECK-LABEL: vqshrni32_smaxmin: ; CHECK-LABEL: vqshrni32_smaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.s32 q0, q0, #3 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #3
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3> %s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
%c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767> %c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
%c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768> %c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768> %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
ret <4 x i32> %s2 ret <4 x i32> %s2
} }
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_sminmax(<4 x i32> %so) { define arm_aapcs_vfpcc <4 x i32> @vqshrni32_sminmax(<4 x i32> %so) {
; CHECK-LABEL: vqshrni32_sminmax: ; CHECK-LABEL: vqshrni32_sminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.s32 q0, q0, #3 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #3
; CHECK-NEXT: vqmovnb.s32 q0, q0
; CHECK-NEXT: vmovlb.s16 q0, q0 ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3> %s0 = ashr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
%c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768> %c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768> %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
%c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767> %c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>
%s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767> %s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
ret <4 x i32> %s2 ret <4 x i32> %s2
} }
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_umaxmin(<4 x i32> %so) { define arm_aapcs_vfpcc <4 x i32> @vqshrni32_umaxmin(<4 x i32> %so) {
; CHECK-LABEL: vqshrni32_umaxmin: ; CHECK-LABEL: vqshrni32_umaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.u32 q0, q0, #3 ; CHECK-NEXT: vqshrnb.u32 q0, q0, #3
; CHECK-NEXT: vqmovnb.u32 q0, q0
; CHECK-NEXT: vmovlb.u16 q0, q0 ; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3> %s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
%c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535> %c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> %s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %s1 ret <4 x i32> %s1
} }
define arm_aapcs_vfpcc <4 x i32> @vqshrni32_uminmax(<4 x i32> %so) { define arm_aapcs_vfpcc <4 x i32> @vqshrni32_uminmax(<4 x i32> %so) {
; CHECK-LABEL: vqshrni32_uminmax: ; CHECK-LABEL: vqshrni32_uminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.u32 q0, q0, #3 ; CHECK-NEXT: vqshrnb.u32 q0, q0, #3
; CHECK-NEXT: vqmovnb.u32 q0, q0
; CHECK-NEXT: vmovlb.u16 q0, q0 ; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3> %s0 = lshr <4 x i32> %so, <i32 3, i32 3, i32 3, i32 3>
%c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535> %c2 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
%s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535> %s2 = select <4 x i1> %c2, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %s2 ret <4 x i32> %s2
} }
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_smaxmin(<8 x i16> %so) { define arm_aapcs_vfpcc <8 x i16> @vqshrni16_smaxmin(<8 x i16> %so) {
; CHECK-LABEL: vqshrni16_smaxmin: ; CHECK-LABEL: vqshrni16_smaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.s16 q0, q0, #3 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #3
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
%c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> %c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
%s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
ret <8 x i16> %s2 ret <8 x i16> %s2
} }
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_sminmax(<8 x i16> %so) { define arm_aapcs_vfpcc <8 x i16> @vqshrni16_sminmax(<8 x i16> %so) {
; CHECK-LABEL: vqshrni16_sminmax: ; CHECK-LABEL: vqshrni16_sminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.s16 q0, q0, #3 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #3
; CHECK-NEXT: vqmovnb.s16 q0, q0
; CHECK-NEXT: vmovlb.s8 q0, q0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %s0 = ashr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
%c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> %c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128> %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
%c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
ret <8 x i16> %s2 ret <8 x i16> %s2
} }
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_umaxmin(<8 x i16> %so) { define arm_aapcs_vfpcc <8 x i16> @vqshrni16_umaxmin(<8 x i16> %so) {
; CHECK-LABEL: vqshrni16_umaxmin: ; CHECK-LABEL: vqshrni16_umaxmin:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.u16 q0, q0, #3 ; CHECK-NEXT: vqshrnb.u16 q0, q0, #3
; CHECK-NEXT: vqmovnb.u16 q0, q0
; CHECK-NEXT: vmovlb.u8 q0, q0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
%c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %s1 ret <8 x i16> %s1
} }
define arm_aapcs_vfpcc <8 x i16> @vqshrni16_uminmax(<8 x i16> %so) { define arm_aapcs_vfpcc <8 x i16> @vqshrni16_uminmax(<8 x i16> %so) {
; CHECK-LABEL: vqshrni16_uminmax: ; CHECK-LABEL: vqshrni16_uminmax:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vshr.u16 q0, q0, #3 ; CHECK-NEXT: vqshrnb.u16 q0, q0, #3
; CHECK-NEXT: vqmovnb.u16 q0, q0
; CHECK-NEXT: vmovlb.u8 q0, q0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %s0 = lshr <8 x i16> %so, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
%c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %c2 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
%s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %s2 = select <8 x i1> %c2, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %s2 ret <8 x i16> %s2
} }
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