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Differential D77210

[GlobalISel] Combine sext([sz]ext) -> [sz]ext, zext(zext) -> zext
ClosedPublic

Authored by gargaroff on Apr 1 2020, 4:13 AM.

Details

Reviewers
arsenm
volkan
aemerson
aditya_nandakumar
Commits
rG432720f1c4c6: [GlobalISel] Combine sext([sz]ext) -> [sz]ext, zext(zext) -> zext
Summary

Combine sext(zext x) to (zext x) since the sign-bit is 0
after the zero-extension.

Combine sext(sext x) to (sext x) and ext(zext x) to (zext x)
since the intermediate step is not needed.

Diff Detail

Event Timeline

gargaroff created this revision.Apr 1 2020, 4:13 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 1 2020, 4:13 AM
Herald added subscribers: llvm-commits, kerbowa, rovka and 3 others. · View Herald Transcript
gargaroff updated this revision to Diff 254163.Apr 1 2020, 4:16 AM

Remove unrelated changes

Harbormaster completed remote builds in B51276: Diff 254163.Apr 1 2020, 4:58 AM
Harbormaster completed remote builds in B51275: Diff 254161.
arsenm added inline comments.Apr 1 2020, 8:55 AM
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
128

Can you just replace the source?

180

Why the m_all_of?

gargaroff updated this revision to Diff 254466.Apr 2 2020, 2:43 AM
gargaroff marked an inline comment as done.

Add DstReg to UpdatedDefs

Replace source

gargaroff marked an inline comment as done.Apr 2 2020, 2:43 AM
gargaroff added inline comments.
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
180

This is needed to get the matched extension instruction. I didn't find any other way to easily get the instruction. Using it in place of m_Reg gives me the def of ExtSrc and I'm not aware of any matcher which give you the *matched* instruction. That's why I use m_all_of. This pattern is also used in tryCombineAnyExt.

Harbormaster completed remote builds in B51451: Diff 254466.Apr 2 2020, 3:45 AM
gargaroff added a comment.Apr 7 2020, 12:42 AM

Ping

arsenm accepted this revision.Apr 7 2020, 11:46 AM

Pattern seems convoluted to me, but OK I guess if it's already used

This revision is now accepted and ready to land.Apr 7 2020, 11:46 AM
Closed by commit rG432720f1c4c6: [GlobalISel] Combine sext([sz]ext) -> [sz]ext, zext(zext) -> zext (authored by gargaroff). · Explain WhyApr 8 2020, 2:40 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
27 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
48 lines
24 lines
24 lines

Diff 254161

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines bool tryCombineZExt(MachineInstr &MI,
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) { if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
LLT DstTy = MRI.getType(DstReg); LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) || if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
isConstantUnsupported(DstTy)) isConstantUnsupported(DstTy))
return false; return false;
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;); LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
APInt Mask = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits()); APInt Mask = APInt::getAllOnesValue(SrcTy.getScalarSizeInBits());
auto MIBMask = Builder.buildConstant( auto MIBMask =
DstTy, Mask.zext(DstTy.getScalarSizeInBits())); Builder.buildConstant(DstTy, Mask.zext(DstTy.getScalarSizeInBits()));
Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), Builder.buildAnd(DstReg, Builder.buildAnyExtOrTrunc(DstTy, TruncSrc),
MIBMask); MIBMask);
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true; return true;
} }
// zext(zext x) -> (zext x)
Register ZextSrc;
if (mi_match(SrcReg, MRI, m_GZExt(m_Reg(ZextSrc)))) {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
Builder.buildZExt(DstReg, ZextSrc);
arsenmUnsubmitted
Done
ReplyInline Actions

Can you just replace the source?

arsenm: Can you just replace the source?
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
}
// Try to fold zext(g_constant) when the larger constant type is legal. // Try to fold zext(g_constant) when the larger constant type is legal.
// Can't use MIPattern because we don't have a specific constant in mind. // Can't use MIPattern because we don't have a specific constant in mind.
auto *SrcMI = MRI.getVRegDef(SrcReg); auto *SrcMI = MRI.getVRegDef(SrcReg);
if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) { if (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) {
const LLT DstTy = MRI.getType(DstReg); const LLT DstTy = MRI.getType(DstReg);
if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) { if (isInstLegal({TargetOpcode::G_CONSTANT, {DstTy}})) {
auto &CstVal = SrcMI->getOperand(1); auto &CstVal = SrcMI->getOperand(1);
Builder.buildConstant( Builder.buildConstant(
Show All 25 Lines if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
LLT SrcTy = MRI.getType(SrcReg); LLT SrcTy = MRI.getType(SrcReg);
uint64_t SizeInBits = SrcTy.getScalarSizeInBits(); uint64_t SizeInBits = SrcTy.getScalarSizeInBits();
Builder.buildInstr( Builder.buildInstr(
TargetOpcode::G_SEXT_INREG, {DstReg}, TargetOpcode::G_SEXT_INREG, {DstReg},
{Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), SizeInBits}); {Builder.buildAnyExtOrTrunc(DstTy, TruncSrc), SizeInBits});
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts); markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true; return true;
} }
// sext(zext x) -> (zext x)
// sext(sext x) -> (sext x)
Register ExtSrc;
MachineInstr *ExtMI;
if (mi_match(SrcReg, MRI,
m_all_of(m_MInstr(ExtMI), m_any_of(m_GZExt(m_Reg(ExtSrc)),
arsenmUnsubmitted
Not Done
ReplyInline Actions

Why the m_all_of?

arsenm: Why the m_all_of?
gargaroffAuthorUnsubmitted
Done
ReplyInline Actions

This is needed to get the matched extension instruction. I didn't find any other way to easily get the instruction. Using it in place of m_Reg gives me the def of ExtSrc and I'm not aware of any matcher which give you the *matched* instruction. That's why I use m_all_of. This pattern is also used in tryCombineAnyExt.

gargaroff: This is needed to get the matched extension instruction. I didn't find any other way to easily…
m_GSExt(m_Reg(ExtSrc)))))) {
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI);
Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc});
markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
return true;
}
return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs); return tryFoldImplicitDef(MI, DeadInsts, UpdatedDefs);
} }
bool tryCombineTrunc(MachineInstr &MI, bool tryCombineTrunc(MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DeadInsts, SmallVectorImpl<MachineInstr *> &DeadInsts,
SmallVectorImpl<Register> &UpdatedDefs, SmallVectorImpl<Register> &UpdatedDefs,
GISelObserverWrapper &Observer) { GISelObserverWrapper &Observer) {
assert(MI.getOpcode() == TargetOpcode::G_TRUNC); assert(MI.getOpcode() == TargetOpcode::G_TRUNC);
▲ Show 20 Lines • Show All 578 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ext-legalizer.mir

Show All 29 Lines bb.0:
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[AND]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_TRUNC %0 %1:_(s32) = G_TRUNC %0
%2:_(s64) = G_ZEXT %1 %2:_(s64) = G_ZEXT %1
$vgpr0_vgpr1 = COPY %2 $vgpr0_vgpr1 = COPY %2
... ...
---
name: test_zext_zext_i32_i48_i64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_zext_zext_i32_i48_i64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s48) = G_ZEXT %0
%2:_(s64) = G_ZEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: test_sext_zext_i32_i48_i64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_zext_i32_i48_i64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s48) = G_ZEXT %0
%2:_(s64) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2
...
---
name: test_sext_sext_i32_i48_i64
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_sext_sext_i32_i48_i64
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(s32) = COPY $vgpr0
%1:_(s48) = G_SEXT %0
%2:_(s64) = G_SEXT %1
$vgpr0_vgpr1 = COPY %2
...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir

Show All 12 Lines bb.0:
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY3]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 7 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 7
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 7 ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 7
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8 ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 7
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]] ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 7
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 7
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 7
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 8
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 8
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG6]](s32), [[SEXT_INREG7]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]] ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK: $vgpr0 = COPY [[AND]](s32) ; CHECK: $vgpr0 = COPY [[AND]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
%4:_(s7), %5:_(s1) = G_SADDO %2, %3 %4:_(s7), %5:_(s1) = G_SADDO %2, %3
▲ Show 20 Lines • Show All 415 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir

Show All 12 Lines bb.0:
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY2]], [[COPY3]]
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 7 ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY4]], 7
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 7 ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY5]], 7
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG]](s32), [[SEXT_INREG1]]
; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 8 ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG1]](s32) ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY6]], 7
; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 8 ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]] ; CHECK: [[SEXT_INREG3:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY7]], 7
; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG2]](s32), [[SEXT_INREG3]]
; CHECK: [[SEXT_INREG4:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY8]], 7
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C]](s32)
; CHECK: [[SEXT_INREG5:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY9]], 7
; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG4]](s32)
; CHECK: [[SEXT_INREG6:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY10]], 8
; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SEXT_INREG5]](s32)
; CHECK: [[SEXT_INREG7:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY11]], 8
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SEXT_INREG6]](s32), [[SEXT_INREG7]]
; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]] ; CHECK: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[ICMP1]], [[ICMP]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[XOR]](s1)
; CHECK: $vgpr0 = COPY [[AND]](s32) ; CHECK: $vgpr0 = COPY [[AND]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
%4:_(s7), %5:_(s1) = G_SSUBO %2, %3 %4:_(s7), %5:_(s1) = G_SSUBO %2, %3
▲ Show 20 Lines • Show All 415 Lines • Show Last 20 Lines