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Differential D77019

AMDGPU/GlobalISel: Form CVT_F32_UBYTE0
ClosedPublic

Authored by arsenm on Mar 29 2020, 10:39 AM.

Details

Reviewers
nhaehnle
foad
kerbowa
hsmhsm

Diff Detail

Event Timeline

arsenm created this revision.Mar 29 2020, 10:39 AM
Herald added subscribers: hiraditya, t-tye, tpr and 6 others. · View Herald TranscriptMar 29 2020, 10:39 AM
arsenm added a parent revision: D77001: GlobalISel: Add accessor to known bits to CombinerHelper.Mar 29 2020, 10:39 AM
foad accepted this revision.Mar 30 2020, 1:06 AM

LGTM.

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
15

Is there a plan for removing this redundant AND?

This revision is now accepted and ready to land.Mar 30 2020, 1:06 AM
arsenm marked an inline comment as done.Mar 30 2020, 2:46 PM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir
15

We need a SimplifyDemandedBits equivalent somewhere

arsenm closed this revision.Mar 30 2020, 2:52 PM

b27d255e1e40bc065e68e39c6e1eaf3a5a16f005

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
9 lines
5 lines
37 lines
4 lines
8 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
175 lines

Diff 253436

llvm/lib/Target/AMDGPU/AMDGPUCombine.td

Show All 14 Lines
def fcmp_select_to_fmin_fmax_legacy : GICombineRule< def fcmp_select_to_fmin_fmax_legacy : GICombineRule<
(defs root:$select, fmin_fmax_legacy_matchdata:$matchinfo), (defs root:$select, fmin_fmax_legacy_matchdata:$matchinfo),
(match (wip_match_opcode G_SELECT):$select, (match (wip_match_opcode G_SELECT):$select,
[{ return matchFMinFMaxLegacy(*${select}, MRI, *MF, ${matchinfo}); }]), [{ return matchFMinFMaxLegacy(*${select}, MRI, *MF, ${matchinfo}); }]),
(apply [{ applySelectFCmpToFMinToFMaxLegacy(*${select}, ${matchinfo}); }])>; (apply [{ applySelectFCmpToFMinToFMaxLegacy(*${select}, ${matchinfo}); }])>;
def uchar_to_float : GICombineRule<
(defs root:$itofp),
(match (wip_match_opcode G_UITOFP, G_SITOFP):$itofp,
[{ return matchUCharToFloat(*${itofp}, MRI, *MF, Helper); }]),
(apply [{ applyUCharToFloat(*${itofp}); }])>;
// Combines which should only apply on SI/VI // Combines which should only apply on SI/VI
def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>; def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPreLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPreLegalizerCombinerHelper", [all_combines, "AMDGPUGenPreLegalizerCombinerHelper", [all_combines,
elide_br_by_inverting_cond]> { elide_br_by_inverting_cond]> {
let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpuprelegalizercombiner-disable-rule";
} }
def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper< def AMDGPUPostLegalizerCombinerHelper: GICombinerHelper<
"AMDGPUGenPostLegalizerCombinerHelper", [all_combines, "AMDGPUGenPostLegalizerCombinerHelper", [all_combines,
gfx6gfx7_combines]> { gfx6gfx7_combines, uchar_to_float]> {
let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule"; let DisableRuleOption = "amdgpupostlegalizercombiner-disable-rule";
} }

llvm/lib/Target/AMDGPU/AMDGPUGISel.td

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>; def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>;
def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>; def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>;
def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>; def : GINodeEquiv<G_AMDGPU_FFBH_U32, AMDGPUffbh_u32_impl>;
def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>; def : GINodeEquiv<G_AMDGPU_FMIN_LEGACY, AMDGPUfmin_legacy>;
def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>; def : GINodeEquiv<G_AMDGPU_FMAX_LEGACY, AMDGPUfmax_legacy>;
def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>; def : GINodeEquiv<G_AMDGPU_RCP_IFLAG, AMDGPUrcp_iflag>;
def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE0, AMDGPUcvt_f32_ubyte0>;
def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE1, AMDGPUcvt_f32_ubyte1>;
def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE2, AMDGPUcvt_f32_ubyte2>;
def : GINodeEquiv<G_AMDGPU_CVT_F32_UBYTE3, AMDGPUcvt_f32_ubyte3>;
def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>; def : GINodeEquiv<G_AMDGPU_ATOMIC_CMPXCHG, AMDGPUatomic_cmp_swap>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>; def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD, SIbuffer_load>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>; def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_USHORT, SIbuffer_load_ushort>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>; def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_UBYTE, SIbuffer_load_ubyte>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>; def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SSHORT, SIbuffer_load_short>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>; def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_SBYTE, SIbuffer_load_byte>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>; def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT, SIbuffer_load_format>;
def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>; def : GINodeEquiv<G_AMDGPU_BUFFER_LOAD_FORMAT_D16, SIbuffer_load_format_d16>;
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Linesstatic void applySelectFCmpToFMinToFMaxLegacy(MachineInstr &MI,
} }
default: default:
llvm_unreachable("predicate should not have matched"); llvm_unreachable("predicate should not have matched");
} }
MI.eraseFromParent(); MI.eraseFromParent();
} }
static bool matchUCharToFloat(MachineInstr &MI, MachineRegisterInfo &MRI,
MachineFunction &MF, CombinerHelper &Helper) {
Register DstReg = MI.getOperand(0).getReg();
// TODO: We could try to match extracting the higher bytes, which would be
// easier if i8 vectors weren't promoted to i32 vectors, particularly after
// types are legalized. v4i8 -> v4f32 is probably the only case to worry
// about in practice.
LLT Ty = MRI.getType(DstReg);
if (Ty == LLT::scalar(32) || Ty == LLT::scalar(16)) {
const APInt Mask = APInt::getHighBitsSet(32, 24);
return Helper.getKnownBits()->maskedValueIsZero(MI.getOperand(1).getReg(),
Mask);
}
return false;
}
static void applyUCharToFloat(MachineInstr &MI) {
MachineIRBuilder B(MI);
const LLT S32 = LLT::scalar(32);
Register DstReg = MI.getOperand(0).getReg();
LLT Ty = B.getMRI()->getType(DstReg);
if (Ty == S32) {
B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {DstReg},
{MI.getOperand(1)}, MI.getFlags());
} else {
auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32},
{MI.getOperand(1)}, MI.getFlags());
B.buildFPTrunc(DstReg, Cvt0, MI.getFlags());
}
MI.eraseFromParent();
}
#define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
#include "AMDGPUGenPostLegalizeGICombiner.inc" #include "AMDGPUGenPostLegalizeGICombiner.inc"
#undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS #undef AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
namespace { namespace {
#define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H #define AMDGPUPOSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
#include "AMDGPUGenPostLegalizeGICombiner.inc" #include "AMDGPUGenPostLegalizeGICombiner.inc"
▲ Show 20 Lines • Show All 124 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 3,282 Lines • ▼ Show 20 LinesAMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_FMAXNUM_IEEE: case AMDGPU::G_FMAXNUM_IEEE:
case AMDGPU::G_FCANONICALIZE: case AMDGPU::G_FCANONICALIZE:
case AMDGPU::G_INTRINSIC_TRUNC: case AMDGPU::G_INTRINSIC_TRUNC:
case AMDGPU::G_BSWAP: // TODO: Somehow expand for scalar? case AMDGPU::G_BSWAP: // TODO: Somehow expand for scalar?
case AMDGPU::G_AMDGPU_FFBH_U32: case AMDGPU::G_AMDGPU_FFBH_U32:
case AMDGPU::G_AMDGPU_FMIN_LEGACY: case AMDGPU::G_AMDGPU_FMIN_LEGACY:
case AMDGPU::G_AMDGPU_FMAX_LEGACY: case AMDGPU::G_AMDGPU_FMAX_LEGACY:
case AMDGPU::G_AMDGPU_RCP_IFLAG: case AMDGPU::G_AMDGPU_RCP_IFLAG:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE0:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE1:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE2:
case AMDGPU::G_AMDGPU_CVT_F32_UBYTE3:
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
case AMDGPU::G_UMULH: case AMDGPU::G_UMULH:
case AMDGPU::G_SMULH: { case AMDGPU::G_SMULH: {
if (Subtarget.hasScalarMulHiInsts() && isSALUMapping(MI)) if (Subtarget.hasScalarMulHiInsts() && isSALUMapping(MI))
return getDefaultMappingSOP(MI); return getDefaultMappingSOP(MI);
return getDefaultMappingVOP(MI); return getDefaultMappingVOP(MI);
} }
case AMDGPU::G_IMPLICIT_DEF: { case AMDGPU::G_IMPLICIT_DEF: {
▲ Show 20 Lines • Show All 804 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 2,291 Lines • ▼ Show 20 Lines
} }
def G_AMDGPU_FMAX_LEGACY : AMDGPUGenericInstruction { def G_AMDGPU_FMAX_LEGACY : AMDGPUGenericInstruction {
let OutOperandList = (outs type0:$dst); let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1); let InOperandList = (ins type0:$src0, type0:$src1);
let hasSideEffects = 0; let hasSideEffects = 0;
} }
foreach N = 0-3 in {
def G_AMDGPU_CVT_F32_UBYTE#N : AMDGPUGenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0);
let hasSideEffects = 0;
}
}
// Atomic cmpxchg. $cmpval ad $newval are packed in a single vector // Atomic cmpxchg. $cmpval ad $newval are packed in a single vector
// operand Expects a MachineMemOperand in addition to explicit // operand Expects a MachineMemOperand in addition to explicit
// operands. // operands.
def G_AMDGPU_ATOMIC_CMPXCHG : AMDGPUGenericInstruction { def G_AMDGPU_ATOMIC_CMPXCHG : AMDGPUGenericInstruction {
let OutOperandList = (outs type0:$oldval); let OutOperandList = (outs type0:$oldval);
let InOperandList = (ins ptype1:$addr, type0:$cmpval_newval); let InOperandList = (ins ptype1:$addr, type0:$cmpval_newval);
let hasSideEffects = 0; let hasSideEffects = 0;
let mayLoad = 1; let mayLoad = 1;
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-itofp.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: uitofp_char_to_f32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: uitofp_char_to_f32
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
foadUnsubmitted
Not Done
ReplyInline Actions

Is there a plan for removing this redundant AND?

foad: Is there a plan for removing this redundant AND?
arsenmAuthorUnsubmitted
Done
ReplyInline Actions

We need a SimplifyDemandedBits equivalent somewhere

arsenm: We need a SimplifyDemandedBits equivalent somewhere
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_AND %0, %1
%3:_(s32) = G_UITOFP %2
$vgpr0 = COPY %3
...
---
name: uitofp_too_many_bits_to_f32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: uitofp_too_many_bits_to_f32
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[AND]](s32)
; CHECK: $vgpr0 = COPY [[UITOFP]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 256
%2:_(s32) = G_AND %0, %1
%3:_(s32) = G_UITOFP %2
$vgpr0 = COPY %3
...
---
name: sitofp_char_to_f32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: sitofp_char_to_f32
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_AND %0, %1
%3:_(s32) = G_SITOFP %2
$vgpr0 = COPY %3
...
---
name: sitofp_bits127_to_f32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: sitofp_bits127_to_f32
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 127
%2:_(s32) = G_AND %0, %1
%3:_(s32) = G_SITOFP %2
$vgpr0 = COPY %3
...
---
name: sitofp_bits128_to_f32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: sitofp_bits128_to_f32
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
; CHECK: $vgpr0 = COPY [[AMDGPU_CVT_F32_UBYTE0_]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 128
%2:_(s32) = G_AND %0, %1
%3:_(s32) = G_SITOFP %2
$vgpr0 = COPY %3
...
---
name: sitofp_too_many_bits_to_f32
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: sitofp_too_many_bits_to_f32
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[SITOFP:%[0-9]+]]:_(s32) = G_SITOFP [[AND]](s32)
; CHECK: $vgpr0 = COPY [[SITOFP]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 256
%2:_(s32) = G_AND %0, %1
%3:_(s32) = G_SITOFP %2
$vgpr0 = COPY %3
...
---
name: uitofp_char_to_f16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: uitofp_char_to_f16
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_AND %0, %1
%3:_(s16) = G_UITOFP %2
%4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4
...
---
name: sitofp_char_to_f16
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: sitofp_char_to_f16
; CHECK: liveins: $vgpr0
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
; CHECK: [[AMDGPU_CVT_F32_UBYTE0_:%[0-9]+]]:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 [[AND]]
; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[AMDGPU_CVT_F32_UBYTE0_]](s32)
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CONSTANT i32 255
%2:_(s32) = G_AND %0, %1
%3:_(s16) = G_SITOFP %2
%4:_(s32) = G_ANYEXT %3
$vgpr0 = COPY %4
...