[ARM][MVE] Add DoubleWidthResult flag

[samparker]

Summary

Add a flag for those instructions which read from the top/bottom halves of their inputs and produce a vector of results of double width elements.

[samparker]

Rebased.

[SjoerdMeijer]

Looks reasonable to me.

llvm/lib/Target/ARM/ARMInstrFormats.td

class InstTemplate<AddrMode am, int sz, IndexMode im,
   bit canXformTo16Bit = 0;
   // The instruction is a 16-bit flag setting Thumb instruction. Used
   // by the parser to determine whether to require the 'S' suffix on the
   // mnemonic (when not in an IT block) or preclude it (when in an IT block).
   bit thumbArithFlagSetting = 0;
 
   bit validForTailPredication = 0;
   bit retainsPreviousHalfElement = 0;
+  bit doubleWidthResult = 0;
 
   // If this is a pseudo instruction, mark it isCodeGenOnly.
   let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
 
   // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
   let TSFlags{4-0}   = AM.Value;
   let TSFlags{6-5}   = IndexModeBits;
   let TSFlags{12-7} = Form;
   let TSFlags{13}    = isUnaryDataProc;
   let TSFlags{14}    = canXformTo16Bit;
   let TSFlags{18-15} = D.Value;
   let TSFlags{19}    = thumbArithFlagSetting;
   let TSFlags{20}    = validForTailPredication;
   let TSFlags{21}    = retainsPreviousHalfElement;
+  let TSFlags{22}    = doubleWidthResult;
 
   let Constraints = cstr;
   let Itinerary = itin;
 }
 
 class Encoding {
   field bits<32> Inst;
   // Mask of bits that cause an encoding to be UNPREDICTABLE.

llvm/lib/Target/ARM/ARMInstrMVE.td

   let Inst{25-23} = 0b101;
   let Inst{21} = 0b1;
   let Inst{20-19} = sz{1-0};
   let Inst{18-16} = 0b000;
   let Inst{12} = top;
   let Inst{11-6} = 0b111101;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let doubleWidthResult = 1;
 }
 
 multiclass MVE_VMOVL_m<bit top, string chr, MVEVectorVTInfo OutVTI,
                        MVEVectorVTInfo InVTI> {
   def "": MVE_VMOVL<"vmovl" # chr, InVTI.Suffix, OutVTI.Size,
                     InVTI.Unsigned, top>;
   defvar Inst = !cast<Instruction>(NAME);
 

   let Inst{21} = 0b1;
   let Inst{12} = th;
   let Inst{11-6} = 0b111101;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
 
   // For the MVE_VSHLL_patterns multiclass to refer to
   Operand immediateType = immtype;
+
+  let doubleWidthResult = 1;
 }
 
 // The immediate VSHLL instructions accept shift counts from 1 up to
 // the lane width (8 or 16), but the full-width shifts have an
 // entirely separate encoding, given below with 'lw' in the name.
 
 class MVE_VSHLL_imm8<string iname, string suffix,
                      bit U, bit th, list<dag> pattern=[]>

   let Inst{28} = U;
   let Inst{25-23} = 0b100;
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size{1-0};
   let Inst{17-16} = 0b01;
   let Inst{11-6} = 0b111000;
   let Inst{4} = 0b0;
   let Inst{0} = 0b1;
+  let doubleWidthResult = 1;
 }
 
 multiclass MVE_VSHLL_lw<string iname, string suffix, bits<2> sz, bit U,
                               string ops, list<dag> pattern=[]> {
   def bh : MVE_VSHLL_by_lane_width<iname#"b", suffix, sz, U, ops, pattern> {
     let Inst{12} = 0b0;
   }
   def th : MVE_VSHLL_by_lane_width<iname#"t", suffix, sz, U, ops, pattern> {

   let Inst{21-20} = bits_21_20;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b1;
   let Inst{12} = T;
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b0;
   let validForTailPredication = 1;
+  let doubleWidthResult = 1;
 }
 
 multiclass MVE_VMULL_m<MVEVectorVTInfo VTI,
                        SDNode unpred_op, Intrinsic pred_int,
                        bit Top, string cstr=""> {
   def "" : MVE_VMULL<"vmull" # !if(Top, "t", "b"), VTI.Suffix, VTI.Unsigned,
                      VTI.Size, Top, cstr>;
   defvar Inst = !cast<Instruction>(NAME);

   let Inst{21-20} = 0b11;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = T;
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b1;
   let validForTailPredication = 1;
+  let doubleWidthResult = 1;
 }
 
 multiclass MVE_VQDMULL_m<string iname, MVEVectorVTInfo VTI, bit size, bit T,
                          string cstr> {
   def "" : MVE_VQDMULL<iname, VTI.Suffix, size, T, cstr>;
   defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {

 
   let Inst{28} = size;
   let Inst{21-20} = 0b11;
   let Inst{16} = 0b0;
   let Inst{12} = T;
   let Inst{8} = 0b1;
   let Inst{5} = 0b1;
   let validForTailPredication = 1;
+  let doubleWidthResult = 1;
 }
 
 multiclass MVE_VQDMULL_qr_m<string iname, MVEVectorVTInfo VTI, bit size,
                             bit T, string cstr> {
   def "" : MVE_VQDMULL_qr<iname, VTI.Suffix, size, T, cstr>;
   defvar Inst = !cast<Instruction>(NAME);
 
   let Predicates = [HasMVEInt] in {

llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

namespace ARMII {
   };
 
   enum {
     //===------------------------------------------------------------------===//
     // Instruction Flags.
 
     //===------------------------------------------------------------------===//
     // This four-bit field describes the addressing mode used.
     AddrModeMask  = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
 
     // IndexMode - Unindex, pre-indexed, or post-indexed are valid for load
     // and store ops only.  Generic "updating" flag is used for ld/st multiple.
     // The index mode enums are declared in ARMBaseInfo.h
     IndexModeShift = 5,
     IndexModeMask  = 3 << IndexModeShift,
 
     //===------------------------------------------------------------------===//
     // Instruction encoding formats.
     //
     FormShift     = 7,
     FormMask      = 0x3f << FormShift,
 
     // Pseudo instructions
     Pseudo        = 0  << FormShift,
 
     // Multiply instructions
     MulFrm        = 1  << FormShift,
 
     // Branch instructions
     BrFrm         = 2  << FormShift,
     BrMiscFrm     = 3  << FormShift,
 
     // Data Processing instructions
     DPFrm         = 4  << FormShift,
     DPSoRegFrm    = 5  << FormShift,
 
     // Load and Store
     LdFrm         = 6  << FormShift,
     StFrm         = 7  << FormShift,
     LdMiscFrm     = 8  << FormShift,
     StMiscFrm     = 9  << FormShift,
     LdStMulFrm    = 10 << FormShift,
 
     LdStExFrm     = 11 << FormShift,
 
     // Miscellaneous arithmetic instructions
     ArithMiscFrm  = 12 << FormShift,
     SatFrm        = 13 << FormShift,
 
     // Extend instructions
     ExtFrm        = 14 << FormShift,
 
     // VFP formats
     VFPUnaryFrm   = 15 << FormShift,
     VFPBinaryFrm  = 16 << FormShift,
     VFPConv1Frm   = 17 << FormShift,
     VFPConv2Frm   = 18 << FormShift,
     VFPConv3Frm   = 19 << FormShift,
     VFPConv4Frm   = 20 << FormShift,
     VFPConv5Frm   = 21 << FormShift,
     VFPLdStFrm    = 22 << FormShift,
     VFPLdStMulFrm = 23 << FormShift,
     VFPMiscFrm    = 24 << FormShift,
 
     // Thumb format
     ThumbFrm      = 25 << FormShift,
 
     // Miscelleaneous format
     MiscFrm       = 26 << FormShift,
 
     // NEON formats
     NGetLnFrm     = 27 << FormShift,
     NSetLnFrm     = 28 << FormShift,
     NDupFrm       = 29 << FormShift,
     NLdStFrm      = 30 << FormShift,
     N1RegModImmFrm= 31 << FormShift,
     N2RegFrm      = 32 << FormShift,
     NVCVTFrm      = 33 << FormShift,
     NVDupLnFrm    = 34 << FormShift,
     N2RegVShLFrm  = 35 << FormShift,
     N2RegVShRFrm  = 36 << FormShift,
     N3RegFrm      = 37 << FormShift,
     N3RegVShFrm   = 38 << FormShift,
     NVExtFrm      = 39 << FormShift,
     NVMulSLFrm    = 40 << FormShift,
     NVTBLFrm      = 41 << FormShift,
     N3RegCplxFrm  = 43 << FormShift,
 
     //===------------------------------------------------------------------===//
     // Misc flags.
 
     // UnaryDP - Indicates this is a unary data processing instruction, i.e.
     // it doesn't have a Rn operand.
     UnaryDP       = 1 << 13,
 
     // Xform16Bit - Indicates this Thumb2 instruction may be transformed into
     // a 16-bit Thumb instruction if certain conditions are met.
     Xform16Bit    = 1 << 14,
 
     // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
     // instruction. Used by the parser to determine whether to require the 'S'
     // suffix on the mnemonic (when not in an IT block) or preclude it (when
     // in an IT block).
     ThumbArithFlagSetting = 1 << 19,
 
     // Whether an instruction can be included in an MVE tail-predicated loop.
     ValidForTailPredication = 1 << 20,
 
     // Whether an instruction writes to the top/bottom half of a vector element
     // and leaves the other half untouched.
     RetainsPreviousHalfElement = 1 << 21,
 
+    // Whether this instruction produces a vector result that is larger than
+    // its input, typically reading from the top/bottom halves of the input(s).
+    DoubleWidthResult = 1 << 22,
+
     //===------------------------------------------------------------------===//
     // Code domain.
     DomainShift   = 15,
     DomainMask    = 15 << DomainShift,
     DomainGeneral = 0 << DomainShift,
     DomainVFP     = 1 << DomainShift,
     DomainNEON    = 2 << DomainShift,
     DomainNEONA8  = 4 << DomainShift,
     DomainMVE     = 8 << DomainShift,
 
     //===------------------------------------------------------------------===//
     // Field shifts - such shifts are used to set field while generating
     // machine instructions.
     //
     // FIXME: This list will need adjusting/fixing as the MC code emitter
     // takes shape and the ARMCodeEmitter.cpp bits go away.
     ShiftTypeShift = 4,
 
     M_BitShift     = 5,
     ShiftImmShift  = 5,
     ShiftShift     = 7,
     N_BitShift     = 7,
     ImmHiShift     = 8,
     SoRotImmShift  = 8,
     RegRsShift     = 8,
     ExtRotImmShift = 10,
     RegRdLoShift   = 12,
     RegRdShift     = 12,
     RegRdHiShift   = 16,
     RegRnShift     = 16,
     S_BitShift     = 20,
     W_BitShift     = 21,
     AM3_I_BitShift = 22,
     D_BitShift     = 22,
     U_BitShift     = 23,
     P_BitShift     = 24,
     I_BitShift     = 25,
     CondShift      = 28
   };
 
 } // end namespace ARMII
 
 } // end namespace llvm;
 
 #endif

llvm/unittests/Target/ARM/MachineInstrTest.cpp

 #include "ARMBaseInstrInfo.h"
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
+TEST(MachineInstructionDoubleWidthResult, IsCorrect) {
+  using namespace ARM;
+
+  auto DoubleWidthResult = [](unsigned Opcode) {
+    switch (Opcode) {
+    default:
+      break;
+    case MVE_VMULLBp16:
+    case MVE_VMULLBp8:
+    case MVE_VMULLBs16:
+    case MVE_VMULLBs32:
+    case MVE_VMULLBs8:
+    case MVE_VMULLBu16:
+    case MVE_VMULLBu32:
+    case MVE_VMULLBu8:
+    case MVE_VMULLTp16:
+    case MVE_VMULLTp8:
+    case MVE_VMULLTs16:
+    case MVE_VMULLTs32:
+    case MVE_VMULLTs8:
+    case MVE_VMULLTu16:
+    case MVE_VMULLTu32:
+    case MVE_VMULLTu8:
+    case MVE_VQDMULL_qr_s16bh:
+    case MVE_VQDMULL_qr_s16th:
+    case MVE_VQDMULL_qr_s32bh:
+    case MVE_VQDMULL_qr_s32th:
+    case MVE_VQDMULLs16bh:
+    case MVE_VQDMULLs16th:
+    case MVE_VQDMULLs32bh:
+    case MVE_VQDMULLs32th:
+    case MVE_VMOVLs16bh:
+    case MVE_VMOVLs16th:
+    case MVE_VMOVLs8bh:
+    case MVE_VMOVLs8th:
+    case MVE_VMOVLu16bh:
+    case MVE_VMOVLu16th:
+    case MVE_VMOVLu8bh:
+    case MVE_VMOVLu8th:
+    case MVE_VSHLL_imms16bh:
+    case MVE_VSHLL_imms16th:
+    case MVE_VSHLL_imms8bh:
+    case MVE_VSHLL_imms8th:
+    case MVE_VSHLL_immu16bh:
+    case MVE_VSHLL_immu16th:
+    case MVE_VSHLL_immu8bh:
+    case MVE_VSHLL_immu8th:
+    case MVE_VSHLL_lws16bh:
+    case MVE_VSHLL_lws16th:
+    case MVE_VSHLL_lws8bh:
+    case MVE_VSHLL_lws8th:
+    case MVE_VSHLL_lwu16bh:
+    case MVE_VSHLL_lwu16th:
+    case MVE_VSHLL_lwu8bh:
+    case MVE_VSHLL_lwu8th:
+      return true;
+    }
+    return false;
+  };
+
+  LLVMInitializeARMTargetInfo();
+  LLVMInitializeARMTarget();
+  LLVMInitializeARMTargetMC();
+
+  auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
+  std::string Error;
+  const Target *T = TargetRegistry::lookupTarget(TT, Error);
+  if (!T) {
+    dbgs() << Error;
+    return;
+  }
+
+  TargetOptions Options;
+  auto TM = std::unique_ptr<LLVMTargetMachine>(
+    static_cast<LLVMTargetMachine*>(
+      T->createTargetMachine(TT, "generic", "", Options, None, None,
+                             CodeGenOpt::Default)));
+  ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
+                  std::string(TM->getTargetFeatureString()),
+                  *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
+  const ARMBaseInstrInfo *TII = ST.getInstrInfo();
+  auto MII = TM->getMCInstrInfo();
+
+  for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
+    const MCInstrDesc &Desc = TII->get(i);
+
+    uint64_t Flags = Desc.TSFlags;
+    if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
+      continue;
+
+    bool Valid = (Flags & ARMII::DoubleWidthResult) != 0;
+    ASSERT_EQ(DoubleWidthResult(i), Valid)
+              << MII->getName(i)
+              << ": mismatched expectation for tail-predicated safety\n";
+  }
+}
+
 TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
   using namespace ARM;
 
   auto RetainsPreviousHalfElement = [](unsigned Opcode) {
     switch (Opcode) {
     default:
       break;
     case MVE_VMOVNi16bh: