[ARM][LowOverheadLoops] DoubleWidthResult instructions canGenerateZeros

[samparker]

Summary

Given that some instructions generate wider result elements than their inputs, flag them as being able to generate non zeros in the false lanes.

[SjoerdMeijer]

A few irrelevant nits inlined, but also one question about the test.

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

530

nit: this is absolutely fine of course, but you do have a little helper function just below this function for the similar RetainsPreviousHalfElement MI description. Perhaps a bit more consistent to add this as a helper too, and that would nicely cluster these helpers.

539

Nit: probably better to just remove these commented out cases, and mention these opcodes in the FIXME, so that also the FIXME becomes a bit more descriptive.

541

Nit: now that we have more classes of instructions that don't respect the lane values, the double width instructions added above, can you comment what's "wrong" with the opcodes below.

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir

754

Do we need to test some other opcodes too that have been marked as DoubleWidth? Like MVE_VSHLL, VMOVL, VQDMULL? Or is this perhaps already tested elsewhere?

[samparker]

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

530

Yeah, I had the same thought.

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir

754

I want to use the unit test to cover the opcodes, and this test was to check that the logic in the pass was reading the flags correctly.

[SjoerdMeijer]

Cheers, with some nits addressed this looks good.

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir

754

Ah yeah, somehow I keep forgetting these unit tests.

[samparker]

• Made a helper
• Modified/added some comments.

[SjoerdMeijer]

Cheers, LGTM

llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp

static bool isVectorPredicated(MachineInstr *MI) {
   return PIdx != -1 && MI->getOperand(PIdx + 1).getReg() == ARM::VPR;
 }
 
 static bool isRegInClass(const MachineOperand &MO,
                          const TargetRegisterClass *Class) {
   return MO.isReg() && MO.getReg() && Class->contains(MO.getReg());
 }
 
+// MVE 'narrowing' operate on half a lane, reading from half and writing
+// to half, which are referred to has the top and bottom half. The other
+// half retains its previous value.
+static bool retainsPreviousHalfElement(const MachineInstr &MI) {
+  const MCInstrDesc &MCID = MI.getDesc();
+  uint64_t Flags = MCID.TSFlags;
+  return (Flags & ARMII::RetainsPreviousHalfElement) != 0;
+}
+
+// Some MVE instructions read from the top/bottom halves of their operand(s)
+// and generate a vector result with result elements that are double the
+// width of the input.
+static bool producesDoubleWidthResult(const MachineInstr &MI) {
+  const MCInstrDesc &MCID = MI.getDesc();
+  uint64_t Flags = MCID.TSFlags;
+  return (Flags & ARMII::DoubleWidthResult) != 0;
+}
+
 // Can this instruction generate a non-zero result when given only zeroed
 // operands? This allows us to know that, given operands with false bytes
 // zeroed by masked loads, that the result will also contain zeros in those
 // bytes.
 static bool canGenerateNonZeros(const MachineInstr &MI) {
+
+  // Check for instructions which can write into a larger element size,
+  // possibly writing into a previous zero'd lane.
+  if (producesDoubleWidthResult(MI))
+    return true;
+
   switch (MI.getOpcode()) {
   default:
     break;
-  // FIXME: FP minus 0?
-  //case ARM::MVE_VNEGf16:
-  //case ARM::MVE_VNEGf32:
+  // FIXME: VNEG FP and -0? I think we'll need to handle this once we allow
+  // fp16 -> fp32 vector conversions.
+  // Instructions that perform a NOT will generate 1s from 0s.
   case ARM::MVE_VMVN:
   case ARM::MVE_VORN:
+  // Count leading zeros will do just that!
   case ARM::MVE_VCLZs8:
   case ARM::MVE_VCLZs16:
   case ARM::MVE_VCLZs32:
     return true;
   }
   return false;
 }
 
-// MVE 'narrowing' operate on half a lane, reading from half and writing
-// to half, which are referred to has the top and bottom half. The other
-// half retains its previous value.
-static bool retainsPreviousHalfElement(const MachineInstr &MI) {
-  const MCInstrDesc &MCID = MI.getDesc();
-  uint64_t Flags = MCID.TSFlags;
-  return (Flags & ARMII::RetainsPreviousHalfElement) != 0;
-}
 
 // Look at its register uses to see if it only can only receive zeros
 // into its false lanes which would then produce zeros. Also check that
 // the output register is also defined by an FalseLaneZeros instruction
 // so that if tail-predication happens, the lanes that aren't updated will
 // still be zeros.
 static bool producesFalseLaneZeros(MachineInstr &MI,
                                    const TargetRegisterClass *QPRs,

llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir

while.body:                                       ; preds = %while.body.preheader, %while.body
     %7 = icmp ne i32 %6, 0
     br i1 %7, label %while.body, label %while.end
 
   while.end:                                        ; preds = %while.body, %entry
     %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]
     ret i32 %res
   }
 
+  define hidden i32 @illegal_vmull_non_zero(i16* %x, i16* %y, i16* %z, i32 %n) {
+  entry:
+    %cmp22 = icmp sgt i32 %n, 0
+    %0 = add i32 %n, 7
+    %1 = icmp slt i32 %n, 8
+    %smin = select i1 %1, i32 %n, i32 8
+    %2 = sub i32 %0, %smin
+    %3 = lshr i32 %2, 3
+    %4 = add nuw nsw i32 %3, 1
+    br i1 %cmp22, label %while.body.preheader, label %while.end
+
+  while.body.preheader:                             ; preds = %entry
+    call void @llvm.set.loop.iterations.i32(i32 %4)
+    br label %while.body
+
+  while.body:                                       ; preds = %while.body.preheader, %while.body
+    %x.addr.026 = phi i16* [ %add.ptr, %while.body ], [ %x, %while.body.preheader ]
+    %y.addr.025 = phi i16* [ %add.ptr4, %while.body ], [ %y, %while.body.preheader ]
+    %n.addr.023 = phi i32 [ %sub, %while.body ], [ %n, %while.body.preheader ]
+    %acc = phi i32 [ %acc.next, %while.body ], [ 0, %while.body.preheader ]
+    %5 = phi i32 [ %4, %while.body.preheader ], [ %6, %while.body ]
+    %tmp3 = bitcast i16* %y.addr.025 to <8 x i16>*
+    %tmp1 = bitcast i16* %x.addr.026 to <8 x i16>*
+    %tmp = tail call <8 x i1> @llvm.arm.mve.vctp16(i32 %n.addr.023)
+    %tmp2 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp1, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
+    %tmp4 = tail call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %tmp3, i32 2, <8 x i1> %tmp, <8 x i16> zeroinitializer)
+    %mul = tail call <4 x i32> @llvm.arm.mve.vmull.v4i32.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp4, i32 0, i32 1)
+    %reduce = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> %mul)
+    %acc.next = add i32 %reduce, %acc
+    %add.ptr = getelementptr inbounds i16, i16* %x.addr.026, i32 8
+    %add.ptr4 = getelementptr inbounds i16, i16* %y.addr.025, i32 8
+    %sub = add nsw i32 %n.addr.023, -8
+    %6 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %5, i32 1)
+    %7 = icmp ne i32 %6, 0
+    br i1 %7, label %while.body, label %while.end
+
+  while.end:                                        ; preds = %while.body, %entry
+    %res = phi i32 [ 0, %entry ], [ %acc.next, %while.body ]
+    ret i32 %res
+  }
+
   declare <8 x i8> @llvm.masked.load.v8i8.p0v8i8(<8 x i8>*, i32 immarg, <8 x i1>, <8 x i8>)
   declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
   declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
   declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
   declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
   declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
   declare i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32>)
   declare i32 @llvm.experimental.vector.reduce.add.v8i32(<8 x i32>)
bb.3.while.end:
     tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
 
   bb.4:
     renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
     $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
     tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
 
 ...
+---
+name:            illegal_vmull_non_zero
+alignment:       2
+tracksRegLiveness: true
+registers:       []
+liveins:
+  - { reg: '$r0', virtual-reg: '' }
+  - { reg: '$r1', virtual-reg: '' }
+  - { reg: '$r3', virtual-reg: '' }
+frameInfo:
+  stackSize:       8
+  offsetAdjustment: 0
+  maxAlignment:    4
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: illegal_vmull_non_zero
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.4(0x30000000)
+  ; CHECK:   liveins: $lr, $r0, $r1, $r3, $r7
+  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
+  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
+  ; CHECK:   tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
+  ; CHECK:   $r2 = tMOVr $r3, 14 /* CC::al */, $noreg
+  ; CHECK:   t2IT 10, 8, implicit-def $itstate
+  ; CHECK:   renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
+  ; CHECK:   tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+  ; CHECK:   tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
+  ; CHECK: bb.1.while.body.preheader:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   liveins: $r0, $r1, $r2, $r3
+  ; CHECK:   renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
+  ; CHECK:   renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg
+  ; CHECK:   renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+  ; CHECK:   renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
+  ; CHECK:   dead $lr = t2DLS renamable $r2
+  ; CHECK:   $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+  ; CHECK:   renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+  ; CHECK: bb.2.while.body:
+  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r12
+  ; CHECK:   renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
+  ; CHECK:   MVE_VPST 4, implicit $vpr
+  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2)
+  ; CHECK:   renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2)
+  ; CHECK:   $lr = tMOVr $r12, 14 /* CC::al */, $noreg
+  ; CHECK:   renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
+  ; CHECK:   renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
+  ; CHECK:   renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
+  ; CHECK:   renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg
+  ; CHECK:   dead $lr = t2LEUpdate killed renamable $lr, %bb.2
+  ; CHECK: bb.3.while.end:
+  ; CHECK:   liveins: $r2
+  ; CHECK:   $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+  ; CHECK: bb.4:
+  ; CHECK:   renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+  ; CHECK:   $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+  bb.0.entry:
+    successors: %bb.1(0x50000000), %bb.4(0x30000000)
+    liveins: $r0, $r1, $r3, $r7, $lr
+
+    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
+    frame-setup CFI_INSTRUCTION def_cfa_offset 8
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r7, -8
+    tCMPi8 renamable $r3, 8, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    $r2 = tMOVr $r3, 14 /* CC::al */, $noreg
+    t2IT 10, 8, implicit-def $itstate
+    renamable $r2 = tMOVi8 $noreg, 8, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
+    tCMPi8 renamable $r3, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
+    tBcc %bb.4, 11 /* CC::lt */, killed $cpsr
+
+  bb.1.while.body.preheader:
+    successors: %bb.2(0x80000000)
+    liveins: $r0, $r1, $r2, $r3
+
+    renamable $r2, dead $cpsr = tSUBrr renamable $r3, killed renamable $r2, 14 /* CC::al */, $noreg
+    renamable $r12 = t2ADDri killed renamable $r2, 7, 14 /* CC::al */, $noreg, $noreg
+    renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+    renamable $r2 = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r12, 27, 14 /* CC::al */, $noreg, $noreg
+    t2DoLoopStart renamable $r2
+    $r12 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+    renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+
+  bb.2.while.body:
+    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
+    liveins: $r0, $r1, $r2, $r3, $r12
+
+    renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg
+    MVE_VPST 4, implicit $vpr
+    renamable $r1, renamable $q0 = MVE_VLDRHU16_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.tmp3, align 2)
+    renamable $r0, renamable $q1 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, killed renamable $vpr :: (load 16 from %ir.tmp1, align 2)
+    $lr = tMOVr $r12, 14 /* CC::al */, $noreg
+    renamable $q0 = MVE_VMULLTs16 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
+    renamable $r12 = nsw t2SUBri killed $r12, 1, 14 /* CC::al */, $noreg, $noreg
+    renamable $r3, dead $cpsr = nsw tSUBi8 killed renamable $r3, 8, 14 /* CC::al */, $noreg
+    renamable $r2 = MVE_VADDVu32acc killed renamable $r2, killed renamable $q0, 0, $noreg
+    renamable $lr = t2LoopDec killed renamable $lr, 1
+    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
+    tB %bb.3, 14 /* CC::al */, $noreg
+
+  bb.3.while.end:
+    liveins: $r2
+
+    $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+  bb.4:
+    renamable $r2, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
+    $r0 = tMOVr killed $r2, 14 /* CC::al */, $noreg
+    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
+
+...