[AMDGPU] Fix PC register mapping in wave32 mode

[scott.linder]

Summary

The PC_32 DWARF register is for a 32-bit process address space which we
don't implement in AMDGCN; another way of putting this is that the size
of the PC register is not a function of the wavefront size. If we ever
implement a 32-bit process address space we will need to add two more
DwarfFlavours i.e. we will need to represent the product of (wave32,
wave64) x (64-bit address space, 32-bit address space).

[scott.linder]

Sorry for missing this in the initial review, I caught it as I was rebasing my CFI changes and adding tests for wave32.

[RamNalamothu]

In D76732#1940121, @scott.linder wrote:

Sorry for missing this in the initial review, I caught it as I was rebasing my CFI changes and adding tests for wave32.

Ah, it's my mistake and oversight. Thanks for catching and fixing it.

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

 
 // Pseudo-registers: Used as placeholders during isel and immediately
 // replaced, never seeing the verifier.
 def PRIVATE_RSRC_REG : SIReg<"private_rsrc", 0>;
 def FP_REG : SIReg<"fp", 0>;
 def SP_REG : SIReg<"sp", 0>;
 
 // Pseudo-register to represent the program-counter DWARF register.
-def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 0]> {
+def PC_REG : SIReg<"pc", 0>, DwarfRegNum<[16, 16]> {
   // There is no physical register corresponding to a "program counter", but
   // we need to encode the concept in debug information in order to represent
   // things like the return value in unwind information.
   let isArtificial = 1;
 }
 
 // VCC for 64-bit instructions
 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]> {

llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp

 
 TEST(AMDGPUDwarfRegMappingTests, TestWave32DwarfRegMapping) {
   for (auto Triple :
        {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
     auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
     if (TM && TM->getMCRegisterInfo()) {
       auto MRI = TM->getMCRegisterInfo();
       // Wave32 Dwarf register mapping test numbers
-      // PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
+      // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
       // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
       // A0 => 2048, A255 => 2303
-      for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
+      for (int llvmReg : {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
         MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
         EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
       }
     }
   }
 }

llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

for (auto Triple :
        {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
     auto TM = createTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
     if (TM) {
       GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
                       std::string(TM->getTargetFeatureString()), *TM);
       auto MRI = ST.getRegisterInfo();
       if (MRI) {
         // Wave32 Dwarf register mapping test numbers
-        // PC_32 => 0, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
+        // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
         // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
         // A0 => 2048, A255 => 2303
-        for (int llvmReg : {0, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
+        for (int llvmReg :
+             {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
           MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
           EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
         }
       }
     }
   }
 }