[AArch64][SVE] Add more DestructiveBinaryImm DestructiveInstType patterns

[cameron.mcinally]

Summary

This patch starts filling in some of the DestructiveBinaryImm DestructiveInstType patterns. Both zero merging and undef merging are included.

It's questionable whether the undef merging tests are needed. The select with an undefined false operand should be combined away, so I'm not sure there's a lot of value in those. Thoughts?

[cameron.mcinally]

Ping.

Just noticed I added undef merging tests here, but those can probably be removed. DAGCombine (or similar) will remove the undef before we get to the patterns, so they're not really testing anything.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

def fpimm8 : Operand<i32> {
   let ParserMatchClass = FPImmOperand;
   let PrintMethod = "printFPImmOperand";
 }
 
 def fpimm0 : FPImmLeaf<fAny, [{
   return Imm.isExactlyValue(+0.0);
 }]>;
 
+def fpimm_half : FPImmLeaf<fAny, [{
+  return Imm.isExactlyValue(+0.5);
+}]>;
+
+def fpimm_one : FPImmLeaf<fAny, [{
+  return Imm.isExactlyValue(+1.0);
+}]>;
+
+def fpimm_two : FPImmLeaf<fAny, [{
+  return Imm.isExactlyValue(+2.0);
+}]>;
+
 // Vector lane operands
 class AsmVectorIndex<int Min, int Max, string NamePrefix=""> : AsmOperandClass {
   let Name = NamePrefix # "IndexRange" # Min # "_" # Max;
   let DiagnosticType = "Invalid" # Name;
   let PredicateMethod = "isVectorIndex<" # Min # ", " # Max #  ">";
   let RenderMethod = "addVectorIndexOperands";
 }
 

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin", int_aarch64_sve_smin>;
   defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin", int_aarch64_sve_umin>;
   defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd", int_aarch64_sve_sabd>;
   defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd", int_aarch64_sve_uabd>;
 
   defm FRECPE_ZZ  : sve_fp_2op_u_zd<0b110, "frecpe",  int_aarch64_sve_frecpe_x>;
   defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte", int_aarch64_sve_frsqrte_x>;
 
-  defm FADD_ZPmI    : sve_fp_2op_i_p_zds<0b000, "fadd", sve_fpimm_half_one>;
-  defm FSUB_ZPmI    : sve_fp_2op_i_p_zds<0b001, "fsub", sve_fpimm_half_one>;
-  defm FMUL_ZPmI    : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
-  defm FSUBR_ZPmI   : sve_fp_2op_i_p_zds<0b011, "fsubr", sve_fpimm_half_one>;
-  defm FMAXNM_ZPmI  : sve_fp_2op_i_p_zds<0b100, "fmaxnm", sve_fpimm_zero_one>;
-  defm FMINNM_ZPmI  : sve_fp_2op_i_p_zds<0b101, "fminnm", sve_fpimm_zero_one>;
-  defm FMAX_ZPmI    : sve_fp_2op_i_p_zds<0b110, "fmax", sve_fpimm_zero_one>;
-  defm FMIN_ZPmI    : sve_fp_2op_i_p_zds<0b111, "fmin", sve_fpimm_zero_one>;
+  defm FADD_ZPmI    : sve_fp_2op_i_p_zds<0b000, "fadd", "FADD_ZPZI", sve_fpimm_half_one>;
+  defm FSUB_ZPmI    : sve_fp_2op_i_p_zds<0b001, "fsub", "FSUB_ZPZI", sve_fpimm_half_one>;
+  defm FMUL_ZPmI    : sve_fp_2op_i_p_zds<0b010, "fmul", "FMUL_ZPZI", sve_fpimm_half_two>;
+  defm FSUBR_ZPmI   : sve_fp_2op_i_p_zds<0b011, "fsubr", "FSUBR_ZPZI", sve_fpimm_half_one>;
+  defm FMAXNM_ZPmI  : sve_fp_2op_i_p_zds<0b100, "fmaxnm", "FMAXNM_ZPZI", sve_fpimm_zero_one>;
+  defm FMINNM_ZPmI  : sve_fp_2op_i_p_zds<0b101, "fminnm", "FMINNM_ZPZI", sve_fpimm_zero_one>;
+  defm FMAX_ZPmI    : sve_fp_2op_i_p_zds<0b110, "fmax", "FMAX_ZPZI", sve_fpimm_zero_one>;
+  defm FMIN_ZPmI    : sve_fp_2op_i_p_zds<0b111, "fmin", "FMIN_ZPZI", sve_fpimm_zero_one>;
+
+  defm FADD_ZPZI    : sve_fp_2op_i_p_zds_zx<sve_fpimm_half_one>;
+  defm FSUB_ZPZI    : sve_fp_2op_i_p_zds_zx<sve_fpimm_half_one>;
+  defm FMUL_ZPZI    : sve_fp_2op_i_p_zds_zx<sve_fpimm_half_two>;
+  defm FSUBR_ZPZI   : sve_fp_2op_i_p_zds_zx<sve_fpimm_half_one>;
+  defm FMAXNM_ZPZI  : sve_fp_2op_i_p_zds_zx<sve_fpimm_zero_one>;
+  defm FMINNM_ZPZI  : sve_fp_2op_i_p_zds_zx<sve_fpimm_zero_one>;
+  defm FMAX_ZPZI    : sve_fp_2op_i_p_zds_zx<sve_fpimm_zero_one>;
+  defm FMIN_ZPZI    : sve_fp_2op_i_p_zds_zx<sve_fpimm_zero_one>;
+
+  /// Compact single bit fp immediates
+  multiclass intrinsic_compact_fp_immediates<string I, string IZ, string IX,
+                    PatLeaf A, PatLeaf B,
+                    SDPatternOperator op, SDPatternOperator ir_op = null_frag> {
+    def : Pat<(nxv8f16 (op (nxv8i1 PPR_3b:$Pg),
+                           (nxv8f16 ZPR:$Zs1),
+                           (nxv8f16 (AArch64dup (f16 A))))),
+              (!cast<Instruction>(I # "_H") PPR_3b:$Pg, ZPR:$Zs1, 0)>;
+    def : Pat<(nxv8f16 (op (nxv8i1 PPR_3b:$Pg),
+                           (nxv8f16 ZPR:$Zs1),
+                           (nxv8f16 (AArch64dup (f16 B))))),
+              (!cast<Instruction>(I # "_H") PPR_3b:$Pg, ZPR:$Zs1, 1)>;
+    def : Pat<(nxv4f32 (op (nxv4i1 PPR_3b:$Pg),
+                           (nxv4f32 ZPR:$Zs1),
+                           (nxv4f32 (AArch64dup (f32 A))))),
+              (!cast<Instruction>(I # "_S") PPR_3b:$Pg, ZPR:$Zs1, 0)>;
+    def : Pat<(nxv4f32 (op (nxv4i1 PPR_3b:$Pg),
+                           (nxv4f32 ZPR:$Zs1),
+                           (nxv4f32 (AArch64dup (f32 B))))),
+              (!cast<Instruction>(I # "_S") PPR_3b:$Pg, ZPR:$Zs1, 1)>;
+    def : Pat<(nxv2f64 (op (nxv2i1 PPR_3b:$Pg),
+                           (nxv2f64 ZPR:$Zs1),
+                           (nxv2f64 (AArch64dup (f64 A))))),
+              (!cast<Instruction>(I # "_D") PPR_3b:$Pg, ZPR:$Zs1, 0)>;
+    def : Pat<(nxv2f64 (op (nxv2i1 PPR_3b:$Pg),
+                           (nxv2f64 ZPR:$Zs1),
+                           (nxv2f64 (AArch64dup (f64 B))))),
+              (!cast<Instruction>(I # "_D") PPR_3b:$Pg, ZPR:$Zs1, 1)>;
+
+    def : Pat<(nxv8f16 (ir_op (nxv8f16 ZPR:$Zs1),
+                              (nxv8f16 (AArch64dup (f16 A))))),
+              (!cast<Instruction>(IX # "_H") (PTRUE_H 31), ZPR:$Zs1, 0)>;
+    def : Pat<(nxv8f16 (ir_op (nxv8f16 ZPR:$Zs1),
+                              (nxv8f16 (AArch64dup (f16 B))))),
+              (!cast<Instruction>(IX # "_H") (PTRUE_H 31), ZPR:$Zs1, 1)>;
+    def : Pat<(nxv4f32 (ir_op (nxv4f32 ZPR:$Zs1),
+                              (nxv4f32 (AArch64dup (f32 A))))),
+              (!cast<Instruction>(IX # "_S") (PTRUE_S 31), ZPR:$Zs1, 0)>;
+    def : Pat<(nxv4f32 (ir_op (nxv4f32 ZPR:$Zs1),
+                              (nxv4f32 (AArch64dup (f32 B))))),
+              (!cast<Instruction>(IX # "_S") (PTRUE_S 31), ZPR:$Zs1, 1)>;
+    def : Pat<(nxv2f64 (ir_op (nxv2f64 ZPR:$Zs1),
+                              (nxv2f64 (AArch64dup (f64 A))))),
+              (!cast<Instruction>(IX # "_D") (PTRUE_D 31), ZPR:$Zs1, 0)>;
+    def : Pat<(nxv2f64 (ir_op (nxv2f64 ZPR:$Zs1),
+                              (nxv2f64 (AArch64dup (f64 B))))),
+              (!cast<Instruction>(IX # "_D") (PTRUE_D 31), ZPR:$Zs1, 1)>;
+
+    let AddedComplexity = 2 in {
+    // When Intrinsic combined with SELECT
+    def : Pat<(nxv8f16 (op nxv8i1:$Pg,
+                           (vselect nxv8i1:$Pg, nxv8f16:$Zs1, (SVEDup0)),
+                           (nxv8f16 (AArch64dup (f16 A))))),
+              (!cast<Instruction>(IZ # "_H") $Pg, $Zs1, 0)>;
+    def : Pat<(nxv8f16 (op nxv8i1:$Pg,
+                           (vselect nxv8i1:$Pg, nxv8f16:$Zs1, (SVEDup0)),
+                           (nxv8f16 (AArch64dup (f16 B))))),
+              (!cast<Instruction>(IZ # "_H") $Pg, $Zs1, 1)>;
+    def : Pat<(nxv4f32 (op nxv4i1:$Pg,
+                           (vselect nxv4i1:$Pg, nxv4f32:$Zs1, (SVEDup0)),
+                           (nxv4f32 (AArch64dup (f32 A))))),
+              (!cast<Instruction>(IZ # "_S") $Pg, $Zs1, 0)>;
+    def : Pat<(nxv4f32 (op nxv4i1:$Pg,
+                           (vselect nxv4i1:$Pg, nxv4f32:$Zs1, (SVEDup0)),
+                           (nxv4f32 (AArch64dup (f32 B))))),
+              (!cast<Instruction>(IZ # "_S") $Pg, $Zs1, 1)>;
+    def : Pat<(nxv2f64 (op nxv2i1:$Pg,
+                           (vselect nxv2i1:$Pg, nxv2f64:$Zs1, (SVEDup0)),
+                           (nxv2f64 (AArch64dup (f64 A))))),
+              (!cast<Instruction>(IZ # "_D") $Pg, $Zs1, 0)>;
+    def : Pat<(nxv2f64 (op nxv2i1:$Pg,
+                           (vselect nxv2i1:$Pg, nxv2f64:$Zs1, (SVEDup0)),
+                           (nxv2f64 (AArch64dup (f64 B))))),
+              (!cast<Instruction>(IZ # "_D") $Pg, $Zs1, 1)>;
+    }
+  }
+
+  defm : intrinsic_compact_fp_immediates<"FADD_ZPmI",  "FADD_ZPZI_ZERO",  "FADD_ZPZI_UNDEF",   fpimm_half, fpimm_one, int_aarch64_sve_fadd, fadd>;
+  defm : intrinsic_compact_fp_immediates<"FSUB_ZPmI",  "FSUB_ZPZI_ZERO",  "FSUB_ZPZI_UNDEF",   fpimm_half, fpimm_one, int_aarch64_sve_fsub, fsub>;
+  defm : intrinsic_compact_fp_immediates<"FSUBR_ZPmI", "FSUBR_ZPZI_ZERO", "FSUBR_ZPZI_UNDEF",  fpimm_half, fpimm_one, int_aarch64_sve_fsubr>;
+  defm : intrinsic_compact_fp_immediates<"FMUL_ZPmI",  "FMUL_ZPZI_ZERO",  "FMUL_ZPZI_UNDEF",   fpimm_half, fpimm_two, int_aarch64_sve_fmul, fmul>;
+  defm : intrinsic_compact_fp_immediates<"FMAX_ZPmI",  "FMAX_ZPZI_ZERO",  "FMAX_ZPZI_UNDEF",   fpimm0, fpimm_one, int_aarch64_sve_fmax>;
+  defm : intrinsic_compact_fp_immediates<"FMIN_ZPmI",  "FMIN_ZPZI_ZERO",  "FMIN_ZPZI_UNDEF",   fpimm0, fpimm_one, int_aarch64_sve_fmin>;
+  defm : intrinsic_compact_fp_immediates<"FMAXNM_ZPmI","FMAXNM_ZPZI_ZERO","FMAXNM_ZPZI_UNDEF", fpimm0, fpimm_one, int_aarch64_sve_fmaxnm>;
+  defm : intrinsic_compact_fp_immediates<"FMINNM_ZPmI","FMINNM_ZPZI_ZERO","FMINNM_ZPZI_UNDEF", fpimm0, fpimm_one, int_aarch64_sve_fminnm>;
 
   defm FADD_ZPmZ   : sve_fp_2op_p_zds<0b0000, "fadd", "FADD_ZPZZ", int_aarch64_sve_fadd, DestructiveBinaryComm>;
   defm FSUB_ZPmZ   : sve_fp_2op_p_zds<0b0001, "fsub", "FSUB_ZPZZ", int_aarch64_sve_fsub, DestructiveBinaryCommWithRev, "FSUBR_ZPmZ", 1>;
   defm FMUL_ZPmZ   : sve_fp_2op_p_zds<0b0010, "fmul", "FMUL_ZPZZ", int_aarch64_sve_fmul, DestructiveBinaryComm>;
   defm FSUBR_ZPmZ  : sve_fp_2op_p_zds<0b0011, "fsubr", "FSUBR_ZPZZ", int_aarch64_sve_fsubr, DestructiveBinaryCommWithRev, "FSUB_ZPmZ", 0>;
   defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm", "FMAXNM_ZPZZ", int_aarch64_sve_fmaxnm, DestructiveBinaryComm>;
   defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm", "FMINNM_ZPZZ", int_aarch64_sve_fminnm, DestructiveBinaryComm>;
   defm FMAX_ZPmZ   : sve_fp_2op_p_zds<0b0110, "fmax", "FMAX_ZPZZ", int_aarch64_sve_fmax, DestructiveBinaryComm>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, imm_ty:$i1),
   let Inst{5}     = i1;
   let Inst{4-0}   = Zdn;
 
   let Constraints = "$Zdn = $_Zdn";
   let DestructiveInstType = DestructiveOther;
   let ElementSize = zprty.ElementSize;
 }
 
-multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, Operand imm_ty> {
-  def _H : sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>;
-  def _S : sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>;
-  def _D : sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
+multiclass sve_fp_2op_i_p_zds<bits<3> opc, string asm, string Ps,
+                              Operand imm_ty> {
+  let DestructiveInstType = DestructiveBinaryImm in {
+  def _H : SVEPseudo2Instr<Ps # _H, 1>, sve_fp_2op_i_p_zds<0b01, opc, asm, ZPR16, imm_ty>;
+  def _S : SVEPseudo2Instr<Ps # _S, 1>, sve_fp_2op_i_p_zds<0b10, opc, asm, ZPR32, imm_ty>;
+  def _D : SVEPseudo2Instr<Ps # _D, 1>, sve_fp_2op_i_p_zds<0b11, opc, asm, ZPR64, imm_ty>;
+  }
+}
+
+multiclass sve_fp_2op_i_p_zds_zx<Operand imm_ty> {
+  def _UNDEF_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, imm_ty, FalseLanesUndef>;
+  def _UNDEF_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, imm_ty, FalseLanesUndef>;
+  def _UNDEF_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, imm_ty, FalseLanesUndef>;
+
+  def _ZERO_H : PredTwoOpImmPseudo<NAME # _H, ZPR16, imm_ty, FalseLanesZero>;
+  def _ZERO_S : PredTwoOpImmPseudo<NAME # _S, ZPR32, imm_ty, FalseLanesZero>;
+  def _ZERO_D : PredTwoOpImmPseudo<NAME # _D, ZPR64, imm_ty, FalseLanesZero>;
 }
 
 class sve_fp_2op_p_zds<bits<2> sz, bits<4> opc, string asm,
                        ZPRRegOp zprty>
 : I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
   asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
   "",
   []>, Sched<[]> {

llvm/test/CodeGen/AArch64/sve-fp-immediates-merging.ll

+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+;
+; FADD
+;
+
+define <vscale x 8 x half> @fadd_h_immhalf(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fadd_h_immhalf:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK:       fadd z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fadd_h_immhalf_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fadd_h_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fadd z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fadd_h_immone(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fadd_h_immone:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fadd z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fadd_h_immone_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fadd_h_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fadd z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fadd_s_immhalf(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fadd_s_immhalf:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fadd z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fadd_s_immhalf_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fadd_s_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fadd z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fadd_s_immone(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fadd_s_immone:
+; CHECK:      movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT: fadd z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT: ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fadd_s_immone_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fadd_s_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fadd z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fadd_d_immhalf(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fadd_d_immhalf:
+; CHECK:      movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT: ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fadd_d_immhalf_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fadd_d_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fadd z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fadd_d_immone(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fadd_d_immone:
+; CHECK:      movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT: fadd z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT: ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fadd_d_immone_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fadd_d_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fadd z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;
+; FMAX
+;
+
+define <vscale x 8 x half> @fmax_h_immzero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmax_h_immzero:
+; CHECK:       movprfx  z0.h, p0/z, z0.
+; CHECK-NEXT:  fmax z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmax.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmax_h_immzero_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmax_h_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmax z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmax.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmax_h_immone(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmax_h_immone:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fmax z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmax.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmax_h_immone_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmax_h_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmax z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmax.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fmax_s_immzero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmax_s_immzero:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmax z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmax_s_immzero_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmax_s_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmax z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmax_s_immone(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmax_s_immone:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmax z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmax_s_immone_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmax_s_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmax z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fmax_d_immzero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmax_d_immzero:
+; CHECK:      movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT: fmax z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT: ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmax_d_immzero_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmax_d_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmax z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmax_d_immone(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmax_d_immone:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fmax z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmax_d_immone_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmax_d_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmax z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;
+; FMAXNM
+;
+
+define <vscale x 8 x half> @fmaxnm_h_immzero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmaxnm_h_immzero:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fmaxnm z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmaxnm_h_immzero_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmaxnm_h_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmaxnm z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmaxnm_h_immone(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmaxnm_h_immone:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fmaxnm z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmaxnm_h_immone_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmaxnm_h_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmaxnm z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fmaxnm_s_immzero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmaxnm_s_immzero:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmaxnm z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmaxnm_s_immzero_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmaxnm_s_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmaxnm z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmaxnm_s_immone(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmaxnm_s_immone:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmaxnm z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmaxnm_s_immone_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmaxnm_s_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmaxnm z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fmaxnm_d_immzero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmaxnm_d_immzero:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fmaxnm z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmaxnm_d_immzero_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmaxnm_d_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmaxnm z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmaxnm_d_immone(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmaxnm_d_immone:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fmaxnm z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmaxnm_d_immone_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmaxnm_d_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmaxnm z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;
+; FMIN
+;
+
+define <vscale x 8 x half> @fmin_h_immzero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmin_h_immzero:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fmin z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmin.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmin_h_immzero_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmin_h_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmin z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmin.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmin_h_immone(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmin_h_immone:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fmin z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmin.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmin_h_immone_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmin_h_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmin z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmin.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fmin_s_immzero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmin_s_immzero:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmin z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmin_s_immzero_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmin_s_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmin z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmin_s_immone(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmin_s_immone:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmin z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmin_s_immone_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmin_s_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmin z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fmin_d_immzero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmin_d_immzero:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fmin z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmin_d_immzero_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmin_d_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmin z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmin_d_immone(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmin_d_immone:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fmin z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmin_d_immone_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmin_d_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmin z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;
+; FMINNM
+;
+
+define <vscale x 8 x half> @fminnm_h_immzero(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fminnm_h_immzero:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fminnm z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fminnm_h_immzero_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fminnm_h_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fminnm z0.h, p0/m, z0.h, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fminnm_h_immone(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fminnm_h_immone:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fminnm z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fminnm_h_immone_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fminnm_h_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fminnm z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1> %pg,
+                                                              <vscale x 8 x half> %a_z,
+                                                              <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fminnm_s_immzero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fminnm_s_immzero:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fminnm z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fminnm_s_immzero_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fminnm_s_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fminnm z0.s, p0/m, z0.s, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fminnm_s_immone(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fminnm_s_immone:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fminnm z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fminnm_s_immone_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fminnm_s_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fminnm z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1> %pg,
+                                                               <vscale x 4 x float> %a_z,
+                                                               <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fminnm_d_immzero(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fminnm_d_immzero:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fminnm z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fminnm_d_immzero_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fminnm_d_immzero_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fminnm z0.d, p0/m, z0.d, #0.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fminnm_d_immone(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fminnm_d_immone:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fminnm z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fminnm_d_immone_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fminnm_d_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fminnm z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1> %pg,
+                                                                <vscale x 2 x double> %a_z,
+                                                                <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;
+; FMUL
+;
+
+define <vscale x 8 x half> @fmul_h_immhalf(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmul_h_immhalf:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fmul z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmul_h_immhalf_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmul_h_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmul z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmul_h_immtwo(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmul_h_immtwo:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fmul z0.h, p0/m, z0.h, #2.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 2.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fmul_h_immtwo_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fmul_h_immtwo_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmul z0.h, p0/m, z0.h, #2.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 2.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fmul_s_immhalf(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmul_s_immhalf:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmul z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmul_s_immhalf_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmul_s_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmul z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmul_s_immtwo(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmul_s_immtwo:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fmul z0.s, p0/m, z0.s, #2.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 2.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fmul_s_immtwo_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fmul_s_immtwo_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmul z0.s, p0/m, z0.s, #2.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 2.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fmul_d_immhalf(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmul_d_immhalf:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fmul z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmul_d_immhalf_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmul_d_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmul z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmul_d_immtwo(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmul_d_immtwo:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fmul z0.d, p0/m, z0.d, #2.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 2.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fmul_d_immtwo_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fmul_d_immtwo_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fmul z0.d, p0/m, z0.d, #2.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 2.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;
+; FSUB
+;
+
+define <vscale x 8 x half> @fsub_h_immhalf(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsub_h_immhalf:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fsub z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsub_h_immhalf_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsub_h_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsub z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsub_h_immone(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsub_h_immone:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fsub z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsub_h_immone_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsub_h_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsub z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1> %pg,
+                                                            <vscale x 8 x half> %a_z,
+                                                            <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fsub_s_immhalf(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsub_s_immhalf:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fsub z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsub_s_immhalf_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsub_s_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsub z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsub_s_immone(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsub_s_immone:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fsub z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsub_s_immone_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsub_s_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsub z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
+                                                             <vscale x 4 x float> %a_z,
+                                                             <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fsub_d_immhalf(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsub_d_immhalf:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fsub z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsub_d_immhalf_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsub_d_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsub z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsub_d_immone(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsub_d_immone:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fsub z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsub_d_immone_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsub_d_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsub z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1> %pg,
+                                                              <vscale x 2 x double> %a_z,
+                                                              <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;
+; FSUBR
+;
+
+define <vscale x 8 x half> @fsubr_h_immhalf(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsubr_h_immhalf:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsubr.nxv8f16(<vscale x 8 x i1> %pg,
+                                                             <vscale x 8 x half> %a_z,
+                                                             <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsubr_h_immhalf_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsubr_h_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsubr z0.h, p0/m, z0.h, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsubr.nxv8f16(<vscale x 8 x i1> %pg,
+                                                             <vscale x 8 x half> %a_z,
+                                                             <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsubr_h_immone(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsubr_h_immone:
+; CHECK:       movprfx z0.h, p0/z, z0.h
+; CHECK-NEXT:  fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> zeroinitializer
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsubr.nxv8f16(<vscale x 8 x i1> %pg,
+                                                             <vscale x 8 x half> %a_z,
+                                                             <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 8 x half> @fsubr_h_immone_undef(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) {
+; CHECK-LABEL: fsubr_h_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsubr z0.h, p0/m, z0.h, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 8 x half> undef, half 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 8 x half> %elt, <vscale x 8 x half> undef, <vscale x 8 x i32> zeroinitializer
+  %a_z = select <vscale x 8 x i1> %pg, <vscale x 8 x half> %a, <vscale x 8 x half> undef
+  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fsubr.nxv8f16(<vscale x 8 x i1> %pg,
+                                                             <vscale x 8 x half> %a_z,
+                                                             <vscale x 8 x half> %splat)
+  ret <vscale x 8 x half> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immhalf(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsubr_s_immhalf:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fsubr z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg,
+                                                              <vscale x 4 x float> %a_z,
+                                                              <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immhalf_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsubr_s_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsubr z0.s, p0/m, z0.s, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg,
+                                                              <vscale x 4 x float> %a_z,
+                                                              <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immone(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsubr_s_immone:
+; CHECK:       movprfx z0.s, p0/z, z0.s
+; CHECK-NEXT:  fsubr z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg,
+                                                              <vscale x 4 x float> %a_z,
+                                                              <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 4 x float> @fsubr_s_immone_undef(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) {
+; CHECK-LABEL: fsubr_s_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsubr z0.s, p0/m, z0.s, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 4 x float> undef, float 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 4 x float> %elt, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer
+  %a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> undef
+  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg,
+                                                              <vscale x 4 x float> %a_z,
+                                                              <vscale x 4 x float> %splat)
+  ret <vscale x 4 x float> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immhalf(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsubr_d_immhalf:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fsubr z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1> %pg,
+                                                               <vscale x 2 x double> %a_z,
+                                                               <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immhalf_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsubr_d_immhalf_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsubr z0.d, p0/m, z0.d, #0.5
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 0.500000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1> %pg,
+                                                               <vscale x 2 x double> %a_z,
+                                                               <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immone(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsubr_d_immone:
+; CHECK:       movprfx z0.d, p0/z, z0.d
+; CHECK-NEXT:  fsubr z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> zeroinitializer
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1> %pg,
+                                                               <vscale x 2 x double> %a_z,
+                                                               <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+define <vscale x 2 x double> @fsubr_d_immone_undef(<vscale x 2 x i1> %pg, <vscale x 2 x double> %a) {
+; CHECK-LABEL: fsubr_d_immone_undef:
+; CHECK-NOT:   movprfx
+; CHECK:       fsubr z0.d, p0/m, z0.d, #1.0
+; CHECK-NEXT:  ret
+  %elt   = insertelement <vscale x 2 x double> undef, double 1.000000e+00, i32 0
+  %splat = shufflevector <vscale x 2 x double> %elt, <vscale x 2 x double> undef, <vscale x 2 x i32> zeroinitializer
+  %a_z = select <vscale x 2 x i1> %pg, <vscale x 2 x double> %a, <vscale x 2 x double> undef
+  %out = call <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1> %pg,
+                                                               <vscale x 2 x double> %a_z,
+                                                               <vscale x 2 x double> %splat)
+  ret <vscale x 2 x double> %out
+}
+
+;; Arithmetic intrinsic declarations
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fadd.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fadd.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fmax.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fmax.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fmax.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fmaxnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fmaxnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fmaxnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fmin.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fmin.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fminnm.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fminnm.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fminnm.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fmul.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fmul.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fsub.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fsub.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.fsubr.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>, <vscale x 8 x half>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.fsubr.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>, <vscale x 2 x double>)