[GlobalISel] combine trunc(trunc) pattern

[gargaroff]

Summary

Legalization can introduce the trunc(trunc) pattern. This can cause
problems if one of these intermediate truncs is not legal.
Combine truncs of this pattern, if the resulting trunc is legal.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

258–259

Scalar truncate always needs to be legal?

[gargaroff]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

258–259

Maybe I misunderstood the official docs. There it says for the minimal rule set:

G_TRUNC must be legal for all inputs from the producer type set and all smaller outputs from the consumer type set.

Is this out-of-date or misleading? If so, I'll remove the check (or maybe assert it). Downstream we were actually planning on making our G_TRUNC only legal if it fits our register size (with s1 being an exception), which is why we need this combine rule. If G_TRUNC always needs to be legal, should this be reflected in the documentation?

[gargaroff]

Ping

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

258–259

I'm not sure. That rule doesn't reflect what is implemented in the in-tree targets. AArch64 for example does getActionDefinitionsBuilder(G_TRUNC).alwaysLegal(). For AMDGPU, I'm decomposing any vector truncates, but allowing any scalar up to the maximum bitwidth. One case I've been taking care around is degenerate, impossible to legalize cases. If you have an implicit use on a target instruction with an illegal truncate result type, we should probably just accept it regardless of legality (and not infinite loop in the legalizer).

[gargaroff]

remove legality check for resulting combined trunc

[gargaroff]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

258–259

I see, that is a good point. I guess we could safely remove this check. Most (all?) of the time the final remaining truncates after legalization should all result in legal result types anyway (thanks to the artifact combiner). If you somehow end up in a situation where all your instructions are already legal but a truncate is not, then you violated the rule that truncate must be legal for all smaller outputs from the consumer type set.

I guess that because truncates where not combined so far, you would often end up with this trunc(trunc) pattern which more or less forces you to have an alwaysLegal rule, because now suddenly the producer-set of trunc becomes the consumer-set of it too.

If you have an implicit use on a target instruction with an illegal truncate result type, we should probably just accept it regardless of legality

Wouldn't you say that an implicit-use is still a consumer and should therefore be legal according to the rule in the docs? Doesn't really matter here anymore, since I will remove the check anyway, but would be interesting to hear your opinion on this.

[gargaroff]

@arsenm Is this good to go then or is there something else?

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

258–259

Wouldn't you say that an implicit-use is still a consumer and should therefore be legal according to the rule in the docs? Doesn't really matter here anymore, since I will remove the check anyway, but would be interesting to hear your opinion on this.

Yes, although it's a bit contrived since any possible smaller type needs to be handled. Every target has unlegalizable consumers through arbitrary implicit uses

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

if (SrcMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) {
         // Unable to combine
         return false;
       }
 
       markInstAndDefDead(MI, *SrcMI, DeadInsts);
       return true;
     }
 
+    // trunc(trunc) -> trunc
+    Register TruncSrc;
+    if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
+      const LLT DstTy = MRI.getType(DstReg);
+      const LLT TruncSrcTy = MRI.getType(TruncSrc);
+      if (!isInstLegal({TargetOpcode::G_TRUNC, {DstTy, TruncSrcTy}}))
+        return false;
+
+      LLVM_DEBUG(dbgs() << ".. Combine G_TRUNC(G_TRUNC): " << MI);
+
+      Builder.buildTrunc(DstReg, TruncSrc);
+      UpdatedDefs.push_back(DstReg);
+      markInstAndDefDead(MI, *MRI.getVRegDef(TruncSrc), DeadInsts);
+      return true;
+    }
+
     return false;
   }
 
   /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
   bool tryFoldImplicitDef(MachineInstr &MI,
                           SmallVectorImpl<MachineInstr *> &DeadInsts,
                           SmallVectorImpl<Register> &UpdatedDefs) {
     unsigned Opcode = MI.getOpcode();

llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
 ---
 name:            test_load_trunc
 stack:
   - { id: 0, type: default, offset: 0, size: 2,
       alignment: 2, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
       debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
 body: |
   bb.0.entry:
 
     ; CHECK-LABEL: name: test_load_trunc
     ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
     ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p0) :: (load 2)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s10) = G_TRUNC [[LOAD]](s16)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNC]](s10)
-    ; CHECK: RET_ReallyLR implicit [[TRUNC1]](s1)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[LOAD]](s16)
+    ; CHECK: RET_ReallyLR implicit [[TRUNC]](s1)
     %0:_(p0) = G_FRAME_INDEX %stack.0
     %1:_(s10) = G_LOAD %0(p0) :: (load 2)
     %2:_(s1) = G_TRUNC %1(s10)
     RET_ReallyLR implicit %2(s1)
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir

bb.0:
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
 ...
 
 ---
 name: trunc_s68_merge_s128_s32
 
 body: |
   bb.0:
-    ; Test that trunc(merge) with trunc-size > merge-source-size is not combined
-    ; if trunc-size % merge-source-size != 0
+    ; Test that trunc(merge) with trunc-size > merge-source-size and
+    ; trunc-size % merge-source-size != 0 can be combined after the G_TRUNCs
+    ; have been combined.
     ; CHECK-LABEL: name: trunc_s68_merge_s128_s32
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
-    ; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](s32), [[C1]](s32), [[C]](s32), [[C1]](s32)
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s68) = G_TRUNC [[MV]](s128)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s68)
-    ; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
+    ; CHECK: $vgpr0 = COPY [[C]](s32)
     %0:_(s32) = G_CONSTANT i32 0
     %1:_(s32) = G_CONSTANT i32 1
     %2:_(s128) = G_MERGE_VALUES %0, %1, %0, %1
     %3:_(s68) = G_TRUNC %2
     %4:_(s32) = G_TRUNC %3
     $vgpr0 = COPY %4
 ...
+
+---
+name: trunc_trunc
+
+body: |
+  bb.0:
+    ; Test that trunc(trunc) is combined to a single trunc
+    ; CHECK-LABEL: name: trunc_trunc
+    ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
+    ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
+    %0:_(s64) = G_IMPLICIT_DEF
+    %1:_(s48) = G_TRUNC %0
+    %2:_(s32) = G_TRUNC %1
+    $vgpr0 = COPY %2
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir

bb.0:
     ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
     ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
     ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
     ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
     ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
     ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
     ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
-    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]]
     ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
     ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
     ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
     ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
     ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
     ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
     ; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
     ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
     ; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
     ; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
     ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
     ; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
     ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
-    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
-    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
-    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
-    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
     ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s48) = G_TRUNC %0
     %2:_(<3 x s16>) = G_BITCAST %1
     %3:_(<3 x s32>) = G_ANYEXT %2
     $vgpr0_vgpr1_vgpr2 = COPY %3
 ...
 

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

 name: test_extract_s16_s31_offset0
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_extract_s16_s31_offset0
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32)
-    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+    ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s31) = G_TRUNC %0
     %2:_(s16) = G_EXTRACT %1, 0
     %3:_(s32) = G_ANYEXT %2
     $vgpr0 = COPY %3
 ...
 
 ---

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir

 ---
 name: test_inttoptr_s33_to_p3
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
 
     ; CHECK-LABEL: name: test_inttoptr_s33_to_p3
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s33) = G_TRUNC [[COPY]](s64)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s33)
-    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](s32)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+    ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32)
     ; CHECK: S_ENDPGM 0, implicit [[INTTOPTR]](p3)
     %0:_(s64) = COPY $vgpr0_vgpr1
     %1:_(s33) = G_TRUNC %0
     %2:_(p3) = G_INTTOPTR %1
     S_ENDPGM 0, implicit %2
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir

 ---
 name: test_trunc_s16_to_s1
 body: |
   bb.0:
     liveins: $vgpr0
 
     ; CHECK-LABEL: name: test_trunc_s16_to_s1
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
-    ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
-    ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNC]](s16)
-    ; CHECK: S_ENDPGM 0, implicit [[TRUNC1]](s1)
+    ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
+    ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s1)
     %0:_(s32) = COPY $vgpr0
     %1:_(s16) = G_TRUNC %0
     %2:_(s1) = G_TRUNC %1
     S_ENDPGM 0, implicit %2
 ...
 
 ---
 name: test_trunc_v4s32_to_v4s1