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Differential D76601

[GlobalISel] combine trunc(trunc) pattern
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Authored by gargaroff on Mar 23 2020, 5:03 AM.

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Reviewers
arsenm
aemerson
dsanders
Commits
rGc8393240abc1: [GlobalISel] combine trunc(trunc) pattern
Summary

Legalization can introduce the trunc(trunc) pattern. This can cause
problems if one of these intermediate truncs is not legal.
Combine truncs of this pattern, if the resulting trunc is legal.

Diff Detail

Event Timeline

gargaroff created this revision.Mar 23 2020, 5:03 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 23 2020, 5:03 AM
Herald added subscribers: llvm-commits, kerbowa, rovka and 3 others. · View Herald Transcript
Harbormaster completed remote builds in B50097: Diff 251996.Mar 23 2020, 5:58 AM
arsenm added inline comments.Mar 23 2020, 10:23 AM
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
286–287

Scalar truncate always needs to be legal?

gargaroff added inline comments.Mar 23 2020, 10:36 AM
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
286–287

Maybe I misunderstood the official docs. There it says for the minimal rule set:

G_TRUNC must be legal for all inputs from the producer type set and all smaller outputs from the consumer type set.

Is this out-of-date or misleading? If so, I'll remove the check (or maybe assert it). Downstream we were actually planning on making our G_TRUNC only legal if it fits our register size (with s1 being an exception), which is why we need this combine rule. If G_TRUNC always needs to be legal, should this be reflected in the documentation?

gargaroff added a comment.Mar 30 2020, 12:13 AM

Ping

arsenm added inline comments.Mar 30 2020, 7:32 AM
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
286–287

I'm not sure. That rule doesn't reflect what is implemented in the in-tree targets. AArch64 for example does getActionDefinitionsBuilder(G_TRUNC).alwaysLegal(). For AMDGPU, I'm decomposing any vector truncates, but allowing any scalar up to the maximum bitwidth. One case I've been taking care around is degenerate, impossible to legalize cases. If you have an implicit use on a target instruction with an illegal truncate result type, we should probably just accept it regardless of legality (and not infinite loop in the legalizer).

gargaroff updated this revision to Diff 253799.Mar 31 2020, 1:12 AM
gargaroff marked an inline comment as done.

remove legality check for resulting combined trunc

gargaroff marked 3 inline comments as done.Mar 31 2020, 1:12 AM
gargaroff added inline comments.
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
286–287

I see, that is a good point. I guess we could safely remove this check. Most (all?) of the time the final remaining truncates after legalization should all result in legal result types anyway (thanks to the artifact combiner). If you somehow end up in a situation where all your instructions are already legal but a truncate is not, then you violated the rule that truncate must be legal for all smaller outputs from the consumer type set.

I guess that because truncates where not combined so far, you would often end up with this trunc(trunc) pattern which more or less forces you to have an alwaysLegal rule, because now suddenly the producer-set of trunc becomes the consumer-set of it too.

If you have an implicit use on a target instruction with an illegal truncate result type, we should probably just accept it regardless of legality

Wouldn't you say that an implicit-use is still a consumer and should therefore be legal according to the rule in the docs? Doesn't really matter here anymore, since I will remove the check anyway, but would be interesting to hear your opinion on this.

Harbormaster completed remote builds in B51098: Diff 253799.Mar 31 2020, 2:10 AM
gargaroff marked an inline comment as done.Apr 7 2020, 12:42 AM

@arsenm Is this good to go then or is there something else?

arsenm accepted this revision.Apr 7 2020, 8:17 AM
arsenm added inline comments.
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
286–287

Wouldn't you say that an implicit-use is still a consumer and should therefore be legal according to the rule in the docs? Doesn't really matter here anymore, since I will remove the check anyway, but would be interesting to hear your opinion on this.

Yes, although it's a bit contrived since any possible smaller type needs to be handled. Every target has unlegalizable consumers through arbitrary implicit uses

This revision is now accepted and ready to land.Apr 7 2020, 8:17 AM
Closed by commit rGc8393240abc1: [GlobalISel] combine trunc(trunc) pattern (authored by gargaroff). · Explain WhyApr 8 2020, 3:13 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
14 lines
test/
CodeGen/
AArch64/
GlobalISel/
5 lines
AMDGPU/
GlobalISel/
26 lines
11 lines
3 lines
513 lines
21 lines
5 lines
5 lines

Diff 255947

llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h

Show First 20 Lines • Show All 272 Lines • ▼ Show 20 Lines if (SrcMI->getOpcode() == TargetOpcode::G_MERGE_VALUES) {
// Unable to combine // Unable to combine
return false; return false;
} }
markInstAndDefDead(MI, *SrcMI, DeadInsts); markInstAndDefDead(MI, *SrcMI, DeadInsts);
return true; return true;
} }
// trunc(trunc) -> trunc
Register TruncSrc;
if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
// Always combine trunc(trunc) since the eventual resulting trunc must be
// legal anyway as it must be legal for all outputs of the consumer type
// set.
LLVM_DEBUG(dbgs() << ".. Combine G_TRUNC(G_TRUNC): " << MI);
arsenmUnsubmitted
Done
ReplyInline Actions

Scalar truncate always needs to be legal?

arsenm: Scalar truncate always needs to be legal?
gargaroffAuthorUnsubmitted
Done
ReplyInline Actions

Maybe I misunderstood the official docs. There it says for the minimal rule set:

G_TRUNC must be legal for all inputs from the producer type set and all smaller outputs from the consumer type set.

Is this out-of-date or misleading? If so, I'll remove the check (or maybe assert it). Downstream we were actually planning on making our G_TRUNC only legal if it fits our register size (with s1 being an exception), which is why we need this combine rule. If G_TRUNC always needs to be legal, should this be reflected in the documentation?

gargaroff: Maybe I misunderstood the official docs. There it says for the minimal rule set: >G_TRUNC must…
arsenmUnsubmitted
Done
ReplyInline Actions

I'm not sure. That rule doesn't reflect what is implemented in the in-tree targets. AArch64 for example does getActionDefinitionsBuilder(G_TRUNC).alwaysLegal(). For AMDGPU, I'm decomposing any vector truncates, but allowing any scalar up to the maximum bitwidth. One case I've been taking care around is degenerate, impossible to legalize cases. If you have an implicit use on a target instruction with an illegal truncate result type, we should probably just accept it regardless of legality (and not infinite loop in the legalizer).

arsenm: I'm not sure. That rule doesn't reflect what is implemented in the in-tree targets. AArch64 for…
gargaroffAuthorUnsubmitted
Done
ReplyInline Actions

I see, that is a good point. I guess we could safely remove this check. Most (all?) of the time the final remaining truncates after legalization should all result in legal result types anyway (thanks to the artifact combiner). If you somehow end up in a situation where all your instructions are already legal but a truncate is not, then you violated the rule that truncate must be legal for all smaller outputs from the consumer type set.

I guess that because truncates where not combined so far, you would often end up with this trunc(trunc) pattern which more or less forces you to have an alwaysLegal rule, because now suddenly the producer-set of trunc becomes the consumer-set of it too.

If you have an implicit use on a target instruction with an illegal truncate result type, we should probably just accept it regardless of legality

Wouldn't you say that an implicit-use is still a consumer and should therefore be legal according to the rule in the docs? Doesn't really matter here anymore, since I will remove the check anyway, but would be interesting to hear your opinion on this.

gargaroff: I see, that is a good point. I guess we could safely remove this check. Most (all?) of the time…
arsenmUnsubmitted
Not Done
ReplyInline Actions

Wouldn't you say that an implicit-use is still a consumer and should therefore be legal according to the rule in the docs? Doesn't really matter here anymore, since I will remove the check anyway, but would be interesting to hear your opinion on this.

Yes, although it's a bit contrived since any possible smaller type needs to be handled. Every target has unlegalizable consumers through arbitrary implicit uses

arsenm: > Wouldn't you say that an implicit-use is still a consumer and should therefore be legal…
Builder.buildTrunc(DstReg, TruncSrc);
UpdatedDefs.push_back(DstReg);
markInstAndDefDead(MI, *MRI.getVRegDef(TruncSrc), DeadInsts);
return true;
}
return false; return false;
} }
/// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF). /// Try to fold G_[ASZ]EXT (G_IMPLICIT_DEF).
bool tryFoldImplicitDef(MachineInstr &MI, bool tryFoldImplicitDef(MachineInstr &MI,
SmallVectorImpl<MachineInstr *> &DeadInsts, SmallVectorImpl<MachineInstr *> &DeadInsts,
SmallVectorImpl<Register> &UpdatedDefs) { SmallVectorImpl<Register> &UpdatedDefs) {
unsigned Opcode = MI.getOpcode(); unsigned Opcode = MI.getOpcode();
▲ Show 20 Lines • Show All 499 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-trunc.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s # RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
--- ---
name: test_load_trunc name: test_load_trunc
stack: stack:
- { id: 0, type: default, offset: 0, size: 2, - { id: 0, type: default, offset: 0, size: 2,
alignment: 2, stack-id: default, callee-saved-register: '', callee-saved-restored: true, alignment: 2, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_load_trunc ; CHECK-LABEL: name: test_load_trunc
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0 ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p0) :: (load 2) ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p0) :: (load 2)
; CHECK: [[TRUNC:%[0-9]+]]:_(s10) = G_TRUNC [[LOAD]](s16) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[LOAD]](s16)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNC]](s10) ; CHECK: RET_ReallyLR implicit [[TRUNC]](s1)
; CHECK: RET_ReallyLR implicit [[TRUNC1]](s1)
%0:_(p0) = G_FRAME_INDEX %stack.0 %0:_(p0) = G_FRAME_INDEX %stack.0
%1:_(s10) = G_LOAD %0(p0) :: (load 2) %1:_(s10) = G_LOAD %0(p0) :: (load 2)
%2:_(s1) = G_TRUNC %1(s10) %2:_(s1) = G_TRUNC %1(s10)
RET_ReallyLR implicit %2(s1) RET_ReallyLR implicit %2(s1)
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir

Show First 20 Lines • Show All 112 Lines • ▼ Show 20 Lines bb.0:
$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
... ...
--- ---
name: trunc_s68_merge_s128_s32 name: trunc_s68_merge_s128_s32
body: | body: |
bb.0: bb.0:
; Test that trunc(merge) with trunc-size > merge-source-size is not combined ; Test that trunc(merge) with trunc-size > merge-source-size and
; if trunc-size % merge-source-size != 0 ; trunc-size % merge-source-size != 0 can be combined after the G_TRUNCs
; have been combined.
; CHECK-LABEL: name: trunc_s68_merge_s128_s32 ; CHECK-LABEL: name: trunc_s68_merge_s128_s32
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[C]](s32), [[C1]](s32), [[C]](s32), [[C1]](s32) ; CHECK: $vgpr0 = COPY [[C]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s68) = G_TRUNC [[MV]](s128)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s68)
; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
%0:_(s32) = G_CONSTANT i32 0 %0:_(s32) = G_CONSTANT i32 0
%1:_(s32) = G_CONSTANT i32 1 %1:_(s32) = G_CONSTANT i32 1
%2:_(s128) = G_MERGE_VALUES %0, %1, %0, %1 %2:_(s128) = G_MERGE_VALUES %0, %1, %0, %1
%3:_(s68) = G_TRUNC %2 %3:_(s68) = G_TRUNC %2
%4:_(s32) = G_TRUNC %3 %4:_(s32) = G_TRUNC %3
$vgpr0 = COPY %4 $vgpr0 = COPY %4
... ...
---
name: trunc_trunc
body: |
bb.0:
; Test that trunc(trunc) is combined to a single trunc
; CHECK-LABEL: name: trunc_trunc
; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[DEF]](s64)
; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
%0:_(s64) = G_IMPLICIT_DEF
%1:_(s48) = G_TRUNC %0
%2:_(s32) = G_TRUNC %1
$vgpr0 = COPY %2
...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir

Show First 20 Lines • Show All 334 Lines • ▼ Show 20 Lines bb.0:
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C1]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]]
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) ; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32) ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[C2]], [[C]](s32)
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]] ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL1]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32) ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR1]](s32)
; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>) ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s16>) = G_CONCAT_VECTORS [[BITCAST]](<2 x s16>), [[BITCAST1]](<2 x s16>)
; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0 ; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[CONCAT_VECTORS]](<4 x s16>), 0
; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0 ; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[EXTRACT]](<3 x s16>), 0
; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>) ; CHECK: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[INSERT]](<4 x s16>)
; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>) ; CHECK: [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[UV2]](<2 x s16>)
; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32) ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST2]], [[C]](s32)
; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>) ; CHECK: [[BITCAST3:%[0-9]+]]:_(s32) = G_BITCAST [[UV3]](<2 x s16>)
; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32) ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST3]], [[C]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[BITCAST2]](s32)
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[BITCAST3]](s32)
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>) ; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s48) = G_TRUNC %0 %1:_(s48) = G_TRUNC %0
%2:_(<3 x s16>) = G_BITCAST %1 %2:_(<3 x s16>) = G_BITCAST %1
%3:_(<3 x s32>) = G_ANYEXT %2 %3:_(<3 x s32>) = G_ANYEXT %2
$vgpr0_vgpr1_vgpr2 = COPY %3 $vgpr0_vgpr1_vgpr2 = COPY %3
... ...
▲ Show 20 Lines • Show All 130 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
name: test_extract_s16_s31_offset0 name: test_extract_s16_s31_offset0
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_extract_s16_s31_offset0 ; CHECK-LABEL: name: test_extract_s16_s31_offset0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[TRUNC]](s32) ; CHECK: $vgpr0 = COPY [[TRUNC]](s32)
; CHECK: $vgpr0 = COPY [[COPY1]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s31) = G_TRUNC %0 %1:_(s31) = G_TRUNC %0
%2:_(s16) = G_EXTRACT %1, 0 %2:_(s16) = G_EXTRACT %1, 0
%3:_(s32) = G_ANYEXT %2 %3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
▲ Show 20 Lines • Show All 1,091 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir

# RUN: not --crash llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - 2>&1 | FileCheck %s # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: not --crash llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - 2>&1 | FileCheck %s # RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=TAHITI
# RUN: llc -O0 -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=FIJI
# This test is not legalizable and produces more than 9000 instructions for it
# before it fails, including legalizer artifacts like
# %foo:_(s65600) = G_MERGE_VALUES. Since it is not really feasible to have that
# many CHECK-lines, only the presence of the error is checked.
--- ---
name: test_implicit_def_s1025 name: test_implicit_def_s1025
body: | body: |
bb.0: bb.0:
; CHECK: LLVM ERROR: unable to legalize instruction: %{{[0-9]+}}:_(s65600) = G_MERGE_VALUES ; TAHITI-LABEL: name: test_implicit_def_s1025
; TAHITI: [[DEF:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF
; TAHITI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s1024)
; TAHITI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; TAHITI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; TAHITI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; TAHITI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; TAHITI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; TAHITI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; TAHITI: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; TAHITI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; TAHITI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C3]]
; TAHITI: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY]](s32)
; TAHITI: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; TAHITI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; TAHITI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
; TAHITI: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY2]](s32)
; TAHITI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
; TAHITI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; TAHITI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C3]]
; TAHITI: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY4]](s32)
; TAHITI: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; TAHITI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; TAHITI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C3]]
; TAHITI: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY6]](s32)
; TAHITI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; TAHITI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; TAHITI: [[COPY9:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
; TAHITI: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY8]](s32)
; TAHITI: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
; TAHITI: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; TAHITI: [[COPY11:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
; TAHITI: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY10]](s32)
; TAHITI: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
; TAHITI: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; TAHITI: [[COPY13:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
; TAHITI: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY12]](s32)
; TAHITI: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; TAHITI: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; TAHITI: [[COPY15:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
; TAHITI: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY14]](s32)
; TAHITI: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; TAHITI: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; TAHITI: [[COPY17:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C3]]
; TAHITI: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY16]](s32)
; TAHITI: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; TAHITI: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; TAHITI: [[COPY19:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C3]]
; TAHITI: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[COPY18]](s32)
; TAHITI: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
; TAHITI: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; TAHITI: [[COPY21:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C3]]
; TAHITI: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[COPY20]](s32)
; TAHITI: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
; TAHITI: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; TAHITI: [[COPY23:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY23]], [[C3]]
; TAHITI: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[COPY22]](s32)
; TAHITI: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 13
; TAHITI: [[COPY24:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; TAHITI: [[COPY25:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY25]], [[C3]]
; TAHITI: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND12]], [[COPY24]](s32)
; TAHITI: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 14
; TAHITI: [[COPY26:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; TAHITI: [[COPY27:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY27]], [[C3]]
; TAHITI: [[LSHR14:%[0-9]+]]:_(s32) = G_LSHR [[AND13]], [[COPY26]](s32)
; TAHITI: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
; TAHITI: [[COPY28:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; TAHITI: [[COPY29:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
; TAHITI: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY29]], [[C3]]
; TAHITI: [[LSHR15:%[0-9]+]]:_(s32) = G_LSHR [[AND14]], [[COPY28]](s32)
; TAHITI: [[COPY30:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; TAHITI: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY31]], [[C3]]
; TAHITI: [[LSHR16:%[0-9]+]]:_(s32) = G_LSHR [[AND15]], [[COPY30]](s32)
; TAHITI: [[COPY32:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; TAHITI: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY33]], [[C3]]
; TAHITI: [[LSHR17:%[0-9]+]]:_(s32) = G_LSHR [[AND16]], [[COPY32]](s32)
; TAHITI: [[COPY34:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; TAHITI: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY35]], [[C3]]
; TAHITI: [[LSHR18:%[0-9]+]]:_(s32) = G_LSHR [[AND17]], [[COPY34]](s32)
; TAHITI: [[COPY36:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; TAHITI: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND18:%[0-9]+]]:_(s32) = G_AND [[COPY37]], [[C3]]
; TAHITI: [[LSHR19:%[0-9]+]]:_(s32) = G_LSHR [[AND18]], [[COPY36]](s32)
; TAHITI: [[COPY38:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; TAHITI: [[COPY39:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND19:%[0-9]+]]:_(s32) = G_AND [[COPY39]], [[C3]]
; TAHITI: [[LSHR20:%[0-9]+]]:_(s32) = G_LSHR [[AND19]], [[COPY38]](s32)
; TAHITI: [[COPY40:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; TAHITI: [[COPY41:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND20:%[0-9]+]]:_(s32) = G_AND [[COPY41]], [[C3]]
; TAHITI: [[LSHR21:%[0-9]+]]:_(s32) = G_LSHR [[AND20]], [[COPY40]](s32)
; TAHITI: [[COPY42:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; TAHITI: [[COPY43:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND21:%[0-9]+]]:_(s32) = G_AND [[COPY43]], [[C3]]
; TAHITI: [[LSHR22:%[0-9]+]]:_(s32) = G_LSHR [[AND21]], [[COPY42]](s32)
; TAHITI: [[COPY44:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; TAHITI: [[COPY45:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND22:%[0-9]+]]:_(s32) = G_AND [[COPY45]], [[C3]]
; TAHITI: [[LSHR23:%[0-9]+]]:_(s32) = G_LSHR [[AND22]], [[COPY44]](s32)
; TAHITI: [[COPY46:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; TAHITI: [[COPY47:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND23:%[0-9]+]]:_(s32) = G_AND [[COPY47]], [[C3]]
; TAHITI: [[LSHR24:%[0-9]+]]:_(s32) = G_LSHR [[AND23]], [[COPY46]](s32)
; TAHITI: [[COPY48:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; TAHITI: [[COPY49:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND24:%[0-9]+]]:_(s32) = G_AND [[COPY49]], [[C3]]
; TAHITI: [[LSHR25:%[0-9]+]]:_(s32) = G_LSHR [[AND24]], [[COPY48]](s32)
; TAHITI: [[COPY50:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; TAHITI: [[COPY51:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND25:%[0-9]+]]:_(s32) = G_AND [[COPY51]], [[C3]]
; TAHITI: [[LSHR26:%[0-9]+]]:_(s32) = G_LSHR [[AND25]], [[COPY50]](s32)
; TAHITI: [[COPY52:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; TAHITI: [[COPY53:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND26:%[0-9]+]]:_(s32) = G_AND [[COPY53]], [[C3]]
; TAHITI: [[LSHR27:%[0-9]+]]:_(s32) = G_LSHR [[AND26]], [[COPY52]](s32)
; TAHITI: [[COPY54:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; TAHITI: [[COPY55:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND27:%[0-9]+]]:_(s32) = G_AND [[COPY55]], [[C3]]
; TAHITI: [[LSHR28:%[0-9]+]]:_(s32) = G_LSHR [[AND27]], [[COPY54]](s32)
; TAHITI: [[COPY56:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; TAHITI: [[COPY57:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND28:%[0-9]+]]:_(s32) = G_AND [[COPY57]], [[C3]]
; TAHITI: [[LSHR29:%[0-9]+]]:_(s32) = G_LSHR [[AND28]], [[COPY56]](s32)
; TAHITI: [[COPY58:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; TAHITI: [[COPY59:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; TAHITI: [[AND29:%[0-9]+]]:_(s32) = G_AND [[COPY59]], [[C3]]
; TAHITI: [[LSHR30:%[0-9]+]]:_(s32) = G_LSHR [[AND29]], [[COPY58]](s32)
; TAHITI: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; TAHITI: [[COPY60:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; TAHITI: [[AND30:%[0-9]+]]:_(s16) = G_AND [[COPY60]], [[C1]]
; TAHITI: [[COPY61:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; TAHITI: [[COPY62:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
; TAHITI: [[AND31:%[0-9]+]]:_(s32) = G_AND [[COPY62]], [[C2]]
; TAHITI: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND31]], [[COPY61]](s32)
; TAHITI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
; TAHITI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND30]], [[TRUNC2]]
; TAHITI: [[COPY63:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
; TAHITI: [[COPY64:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
; TAHITI: [[AND32:%[0-9]+]]:_(s32) = G_AND [[COPY64]], [[C2]]
; TAHITI: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND32]], [[COPY63]](s32)
; TAHITI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
; TAHITI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[TRUNC3]]
; TAHITI: [[COPY65:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
; TAHITI: [[COPY66:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
; TAHITI: [[AND33:%[0-9]+]]:_(s32) = G_AND [[COPY66]], [[C2]]
; TAHITI: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND33]], [[COPY65]](s32)
; TAHITI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
; TAHITI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[TRUNC4]]
; TAHITI: [[COPY67:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
; TAHITI: [[COPY68:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
; TAHITI: [[AND34:%[0-9]+]]:_(s32) = G_AND [[COPY68]], [[C2]]
; TAHITI: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND34]], [[COPY67]](s32)
; TAHITI: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
; TAHITI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[OR2]], [[TRUNC5]]
; TAHITI: [[COPY69:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
; TAHITI: [[COPY70:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
; TAHITI: [[AND35:%[0-9]+]]:_(s32) = G_AND [[COPY70]], [[C2]]
; TAHITI: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND35]], [[COPY69]](s32)
; TAHITI: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
; TAHITI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[TRUNC6]]
; TAHITI: [[COPY71:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
; TAHITI: [[COPY72:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
; TAHITI: [[AND36:%[0-9]+]]:_(s32) = G_AND [[COPY72]], [[C2]]
; TAHITI: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND36]], [[COPY71]](s32)
; TAHITI: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
; TAHITI: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[TRUNC7]]
; TAHITI: [[COPY73:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
; TAHITI: [[COPY74:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
; TAHITI: [[AND37:%[0-9]+]]:_(s32) = G_AND [[COPY74]], [[C2]]
; TAHITI: [[SHL6:%[0-9]+]]:_(s32) = G_SHL [[AND37]], [[COPY73]](s32)
; TAHITI: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL6]](s32)
; TAHITI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[OR5]], [[TRUNC8]]
; TAHITI: [[COPY75:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
; TAHITI: [[COPY76:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
; TAHITI: [[AND38:%[0-9]+]]:_(s32) = G_AND [[COPY76]], [[C2]]
; TAHITI: [[SHL7:%[0-9]+]]:_(s32) = G_SHL [[AND38]], [[COPY75]](s32)
; TAHITI: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[SHL7]](s32)
; TAHITI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[OR6]], [[TRUNC9]]
; TAHITI: [[COPY77:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
; TAHITI: [[COPY78:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
; TAHITI: [[AND39:%[0-9]+]]:_(s32) = G_AND [[COPY78]], [[C2]]
; TAHITI: [[SHL8:%[0-9]+]]:_(s32) = G_SHL [[AND39]], [[COPY77]](s32)
; TAHITI: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL8]](s32)
; TAHITI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[OR7]], [[TRUNC10]]
; TAHITI: [[COPY79:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
; TAHITI: [[COPY80:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
; TAHITI: [[AND40:%[0-9]+]]:_(s32) = G_AND [[COPY80]], [[C2]]
; TAHITI: [[SHL9:%[0-9]+]]:_(s32) = G_SHL [[AND40]], [[COPY79]](s32)
; TAHITI: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[SHL9]](s32)
; TAHITI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[OR8]], [[TRUNC11]]
; TAHITI: [[COPY81:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
; TAHITI: [[COPY82:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
; TAHITI: [[AND41:%[0-9]+]]:_(s32) = G_AND [[COPY82]], [[C2]]
; TAHITI: [[SHL10:%[0-9]+]]:_(s32) = G_SHL [[AND41]], [[COPY81]](s32)
; TAHITI: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL10]](s32)
; TAHITI: [[OR10:%[0-9]+]]:_(s16) = G_OR [[OR9]], [[TRUNC12]]
; TAHITI: [[COPY83:%[0-9]+]]:_(s32) = COPY [[C14]](s32)
; TAHITI: [[COPY84:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
; TAHITI: [[AND42:%[0-9]+]]:_(s32) = G_AND [[COPY84]], [[C2]]
; TAHITI: [[SHL11:%[0-9]+]]:_(s32) = G_SHL [[AND42]], [[COPY83]](s32)
; TAHITI: [[TRUNC13:%[0-9]+]]:_(s16) = G_TRUNC [[SHL11]](s32)
; TAHITI: [[OR11:%[0-9]+]]:_(s16) = G_OR [[OR10]], [[TRUNC13]]
; TAHITI: [[COPY85:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
; TAHITI: [[COPY86:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
; TAHITI: [[AND43:%[0-9]+]]:_(s32) = G_AND [[COPY86]], [[C2]]
; TAHITI: [[SHL12:%[0-9]+]]:_(s32) = G_SHL [[AND43]], [[COPY85]](s32)
; TAHITI: [[TRUNC14:%[0-9]+]]:_(s16) = G_TRUNC [[SHL12]](s32)
; TAHITI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[OR11]], [[TRUNC14]]
; TAHITI: [[COPY87:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
; TAHITI: [[COPY88:%[0-9]+]]:_(s32) = COPY [[LSHR14]](s32)
; TAHITI: [[AND44:%[0-9]+]]:_(s32) = G_AND [[COPY88]], [[C2]]
; TAHITI: [[SHL13:%[0-9]+]]:_(s32) = G_SHL [[AND44]], [[COPY87]](s32)
; TAHITI: [[TRUNC15:%[0-9]+]]:_(s16) = G_TRUNC [[SHL13]](s32)
; TAHITI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[OR12]], [[TRUNC15]]
; TAHITI: [[COPY89:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
; TAHITI: [[COPY90:%[0-9]+]]:_(s32) = COPY [[LSHR15]](s32)
; TAHITI: [[AND45:%[0-9]+]]:_(s32) = G_AND [[COPY90]], [[C2]]
; TAHITI: [[SHL14:%[0-9]+]]:_(s32) = G_SHL [[AND45]], [[COPY89]](s32)
; TAHITI: [[TRUNC16:%[0-9]+]]:_(s16) = G_TRUNC [[SHL14]](s32)
; TAHITI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[OR13]], [[TRUNC16]]
; TAHITI: [[COPY91:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; TAHITI: [[AND46:%[0-9]+]]:_(s16) = G_AND [[COPY91]], [[C1]]
; TAHITI: [[COPY92:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
; TAHITI: [[COPY93:%[0-9]+]]:_(s32) = COPY [[LSHR16]](s32)
; TAHITI: [[AND47:%[0-9]+]]:_(s32) = G_AND [[COPY93]], [[C2]]
; TAHITI: [[SHL15:%[0-9]+]]:_(s32) = G_SHL [[AND47]], [[COPY92]](s32)
; TAHITI: [[TRUNC17:%[0-9]+]]:_(s16) = G_TRUNC [[SHL15]](s32)
; TAHITI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND46]], [[TRUNC17]]
; TAHITI: [[COPY94:%[0-9]+]]:_(s32) = COPY [[LSHR17]](s32)
; TAHITI: [[AND48:%[0-9]+]]:_(s32) = G_AND [[COPY94]], [[C2]]
; TAHITI: [[SHL16:%[0-9]+]]:_(s32) = G_SHL [[AND48]], [[C4]](s32)
; TAHITI: [[TRUNC18:%[0-9]+]]:_(s16) = G_TRUNC [[SHL16]](s32)
; TAHITI: [[OR16:%[0-9]+]]:_(s16) = G_OR [[OR15]], [[TRUNC18]]
; TAHITI: [[COPY95:%[0-9]+]]:_(s32) = COPY [[LSHR18]](s32)
; TAHITI: [[AND49:%[0-9]+]]:_(s32) = G_AND [[COPY95]], [[C2]]
; TAHITI: [[SHL17:%[0-9]+]]:_(s32) = G_SHL [[AND49]], [[C5]](s32)
; TAHITI: [[TRUNC19:%[0-9]+]]:_(s16) = G_TRUNC [[SHL17]](s32)
; TAHITI: [[OR17:%[0-9]+]]:_(s16) = G_OR [[OR16]], [[TRUNC19]]
; TAHITI: [[COPY96:%[0-9]+]]:_(s32) = COPY [[LSHR19]](s32)
; TAHITI: [[AND50:%[0-9]+]]:_(s32) = G_AND [[COPY96]], [[C2]]
; TAHITI: [[SHL18:%[0-9]+]]:_(s32) = G_SHL [[AND50]], [[C6]](s32)
; TAHITI: [[TRUNC20:%[0-9]+]]:_(s16) = G_TRUNC [[SHL18]](s32)
; TAHITI: [[OR18:%[0-9]+]]:_(s16) = G_OR [[OR17]], [[TRUNC20]]
; TAHITI: [[COPY97:%[0-9]+]]:_(s32) = COPY [[LSHR20]](s32)
; TAHITI: [[AND51:%[0-9]+]]:_(s32) = G_AND [[COPY97]], [[C2]]
; TAHITI: [[SHL19:%[0-9]+]]:_(s32) = G_SHL [[AND51]], [[C7]](s32)
; TAHITI: [[TRUNC21:%[0-9]+]]:_(s16) = G_TRUNC [[SHL19]](s32)
; TAHITI: [[OR19:%[0-9]+]]:_(s16) = G_OR [[OR18]], [[TRUNC21]]
; TAHITI: [[COPY98:%[0-9]+]]:_(s32) = COPY [[LSHR21]](s32)
; TAHITI: [[AND52:%[0-9]+]]:_(s32) = G_AND [[COPY98]], [[C2]]
; TAHITI: [[SHL20:%[0-9]+]]:_(s32) = G_SHL [[AND52]], [[C8]](s32)
; TAHITI: [[TRUNC22:%[0-9]+]]:_(s16) = G_TRUNC [[SHL20]](s32)
; TAHITI: [[OR20:%[0-9]+]]:_(s16) = G_OR [[OR19]], [[TRUNC22]]
; TAHITI: [[COPY99:%[0-9]+]]:_(s32) = COPY [[LSHR22]](s32)
; TAHITI: [[AND53:%[0-9]+]]:_(s32) = G_AND [[COPY99]], [[C2]]
; TAHITI: [[SHL21:%[0-9]+]]:_(s32) = G_SHL [[AND53]], [[C9]](s32)
; TAHITI: [[TRUNC23:%[0-9]+]]:_(s16) = G_TRUNC [[SHL21]](s32)
; TAHITI: [[OR21:%[0-9]+]]:_(s16) = G_OR [[OR20]], [[TRUNC23]]
; TAHITI: [[COPY100:%[0-9]+]]:_(s32) = COPY [[LSHR23]](s32)
; TAHITI: [[AND54:%[0-9]+]]:_(s32) = G_AND [[COPY100]], [[C2]]
; TAHITI: [[SHL22:%[0-9]+]]:_(s32) = G_SHL [[AND54]], [[C10]](s32)
; TAHITI: [[TRUNC24:%[0-9]+]]:_(s16) = G_TRUNC [[SHL22]](s32)
; TAHITI: [[OR22:%[0-9]+]]:_(s16) = G_OR [[OR21]], [[TRUNC24]]
; TAHITI: [[COPY101:%[0-9]+]]:_(s32) = COPY [[LSHR24]](s32)
; TAHITI: [[AND55:%[0-9]+]]:_(s32) = G_AND [[COPY101]], [[C2]]
; TAHITI: [[SHL23:%[0-9]+]]:_(s32) = G_SHL [[AND55]], [[C11]](s32)
; TAHITI: [[TRUNC25:%[0-9]+]]:_(s16) = G_TRUNC [[SHL23]](s32)
; TAHITI: [[OR23:%[0-9]+]]:_(s16) = G_OR [[OR22]], [[TRUNC25]]
; TAHITI: [[COPY102:%[0-9]+]]:_(s32) = COPY [[LSHR25]](s32)
; TAHITI: [[AND56:%[0-9]+]]:_(s32) = G_AND [[COPY102]], [[C2]]
; TAHITI: [[SHL24:%[0-9]+]]:_(s32) = G_SHL [[AND56]], [[C12]](s32)
; TAHITI: [[TRUNC26:%[0-9]+]]:_(s16) = G_TRUNC [[SHL24]](s32)
; TAHITI: [[OR24:%[0-9]+]]:_(s16) = G_OR [[OR23]], [[TRUNC26]]
; TAHITI: [[COPY103:%[0-9]+]]:_(s32) = COPY [[LSHR26]](s32)
; TAHITI: [[AND57:%[0-9]+]]:_(s32) = G_AND [[COPY103]], [[C2]]
; TAHITI: [[SHL25:%[0-9]+]]:_(s32) = G_SHL [[AND57]], [[C13]](s32)
; TAHITI: [[TRUNC27:%[0-9]+]]:_(s16) = G_TRUNC [[SHL25]](s32)
; TAHITI: [[OR25:%[0-9]+]]:_(s16) = G_OR [[OR24]], [[TRUNC27]]
; TAHITI: [[COPY104:%[0-9]+]]:_(s32) = COPY [[LSHR27]](s32)
; TAHITI: [[AND58:%[0-9]+]]:_(s32) = G_AND [[COPY104]], [[C2]]
; TAHITI: [[SHL26:%[0-9]+]]:_(s32) = G_SHL [[AND58]], [[C14]](s32)
; TAHITI: [[TRUNC28:%[0-9]+]]:_(s16) = G_TRUNC [[SHL26]](s32)
; TAHITI: [[OR26:%[0-9]+]]:_(s16) = G_OR [[OR25]], [[TRUNC28]]
; TAHITI: [[COPY105:%[0-9]+]]:_(s32) = COPY [[LSHR28]](s32)
; TAHITI: [[AND59:%[0-9]+]]:_(s32) = G_AND [[COPY105]], [[C2]]
; TAHITI: [[SHL27:%[0-9]+]]:_(s32) = G_SHL [[AND59]], [[C15]](s32)
; TAHITI: [[TRUNC29:%[0-9]+]]:_(s16) = G_TRUNC [[SHL27]](s32)
; TAHITI: [[OR27:%[0-9]+]]:_(s16) = G_OR [[OR26]], [[TRUNC29]]
; TAHITI: [[COPY106:%[0-9]+]]:_(s32) = COPY [[LSHR29]](s32)
; TAHITI: [[AND60:%[0-9]+]]:_(s32) = G_AND [[COPY106]], [[C2]]
; TAHITI: [[SHL28:%[0-9]+]]:_(s32) = G_SHL [[AND60]], [[C16]](s32)
; TAHITI: [[TRUNC30:%[0-9]+]]:_(s16) = G_TRUNC [[SHL28]](s32)
; TAHITI: [[OR28:%[0-9]+]]:_(s16) = G_OR [[OR27]], [[TRUNC30]]
; TAHITI: [[COPY107:%[0-9]+]]:_(s32) = COPY [[LSHR30]](s32)
; TAHITI: [[AND61:%[0-9]+]]:_(s32) = G_AND [[COPY107]], [[C2]]
; TAHITI: [[SHL29:%[0-9]+]]:_(s32) = G_SHL [[AND61]], [[C17]](s32)
; TAHITI: [[TRUNC31:%[0-9]+]]:_(s16) = G_TRUNC [[SHL29]](s32)
; TAHITI: [[OR29:%[0-9]+]]:_(s16) = G_OR [[OR28]], [[TRUNC31]]
; TAHITI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR14]](s16)
; TAHITI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR29]](s16)
; TAHITI: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; TAHITI: [[OR30:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL30]]
; TAHITI: $vgpr0 = COPY [[OR30]](s32)
; FIJI-LABEL: name: test_implicit_def_s1025
; FIJI: [[DEF:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF
; FIJI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s1024)
; FIJI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[UV]](s32)
; FIJI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; FIJI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
; FIJI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
; FIJI: [[C1:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
; FIJI: [[LSHR1:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C1]](s16)
; FIJI: [[C2:%[0-9]+]]:_(s16) = G_CONSTANT i16 2
; FIJI: [[LSHR2:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C2]](s16)
; FIJI: [[C3:%[0-9]+]]:_(s16) = G_CONSTANT i16 3
; FIJI: [[LSHR3:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C3]](s16)
; FIJI: [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; FIJI: [[LSHR4:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C4]](s16)
; FIJI: [[C5:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
; FIJI: [[LSHR5:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C5]](s16)
; FIJI: [[C6:%[0-9]+]]:_(s16) = G_CONSTANT i16 6
; FIJI: [[LSHR6:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C6]](s16)
; FIJI: [[C7:%[0-9]+]]:_(s16) = G_CONSTANT i16 7
; FIJI: [[LSHR7:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C7]](s16)
; FIJI: [[C8:%[0-9]+]]:_(s16) = G_CONSTANT i16 8
; FIJI: [[LSHR8:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C8]](s16)
; FIJI: [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 9
; FIJI: [[LSHR9:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C9]](s16)
; FIJI: [[C10:%[0-9]+]]:_(s16) = G_CONSTANT i16 10
; FIJI: [[LSHR10:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C10]](s16)
; FIJI: [[C11:%[0-9]+]]:_(s16) = G_CONSTANT i16 11
; FIJI: [[LSHR11:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C11]](s16)
; FIJI: [[C12:%[0-9]+]]:_(s16) = G_CONSTANT i16 12
; FIJI: [[LSHR12:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C12]](s16)
; FIJI: [[C13:%[0-9]+]]:_(s16) = G_CONSTANT i16 13
; FIJI: [[LSHR13:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C13]](s16)
; FIJI: [[C14:%[0-9]+]]:_(s16) = G_CONSTANT i16 14
; FIJI: [[LSHR14:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C14]](s16)
; FIJI: [[C15:%[0-9]+]]:_(s16) = G_CONSTANT i16 15
; FIJI: [[LSHR15:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[C15]](s16)
; FIJI: [[LSHR16:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C1]](s16)
; FIJI: [[LSHR17:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C2]](s16)
; FIJI: [[LSHR18:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C3]](s16)
; FIJI: [[LSHR19:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C4]](s16)
; FIJI: [[LSHR20:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C5]](s16)
; FIJI: [[LSHR21:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C6]](s16)
; FIJI: [[LSHR22:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C7]](s16)
; FIJI: [[LSHR23:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C8]](s16)
; FIJI: [[LSHR24:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C9]](s16)
; FIJI: [[LSHR25:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C10]](s16)
; FIJI: [[LSHR26:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C11]](s16)
; FIJI: [[LSHR27:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C12]](s16)
; FIJI: [[LSHR28:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C13]](s16)
; FIJI: [[LSHR29:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C14]](s16)
; FIJI: [[LSHR30:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[C15]](s16)
; FIJI: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; FIJI: [[COPY:%[0-9]+]]:_(s16) = COPY [[TRUNC]](s16)
; FIJI: [[AND:%[0-9]+]]:_(s16) = G_AND [[COPY]], [[C1]]
; FIJI: [[COPY1:%[0-9]+]]:_(s16) = COPY [[LSHR1]](s16)
; FIJI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[COPY1]], [[C1]]
; FIJI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[AND1]], [[C1]](s16)
; FIJI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[SHL]]
; FIJI: [[COPY2:%[0-9]+]]:_(s16) = COPY [[LSHR2]](s16)
; FIJI: [[AND2:%[0-9]+]]:_(s16) = G_AND [[COPY2]], [[C1]]
; FIJI: [[SHL1:%[0-9]+]]:_(s16) = G_SHL [[AND2]], [[C2]](s16)
; FIJI: [[OR1:%[0-9]+]]:_(s16) = G_OR [[OR]], [[SHL1]]
; FIJI: [[COPY3:%[0-9]+]]:_(s16) = COPY [[LSHR3]](s16)
; FIJI: [[AND3:%[0-9]+]]:_(s16) = G_AND [[COPY3]], [[C1]]
; FIJI: [[SHL2:%[0-9]+]]:_(s16) = G_SHL [[AND3]], [[C3]](s16)
; FIJI: [[OR2:%[0-9]+]]:_(s16) = G_OR [[OR1]], [[SHL2]]
; FIJI: [[COPY4:%[0-9]+]]:_(s16) = COPY [[LSHR4]](s16)
; FIJI: [[AND4:%[0-9]+]]:_(s16) = G_AND [[COPY4]], [[C1]]
; FIJI: [[SHL3:%[0-9]+]]:_(s16) = G_SHL [[AND4]], [[C4]](s16)
; FIJI: [[OR3:%[0-9]+]]:_(s16) = G_OR [[OR2]], [[SHL3]]
; FIJI: [[COPY5:%[0-9]+]]:_(s16) = COPY [[LSHR5]](s16)
; FIJI: [[AND5:%[0-9]+]]:_(s16) = G_AND [[COPY5]], [[C1]]
; FIJI: [[SHL4:%[0-9]+]]:_(s16) = G_SHL [[AND5]], [[C5]](s16)
; FIJI: [[OR4:%[0-9]+]]:_(s16) = G_OR [[OR3]], [[SHL4]]
; FIJI: [[COPY6:%[0-9]+]]:_(s16) = COPY [[LSHR6]](s16)
; FIJI: [[AND6:%[0-9]+]]:_(s16) = G_AND [[COPY6]], [[C1]]
; FIJI: [[SHL5:%[0-9]+]]:_(s16) = G_SHL [[AND6]], [[C6]](s16)
; FIJI: [[OR5:%[0-9]+]]:_(s16) = G_OR [[OR4]], [[SHL5]]
; FIJI: [[COPY7:%[0-9]+]]:_(s16) = COPY [[LSHR7]](s16)
; FIJI: [[AND7:%[0-9]+]]:_(s16) = G_AND [[COPY7]], [[C1]]
; FIJI: [[SHL6:%[0-9]+]]:_(s16) = G_SHL [[AND7]], [[C7]](s16)
; FIJI: [[OR6:%[0-9]+]]:_(s16) = G_OR [[OR5]], [[SHL6]]
; FIJI: [[COPY8:%[0-9]+]]:_(s16) = COPY [[LSHR8]](s16)
; FIJI: [[AND8:%[0-9]+]]:_(s16) = G_AND [[COPY8]], [[C1]]
; FIJI: [[SHL7:%[0-9]+]]:_(s16) = G_SHL [[AND8]], [[C8]](s16)
; FIJI: [[OR7:%[0-9]+]]:_(s16) = G_OR [[OR6]], [[SHL7]]
; FIJI: [[COPY9:%[0-9]+]]:_(s16) = COPY [[LSHR9]](s16)
; FIJI: [[AND9:%[0-9]+]]:_(s16) = G_AND [[COPY9]], [[C1]]
; FIJI: [[SHL8:%[0-9]+]]:_(s16) = G_SHL [[AND9]], [[C9]](s16)
; FIJI: [[OR8:%[0-9]+]]:_(s16) = G_OR [[OR7]], [[SHL8]]
; FIJI: [[COPY10:%[0-9]+]]:_(s16) = COPY [[LSHR10]](s16)
; FIJI: [[AND10:%[0-9]+]]:_(s16) = G_AND [[COPY10]], [[C1]]
; FIJI: [[SHL9:%[0-9]+]]:_(s16) = G_SHL [[AND10]], [[C10]](s16)
; FIJI: [[OR9:%[0-9]+]]:_(s16) = G_OR [[OR8]], [[SHL9]]
; FIJI: [[COPY11:%[0-9]+]]:_(s16) = COPY [[LSHR11]](s16)
; FIJI: [[AND11:%[0-9]+]]:_(s16) = G_AND [[COPY11]], [[C1]]
; FIJI: [[SHL10:%[0-9]+]]:_(s16) = G_SHL [[AND11]], [[C11]](s16)
; FIJI: [[OR10:%[0-9]+]]:_(s16) = G_OR [[OR9]], [[SHL10]]
; FIJI: [[COPY12:%[0-9]+]]:_(s16) = COPY [[LSHR12]](s16)
; FIJI: [[AND12:%[0-9]+]]:_(s16) = G_AND [[COPY12]], [[C1]]
; FIJI: [[SHL11:%[0-9]+]]:_(s16) = G_SHL [[AND12]], [[C12]](s16)
; FIJI: [[OR11:%[0-9]+]]:_(s16) = G_OR [[OR10]], [[SHL11]]
; FIJI: [[COPY13:%[0-9]+]]:_(s16) = COPY [[LSHR13]](s16)
; FIJI: [[AND13:%[0-9]+]]:_(s16) = G_AND [[COPY13]], [[C1]]
; FIJI: [[SHL12:%[0-9]+]]:_(s16) = G_SHL [[AND13]], [[C13]](s16)
; FIJI: [[OR12:%[0-9]+]]:_(s16) = G_OR [[OR11]], [[SHL12]]
; FIJI: [[COPY14:%[0-9]+]]:_(s16) = COPY [[LSHR14]](s16)
; FIJI: [[AND14:%[0-9]+]]:_(s16) = G_AND [[COPY14]], [[C1]]
; FIJI: [[SHL13:%[0-9]+]]:_(s16) = G_SHL [[AND14]], [[C14]](s16)
; FIJI: [[OR13:%[0-9]+]]:_(s16) = G_OR [[OR12]], [[SHL13]]
; FIJI: [[COPY15:%[0-9]+]]:_(s16) = COPY [[LSHR15]](s16)
; FIJI: [[AND15:%[0-9]+]]:_(s16) = G_AND [[COPY15]], [[C1]]
; FIJI: [[SHL14:%[0-9]+]]:_(s16) = G_SHL [[AND15]], [[C15]](s16)
; FIJI: [[OR14:%[0-9]+]]:_(s16) = G_OR [[OR13]], [[SHL14]]
; FIJI: [[COPY16:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; FIJI: [[AND16:%[0-9]+]]:_(s16) = G_AND [[COPY16]], [[C1]]
; FIJI: [[COPY17:%[0-9]+]]:_(s16) = COPY [[LSHR16]](s16)
; FIJI: [[AND17:%[0-9]+]]:_(s16) = G_AND [[COPY17]], [[C1]]
; FIJI: [[SHL15:%[0-9]+]]:_(s16) = G_SHL [[AND17]], [[C1]](s16)
; FIJI: [[OR15:%[0-9]+]]:_(s16) = G_OR [[AND16]], [[SHL15]]
; FIJI: [[COPY18:%[0-9]+]]:_(s16) = COPY [[LSHR17]](s16)
; FIJI: [[AND18:%[0-9]+]]:_(s16) = G_AND [[COPY18]], [[C1]]
; FIJI: [[SHL16:%[0-9]+]]:_(s16) = G_SHL [[AND18]], [[C2]](s16)
; FIJI: [[OR16:%[0-9]+]]:_(s16) = G_OR [[OR15]], [[SHL16]]
; FIJI: [[COPY19:%[0-9]+]]:_(s16) = COPY [[LSHR18]](s16)
; FIJI: [[AND19:%[0-9]+]]:_(s16) = G_AND [[COPY19]], [[C1]]
; FIJI: [[SHL17:%[0-9]+]]:_(s16) = G_SHL [[AND19]], [[C3]](s16)
; FIJI: [[OR17:%[0-9]+]]:_(s16) = G_OR [[OR16]], [[SHL17]]
; FIJI: [[COPY20:%[0-9]+]]:_(s16) = COPY [[LSHR19]](s16)
; FIJI: [[AND20:%[0-9]+]]:_(s16) = G_AND [[COPY20]], [[C1]]
; FIJI: [[SHL18:%[0-9]+]]:_(s16) = G_SHL [[AND20]], [[C4]](s16)
; FIJI: [[OR18:%[0-9]+]]:_(s16) = G_OR [[OR17]], [[SHL18]]
; FIJI: [[COPY21:%[0-9]+]]:_(s16) = COPY [[LSHR20]](s16)
; FIJI: [[AND21:%[0-9]+]]:_(s16) = G_AND [[COPY21]], [[C1]]
; FIJI: [[SHL19:%[0-9]+]]:_(s16) = G_SHL [[AND21]], [[C5]](s16)
; FIJI: [[OR19:%[0-9]+]]:_(s16) = G_OR [[OR18]], [[SHL19]]
; FIJI: [[COPY22:%[0-9]+]]:_(s16) = COPY [[LSHR21]](s16)
; FIJI: [[AND22:%[0-9]+]]:_(s16) = G_AND [[COPY22]], [[C1]]
; FIJI: [[SHL20:%[0-9]+]]:_(s16) = G_SHL [[AND22]], [[C6]](s16)
; FIJI: [[OR20:%[0-9]+]]:_(s16) = G_OR [[OR19]], [[SHL20]]
; FIJI: [[COPY23:%[0-9]+]]:_(s16) = COPY [[LSHR22]](s16)
; FIJI: [[AND23:%[0-9]+]]:_(s16) = G_AND [[COPY23]], [[C1]]
; FIJI: [[SHL21:%[0-9]+]]:_(s16) = G_SHL [[AND23]], [[C7]](s16)
; FIJI: [[OR21:%[0-9]+]]:_(s16) = G_OR [[OR20]], [[SHL21]]
; FIJI: [[COPY24:%[0-9]+]]:_(s16) = COPY [[LSHR23]](s16)
; FIJI: [[AND24:%[0-9]+]]:_(s16) = G_AND [[COPY24]], [[C1]]
; FIJI: [[SHL22:%[0-9]+]]:_(s16) = G_SHL [[AND24]], [[C8]](s16)
; FIJI: [[OR22:%[0-9]+]]:_(s16) = G_OR [[OR21]], [[SHL22]]
; FIJI: [[COPY25:%[0-9]+]]:_(s16) = COPY [[LSHR24]](s16)
; FIJI: [[AND25:%[0-9]+]]:_(s16) = G_AND [[COPY25]], [[C1]]
; FIJI: [[SHL23:%[0-9]+]]:_(s16) = G_SHL [[AND25]], [[C9]](s16)
; FIJI: [[OR23:%[0-9]+]]:_(s16) = G_OR [[OR22]], [[SHL23]]
; FIJI: [[COPY26:%[0-9]+]]:_(s16) = COPY [[LSHR25]](s16)
; FIJI: [[AND26:%[0-9]+]]:_(s16) = G_AND [[COPY26]], [[C1]]
; FIJI: [[SHL24:%[0-9]+]]:_(s16) = G_SHL [[AND26]], [[C10]](s16)
; FIJI: [[OR24:%[0-9]+]]:_(s16) = G_OR [[OR23]], [[SHL24]]
; FIJI: [[COPY27:%[0-9]+]]:_(s16) = COPY [[LSHR26]](s16)
; FIJI: [[AND27:%[0-9]+]]:_(s16) = G_AND [[COPY27]], [[C1]]
; FIJI: [[SHL25:%[0-9]+]]:_(s16) = G_SHL [[AND27]], [[C11]](s16)
; FIJI: [[OR25:%[0-9]+]]:_(s16) = G_OR [[OR24]], [[SHL25]]
; FIJI: [[COPY28:%[0-9]+]]:_(s16) = COPY [[LSHR27]](s16)
; FIJI: [[AND28:%[0-9]+]]:_(s16) = G_AND [[COPY28]], [[C1]]
; FIJI: [[SHL26:%[0-9]+]]:_(s16) = G_SHL [[AND28]], [[C12]](s16)
; FIJI: [[OR26:%[0-9]+]]:_(s16) = G_OR [[OR25]], [[SHL26]]
; FIJI: [[COPY29:%[0-9]+]]:_(s16) = COPY [[LSHR28]](s16)
; FIJI: [[AND29:%[0-9]+]]:_(s16) = G_AND [[COPY29]], [[C1]]
; FIJI: [[SHL27:%[0-9]+]]:_(s16) = G_SHL [[AND29]], [[C13]](s16)
; FIJI: [[OR27:%[0-9]+]]:_(s16) = G_OR [[OR26]], [[SHL27]]
; FIJI: [[COPY30:%[0-9]+]]:_(s16) = COPY [[LSHR29]](s16)
; FIJI: [[AND30:%[0-9]+]]:_(s16) = G_AND [[COPY30]], [[C1]]
; FIJI: [[SHL28:%[0-9]+]]:_(s16) = G_SHL [[AND30]], [[C14]](s16)
; FIJI: [[OR28:%[0-9]+]]:_(s16) = G_OR [[OR27]], [[SHL28]]
; FIJI: [[COPY31:%[0-9]+]]:_(s16) = COPY [[LSHR30]](s16)
; FIJI: [[AND31:%[0-9]+]]:_(s16) = G_AND [[COPY31]], [[C1]]
; FIJI: [[SHL29:%[0-9]+]]:_(s16) = G_SHL [[AND31]], [[C15]](s16)
; FIJI: [[OR29:%[0-9]+]]:_(s16) = G_OR [[OR28]], [[SHL29]]
; FIJI: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[OR14]](s16)
; FIJI: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR29]](s16)
; FIJI: [[SHL30:%[0-9]+]]:_(s32) = G_SHL [[ZEXT1]], [[C]](s32)
; FIJI: [[OR30:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SHL30]]
; FIJI: $vgpr0 = COPY [[OR30]](s32)
%0:_(s1025) = G_IMPLICIT_DEF %0:_(s1025) = G_IMPLICIT_DEF
%1:_(s32) = G_TRUNC %0 %1:_(s32) = G_TRUNC %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir

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--- ---
name: test_implicit_def_s1056 name: test_implicit_def_s1056
body: | body: |
bb.0: bb.0:
; CHECK-LABEL: name: test_implicit_def_s1056 ; CHECK-LABEL: name: test_implicit_def_s1056
; CHECK: [[DEF:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:_(s1024) = G_IMPLICIT_DEF
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s1024) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32), [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32), [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32), [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32), [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32), [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32), [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32), [[UV16:%[0-9]+]]:_(s32), [[UV17:%[0-9]+]]:_(s32), [[UV18:%[0-9]+]]:_(s32), [[UV19:%[0-9]+]]:_(s32), [[UV20:%[0-9]+]]:_(s32), [[UV21:%[0-9]+]]:_(s32), [[UV22:%[0-9]+]]:_(s32), [[UV23:%[0-9]+]]:_(s32), [[UV24:%[0-9]+]]:_(s32), [[UV25:%[0-9]+]]:_(s32), [[UV26:%[0-9]+]]:_(s32), [[UV27:%[0-9]+]]:_(s32), [[UV28:%[0-9]+]]:_(s32), [[UV29:%[0-9]+]]:_(s32), [[UV30:%[0-9]+]]:_(s32), [[UV31:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s1024)
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[UV1]](s32)
; CHECK: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV2]](s32), [[UV3]](s32)
; CHECK: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV4]](s32), [[UV5]](s32)
; CHECK: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV6]](s32), [[UV7]](s32)
; CHECK: [[MV4:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV8]](s32), [[UV9]](s32)
; CHECK: [[MV5:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV10]](s32), [[UV11]](s32)
; CHECK: [[MV6:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV12]](s32), [[UV13]](s32)
; CHECK: [[MV7:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV14]](s32), [[UV15]](s32)
; CHECK: [[MV8:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV16]](s32), [[UV17]](s32)
; CHECK: [[MV9:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV18]](s32), [[UV19]](s32)
; CHECK: [[MV10:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV20]](s32), [[UV21]](s32)
; CHECK: [[MV11:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV22]](s32), [[UV23]](s32)
; CHECK: [[MV12:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV24]](s32), [[UV25]](s32)
; CHECK: [[MV13:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV26]](s32), [[UV27]](s32)
; CHECK: [[MV14:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV28]](s32), [[UV29]](s32)
; CHECK: [[MV15:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV30]](s32), [[UV31]](s32)
; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF ; CHECK: [[DEF1:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
; CHECK: [[MV16:%[0-9]+]]:_(s2112) = G_MERGE_VALUES [[MV]](s64), [[MV1]](s64), [[MV2]](s64), [[MV3]](s64), [[MV4]](s64), [[MV5]](s64), [[MV6]](s64), [[MV7]](s64), [[MV8]](s64), [[MV9]](s64), [[MV10]](s64), [[MV11]](s64), [[MV12]](s64), [[MV13]](s64), [[MV14]](s64), [[MV15]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64), [[DEF1]](s64) ; CHECK: $vgpr0 = COPY [[UV]](s32)
; CHECK: [[TRUNC:%[0-9]+]]:_(s1056) = G_TRUNC [[MV16]](s2112)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s1056)
; CHECK: $vgpr0 = COPY [[TRUNC1]](s32)
%0:_(s1056) = G_IMPLICIT_DEF %0:_(s1056) = G_IMPLICIT_DEF
%1:_(s32) = G_TRUNC %0 %1:_(s32) = G_TRUNC %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: test_implicit_def_s2048 name: test_implicit_def_s2048
body: | body: |
▲ Show 20 Lines • Show All 483 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir

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--- ---
name: test_inttoptr_s33_to_p3 name: test_inttoptr_s33_to_p3
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: test_inttoptr_s33_to_p3 ; CHECK-LABEL: name: test_inttoptr_s33_to_p3
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[TRUNC:%[0-9]+]]:_(s33) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s33) ; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](s32)
; CHECK: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](s32)
; CHECK: S_ENDPGM 0, implicit [[INTTOPTR]](p3) ; CHECK: S_ENDPGM 0, implicit [[INTTOPTR]](p3)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0 %1:_(s33) = G_TRUNC %0
%2:_(p3) = G_INTTOPTR %1 %2:_(p3) = G_INTTOPTR %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir

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--- ---
name: test_trunc_s16_to_s1 name: test_trunc_s16_to_s1
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: test_trunc_s16_to_s1 ; CHECK-LABEL: name: test_trunc_s16_to_s1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) ; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[TRUNC]](s16) ; CHECK: S_ENDPGM 0, implicit [[TRUNC]](s1)
; CHECK: S_ENDPGM 0, implicit [[TRUNC1]](s1)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s1) = G_TRUNC %1 %2:_(s1) = G_TRUNC %1
S_ENDPGM 0, implicit %2 S_ENDPGM 0, implicit %2
... ...
--- ---
name: test_trunc_v4s32_to_v4s1 name: test_trunc_v4s32_to_v4s1
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