AMDGPU/GlobalISel: Implement computeNumSignBitsForTargetInstr

[foad]

Looks fine to me but I'm not very familiar with any of this code.

[arsenm]

2ad5fc1d9154807f7fe287139839099438fd54d4

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h

void computeKnownBitsForTargetNode(const SDValue Op,
                                      const APInt &DemandedElts,
                                      const SelectionDAG &DAG,
                                      unsigned Depth = 0) const override;
 
   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
                                            const SelectionDAG &DAG,
                                            unsigned Depth = 0) const override;
 
+  unsigned computeNumSignBitsForTargetInstr(GISelKnownBits &Analysis,
+                                            Register R,
+                                            const APInt &DemandedElts,
+                                            const MachineRegisterInfo &MRI,
+                                            unsigned Depth = 0) const override;
+
   bool isKnownNeverNaNForTargetNode(SDValue Op,
                                     const SelectionDAG &DAG,
                                     bool SNaN = false,
                                     unsigned Depth = 0) const override;
 
   /// Helper function that adds Reg to the LiveIn list of the DAG's
   /// MachineFunction.
   ///

llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
   case AMDGPUISD::FP_TO_FP16:
   case AMDGPUISD::FP16_ZEXT:
     return 16;
   default:
     return 1;
   }
 }
 
+unsigned AMDGPUTargetLowering::computeNumSignBitsForTargetInstr(
+  GISelKnownBits &Analysis, Register R,
+  const APInt &DemandedElts, const MachineRegisterInfo &MRI,
+  unsigned Depth) const {
+  const MachineInstr *MI = MRI.getVRegDef(R);
+  if (!MI)
+    return 1;
+
+  // TODO: Check range metadata on MMO.
+  switch (MI->getOpcode()) {
+  case AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE:
+    return 25;
+  case AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT:
+    return 17;
+  case AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE:
+    return 24;
+  case AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT:
+    return 16;
+  default:
+    return 1;
+  }
+}
+
 bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
                                                         const SelectionDAG &DAG,
                                                         bool SNaN,
                                                         unsigned Depth) const {
   unsigned Opcode = Op.getOpcode();
   switch (Opcode) {
   case AMDGPUISD::FMIN_LEGACY:
   case AMDGPUISD::FMAX_LEGACY: {

llvm/unittests/CodeGen/GlobalISel/GISelMITest.h

 };
 
 class AArch64GISelMITest : public GISelMITest {
   std::unique_ptr<LLVMTargetMachine> createTargetMachine() const override;
   void getTargetTestModuleString(SmallString<512> &S,
                                  StringRef MIRFunc) const override;
 };
 
+class AMDGPUGISelMITest : public GISelMITest {
+  std::unique_ptr<LLVMTargetMachine> createTargetMachine() const override;
+  void getTargetTestModuleString(SmallString<512> &S,
+                                 StringRef MIRFunc) const override;
+};
+
 #define DefineLegalizerInfo(Name, SettingUpActionsBlock)                       \
   class Name##Info : public LegalizerInfo {                                    \
   public:                                                                      \
     Name##Info(const TargetSubtargetInfo &ST) {                                \
       using namespace TargetOpcode;                                            \
       const LLT s8 = LLT::scalar(8);                                           \
       (void)s8;                                                                \
       const LLT s16 = LLT::scalar(16);                                         \

llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp

bb.1:
 
     %0(s64) = COPY $x0
     %1(s64) = COPY $x1
     %2(s64) = COPY $x2
 )MIR") +
    Twine(MIRFunc) + Twine("...\n"))
       .toNullTerminatedStringRef(S);
 }
+
+std::unique_ptr<LLVMTargetMachine>
+AMDGPUGISelMITest::createTargetMachine() const {
+  Triple TargetTriple("amdgcn-amd-amdhsa");
+  std::string Error;
+  const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error);
+  if (!T)
+    return nullptr;
+
+  TargetOptions Options;
+  return std::unique_ptr<LLVMTargetMachine>(
+      static_cast<LLVMTargetMachine *>(T->createTargetMachine(
+          "amdgcn-amd-amdhsa", "gfx900", "", Options, None, None,
+          CodeGenOpt::Aggressive)));
+}
+
+void AMDGPUGISelMITest::getTargetTestModuleString(
+  SmallString<512> &S, StringRef MIRFunc) const {
+  (Twine(R"MIR(
+---
+...
+name: func
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body: |
+  bb.1:
+    liveins: $vgpr0, $vgpr1, $vgpr2
+
+    %0(s32) = COPY $vgpr0
+    %1(s32) = COPY $vgpr1
+    %2(s32) = COPY $vgpr2
+)MIR") + Twine(MIRFunc) + Twine("...\n"))
+                            .toNullTerminatedStringRef(S);
+}

llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp

TEST_F(AArch64GISelMITest, TestNumSignBitsTrunc) {
   Register CopyTruncNeg1 = Copies[Copies.size() - 2];
   Register CopyTrunc7 = Copies[Copies.size() - 1];
 
   GISelKnownBits Info(*MF);
   EXPECT_EQ(1u, Info.computeNumSignBits(CopyTruncLoad));
   EXPECT_EQ(8u, Info.computeNumSignBits(CopyTruncNeg1));
   EXPECT_EQ(5u, Info.computeNumSignBits(CopyTrunc7));
 }
+
+TEST_F(AMDGPUGISelMITest, TestNumSignBitsTrunc) {
+  StringRef MIRString =
+    "  %3:_(<4 x s32>) = G_IMPLICIT_DEF\n"
+    "  %4:_(s32) = G_IMPLICIT_DEF\n"
+    "  %5:_(s32) = G_AMDGPU_BUFFER_LOAD_UBYTE %3, %4, %4, %4, 0, 0, 0 :: (load 1)\n"
+    "  %6:_(s32) = COPY %5\n"
+
+    "  %7:_(s32) = G_AMDGPU_BUFFER_LOAD_SBYTE %3, %4, %4, %4, 0, 0, 0 :: (load 1)\n"
+    "  %8:_(s32) = COPY %7\n"
+
+    "  %9:_(s32) = G_AMDGPU_BUFFER_LOAD_USHORT %3, %4, %4, %4, 0, 0, 0 :: (load 2)\n"
+    "  %10:_(s32) = COPY %9\n"
+
+    "  %11:_(s32) = G_AMDGPU_BUFFER_LOAD_SSHORT %3, %4, %4, %4, 0, 0, 0 :: (load 2)\n"
+    "  %12:_(s32) = COPY %11\n";
+
+  setUp(MIRString);
+  if (!TM)
+    return;
+
+  Register CopyLoadUByte = Copies[Copies.size() - 4];
+  Register CopyLoadSByte = Copies[Copies.size() - 3];
+  Register CopyLoadUShort = Copies[Copies.size() - 2];
+  Register CopyLoadSShort = Copies[Copies.size() - 1];
+
+  GISelKnownBits Info(*MF);
+
+  EXPECT_EQ(24u, Info.computeNumSignBits(CopyLoadUByte));
+  EXPECT_EQ(25u, Info.computeNumSignBits(CopyLoadSByte));
+  EXPECT_EQ(16u, Info.computeNumSignBits(CopyLoadUShort));
+  EXPECT_EQ(17u, Info.computeNumSignBits(CopyLoadSShort));
+}