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[AMDGPU] Enable divergence driven ISel for ADD/SUB i64
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Authored by alex-t on Mar 18 2020, 10:09 AM.

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Summary

Currently we custom select add/sub with carry out to scalar form relying on later replacing them to vector form if necessary.
This change enables custom selection code to take the divergence of adde/addc SDNodes into account and select the appropriate form in one step.

Diff Detail

Event Timeline

alex-t created this revision.Mar 18 2020, 10:09 AM
arsenm added inline comments.Mar 18 2020, 10:22 AM
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
1020

static const

alex-t updated this revision to Diff 251427.Mar 19 2020, 11:37 AM

static const

alex-t marked an inline comment as done.Mar 19 2020, 11:38 AM
arsenm accepted this revision.Mar 19 2020, 12:07 PM
This revision is now accepted and ready to land.Mar 19 2020, 12:07 PM
vpykhtin accepted this revision.Mar 20 2020, 1:02 AM

LGTM.

This revision was automatically updated to reflect the committed changes.
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