[PowerPC] add IR level isFMAFasterThanFMulAndFAdd - NFC

[shchenz]

Summary

NFC patch for add IR level target hook isFMAFasterThanFMulAndFAdd

[steven.zhang]

I don't think this is a NFC patch as you are adding hook for IR version.

[shchenz]

In D76265#1928209, @steven.zhang wrote:

I don't think this is a NFC patch as you are adding hook for IR version.

The IR hook does not have any caller like NFC patches only adding a helper function without any caller?

[steven.zhang]

In D76265#1928228, @shchenz wrote:

In D76265#1928209, @steven.zhang wrote:

I don't think this is a NFC patch as you are adding hook for IR version.

The IR hook does not have any caller like NFC patches only adding a helper function without any caller?

Well, that's really confusing to have hook without caller. And yes, it is NFC.

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15370–15371

Don't get the scalar type as the parameter of "Ty" in IR version is the type of the function.

15370–15371

You don't need this check any more as you don't call the getSimpleVT now.

[shchenz]

In D76265#1928272, @steven.zhang wrote:

In D76265#1928228, @shchenz wrote:

In D76265#1928209, @steven.zhang wrote:

I don't think this is a NFC patch as you are adding hook for IR version.

The IR hook does not have any caller like NFC patches only adding a helper function without any caller?

Well, that's really confusing to have hook without caller. And yes, it is NFC.

actually there is a user isProfitableToHoist in AArch64 target for same purpose as what I do for this patch.

[shchenz]

Thanks for your comments @steven.zhang . Updated accordingly.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15370–15371

Right.

15370–15371

I think You mean in IR version, I already call getScalarType() , so no need to call it again?

[steven.zhang]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15370–15371

My understanding is that, these two hooks have completely the same semantics basing on different data structure. We should pass through the type instead of strip the vector type. And it doesn't make sense as the decision is made inside IR version hook, we cannot make any assumption that it didn't care about the vector type.

[steven.zhang]

LGTM now.

llvm/lib/Target/PowerPC/PPCISelLowering.h

public:
 
     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
     /// expanded to FMAs when this method returns true, otherwise fmuladd is
     /// expanded to fmul + fadd.
     bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
                                     EVT VT) const override;
 
+    bool isFMAFasterThanFMulAndFAdd(const Function &F, Type *Ty) const override;
+
     const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
 
     // Should we expand the build vector with shuffles?
     bool
     shouldExpandBuildVectorWithShuffles(EVT VT,
                                         unsigned DefinedValues) const override;
 
     /// createFastISel - This method returns a target-specific FastISel object,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
 
   if (Fast)
     *Fast = true;
 
   return true;
 }
 
 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
                                                    EVT VT) const {
-  VT = VT.getScalarType();
-
-  if (!VT.isSimple())
-    return false;
+  return isFMAFasterThanFMulAndFAdd(
+      MF.getFunction(), VT.getTypeForEVT(MF.getFunction().getContext()));
+}
 
-  switch (VT.getSimpleVT().SimpleTy) {
-  case MVT::f32:
-  case MVT::f64:
+bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(const Function &F,
+                                                   Type *Ty) const {
+  switch (Ty->getScalarType()->getTypeID()) {
+  case Type::FloatTyID:
+  case Type::DoubleTyID:
     return true;
-  case MVT::f128:
-    return (EnableQuadPrecision && Subtarget.hasP9Vector());
+  case Type::FP128TyID:
+    return EnableQuadPrecision && Subtarget.hasP9Vector();
   default:
-    break;
-  }
-
     return false;
   }
+}
 
 const MCPhysReg *
 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
   // LR is a callee-save register, but we must treat it as clobbered by any call
   // site. Hence we include LR in the scratch registers, which are in turn added
   // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
   // to CTR, which is used by any indirect call.
   static const MCPhysReg ScratchRegs[] = {