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Differential D76135

[MachineLICM] Don't treat cross copies as cheap
Needs ReviewPublic

Authored by dmgreen on Mar 13 2020, 8:25 AM.

Details

Reviewers
efriedma
arsenm
qcolombet
RKSimon
Summary

This adjusts the cost of cross register bank copy instructions in MachineLICM, no longer treating them as expensive in order to allow them to be pulled out of inner loops. This can be especially important for MVE code where we sink VDUP's into blocks attempting to fold them into register variants of vector instructions. Where this scalar is a float value we are left with a COPY from SPR to GPR which then needs to be hoisted.

This is an alternative to D76024.
The isCrossCopy code was taken from DetectDeadLanes with some adjustment/cleanup. I don't feel like an expert on some of these areas like subreg copies.
I'm not 100% sure all these test diffs are better, but most of them look OK to me.

Diff Detail

Event Timeline

dmgreen created this revision.Mar 13 2020, 8:25 AM
Herald added subscribers: kerbowa, asbirlea, hiraditya and 3 others. · View Herald TranscriptMar 13 2020, 8:25 AM
dmgreen mentioned this in D76024: [MachineLICM] Let targets decide to hoist cheap instructions.Mar 13 2020, 8:26 AM
arsenm added inline comments.Mar 13 2020, 9:13 AM
llvm/lib/CodeGen/MachineLICM.cpp
1157–1187

This looks pretty much identical to TargetRegisterInfo::shouldRewriteCopySrc/shareSameRegisterFile

dmgreen updated this revision to Diff 250256.Mar 13 2020, 10:33 AM

Thanks for the suggestion.

I made it call shouldRewriteCopySrc, which allows the target to modify things if it wishes. The AMDGPU/idiv-licm.ll test changed ever so slightly. Let me know if I should change things around to instead call shareSameRegisterFile more directly.

arsenm added a comment.Mar 13 2020, 10:50 AM
In D76135#1921963, @dmgreen wrote:

Thanks for the suggestion.

I made it call shouldRewriteCopySrc, which allows the target to modify things if it wishes. The AMDGPU/idiv-licm.ll test changed ever so slightly. Let me know if I should change things around to instead call shareSameRegisterFile more directly.

If DetectDeadLanes also has the same code, then they should probably be merged and directly exposed

asbirlea removed a subscriber: asbirlea.Mar 13 2020, 2:34 PM
dmgreen updated this revision to Diff 250503.Mar 16 2020, 3:33 AM

Now using TargetRegisterInfo::shareSameRegisterFile.

dmgreen added a comment.Mar 23 2020, 6:57 AM

I have altered the way that MVE VDUP are lowered, and we end up with a VMOV now instead of using a COPY. That means I don't need this any more for MVE at least.

@arsenm, let me know whether you want me to continue with this for AMDGPU or not.

arsenm added inline comments.Mar 23 2020, 9:23 AM
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
533

There's no reason for this to be virtual?

llvm/test/CodeGen/AMDGPU/idiv-licm.ll
276

This probably is an improvement

dmgreen updated this revision to Diff 252263.Mar 24 2020, 4:29 AM

No longer a virtual method.

arsenm added inline comments.Mar 24 2020, 8:54 AM
llvm/lib/CodeGen/MachineLICM.cpp
1179–1181

I'd like to get somebody else's opinion on this too. Based on the isAsCheapAsAMove check, I'm not sure what the intended handling of copies is here. For AMDGPU for example, copies get more expensive with wider register classes, which isn't a property of the register bank

qcolombet added inline comments.May 4 2020, 10:40 AM
llvm/lib/CodeGen/MachineLICM.cpp
1173

I feel we should stick to shouldRewriteCopySrc to take into account the "cheapness" of the copy.

Herald added a project: Restricted Project. · View Herald TranscriptMay 4 2020, 10:40 AM
RKSimon resigned from this revision.Jun 18 2020, 2:08 AM

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
7 lines
lib/
CodeGen/
10 lines
21 lines
19 lines
test/
CodeGen/
AMDGPU/
172 lines
162 lines
5 lines
244 lines
180 lines
147 lines

Diff 252263

llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Show First 20 Lines • Show All 522 Lines • ▼ Show 20 Linespublic:
/// class A so that each register in it has a sub-register of the /// class A so that each register in it has a sub-register of the
/// specified sub-register index which is in the specified register class B. /// specified sub-register index which is in the specified register class B.
/// ///
/// TableGen will synthesize missing A sub-classes. /// TableGen will synthesize missing A sub-classes.
virtual const TargetRegisterClass * virtual const TargetRegisterClass *
getMatchingSuperRegClass(const TargetRegisterClass *A, getMatchingSuperRegClass(const TargetRegisterClass *A,
const TargetRegisterClass *B, unsigned Idx) const; const TargetRegisterClass *B, unsigned Idx) const;
/// Check if the registers defined by the pair (RegisterClass, SubReg)
/// share the same register file.
bool shareSameRegisterFile(const TargetRegisterClass *DefRC,
arsenmUnsubmitted
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There's no reason for this to be virtual?

arsenm: There's no reason for this to be virtual?
unsigned DefSubReg,
const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) const;
// For a copy-like instruction that defines a register of class DefRC with // For a copy-like instruction that defines a register of class DefRC with
// subreg index DefSubReg, reading from another source with class SrcRC and // subreg index DefSubReg, reading from another source with class SrcRC and
// subregister SrcSubReg return true if this is a preferable copy // subregister SrcSubReg return true if this is a preferable copy
// instruction or an earlier use should be used. // instruction or an earlier use should be used.
virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC, virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
unsigned DefSubReg, unsigned DefSubReg,
const TargetRegisterClass *SrcRC, const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) const; unsigned SrcSubReg) const;
▲ Show 20 Lines • Show All 641 Lines • Show Last 20 Lines

llvm/lib/CodeGen/DetectDeadLanes.cpp

Show First 20 Lines • Show All 173 Lines • ▼ Show 20 Lines case TargetOpcode::REG_SEQUENCE: {
break; break;
} }
case TargetOpcode::EXTRACT_SUBREG: { case TargetOpcode::EXTRACT_SUBREG: {
unsigned SubReg = MI.getOperand(2).getImm(); unsigned SubReg = MI.getOperand(2).getImm();
SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
} }
} }
unsigned PreA, PreB; // Unused. return !TRI.shareSameRegisterFile(DstRC, DstSubIdx, SrcRC, SrcSubIdx);
if (SrcSubIdx && DstSubIdx)
return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA,
PreB);
if (SrcSubIdx)
return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx);
if (DstSubIdx)
return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx);
return !TRI.getCommonSubClass(SrcRC, DstRC);
} }
void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO, void DetectDeadLanes::addUsedLanesOnOperand(const MachineOperand &MO,
LaneBitmask UsedLanes) { LaneBitmask UsedLanes) {
if (!MO.readsReg()) if (!MO.readsReg())
return; return;
Register MOReg = MO.getReg(); Register MOReg = MO.getReg();
if (!Register::isVirtualRegister(MOReg)) if (!Register::isVirtualRegister(MOReg))
▲ Show 20 Lines • Show All 400 Lines • Show Last 20 Lines

llvm/lib/CodeGen/MachineLICM.cpp

Show First 20 Lines • Show All 1,148 Lines • ▼ Show 20 Lines for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
// Only look at the first in loop use. // Only look at the first in loop use.
break; break;
} }
return false; return false;
} }
static bool isCrossCopy(const MachineInstr &MI) {
if (!MI.isCopy())
return false;
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
Register DstReg = MI.getOperand(0).getReg();
unsigned DstSubIdx = MI.getOperand(0).getSubReg();
Register SrcReg = MI.getOperand(1).getReg();
unsigned SrcSubIdx = MI.getOperand(1).getSubReg();
if (!SrcReg.isVirtual() || !DstReg.isVirtual())
return false;
const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
return !TRI.shareSameRegisterFile(DstRC, DstSubIdx, SrcRC, SrcSubIdx);
qcolombetUnsubmitted
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I feel we should stick to shouldRewriteCopySrc to take into account the "cheapness" of the copy.

qcolombet: I feel we should stick to shouldRewriteCopySrc to take into account the "cheapness" of the copy.
}
/// Return true if the instruction is marked "cheap" or the operand latency /// Return true if the instruction is marked "cheap" or the operand latency
/// between its def and a use is one or less. /// between its def and a use is one or less.
bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const { bool MachineLICMBase::IsCheapInstruction(MachineInstr &MI) const {
if (isCrossCopy(MI))
return false;
if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike()) if (TII->isAsCheapAsAMove(MI) || MI.isCopyLike())
arsenmUnsubmitted
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I'd like to get somebody else's opinion on this too. Based on the isAsCheapAsAMove check, I'm not sure what the intended handling of copies is here. For AMDGPU for example, copies get more expensive with wider register classes, which isn't a property of the register bank

arsenm: I'd like to get somebody else's opinion on this too. Based on the isAsCheapAsAMove check, I'm…
return true; return true;
bool isCheap = false; bool isCheap = false;
unsigned NumDefs = MI.getDesc().getNumDefs(); unsigned NumDefs = MI.getDesc().getNumDefs();
for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) { for (unsigned i = 0, e = MI.getNumOperands(); NumDefs && i != e; ++i) {
MachineOperand &DefMO = MI.getOperand(i); MachineOperand &DefMO = MI.getOperand(i);
arsenmUnsubmitted
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This looks pretty much identical to TargetRegisterInfo::shouldRewriteCopySrc/shareSameRegisterFile

arsenm: This looks pretty much identical to TargetRegisterInfo…
if (!DefMO.isReg() || !DefMO.isDef()) if (!DefMO.isReg() || !DefMO.isDef())
continue; continue;
--NumDefs; --NumDefs;
Register Reg = DefMO.getReg(); Register Reg = DefMO.getReg();
if (Register::isPhysicalRegister(Reg)) if (Register::isPhysicalRegister(Reg))
continue; continue;
if (!TII->hasLowDefLatency(SchedModel, MI, i)) if (!TII->hasLowDefLatency(SchedModel, MI, i))
▲ Show 20 Lines • Show All 422 Lines • Show Last 20 Lines

llvm/lib/CodeGen/TargetRegisterInfo.cpp

Show First 20 Lines • Show All 353 Lines • ▼ Show 20 Lines for (SuperRegClassIterator IB(RCB, this, true); IB.isValid(); ++IB) {
return BestRC; return BestRC;
} }
} }
return BestRC; return BestRC;
} }
/// Check if the registers defined by the pair (RegisterClass, SubReg) /// Check if the registers defined by the pair (RegisterClass, SubReg)
/// share the same register file. /// share the same register file.
static bool shareSameRegisterFile(const TargetRegisterInfo &TRI, bool TargetRegisterInfo::shareSameRegisterFile(const TargetRegisterClass *DefRC,
const TargetRegisterClass *DefRC,
unsigned DefSubReg, unsigned DefSubReg,
const TargetRegisterClass *SrcRC, const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) { unsigned SrcSubReg) const {
// Same register class. // Same register class.
if (DefRC == SrcRC) if (DefRC == SrcRC)
return true; return true;
// Both operands are sub registers. Check if they share a register class. // Both operands are sub registers. Check if they share a register class.
unsigned SrcIdx, DefIdx; unsigned SrcIdx, DefIdx;
if (SrcSubReg && DefSubReg) { if (SrcSubReg && DefSubReg) {
return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, return getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, SrcIdx,
SrcIdx, DefIdx) != nullptr; DefIdx) != nullptr;
} }
// At most one of the register is a sub register, make it Src to avoid // At most one of the register is a sub register, make it Src to avoid
// duplicating the test. // duplicating the test.
if (!SrcSubReg) { if (!SrcSubReg) {
std::swap(DefSubReg, SrcSubReg); std::swap(DefSubReg, SrcSubReg);
std::swap(DefRC, SrcRC); std::swap(DefRC, SrcRC);
} }
// One of the register is a sub register, check if we can get a superclass. // One of the register is a sub register, check if we can get a superclass.
if (SrcSubReg) if (SrcSubReg)
return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; return getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
// Plain copy. // Plain copy.
return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; return getCommonSubClass(DefRC, SrcRC) != nullptr;
} }
bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
unsigned DefSubReg, unsigned DefSubReg,
const TargetRegisterClass *SrcRC, const TargetRegisterClass *SrcRC,
unsigned SrcSubReg) const { unsigned SrcSubReg) const {
// If this source does not incur a cross register bank copy, use it. // If this source does not incur a cross register bank copy, use it.
return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); return shareSameRegisterFile(DefRC, DefSubReg, SrcRC, SrcSubReg);
} }
// Compute target-independent register allocator hints to help eliminate copies. // Compute target-independent register allocator hints to help eliminate copies.
bool bool
TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg, TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
ArrayRef<MCPhysReg> Order, ArrayRef<MCPhysReg> Order,
SmallVectorImpl<MCPhysReg> &Hints, SmallVectorImpl<MCPhysReg> &Hints,
const MachineFunction &MF, const MachineFunction &MF,
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

Show First 20 Lines • Show All 259 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @udiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) { define amdgpu_kernel void @udiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
; GFX9-LABEL: udiv16_invariant_denom: ; GFX9-LABEL: udiv16_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s3, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s3, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s2, 0xffff ; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s3, s2, s3 ; GFX9-NEXT: s_and_b32 s3, s2, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: s_movk_i32 s3, 0x400 ; GFX9-NEXT: s_movk_i32 s3, 0x400
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: BB4_1: ; %bb3 ; GFX9-NEXT: BB4_1: ; %bb3
arsenmUnsubmitted
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This probably is an improvement

arsenm: This probably is an improvement
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_and_b32_e32 v2, s2, v4 ; GFX9-NEXT: v_and_b32_e32 v1, s2, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v1
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[1:2]
; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: v_add_u16_e32 v5, 1, v5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], s4, v6
; GFX9-NEXT: v_mul_f32_e32 v2, v8, v1 ; GFX9-NEXT: v_mul_f32_e32 v1, v8, v3
; GFX9-NEXT: v_trunc_f32_e32 v2, v2 ; GFX9-NEXT: v_trunc_f32_e32 v1, v1
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] ; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v1
; GFX9-NEXT: v_cvt_u32_f32_e32 v7, v2 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v4, v7, s[0:1]
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_mad_f32 v1, -v1, v0, v8
; GFX9-NEXT: v_mad_f32 v2, -v2, v0, v8 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, v0
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v2|, v0 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v5
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v4 ; GFX9-NEXT: v_addc_co_u32_e64 v1, s[0:1], 0, v9, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e64 v2, s[0:1], 0, v7, s[0:1]
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[6:7], v1, off
; GFX9-NEXT: s_cbranch_vccz BB4_1 ; GFX9-NEXT: s_cbranch_vccz BB4_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 10 Lines
} }
define amdgpu_kernel void @urem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) { define amdgpu_kernel void @urem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
; GFX9-LABEL: urem16_invariant_denom: ; GFX9-LABEL: urem16_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s3, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s3, s[0:1], 0x2c
; GFX9-NEXT: s_mov_b32 s2, 0xffff ; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_movk_i32 s6, 0x400 ; GFX9-NEXT: s_movk_i32 s6, 0x400
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_and_b32 s3, s2, s3 ; GFX9-NEXT: s_and_b32 s3, s2, s3
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3 ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v4, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: BB5_1: ; %bb3 ; GFX9-NEXT: BB5_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_and_b32_e32 v2, s2, v4 ; GFX9-NEXT: v_and_b32_e32 v1, s2, v5
; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v2 ; GFX9-NEXT: v_cvt_f32_u32_e32 v8, v1
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[1:2]
; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: v_add_u16_e32 v5, 1, v5
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], s4, v6
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] ; GFX9-NEXT: v_mul_f32_e32 v9, v8, v3
; GFX9-NEXT: v_mul_f32_e32 v7, v8, v1 ; GFX9-NEXT: v_trunc_f32_e32 v9, v9
; GFX9-NEXT: v_trunc_f32_e32 v7, v7 ; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v9
; GFX9-NEXT: v_cvt_u32_f32_e32 v9, v7 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v4, v7, s[0:1]
; GFX9-NEXT: v_mad_f32 v7, -v7, v0, v8 ; GFX9-NEXT: v_mad_f32 v8, -v9, v0, v8
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v7|, v0 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, v0
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_addc_co_u32_e64 v8, s[0:1], 0, v10, s[0:1]
; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], 0, v9, s[0:1] ; GFX9-NEXT: v_mul_lo_u32 v8, v8, s3
; GFX9-NEXT: v_mul_lo_u32 v7, v7, s3 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s6, v5
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s6, v4
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_sub_u32_e32 v2, v2, v7 ; GFX9-NEXT: v_sub_u32_e32 v1, v1, v8
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[6:7], v1, off
; GFX9-NEXT: s_cbranch_vccz BB5_1 ; GFX9-NEXT: s_cbranch_vccz BB5_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 9 Linesbb3: ; preds = %bb3, %bb
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @sdiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) { define amdgpu_kernel void @sdiv16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
; GFX9-LABEL: sdiv16_invariant_denom: ; GFX9-LABEL: sdiv16_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_movk_i32 s3, 0x400 ; GFX9-NEXT: s_movk_i32 s3, 0x400
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s2, s2 ; GFX9-NEXT: s_sext_i32_i16 s2, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: BB6_1: ; %bb3 ; GFX9-NEXT: BB6_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_bfe_i32 v5, v4, 0, 16 ; GFX9-NEXT: v_bfe_i32 v6, v5, 0, 16
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v4 ; GFX9-NEXT: v_cvt_f32_i32_e32 v9, v6
; GFX9-NEXT: v_cvt_f32_i32_e32 v9, v5 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v5
; GFX9-NEXT: v_xor_b32_e32 v8, s2, v5 ; GFX9-NEXT: v_xor_b32_e32 v8, s2, v6
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[1:2]
; GFX9-NEXT: v_mov_b32_e32 v7, s5 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 30, v8
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5 ; GFX9-NEXT: v_mul_f32_e32 v8, v9, v3
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v7, v6, s[0:1] ; GFX9-NEXT: v_trunc_f32_e32 v8, v8
; GFX9-NEXT: v_mul_f32_e32 v7, v9, v1 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], s4, v6
; GFX9-NEXT: v_trunc_f32_e32 v7, v7 ; GFX9-NEXT: v_cvt_i32_f32_e32 v10, v8
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v8 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v4, v7, s[0:1]
; GFX9-NEXT: v_cvt_i32_f32_e32 v8, v7 ; GFX9-NEXT: v_mad_f32 v8, -v8, v0, v9
; GFX9-NEXT: v_mad_f32 v7, -v7, v0, v9 ; GFX9-NEXT: v_add_u16_e32 v5, 1, v5
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_or_b32_e32 v1, 1, v1
; GFX9-NEXT: v_or_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, |v0|
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v7|, |v0| ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v5
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v4 ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] ; GFX9-NEXT: v_add_u32_e32 v1, v10, v1
; GFX9-NEXT: v_add_u32_e32 v2, v8, v2
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[6:7], v1, off
; GFX9-NEXT: s_cbranch_vccz BB6_1 ; GFX9-NEXT: s_cbranch_vccz BB6_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 9 Linesbb3: ; preds = %bb3, %bb
br i1 %tmp8, label %bb2, label %bb3 br i1 %tmp8, label %bb2, label %bb3
} }
define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) { define amdgpu_kernel void @srem16_invariant_denom(i16 addrspace(1)* nocapture %arg, i16 %arg1) {
; GFX9-LABEL: srem16_invariant_denom: ; GFX9-LABEL: srem16_invariant_denom:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_movk_i32 s3, 0x400 ; GFX9-NEXT: s_movk_i32 s3, 0x400
; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: v_mov_b32_e32 v5, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_sext_i32_i16 s2, s2 ; GFX9-NEXT: s_sext_i32_i16 s2, s2
; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2 ; GFX9-NEXT: v_cvt_f32_i32_e32 v0, s2
; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v4, s5
; GFX9-NEXT: v_rcp_iflag_f32_e32 v3, v0
; GFX9-NEXT: BB7_1: ; %bb3 ; GFX9-NEXT: BB7_1: ; %bb3
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_bfe_i32 v7, v4, 0, 16 ; GFX9-NEXT: v_bfe_i32 v8, v5, 0, 16
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v4 ; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v8
; GFX9-NEXT: v_cvt_f32_i32_e32 v10, v7 ; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v5
; GFX9-NEXT: v_lshlrev_b64 v[5:6], 1, v[2:3] ; GFX9-NEXT: v_xor_b32_e32 v9, s2, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s5 ; GFX9-NEXT: v_lshlrev_b64 v[6:7], 1, v[1:2]
; GFX9-NEXT: v_add_co_u32_e64 v5, s[0:1], s4, v5 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 30, v9
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[0:1], v8, v6, s[0:1] ; GFX9-NEXT: v_mul_f32_e32 v9, v10, v3
; GFX9-NEXT: v_mul_f32_e32 v8, v10, v1 ; GFX9-NEXT: v_trunc_f32_e32 v9, v9
; GFX9-NEXT: v_xor_b32_e32 v9, s2, v7 ; GFX9-NEXT: v_add_co_u32_e64 v6, s[0:1], s4, v6
; GFX9-NEXT: v_trunc_f32_e32 v8, v8 ; GFX9-NEXT: v_cvt_i32_f32_e32 v11, v9
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 30, v9 ; GFX9-NEXT: v_addc_co_u32_e64 v7, s[0:1], v4, v7, s[0:1]
; GFX9-NEXT: v_cvt_i32_f32_e32 v9, v8 ; GFX9-NEXT: v_mad_f32 v9, -v9, v0, v10
; GFX9-NEXT: v_mad_f32 v8, -v8, v0, v10 ; GFX9-NEXT: v_or_b32_e32 v1, 1, v1
; GFX9-NEXT: v_or_b32_e32 v2, 1, v2 ; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v9|, |v0|
; GFX9-NEXT: v_cmp_ge_f32_e64 s[0:1], |v8|, |v0| ; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, v1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, v2, s[0:1] ; GFX9-NEXT: v_add_u32_e32 v1, v11, v1
; GFX9-NEXT: v_add_u32_e32 v2, v9, v2 ; GFX9-NEXT: v_mul_lo_u32 v1, v1, s2
; GFX9-NEXT: v_mul_lo_u32 v2, v2, s2 ; GFX9-NEXT: v_add_u16_e32 v5, 1, v5
; GFX9-NEXT: v_add_u16_e32 v4, 1, v4 ; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v5
; GFX9-NEXT: v_cmp_eq_u16_e32 vcc, s3, v4
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: v_sub_u32_e32 v2, v7, v2 ; GFX9-NEXT: v_sub_u32_e32 v1, v8, v1
; GFX9-NEXT: global_store_short v[5:6], v2, off ; GFX9-NEXT: global_store_short v[6:7], v1, off
; GFX9-NEXT: s_cbranch_vccz BB7_1 ; GFX9-NEXT: s_cbranch_vccz BB7_1
; GFX9-NEXT: ; %bb.2: ; %bb2 ; GFX9-NEXT: ; %bb.2: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
bb: bb:
br label %bb3 br label %bb3
bb2: ; preds = %bb3 bb2: ; preds = %bb3
ret void ret void
Show All 11 Lines

llvm/test/CodeGen/AMDGPU/sdiv64.ll

Show First 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch BB0_6
; GCN-IR-NEXT: BB0_4: ; %udiv-preheader ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[10:11], v4
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[10:11], v4
; GCN-IR-NEXT: s_add_u32 s10, s6, -1 ; GCN-IR-NEXT: s_add_u32 s10, s6, -1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: s_addc_u32 s11, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s11, s7, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s11
; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s10, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s6, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s7, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5
; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB0_7: ; %udiv-end ; GCN-IR-NEXT: BB0_7: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[8:9], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[8:9], s[2:3]
; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0
▲ Show 20 Lines • Show All 822 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[10:11], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: s_cbranch_vccz BB9_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB9_6 ; GCN-IR-NEXT: s_branch BB9_6
; GCN-IR-NEXT: BB9_4: ; %udiv-preheader ; GCN-IR-NEXT: BB9_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[10:11], v4
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[10:11], v4
; GCN-IR-NEXT: s_add_u32 s10, s8, -1 ; GCN-IR-NEXT: s_add_u32 s10, s8, -1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: s_addc_u32 s11, s9, -1 ; GCN-IR-NEXT: s_addc_u32 s11, s9, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s11
; GCN-IR-NEXT: BB9_5: ; %udiv-do-while ; GCN-IR-NEXT: BB9_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s10, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s8, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s9, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: s_cbranch_vccz BB9_5
; GCN-IR-NEXT: BB9_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB9_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB9_7: ; %udiv-end ; GCN-IR-NEXT: BB9_7: ; %udiv-end
; GCN-IR-NEXT: s_xor_b64 s[0:1], s[6:7], s[2:3] ; GCN-IR-NEXT: s_xor_b64 s[0:1], s[6:7], s[2:3]
; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s0, v0
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB10_4 ; GCN-IR-NEXT: s_cbranch_vccz BB10_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB10_6 ; GCN-IR-NEXT: s_branch BB10_6
; GCN-IR-NEXT: BB10_4: ; %udiv-preheader ; GCN-IR-NEXT: BB10_4: ; %udiv-preheader
; GCN-IR-NEXT: s_add_u32 s7, s8, -1 ; GCN-IR-NEXT: s_add_u32 s7, s8, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], 24, v3
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s10, s9, -1 ; GCN-IR-NEXT: s_addc_u32 s10, s9, -1
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_subb_u32_e64 v6, s[0:1], 0, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s10
; GCN-IR-NEXT: BB10_5: ; %udiv-do-while ; GCN-IR-NEXT: BB10_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v3
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v7
; GCN-IR-NEXT: v_mov_b32_e32 v2, s10 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s7, v6 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v11, s8, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s9, v9
; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB10_5 ; GCN-IR-NEXT: s_cbranch_vccz BB10_5
; GCN-IR-NEXT: BB10_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB10_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB10_7: ; %udiv-end ; GCN-IR-NEXT: BB10_7: ; %udiv-end
; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0 ; GCN-IR-NEXT: v_xor_b32_e32 v0, s2, v0
; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1 ; GCN-IR-NEXT: v_xor_b32_e32 v1, s3, v1
▲ Show 20 Lines • Show All 488 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB13_5 ; GCN-IR-NEXT: s_cbranch_execz BB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9 ; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[7:8], v9
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0 ; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 0xffffffcf, v0
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v8, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_mov_b32_e32 v0, 31
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB13_3: ; %udiv-do-while ; GCN-IR-NEXT: BB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1 ; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 31, v4 ; GCN-IR-NEXT: v_lshr_b32_e32 v5, v4, v0
; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0 ; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v5
; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1 ; GCN-IR-NEXT: v_lshl_b64 v[3:4], v[3:4], 1
; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, s12, v9
; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, 0, v10, vcc
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
; GCN-IR-NEXT: v_ashr_i32_e32 v11, v5, v0
; GCN-IR-NEXT: v_and_b32_e32 v13, 0x8000, v11
; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v11
; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v7 ; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v7
; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v5
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4
; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[7:8]
; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v9, 0x8000, v9
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v12
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v6
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0
; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v0, v9 ; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v9, v13
; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v10, v13, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v10, v14, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz BB13_3 ; GCN-IR-NEXT: s_cbranch_execnz BB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: BB13_5: ; %Flow3 ; GCN-IR-NEXT: BB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
▲ Show 20 Lines • Show All 255 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll

Show First 20 Lines • Show All 534 Lines • ▼ Show 20 Linesentry:
store <8 x i8> %tmp19, <8 x i8> addrspace(1)* %arrayidx5, align 8 store <8 x i8> %tmp19, <8 x i8> addrspace(1)* %arrayidx5, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}sdwa_crash_inlineasm_def: ; GCN-LABEL: {{^}}sdwa_crash_inlineasm_def:
; GCN: s_mov_b32 s{{[0-9]+}}, 0xffff ; GCN: s_mov_b32 s{{[0-9]+}}, 0xffff
; GCN: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_and_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
; ;
; TODO: Why is the constant not peepholed into the v_or_b32_e32? ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, 0x10000,
;
; NOSDWA: s_mov_b32 [[CONST:s[0-9]+]], 0x10000
; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, s0,
; SDWA: v_or_b32_e32 v{{[0-9]+}}, 0x10000, ; SDWA: v_or_b32_e32 v{{[0-9]+}}, 0x10000,
define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 { define amdgpu_kernel void @sdwa_crash_inlineasm_def() #0 {
bb: bb:
br label %bb1 br label %bb1
bb1: ; preds = %bb11, %bb bb1: ; preds = %bb11, %bb
%tmp = phi <2 x i32> [ %tmp12, %bb11 ], [ undef, %bb ] %tmp = phi <2 x i32> [ %tmp12, %bb11 ], [ undef, %bb ]
br i1 true, label %bb2, label %bb11 br i1 true, label %bb2, label %bb11
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/srem64.ll

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch BB0_6
; GCN-IR-NEXT: BB0_4: ; %udiv-preheader ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: s_add_u32 s8, s2, -1 ; GCN-IR-NEXT: s_add_u32 s8, s2, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s9, s3, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[6:7], v4
; GCN-IR-NEXT: s_addc_u32 s9, s3, -1
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s9
; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s8, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s9 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s8, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s2, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s3, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5
; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB0_7: ; %udiv-end ; GCN-IR-NEXT: BB0_7: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
▲ Show 20 Lines • Show All 857 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[8:9], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[8:9], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB8_4 ; GCN-IR-NEXT: s_cbranch_vccz BB8_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB8_6 ; GCN-IR-NEXT: s_branch BB8_6
; GCN-IR-NEXT: BB8_4: ; %udiv-preheader ; GCN-IR-NEXT: BB8_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: s_add_u32 s6, s10, -1 ; GCN-IR-NEXT: s_add_u32 s6, s10, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[8:9], v4 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s7, s11, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[8:9], v4
; GCN-IR-NEXT: s_addc_u32 s7, s11, -1
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s7
; GCN-IR-NEXT: BB8_5: ; %udiv-do-while ; GCN-IR-NEXT: BB8_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s10, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s10, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s11, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s11, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB8_5 ; GCN-IR-NEXT: s_cbranch_vccz BB8_5
; GCN-IR-NEXT: BB8_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB8_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB8_7: ; %udiv-end ; GCN-IR-NEXT: BB8_7: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s10, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s10, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s10, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s10, v0
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB9_4 ; GCN-IR-NEXT: s_cbranch_vccz BB9_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB9_6 ; GCN-IR-NEXT: s_branch BB9_6
; GCN-IR-NEXT: BB9_4: ; %udiv-preheader ; GCN-IR-NEXT: BB9_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: s_add_u32 s10, s8, -1 ; GCN-IR-NEXT: s_add_u32 s10, s8, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s11, s9, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[6:7], v4
; GCN-IR-NEXT: s_addc_u32 s11, s9, -1
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s11
; GCN-IR-NEXT: BB9_5: ; %udiv-do-while ; GCN-IR-NEXT: BB9_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s10, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s11 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s10, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s8, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s8, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s9, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s9, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB9_5 ; GCN-IR-NEXT: s_cbranch_vccz BB9_5
; GCN-IR-NEXT: BB9_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB9_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB9_7: ; %udiv-end ; GCN-IR-NEXT: BB9_7: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s8, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s8, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s8, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s8, v0
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB10_4 ; GCN-IR-NEXT: s_cbranch_vccz BB10_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB10_6 ; GCN-IR-NEXT: s_branch BB10_6
; GCN-IR-NEXT: BB10_4: ; %udiv-preheader ; GCN-IR-NEXT: BB10_4: ; %udiv-preheader
; GCN-IR-NEXT: s_add_u32 s7, s2, -1 ; GCN-IR-NEXT: s_add_u32 s7, s2, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], 24, v3
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s8, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s8, s3, -1
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_subb_u32_e64 v6, s[0:1], 0, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s8
; GCN-IR-NEXT: BB10_5: ; %udiv-do-while ; GCN-IR-NEXT: BB10_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v3
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s7, v7
; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s7, v6 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v11, s2, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s3, v9
; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB10_5 ; GCN-IR-NEXT: s_cbranch_vccz BB10_5
; GCN-IR-NEXT: BB10_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB10_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB10_7: ; %udiv-end ; GCN-IR-NEXT: BB10_7: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
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; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB13_5 ; GCN-IR-NEXT: s_cbranch_execz BB13_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_mov_b32_e32 v12, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v13, 0
; GCN-IR-NEXT: v_lshr_b64 v[10:11], v[0:1], v9 ; GCN-IR-NEXT: v_lshr_b64 v[11:12], v[0:1], v9
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 0xffffffcf, v8
; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v9, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0
; GCN-IR-NEXT: v_mov_b32_e32 v10, 31
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB13_3: ; %udiv-do-while ; GCN-IR-NEXT: BB13_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[10:11], 1 ; GCN-IR-NEXT: v_lshl_b64 v[11:12], v[11:12], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 ; GCN-IR-NEXT: v_lshr_b32_e32 v6, v5, v10
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 ; GCN-IR-NEXT: v_or_b32_e32 v11, v11, v6
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v10 ; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, s12, v11
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v11, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, 0, v12, vcc
; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 ; GCN-IR-NEXT: v_or_b32_e32 v4, v13, v4
; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 ; GCN-IR-NEXT: v_ashr_i32_e32 v13, v6, v10
; GCN-IR-NEXT: v_and_b32_e32 v14, 0x8000, v12 ; GCN-IR-NEXT: v_and_b32_e32 v15, 0x8000, v13
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 ; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v13
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v13, vcc, 1, v8
; GCN-IR-NEXT: v_or_b32_e32 v5, v13, v5 ; GCN-IR-NEXT: v_or_b32_e32 v5, v14, v5
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v14, vcc, 0, v9, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[12:13], v[8:9] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[13:14], v[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v8, v12 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v13
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
; GCN-IR-NEXT: v_mov_b32_e32 v9, v13 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v14
; GCN-IR-NEXT: v_mov_b32_e32 v13, v7 ; GCN-IR-NEXT: v_mov_b32_e32 v14, v7
; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v16, 0
; GCN-IR-NEXT: v_sub_i32_e64 v10, s[4:5], v10, v14 ; GCN-IR-NEXT: v_sub_i32_e64 v11, s[4:5], v11, v15
; GCN-IR-NEXT: v_subb_u32_e64 v11, s[4:5], v11, v15, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v12, s[4:5], v12, v16, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v12, v6 ; GCN-IR-NEXT: v_mov_b32_e32 v13, v6
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz BB13_3 ; GCN-IR-NEXT: s_cbranch_execnz BB13_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: BB13_5: ; %Flow3 ; GCN-IR-NEXT: BB13_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 ; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v5
▲ Show 20 Lines • Show All 274 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/udiv64.ll

Show First 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch BB0_6
; GCN-IR-NEXT: BB0_4: ; %udiv-preheader ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[6:7], v4
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4
; GCN-IR-NEXT: s_add_u32 s6, s2, -1 ; GCN-IR-NEXT: s_add_u32 s6, s2, -1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: s_addc_u32 s7, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s7, s3, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s7
; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s2, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s3, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5
; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB0_7: ; %udiv-end ; GCN-IR-NEXT: BB0_7: ; %udiv-end
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
▲ Show 20 Lines • Show All 661 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB7_4 ; GCN-IR-NEXT: s_cbranch_vccz BB7_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB7_6 ; GCN-IR-NEXT: s_branch BB7_6
; GCN-IR-NEXT: BB7_4: ; %udiv-preheader ; GCN-IR-NEXT: BB7_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[6:7], v4
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4
; GCN-IR-NEXT: s_add_u32 s6, s2, -1 ; GCN-IR-NEXT: s_add_u32 s6, s2, -1
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: s_addc_u32 s7, s3, -1 ; GCN-IR-NEXT: s_addc_u32 s7, s3, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s7
; GCN-IR-NEXT: BB7_5: ; %udiv-do-while ; GCN-IR-NEXT: BB7_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s2, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s3, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB7_5 ; GCN-IR-NEXT: s_cbranch_vccz BB7_5
; GCN-IR-NEXT: BB7_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB7_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB7_7: ; %udiv-end ; GCN-IR-NEXT: BB7_7: ; %udiv-end
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_mov_b32 s6, -1
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB8_4 ; GCN-IR-NEXT: s_cbranch_vccz BB8_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB8_6 ; GCN-IR-NEXT: s_branch BB8_6
; GCN-IR-NEXT: BB8_4: ; %udiv-preheader ; GCN-IR-NEXT: BB8_4: ; %udiv-preheader
; GCN-IR-NEXT: s_add_u32 s3, s6, -1 ; GCN-IR-NEXT: s_add_u32 s3, s6, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], 24, v3
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s8, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s8, s7, -1
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_subb_u32_e64 v6, s[0:1], 0, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s8
; GCN-IR-NEXT: BB8_5: ; %udiv-do-while ; GCN-IR-NEXT: BB8_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v3
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s3, v7
; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s3, v6 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v11, s6, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s7, v9
; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB8_5 ; GCN-IR-NEXT: s_cbranch_vccz BB8_5
; GCN-IR-NEXT: BB8_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB8_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB8_7: ; %udiv-end ; GCN-IR-NEXT: BB8_7: ; %udiv-end
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
; GCN-IR-NEXT: s_mov_b32 s6, s2 ; GCN-IR-NEXT: s_mov_b32 s6, s2
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; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB10_5 ; GCN-IR-NEXT: s_cbranch_execz BB10_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 31
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB10_3: ; %udiv-do-while ; GCN-IR-NEXT: BB10_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshr_b32_e32 v4, v3, v6
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v7
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
; GCN-IR-NEXT: v_ashr_i32_e32 v9, v4, v6
; GCN-IR-NEXT: v_and_b32_e32 v11, 0x8000, v9
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v9
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7
; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v9
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v8, v11, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v8, v12, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz BB10_3 ; GCN-IR-NEXT: s_cbranch_execnz BB10_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: BB10_5: ; %Flow3 ; GCN-IR-NEXT: BB10_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: BB11_5: ; %udiv-do-while ; GCN-IR-NEXT: BB11_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v3
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
; GCN-IR-NEXT: v_and_b32_e32 v10, 24, v8 ; GCN-IR-NEXT: v_and_b32_e32 v10, 24, v8
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[0:1], 0, v7, s[0:1] ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v3, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
; GCN-IR-NEXT: s_cbranch_vccz BB11_5 ; GCN-IR-NEXT: s_cbranch_vccz BB11_5
; GCN-IR-NEXT: BB11_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB11_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB11_7: ; %udiv-end ; GCN-IR-NEXT: BB11_7: ; %udiv-end
▲ Show 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB12_5 ; GCN-IR-NEXT: s_cbranch_execz BB12_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6 ; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v6, 31
; GCN-IR-NEXT: BB12_3: ; %udiv-do-while ; GCN-IR-NEXT: BB12_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshr_b32_e32 v4, v3, v6
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 ; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v7
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
; GCN-IR-NEXT: v_ashr_i32_e32 v9, v4, v6
; GCN-IR-NEXT: v_and_b32_e32 v11, 24, v9
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v9
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7
; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v0, v9
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v7, v11
; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v1, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] ; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz BB12_3 ; GCN-IR-NEXT: s_cbranch_execnz BB12_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
▲ Show 20 Lines • Show All 218 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/urem64.ll

Show First 20 Lines • Show All 167 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB0_4 ; GCN-IR-NEXT: s_cbranch_vccz BB0_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB0_6 ; GCN-IR-NEXT: s_branch BB0_6
; GCN-IR-NEXT: BB0_4: ; %udiv-preheader ; GCN-IR-NEXT: BB0_4: ; %udiv-preheader
; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: s_add_u32 s8, s2, -1 ; GCN-IR-NEXT: s_add_u32 s8, s2, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 ; GCN-IR-NEXT: v_not_b32_e32 v2, v2
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 ; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, v2, v3
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s9, s3, -1
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_lshr_b64 v[7:8], s[6:7], v4
; GCN-IR-NEXT: s_addc_u32 s9, s3, -1
; GCN-IR-NEXT: v_addc_u32_e64 v6, s[0:1], -1, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s9
; GCN-IR-NEXT: BB0_5: ; %udiv-do-while ; GCN-IR-NEXT: BB0_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s8, v7
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v2, s9 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s8, v6 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_and_b32_e32 v11, s2, v9
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s3, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB0_5 ; GCN-IR-NEXT: s_cbranch_vccz BB0_5
; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB0_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB0_7: ; %udiv-end ; GCN-IR-NEXT: BB0_7: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s2, v0
▲ Show 20 Lines • Show All 674 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-IR-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-IR-NEXT: s_cbranch_vccz BB6_4 ; GCN-IR-NEXT: s_cbranch_vccz BB6_4
; GCN-IR-NEXT: ; %bb.3: ; GCN-IR-NEXT: ; %bb.3:
; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v2, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: s_branch BB6_6 ; GCN-IR-NEXT: s_branch BB6_6
; GCN-IR-NEXT: BB6_4: ; %udiv-preheader ; GCN-IR-NEXT: BB6_4: ; %udiv-preheader
; GCN-IR-NEXT: s_add_u32 s3, s6, -1 ; GCN-IR-NEXT: s_add_u32 s3, s6, -1
; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 ; GCN-IR-NEXT: v_lshr_b64 v[7:8], 24, v3
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
; GCN-IR-NEXT: s_addc_u32 s8, s7, -1 ; GCN-IR-NEXT: s_addc_u32 s8, s7, -1
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc ; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, 58, v2
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_subb_u32_e64 v6, s[0:1], 0, 0, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: v_mov_b32_e32 v4, s8
; GCN-IR-NEXT: BB6_5: ; %udiv-do-while ; GCN-IR-NEXT: BB6_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v3
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s3, v7
; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v4, v8, vcc
; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s3, v6 ; GCN-IR-NEXT: v_or_b32_e32 v0, v9, v0
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_and_b32_e32 v11, s6, v9
; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v9
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v12, s7, v9
; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 ; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v5
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_or_b32_e32 v1, v10, v1
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v6, vcc
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[5:6]
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_sub_i32_e64 v7, s[0:1], v7, v11
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] ; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v10, v3
; GCN-IR-NEXT: v_subb_u32_e64 v8, s[0:1], v8, v12, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v2
; GCN-IR-NEXT: s_cbranch_vccz BB6_5 ; GCN-IR-NEXT: s_cbranch_vccz BB6_5
; GCN-IR-NEXT: BB6_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB6_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB6_7: ; %udiv-end ; GCN-IR-NEXT: BB6_7: ; %udiv-end
; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1 ; GCN-IR-NEXT: v_mul_lo_u32 v1, s6, v1
; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0 ; GCN-IR-NEXT: v_mul_hi_u32 v2, s6, v0
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, 0
; GCN-IR-NEXT: BB7_5: ; %udiv-do-while ; GCN-IR-NEXT: BB7_5: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 ; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1
; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 ; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v3
; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6 ; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6
; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 ; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2
; GCN-IR-NEXT: v_and_b32_e32 v10, 24, v8 ; GCN-IR-NEXT: v_and_b32_e32 v10, 24, v8
; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 ; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 ; GCN-IR-NEXT: v_mov_b32_e32 v4, v8
; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 ; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10
; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 ; GCN-IR-NEXT: v_mov_b32_e32 v5, v9
; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 ; GCN-IR-NEXT: v_mov_b32_e32 v9, v3
; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[0:1], 0, v7, s[0:1] ; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v3, s[0:1]
; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc ; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 ; GCN-IR-NEXT: v_mov_b32_e32 v8, v2
; GCN-IR-NEXT: s_cbranch_vccz BB7_5 ; GCN-IR-NEXT: s_cbranch_vccz BB7_5
; GCN-IR-NEXT: BB7_6: ; %udiv-loop-exit ; GCN-IR-NEXT: BB7_6: ; %udiv-loop-exit
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 ; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1
; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 ; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0
; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 ; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1
; GCN-IR-NEXT: BB7_7: ; %udiv-end ; GCN-IR-NEXT: BB7_7: ; %udiv-end
▲ Show 20 Lines • Show All 252 Lines • ▼ Show 20 Lines
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0 ; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5] ; GCN-IR-NEXT: s_xor_b64 s[10:11], exec, s[4:5]
; GCN-IR-NEXT: s_cbranch_execz BB9_5 ; GCN-IR-NEXT: s_cbranch_execz BB9_5
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader ; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
; GCN-IR-NEXT: v_lshr_b64 v[8:9], v[0:1], v7 ; GCN-IR-NEXT: v_lshr_b64 v[9:10], v[0:1], v7
; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6 ; GCN-IR-NEXT: v_add_i32_e32 v6, vcc, 0xffffffcf, v6
; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc ; GCN-IR-NEXT: v_addc_u32_e64 v7, s[4:5], 0, -1, vcc
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v12, 0
; GCN-IR-NEXT: v_mov_b32_e32 v8, 31
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff ; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
; GCN-IR-NEXT: BB9_3: ; %udiv-do-while ; GCN-IR-NEXT: BB9_3: ; %udiv-do-while
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 ; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1 ; GCN-IR-NEXT: v_lshl_b64 v[9:10], v[9:10], 1
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 ; GCN-IR-NEXT: v_lshr_b32_e32 v4, v3, v8
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4 ; GCN-IR-NEXT: v_or_b32_e32 v9, v9, v4
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v8 ; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v9
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v9, vcc ; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v10, vcc
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2 ; GCN-IR-NEXT: v_or_b32_e32 v2, v11, v2
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4 ; GCN-IR-NEXT: v_ashr_i32_e32 v11, v4, v8
; GCN-IR-NEXT: v_and_b32_e32 v12, 0x8000, v10 ; GCN-IR-NEXT: v_and_b32_e32 v13, 0x8000, v11
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10 ; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v11
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6 ; GCN-IR-NEXT: v_add_i32_e32 v11, vcc, 1, v6
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3 ; GCN-IR-NEXT: v_or_b32_e32 v3, v12, v3
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc ; GCN-IR-NEXT: v_addc_u32_e32 v12, vcc, 0, v7, vcc
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7] ; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[11:12], v[6:7]
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10 ; GCN-IR-NEXT: v_mov_b32_e32 v6, v11
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11 ; GCN-IR-NEXT: v_mov_b32_e32 v7, v12
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5 ; GCN-IR-NEXT: v_mov_b32_e32 v12, v5
; GCN-IR-NEXT: v_mov_b32_e32 v13, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v14, 0
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v12 ; GCN-IR-NEXT: v_sub_i32_e64 v9, s[4:5], v9, v13
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v13, s[4:5] ; GCN-IR-NEXT: v_subb_u32_e64 v10, s[4:5], v10, v14, s[4:5]
; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9] ; GCN-IR-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4 ; GCN-IR-NEXT: v_mov_b32_e32 v11, v4
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: s_cbranch_execnz BB9_3 ; GCN-IR-NEXT: s_cbranch_execnz BB9_3
; GCN-IR-NEXT: ; %bb.4: ; %Flow ; GCN-IR-NEXT: ; %bb.4: ; %Flow
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
; GCN-IR-NEXT: BB9_5: ; %Flow3 ; GCN-IR-NEXT: BB9_5: ; %Flow3
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] ; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 ; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3 ; GCN-IR-NEXT: v_or_b32_e32 v5, v5, v3
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