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Differential D75990

[ARM] MVE VFMA (reg) and VFMAS patterns
AbandonedPublic

Authored by dmgreen on Mar 11 2020, 7:22 AM.

Details

Reviewers
simon_tatham
SjoerdMeijer
samparker
ostannard
t.p.northover
Summary

These two instructions perform floating point fused multiply add using a GPR as one of the operands. As a result they select from a splat. VFMAS is q*q+r and VFMA is q*r + q

These, like the other floating point instruction using a gpr, will not be used a lot yet as the splat will not be sunk into loops. This will require some extra work to make sure that copies from fpr to gpr do not get stuck in the loop.

Diff Detail

Event Timeline

dmgreen created this revision.Mar 11 2020, 7:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 11 2020, 7:22 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
dmgreen abandoned this revision.Mar 11 2020, 8:20 AM

Simon's already got a better version of this!

simon_tatham added a comment.Mar 11 2020, 8:37 AM

... but I hadn't quite uploaded it yet. Now I have: D75998.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
12 lines
test/
CodeGen/
Thumb2/
14 lines

Diff 249617

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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let Predicates = [HasMVEFloat] in { let Predicates = [HasMVEFloat] in {
def MVE_VFMA_qr_f16 : MVE_VFMAMLA_qr<"vfma", "f16", 0b1, 0b11, 0b0>; def MVE_VFMA_qr_f16 : MVE_VFMAMLA_qr<"vfma", "f16", 0b1, 0b11, 0b0>;
def MVE_VFMA_qr_f32 : MVE_VFMAMLA_qr<"vfma", "f32", 0b0, 0b11, 0b0>; def MVE_VFMA_qr_f32 : MVE_VFMAMLA_qr<"vfma", "f32", 0b0, 0b11, 0b0>;
def MVE_VFMA_qr_Sf16 : MVE_VFMAMLA_qr<"vfmas", "f16", 0b1, 0b11, 0b1>; def MVE_VFMA_qr_Sf16 : MVE_VFMAMLA_qr<"vfmas", "f16", 0b1, 0b11, 0b1>;
def MVE_VFMA_qr_Sf32 : MVE_VFMAMLA_qr<"vfmas", "f32", 0b0, 0b11, 0b1>; def MVE_VFMA_qr_Sf32 : MVE_VFMAMLA_qr<"vfmas", "f32", 0b0, 0b11, 0b1>;
} }
let Predicates = [HasMVEFloat] in {
def : Pat<(v4f32 (fma (v4f32 MQPR:$src1), (v4f32 (ARMvdup SPR:$v2)), (v4f32 MQPR:$src3))),
(v4f32 (MVE_VFMA_qr_f32 $src3, $src1, (i32 (COPY_TO_REGCLASS (f32 SPR:$v2), rGPR))))>;
def : Pat<(v8f16 (fma (v8f16 MQPR:$src1), (v8f16 (ARMvdup HPR:$v2)), (v8f16 MQPR:$src3))),
(v8f16 (MVE_VFMA_qr_f16 $src3, $src1, (i32 (COPY_TO_REGCLASS (f16 HPR:$v2), rGPR))))>;
def : Pat<(v4f32 (fma (v4f32 MQPR:$src1), (v4f32 MQPR:$src2), (v4f32 (ARMvdup SPR:$v3)))),
(v4f32 (MVE_VFMA_qr_Sf32 $src1, $src2, (i32 (COPY_TO_REGCLASS (f32 SPR:$v3), rGPR))))>;
def : Pat<(v8f16 (fma (v8f16 MQPR:$src1), (v8f16 MQPR:$src2), (v8f16 (ARMvdup HPR:$v3)))),
(v8f16 (MVE_VFMA_qr_Sf16 $src1, $src2, (i32 (COPY_TO_REGCLASS (f16 HPR:$v3), rGPR))))>;
}
class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size, class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
bit bit_5, bit bit_12, list<dag> pattern=[]> bit bit_5, bit bit_12, list<dag> pattern=[]>
: MVE_qDestSrc_rSrc<iname, suffix, pattern> { : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
let Inst{28} = U; let Inst{28} = U;
let Inst{21-20} = size; let Inst{21-20} = size;
let Inst{16} = 0b0; let Inst{16} = 0b0;
let Inst{12} = bit_12; let Inst{12} = bit_12;
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llvm/test/CodeGen/Thumb2/mve-fmas.ll

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; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, r0 ; CHECK-MVE-FP-NEXT: vmul.f16 q1, q1, r0
; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, q1 ; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfmar16: ; CHECK-MVE-VMLA-LABEL: vfmar16:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vdup.16 q2, r0 ; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vfma.f16 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar16: ; CHECK-MVE-LABEL: vfmar16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s8, s0 ; CHECK-MVE-NEXT: vmov.f32 s8, s0
; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12 ; CHECK-MVE-NEXT: vmla.f16 s8, s4, s12
; CHECK-MVE-NEXT: vmov.f32 s14, s1 ; CHECK-MVE-NEXT: vmov.f32 s14, s1
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; CHECK-MVE-FP-NEXT: vmov r0, s8 ; CHECK-MVE-FP-NEXT: vmov r0, s8
; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, r0 ; CHECK-MVE-FP-NEXT: vadd.f16 q0, q0, r0
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfma16: ; CHECK-MVE-VMLA-LABEL: vfma16:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8 ; CHECK-MVE-VMLA-NEXT: vcvtb.f16.f32 s8, s8
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vdup.16 q2, r0 ; CHECK-MVE-VMLA-NEXT: vfmas.f16 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vfma.f16 q2, q0, q1
; CHECK-MVE-VMLA-NEXT: vmov q0, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfma16: ; CHECK-MVE-LABEL: vfma16:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8 ; CHECK-MVE-NEXT: vcvtb.f16.f32 s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s10, s0 ; CHECK-MVE-NEXT: vmovx.f16 s10, s0
; CHECK-MVE-NEXT: vmov.f32 s8, s12 ; CHECK-MVE-NEXT: vmov.f32 s8, s12
; CHECK-MVE-NEXT: vmovx.f16 s13, s1 ; CHECK-MVE-NEXT: vmovx.f16 s13, s1
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; CHECK-MVE-FP-NEXT: vmov r0, s8 ; CHECK-MVE-FP-NEXT: vmov r0, s8
; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, r0 ; CHECK-MVE-FP-NEXT: vmul.f32 q1, q1, r0
; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, q1 ; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, q1
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfmar32: ; CHECK-MVE-VMLA-LABEL: vfmar32:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vdup.32 q2, r0 ; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vfma.f32 q0, q1, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmar32: ; CHECK-MVE-LABEL: vfmar32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmla.f32 s3, s7, s8 ; CHECK-MVE-NEXT: vmla.f32 s3, s7, s8
; CHECK-MVE-NEXT: vmla.f32 s2, s6, s8 ; CHECK-MVE-NEXT: vmla.f32 s2, s6, s8
; CHECK-MVE-NEXT: vmla.f32 s1, s5, s8 ; CHECK-MVE-NEXT: vmla.f32 s1, s5, s8
; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8 ; CHECK-MVE-NEXT: vmla.f32 s0, s4, s8
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; CHECK-MVE-FP-NEXT: vmul.f32 q0, q0, q1 ; CHECK-MVE-FP-NEXT: vmul.f32 q0, q0, q1
; CHECK-MVE-FP-NEXT: vmov r0, s8 ; CHECK-MVE-FP-NEXT: vmov r0, s8
; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, r0 ; CHECK-MVE-FP-NEXT: vadd.f32 q0, q0, r0
; CHECK-MVE-FP-NEXT: bx lr ; CHECK-MVE-FP-NEXT: bx lr
; ;
; CHECK-MVE-VMLA-LABEL: vfmas32: ; CHECK-MVE-VMLA-LABEL: vfmas32:
; CHECK-MVE-VMLA: @ %bb.0: @ %entry ; CHECK-MVE-VMLA: @ %bb.0: @ %entry
; CHECK-MVE-VMLA-NEXT: vmov r0, s8 ; CHECK-MVE-VMLA-NEXT: vmov r0, s8
; CHECK-MVE-VMLA-NEXT: vdup.32 q2, r0 ; CHECK-MVE-VMLA-NEXT: vfmas.f32 q0, q1, r0
; CHECK-MVE-VMLA-NEXT: vfma.f32 q2, q0, q1
; CHECK-MVE-VMLA-NEXT: vmov q0, q2
; CHECK-MVE-VMLA-NEXT: bx lr ; CHECK-MVE-VMLA-NEXT: bx lr
; ;
; CHECK-MVE-LABEL: vfmas32: ; CHECK-MVE-LABEL: vfmas32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: @ kill: def $s8 killed $s8 def $q2 ; CHECK-MVE-NEXT: @ kill: def $s8 killed $s8 def $q2
; CHECK-MVE-NEXT: vmov.f32 s11, s8 ; CHECK-MVE-NEXT: vmov.f32 s11, s8
; CHECK-MVE-NEXT: vmla.f32 s11, s3, s7 ; CHECK-MVE-NEXT: vmla.f32 s11, s3, s7
; CHECK-MVE-NEXT: vmov.f32 s10, s8 ; CHECK-MVE-NEXT: vmov.f32 s10, s8
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