[x86][seses] No LFENCEs in basic blocks w/o loads

[zbrid]

Summary

Add a flag to the x86 Speculative Execution Side Effect Suppression Pass
that allows users to turn off adding LFENCEs in basic blocks with no
loads.

This is a part of a set of flags that can be used to experiment with
optimizing this mitigation for Load Value Injection.

One pager on Load Value Injection:
https://software.intel.com/security-software-guidance/software-guidance/load-value-injection

Deep dive on Load Value Injection:
https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection

Results of my performance testing

I ran the BoringSSL benchmarks which run many cryptographic operations
and reports the number of operations per second completed in a given
time.

Modified Mitigation vs Baseline
Geometric mean
0.073 (This can be read as the geomean ops/s of the mitigated program
was 7.3% of the ops/s of the unmitigated program. Similar below.)
Minimum
0.041
Quartile 1
0.060
Median
0.066
Quartile 3
0.081
Maximum
0.234

Fully Mitigated vs Baseline
Geometric mean
0.071
Minimum
0.041
Quartile 1
0.060
Median
0.063
Quartile 3
0.077
Maximum
0.230

[george.burgess.iv]

LGTM modulo a few cosmetic nits. Similar to the previous review, please wait for approval from someone with more ownership here before landing.

Thanks!

llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp

55

nit: please wrap at 80cols, potentially by "splitting the" " string"

91

nit: please delete this line

llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll

13

If these tests are checking for consecutive lines, consider using CHECK-FLAGGED-NEXT. Otherwise, FileCheck won't complain if there are intervening instructions (e.g., an incorrectly placed lfence)

[zbrid]

• Update tests to use CHECK-NEXT
• ClangFormat/nits

[zbrid]

Updated to address comments

llvm/lib/Target/X86/X86SpeculativeExecutionSideEffectSuppression.cpp

cl::desc("Only lfence before groups of terminators where at least one "
              "register other than %rip."),
     cl::init(false), cl::Hidden);
 
 static cl::opt<bool>
     OmitBranchLFENCEs("x86-seses-omit-branch-lfences",
                       cl::desc("Omit all lfences before branch instructions."),
                       cl::init(false), cl::Hidden);
 
+static cl::opt<bool> OmitLFENCEInBasicBlocksWithoutLoads(
+    "x86-seses-omit-lfence-in-bb-without-loads",
+    cl::desc("Omit LFENCE in basic blocks without any loads even if there are "
+             "stores."),
+    cl::init(false), cl::Hidden);
+
 static bool hasConstantAddressingMode(const MachineInstr &MI);
 
 namespace {
 
 class X86SpeculativeExecutionSideEffectSuppressionPass
     : public MachineFunctionPass {
 public:
   X86SpeculativeExecutionSideEffectSuppressionPass() : MachineFunctionPass(ID) {}
if (!EnableSpeculativeExecutionSideEffectSuppression)
     return false;
 
   LLVM_DEBUG(dbgs() << "********** " << getPassName() << " : " << MF.getName()
                     << " **********\n");
   bool Modified = false;
   const X86Subtarget &Subtarget = MF.getSubtarget<X86Subtarget>();
   const X86InstrInfo *TII = Subtarget.getInstrInfo();
   for (MachineBasicBlock &MBB : MF) {
+    if (OmitLFENCEInBasicBlocksWithoutLoads) {
+      bool FoundLoad = false;
+      for (const MachineInstr &MI : MBB) {
+        if (MI.mayLoad()) {
+          FoundLoad = true;
+          break;
+        }
+      }
+      if (!FoundLoad) {
+        continue;
+      }
+    }
+
     MachineInstr *FirstTerminator = nullptr;
 
     for (auto &MI : MBB) {
       // We want to put an LFENCE before any instruction that
       // may load or store. This LFENCE is intended to avoid leaking any secret
       // data due to a given load or store. This results in closing the cache
       // and memory timing side channels. We will treat terminators that load
       // or store separately.

llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression-omit-lfence-in-bb-without-loads.ll

+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable -x86-seses-omit-lfence-in-bb-without-loads %s -o - | FileCheck %s --check-prefix=CHECK-FLAGGED
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable %s -o - | FileCheck %s --check-prefix=CHECK-FULL
+
+define dso_local void @_Z4buzzv() {
+entry:
+  %a = alloca i32, align 4
+  store i32 10, i32* %a, align 4
+  ret void
+}
+
+; CHECK-FLAGGED: .globl _Z4buzzv                # -- Begin function _Z4buzzv
+; CHECK-FLAGGED-NEXT: .p2align 4, 0x90
+; CHECK-FLAGGED-NEXT: .type _Z4buzzv,@function
+; CHECK-FLAGGED-NEXT:_Z4buzzv:                               # @_Z4buzzv
+; CHECK-FLAGGED-NEXT:.L_Z4buzzv$local:
+; CHECK-FLAGGED-NEXT: .cfi_startproc
+; CHECK-FLAGGED-NEXT:# %bb.0:                                # %entry
+; CHECK-FLAGGED-NEXT: movl $10, -4(%rsp)
+; CHECK-FLAGGED-NEXT: retq
+
+
+; CHECK-FULL: .globl _Z4buzzv                # -- Begin function _Z4buzzv
+; CHECK-FULL-NEXT: .p2align 4, 0x90
+; CHECK-FULL-NEXT: .type _Z4buzzv,@function
+; CHECK-FULL-NEXT:_Z4buzzv:                               # @_Z4buzzv
+; CHECK-FULL-NEXT:.L_Z4buzzv$local:
+; CHECK-FULL-NEXT: .cfi_startproc
+; CHECK-FULL-NEXT:# %bb.0:                                # %entry
+; CHECK-FULL-NEXT: lfence
+; CHECK-FULL-NEXT: movl $10, -4(%rsp)
+; CHECK-FULL-NEXT: retq