[AMDGPU] Improve scheduling model for VOP3b instructions

[foad]

Summary

VOP3b instructions like v_addc_u32 write vcc (an sgpr) as well as a vgpr
result. The way this was modelled made the write to vcc take an extra
micro-op, which made the whole instruction take twice as long to issue,
which is inaccurate.

Fix this by introducing a new write class that doesn't consume any
resources.

[rampitec]

llvm/lib/Target/AMDGPU/SISchedule.td

32

The name suggests it is any VCC write, which is not so. In addition it is not always a VCC. Maybe change to WriteAuxSGPR?

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

989

What about AMDGPUMacroFusion which tries to do exactly the opposite?

[foad]

llvm/lib/Target/AMDGPU/SISchedule.td

32

The name suggests it is any VCC write, which is not so.

Good point. I will try to come up with a better name.

In addition it is not always a VCC.

True but the name gives you a hint that it is usually VCC (i.e. we try to persuade the register allocator to use VCC, and if it does then we can use a smaller instruction encoding).

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

989

Why do you say "the opposite"? Macro fusion tries to put the v_add next to the v_addc (but apparently it fails in this case). My patch should not stop this from working.

[rampitec]

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

989

Aren't you adding a latency between vcc def and its use?

[foad]

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

989

No I'm just replacing WriteSALU with WriteVCC which has the same latency. But macro fusion overrides this anyway and forces the latency to 0 for any dependencies between the instructions that it fuses.

[rampitec]

Mostly LGTM, except for the name of the resource.

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

989

OK, makes sense.

[foad]

llvm/lib/Target/AMDGPU/SISchedule.td

32

How about Write32BitAux ? The fact that it is writing an SGPR is not really important, all that matters is the latency, which should be the same as for the first def operand.

So v_addc would be [Write32Bit, Write32BitAux], v_div_scale_f64 would be [WriteDouble, WriteDoubleAux] and so on.

[rampitec]

llvm/lib/Target/AMDGPU/SISchedule.td

32

I think you do not need 2 resources, both 32 bit and 64 bit write the same mask. Maybe just WriteAux?

[foad]

Switch to using multiple "Aux" sched write classes.

[foad]

I think you do not need 2 resources, both 32 bit and 64 bit write the same mask. Maybe just WriteAux?

I want the write to VCC to have the same latency as the main result of the instruction. That's why I used multiple different "Aux" classes as in the updated patch.

[rampitec]

LGTM

[foad]

Rebase without D75909.

llvm/lib/Target/AMDGPU/SISchedule.td

 def WriteSALU   : SchedWrite;
 def WriteSMEM   : SchedWrite;
 def WriteVMEM   : SchedWrite;
 def WriteBarrier : SchedWrite;
 
 def MIVGPRRead  : SchedRead;
 def MIMFMARead  : SchedRead;
 
-// Normal 16 or 32 bit VALU instructions
+// Normal 16 or 32 bit VALU instructions. "Aux" forms are used for the second
+// and subsequent def operands of instructions with multiple results.
 def Write32Bit         : SchedWrite;
+def Write32BitAux      : SchedWrite;
 // Conversion to or from F32 (but not converting F64 to or from F32)
 def WriteFloatCvt      : SchedWrite;
 // F16 or F32 transcendental instructions (these are quarter rate)
 def WriteTrans32       : SchedWrite;
 // Other quarter rate VALU instructions
 def WriteQuarterRate32 : SchedWrite;
 
-def WriteFloatFMA   : SchedWrite;
+def WriteFloatFMA    : SchedWrite;
+def WriteFloatFMAAux : SchedWrite;
 
 // Slow quarter rate f64 instruction.
-def WriteDouble : SchedWrite;
+def WriteDouble    : SchedWrite;
+def WriteDoubleAux : SchedWrite;
 
 // half rate f64 instruction (same as v_add_f64)
 def WriteDoubleAdd  : SchedWrite;
 
 // Conversion to or from f64 instruction
 def WriteDoubleCvt  : SchedWrite;
 
 // F64 "transcendental" (actually only reciprocal and/or square root)
 // instructions
 def WriteTrans64    : SchedWrite;
 
 // Half rate 64-bit instructions.
-def Write64Bit : SchedWrite;
+def Write64Bit    : SchedWrite;
+def Write64BitAux : SchedWrite;
 
 // Integer multiplications.
-def WriteIntMul : SchedWrite;
+def WriteIntMul    : SchedWrite;
+def WriteIntMulAux : SchedWrite;
 
 // mAI multipass instructions.
 def Write2PassMAI  : SchedWrite;
 def Write8PassMAI  : SchedWrite;
 def Write16PassMAI : SchedWrite;
 def Write4PassDGEMM : SchedWrite;
 def Write8PassDGEMM : SchedWrite;
 

 }
 def HWRC   : ProcResource<1> { // Register destination cache
   let BufferSize = 1;
 }
 def HWXDL   : ProcResource<1> { // MFMA CU
   let BufferSize = 0;
 }
 
+// Define the resources and latency of a SchedWrite.
 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
                  int latency> : WriteRes<write, resources> {
   let Latency = latency;
+  // If no resources are specifed then assume that this is for the second or
+  // subsequent operand of an instruction, which we don't want to consume any
+  // additional issue resource.
+  let NumMicroOps = !if(!empty(resources), 0, 1);
 }
 
 class HWVALUWriteRes<SchedWrite write, int latency> :
   HWWriteRes<write, [HWVALU], latency>;
 
+class HWAuxWriteRes<SchedWrite write, int latency> :
+  HWWriteRes<write, [], latency>;
+
 def PredMIReadVGPR : SchedPredicate<[{TII->hasVGPRUses(*MI)}]>;
 
 def MIReadVGPR : SchedReadVariant<[
       SchedVar<PredMIReadVGPR, [MIVGPRRead]>,
       SchedVar<NoSchedPred, [ReadDefault]>]>;
 
 // The latency numbers are taken from AMD Accelerated Parallel Processing
 // guide. They may not be accurate.
 
 // The latency values are 1 / (operations / cycle) / 4.
 multiclass SICommonWriteRes {
 
   def : HWWriteRes<WriteBranch,  [HWBranch], 8>;
   def : HWWriteRes<WriteExport,  [HWExport], 4>;
   def : HWWriteRes<WriteLDS,     [HWLGKM],   5>; // Can be between 2 and 64
   def : HWWriteRes<WriteSALU,    [HWSALU],   1>;
   def : HWWriteRes<WriteSMEM,    [HWLGKM],   5>;
   def : HWWriteRes<WriteVMEM,    [HWVMEM],   80>;
   def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
 
   def : HWVALUWriteRes<Write32Bit,         1>;
+  def : HWAuxWriteRes<Write32BitAux,       1>;
   def : HWVALUWriteRes<WriteFloatCvt,      4>;
   def : HWVALUWriteRes<WriteTrans32,       4>;
   def : HWVALUWriteRes<WriteQuarterRate32, 4>;
 
   def : HWVALUWriteRes<Write4PassDGEMM,    4>;
   def : HWVALUWriteRes<Write8PassDGEMM,   16>;
 
   let ResourceCycles = [2] in
def WriteCopy : SchedWriteVariant<[
     SchedVar<PredIsVGPR64Copy, [Write64Bit]>,
     SchedVar<NoSchedPred, [WriteSALU]>]>;
 
 let SchedModel = SIFullSpeedModel in {
 
 defm : SICommonWriteRes;
 
 def : HWVALUWriteRes<Write64Bit,       2>;
+def : HWAuxWriteRes<Write64BitAux,     2>;
 def : HWVALUWriteRes<WriteIntMul,      4>;
+def : HWAuxWriteRes<WriteIntMulAux,    4>;
 def : HWVALUWriteRes<WriteFloatFMA,    1>;
+def : HWAuxWriteRes<WriteFloatFMAAux,  1>;
 def : HWVALUWriteRes<WriteDouble,      4>;
+def : HWAuxWriteRes<WriteDoubleAux,    4>;
 def : HWVALUWriteRes<WriteDoubleAdd,   2>;
 def : HWVALUWriteRes<WriteDoubleCvt,   4>;
 def : HWVALUWriteRes<WriteTrans64,     4>;
 
 def : InstRW<[WriteCopy], (instrs COPY)>;
 
 } // End SchedModel = SIFullSpeedModel
 
 let SchedModel = SIQuarterSpeedModel in {
 
 defm : SICommonWriteRes;
 
 def : HWVALUWriteRes<Write64Bit,       2>;
+def : HWAuxWriteRes<Write64BitAux,     2>;
 def : HWVALUWriteRes<WriteIntMul,      4>;
+def : HWAuxWriteRes<WriteIntMulAux,    4>;
 def : HWVALUWriteRes<WriteFloatFMA,    16>;
+def : HWAuxWriteRes<WriteFloatFMAAux,  16>;
 def : HWVALUWriteRes<WriteDouble,      16>;
+def : HWAuxWriteRes<WriteDoubleAux,    16>;
 def : HWVALUWriteRes<WriteDoubleAdd,    8>;
 def : HWVALUWriteRes<WriteDoubleCvt,    4>;
 def : HWVALUWriteRes<WriteTrans64,     16>;
 
 def : InstRW<[WriteCopy], (instrs COPY)>;
 def : InstRW<[Write64Bit, MIReadVGPR], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;
 def : InstRW<[Write2PassMAI,  MIMFMARead], (instregex "^V_MFMA_..._4X4X")>;
 def : InstRW<[Write8PassMAI,  MIMFMARead], (instregex "^V_MFMA_..._16X16X")>;
 def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_..._32X32X")>;
 
 }  // End SchedModel = SIQuarterSpeedModel
 
 let SchedModel = SIDPFullSpeedModel in {
 
 defm : SICommonWriteRes;
 
 def : HWVALUWriteRes<WriteFloatFMA,    1>;
+def : HWAuxWriteRes<WriteFloatFMAAux,  1>;
 def : HWVALUWriteRes<WriteDouble,      1>;
+def : HWAuxWriteRes<WriteDoubleAux,    1>;
 def : HWVALUWriteRes<WriteDoubleAdd,   1>;
 def : HWVALUWriteRes<WriteDoubleCvt,   1>;
 def : HWVALUWriteRes<WriteTrans64,     4>;
 def : HWVALUWriteRes<WriteIntMul,      1>;
+def : HWAuxWriteRes<WriteIntMulAux,    1>;
 def : HWVALUWriteRes<Write64Bit,       1>;
+def : HWAuxWriteRes<Write64BitAux,     1>;
 
 def : InstRW<[WriteCopy], (instrs COPY)>;
 def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;
 def : InstRW<[Write2PassMAI,   MIMFMARead], (instregex "^V_MFMA_.32_4X4X")>;
 def : InstRW<[Write8PassMAI,   MIMFMARead], (instregex "^V_MFMA_.32_16X16X")>;
 def : InstRW<[Write16PassMAI,  MIMFMARead], (instregex "^V_MFMA_.32_32X32X")>;
 def : InstRW<[Write4PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_4X4X")>;
 def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;
 
 } // End SchedModel = SIDPFullSpeedModel
 
 let SchedModel = GFX10SpeedModel in {
 
 // The latency values are 1 / (operations / cycle).
 // Add 1 stall cycle for VGPR read.
 def : HWWriteRes<Write32Bit,         [HWVALU, HWRC],   5>;
+def : HWWriteRes<Write32BitAux,      [HWRC],           5>;
 def : HWWriteRes<WriteFloatCvt,      [HWVALU, HWRC],   5>;
 def : HWWriteRes<Write64Bit,         [HWVALU, HWRC],   6>;
+def : HWWriteRes<Write64BitAux,      [HWRC],           6>;
 def : HWWriteRes<WriteTrans32,       [HWVALU, HWRC],   10>;
 def : HWWriteRes<WriteQuarterRate32, [HWVALU, HWRC],   8>;
 def : HWWriteRes<WriteFloatFMA,      [HWVALU, HWRC],   5>;
+def : HWWriteRes<WriteFloatFMAAux,   [HWRC],           5>;
 def : HWWriteRes<WriteDouble,        [HWVALU, HWRC],   22>;
+def : HWWriteRes<WriteDoubleAux,     [HWRC],           22>;
 def : HWWriteRes<WriteDoubleAdd,     [HWVALU, HWRC],   22>;
 def : HWWriteRes<WriteDoubleCvt,     [HWVALU, HWRC],   22>;
 def : HWWriteRes<WriteIntMul,        [HWVALU, HWRC],   8>;
+def : HWWriteRes<WriteIntMulAux,     [HWRC],           8>;
 def : HWWriteRes<WriteTrans64,       [HWVALU, HWRC],   24>;
 
 def : HWWriteRes<WriteBranch,        [HWBranch],       32>;
 def : HWWriteRes<WriteExport,        [HWExport, HWRC], 16>;
 def : HWWriteRes<WriteLDS,           [HWLGKM,   HWRC], 20>;
 def : HWWriteRes<WriteSALU,          [HWSALU,   HWRC], 2>;
 def : HWWriteRes<WriteSMEM,          [HWLGKM,   HWRC], 20>;
 def : HWWriteRes<WriteVMEM,          [HWVMEM,   HWRC], 320>;
 def : HWWriteRes<WriteBarrier,       [HWBranch],       2000>;
 
 def : InstRW<[WriteCopy], (instrs COPY)>;
 
 }  // End SchedModel = GFX10SpeedModel

llvm/lib/Target/AMDGPU/VOP1Instructions.td

def VOP_SWAP_I32 : VOPProfile<[i32, i32, i32, untyped]> {
   let Asm64 = "";
   let Ins64 = (ins);
 }
 
 let SubtargetPredicate = isGFX9Plus in {
   def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {
     let Constraints = "$vdst = $src1, $vdst1 = $src0";
     let DisableEncoding = "$vdst1,$src1";
-    let SchedRW = [Write64Bit, Write64Bit];
+    let SchedRW = [Write64Bit, Write64BitAux];
   }
 
   defm V_SAT_PK_U8_I16    : VOP1Inst<"v_sat_pk_u8_i16", VOP_I32_I32>;
 
   let mayRaiseFPException = 0 in {
     defm V_CVT_NORM_I16_F16 : VOP1Inst<"v_cvt_norm_i16_f16", VOP_I16_F16_SPECIAL_OMOD>;
     defm V_CVT_NORM_U16_F16 : VOP1Inst<"v_cvt_norm_u16_f16", VOP_I16_F16_SPECIAL_OMOD>;
   } // End mayRaiseFPException = 0
 } // End SubtargetPredicate = isGFX9Plus
 
 let SubtargetPredicate = isGFX9Only in {
   defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>;
 } // End SubtargetPredicate = isGFX9Only
 
 let SubtargetPredicate = isGFX10Plus in {
   defm V_PIPEFLUSH        : VOP1Inst<"v_pipeflush", VOP_NONE>;
 
   let Uses = [M0] in {
     defm V_MOVRELSD_2_B32 :
       VOP1Inst<"v_movrelsd_2_b32", VOP_MOVRELSD>;
 
     def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> {
       let Constraints = "$vdst = $src1, $vdst1 = $src0";
       let DisableEncoding = "$vdst1,$src1";
-      let SchedRW = [Write64Bit, Write64Bit];
+      let SchedRW = [Write64Bit, Write64BitAux];
     }
   } // End Uses = [M0]
 } // End SubtargetPredicate = isGFX10Plus
 
 def VOPProfileAccMov : VOP_NO_EXT<VOP_I32_I32> {
   let DstRC = RegisterOperand<AGPR_32>;
   let Src0RC32 = RegisterOperand<AGPR_32>;
   let Asm32 = " $vdst, $src0";

llvm/lib/Target/AMDGPU/VOP2Instructions.td

 
 multiclass VOP2bInst <string opName,
                       VOPProfile P,
                       SDPatternOperator node = null_frag,
                       string revOp = opName,
                       bit GFX9Renamed = 0,
                       bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
   let renamedInGFX9 = GFX9Renamed in {
-    let SchedRW = [Write32Bit, WriteSALU] in {
+    let SchedRW = [Write32Bit, Write32BitAux] in {
       let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
         def _e32 : VOP2_Pseudo <opName, P, VOPPatOrNull<node,P>.ret>,
                    Commutable_REV<revOp#"_e32", !eq(revOp, opName)> {
           let usesCustomInserter = !eq(P.NumSrcArgs, 2);
         }
 
         foreach _ = BoolToList<P.HasExtSDWA>.ret in
           def _sdwa  : VOP2_SDWA_Pseudo <opName, P> {

llvm/lib/Target/AMDGPU/VOP3Instructions.td

 
 let SchedRW = [WriteDoubleAdd], FPDPRounding = 1 in {
   defm V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
   defm V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
 } // End SchedRW = [WriteDoubleAdd], FPDPRounding = 1
 
 
 let mayRaiseFPException = 0 in { // Seems suspicious but manual doesn't say it does.
-  let SchedRW = [WriteFloatFMA, WriteSALU] in
+  let SchedRW = [WriteFloatFMA, WriteFloatFMAAux] in
   defm V_DIV_SCALE_F32 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> ;
 
   // Double precision division pre-scale.
-  let SchedRW = [WriteDouble, WriteSALU], FPDPRounding = 1 in
+  let SchedRW = [WriteDouble, WriteDoubleAux], FPDPRounding = 1 in
   defm V_DIV_SCALE_F64 : VOP3Inst_Pseudo_Wrapper <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1>;
 } // End mayRaiseFPException = 0
 
 defm V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
 
 let Constraints = "@earlyclobber $vdst" in {
 defm V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
 } // End Constraints = "@earlyclobber $vdst"

 let SubtargetPredicate = isGFX7Plus in {
 
 let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
 defm V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
 defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>;
 } // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32]
 
 let isCommutable = 1 in {
-let SchedRW = [WriteIntMul, WriteSALU] in {
+let SchedRW = [WriteIntMul, WriteIntMulAux] in {
 defm V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
 defm V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
-} // End SchedRW = [WriteIntMul, WriteSALU]
+} // End SchedRW = [WriteIntMul, WriteIntMulAux]
 } // End isCommutable = 1
 
 } // End SubtargetPredicate = isGFX7Plus
 
 let FPDPRounding = 1 in {
   let Predicates = [Has16BitInsts, isGFX8Only] in {
     defm V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
     defm V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, any_fma>;

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
 
 ; Check lowering of some large extractelement that use the stack
 ; instead of register indexing.
 
 define i32 @v_extract_v64i32_varidx(<64 x i32> addrspace(1)* %ptr, i32 %idx) {
 ; GCN-LABEL: v_extract_v64i32_varidx:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_add_u32 s33, s32, 0x3fc0
 ; GCN-NEXT:    s_and_b32 s33, s33, 0xffffc000
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v0
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    global_load_dwordx4 v[8:11], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[12:15], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[56:59], v[3:4], off offset:48
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
 ; GCN-NEXT:    s_mov_b32 s5, 0
-; GCN-NEXT:    v_mov_b32_e32 v3, s4
-; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v4, vcc
+; GCN-NEXT:    s_movk_i32 s4, 0x80
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    s_movk_i32 s4, 0xc0
+; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
 ; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
 ; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
 ; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
 ; GCN-NEXT:    global_load_dwordx4 v[28:31], v[0:1], off offset:48
 ; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
 ; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
 ; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
-; GCN-NEXT:    global_load_dwordx4 v[44:47], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[48:51], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[3:4], off offset:48
-; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-NEXT:    v_add_co_u32_e32 v60, vcc, v0, v5
-; GCN-NEXT:    v_addc_co_u32_e32 v61, vcc, v1, v6, vcc
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:16
 ; GCN-NEXT:    v_and_b32_e32 v0, 63, v2
 ; GCN-NEXT:    v_lshrrev_b32_e64 v1, 6, s33
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GCN-NEXT:    v_add_u32_e32 v1, 0x100, v1
 ; GCN-NEXT:    v_add_u32_e32 v0, v1, v0
-; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[4:7], v[60:61], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
 ; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
 ; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:260
 ; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:264
 ; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:268
 ; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:272
 ; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:276
 ; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:280
 ; GCN-NEXT:    buffer_store_dword v23, off, s[0:3], s33 offset:284
 ; GCN-NEXT:    buffer_store_dword v24, off, s[0:3], s33 offset:288
 ; GCN-NEXT:    buffer_store_dword v25, off, s[0:3], s33 offset:292
 ; GCN-NEXT:    buffer_store_dword v26, off, s[0:3], s33 offset:296
 ; GCN-NEXT:    buffer_store_dword v27, off, s[0:3], s33 offset:300
 ; GCN-NEXT:    buffer_store_dword v28, off, s[0:3], s33 offset:304
 ; GCN-NEXT:    buffer_store_dword v29, off, s[0:3], s33 offset:308
 ; GCN-NEXT:    buffer_store_dword v30, off, s[0:3], s33 offset:312
 ; GCN-NEXT:    buffer_store_dword v31, off, s[0:3], s33 offset:316
 ; GCN-NEXT:    buffer_store_dword v32, off, s[0:3], s33 offset:320
 ; GCN-NEXT:    buffer_store_dword v33, off, s[0:3], s33 offset:324
 ; GCN-NEXT:    buffer_store_dword v34, off, s[0:3], s33 offset:328
 ; GCN-NEXT:    buffer_store_dword v35, off, s[0:3], s33 offset:332
 ; GCN-NEXT:    buffer_store_dword v36, off, s[0:3], s33 offset:384
 ; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:388
 ; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:392
 ; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:396
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:336
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:340
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:344
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:348
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:352
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:356
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:360
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:364
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:368
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:372
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:376
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:380
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:416
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:420
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:424
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:428
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v20
-; GCN-NEXT:    v_mov_b32_e32 v13, v21
-; GCN-NEXT:    v_mov_b32_e32 v14, v22
-; GCN-NEXT:    v_mov_b32_e32 v15, v23
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:432
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:436
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:440
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:444
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:336
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:340
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:344
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:348
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v16, v24
+; GCN-NEXT:    v_mov_b32_e32 v17, v25
+; GCN-NEXT:    v_mov_b32_e32 v18, v26
+; GCN-NEXT:    v_mov_b32_e32 v19, v27
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:352
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:356
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:360
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:364
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:368
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:372
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:376
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:380
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:448
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:452
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:456
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:460
-; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
-; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
-; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
-; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:416
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:420
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:424
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:428
+; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:432
+; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:436
+; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:440
+; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:444
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v11
-; GCN-NEXT:    v_mov_b32_e32 v9, v12
-; GCN-NEXT:    v_mov_b32_e32 v10, v13
-; GCN-NEXT:    v_mov_b32_e32 v11, v14
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    v_mov_b32_e32 v4, v7
+; GCN-NEXT:    v_mov_b32_e32 v5, v8
+; GCN-NEXT:    v_mov_b32_e32 v6, v9
+; GCN-NEXT:    v_mov_b32_e32 v7, v10
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v15
-; GCN-NEXT:    v_mov_b32_e32 v13, v16
-; GCN-NEXT:    v_mov_b32_e32 v14, v17
-; GCN-NEXT:    v_mov_b32_e32 v15, v18
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:496
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:500
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:504
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:508
+; GCN-NEXT:    v_mov_b32_e32 v8, v11
+; GCN-NEXT:    v_mov_b32_e32 v9, v12
+; GCN-NEXT:    v_mov_b32_e32 v10, v13
+; GCN-NEXT:    v_mov_b32_e32 v11, v14
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:496
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:500
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:504
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:508
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_mov_b32 s33, s6
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %vec = load <64 x i32>, <64 x i32> addrspace(1)* %ptr
   %elt = extractelement <64 x i32> %vec, i32 %idx
   ret i32 %elt
 }
 
 define i16 @v_extract_v128i16_varidx(<128 x i16> addrspace(1)* %ptr, i32 %idx) {
 ; GCN-LABEL: v_extract_v128i16_varidx:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_add_u32 s33, s32, 0x3fc0
 ; GCN-NEXT:    s_and_b32 s33, s33, 0xffffc000
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v0
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    global_load_dwordx4 v[8:11], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[12:15], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[56:59], v[3:4], off offset:48
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
 ; GCN-NEXT:    s_mov_b32 s5, 0
-; GCN-NEXT:    v_mov_b32_e32 v3, s4
-; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v4, vcc
+; GCN-NEXT:    s_movk_i32 s4, 0x80
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    s_movk_i32 s4, 0xc0
+; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
 ; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
 ; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
 ; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
 ; GCN-NEXT:    global_load_dwordx4 v[28:31], v[0:1], off offset:48
 ; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
 ; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
 ; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
-; GCN-NEXT:    global_load_dwordx4 v[44:47], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[48:51], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[3:4], off offset:48
-; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-NEXT:    v_add_co_u32_e32 v60, vcc, v0, v5
-; GCN-NEXT:    v_addc_co_u32_e32 v61, vcc, v1, v6, vcc
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:16
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, 1, v2
 ; GCN-NEXT:    v_and_b32_e32 v0, 63, v0
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GCN-NEXT:    v_and_b32_e32 v1, 1, v2
 ; GCN-NEXT:    v_lshlrev_b32_e32 v1, 4, v1
-; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[4:7], v[60:61], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
 ; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
 ; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:260
 ; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:264
 ; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:268
 ; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:272
 ; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:276
 ; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:280
 ; GCN-NEXT:    buffer_store_dword v23, off, s[0:3], s33 offset:284
 ; GCN-NEXT:    buffer_store_dword v24, off, s[0:3], s33 offset:288
 ; GCN-NEXT:    buffer_store_dword v25, off, s[0:3], s33 offset:292
 ; GCN-NEXT:    buffer_store_dword v26, off, s[0:3], s33 offset:296
 ; GCN-NEXT:    buffer_store_dword v27, off, s[0:3], s33 offset:300
 ; GCN-NEXT:    buffer_store_dword v28, off, s[0:3], s33 offset:304
 ; GCN-NEXT:    buffer_store_dword v29, off, s[0:3], s33 offset:308
 ; GCN-NEXT:    buffer_store_dword v30, off, s[0:3], s33 offset:312
 ; GCN-NEXT:    buffer_store_dword v31, off, s[0:3], s33 offset:316
 ; GCN-NEXT:    buffer_store_dword v32, off, s[0:3], s33 offset:320
 ; GCN-NEXT:    buffer_store_dword v33, off, s[0:3], s33 offset:324
 ; GCN-NEXT:    buffer_store_dword v34, off, s[0:3], s33 offset:328
 ; GCN-NEXT:    buffer_store_dword v35, off, s[0:3], s33 offset:332
 ; GCN-NEXT:    buffer_store_dword v36, off, s[0:3], s33 offset:384
 ; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:388
 ; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:392
 ; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:396
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:336
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:340
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:344
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:348
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:352
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:356
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:360
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:364
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:368
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:372
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:376
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:380
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:416
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:420
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:424
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:428
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v20
-; GCN-NEXT:    v_mov_b32_e32 v13, v21
-; GCN-NEXT:    v_mov_b32_e32 v14, v22
-; GCN-NEXT:    v_mov_b32_e32 v15, v23
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:432
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:436
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:440
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:444
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:336
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:340
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:344
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:348
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v16, v24
+; GCN-NEXT:    v_mov_b32_e32 v17, v25
+; GCN-NEXT:    v_mov_b32_e32 v18, v26
+; GCN-NEXT:    v_mov_b32_e32 v19, v27
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:352
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:356
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:360
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:364
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:368
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:372
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:376
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:380
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:448
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:452
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:456
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:460
-; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
-; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
-; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
-; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:416
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:420
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:424
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:428
+; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:432
+; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:436
+; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:440
+; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:444
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v11
-; GCN-NEXT:    v_mov_b32_e32 v9, v12
-; GCN-NEXT:    v_mov_b32_e32 v10, v13
-; GCN-NEXT:    v_mov_b32_e32 v11, v14
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    v_mov_b32_e32 v4, v7
+; GCN-NEXT:    v_mov_b32_e32 v5, v8
+; GCN-NEXT:    v_mov_b32_e32 v6, v9
+; GCN-NEXT:    v_mov_b32_e32 v7, v10
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v15
-; GCN-NEXT:    v_mov_b32_e32 v13, v16
-; GCN-NEXT:    v_mov_b32_e32 v14, v17
-; GCN-NEXT:    v_mov_b32_e32 v15, v18
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:496
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:500
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:504
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:508
-; GCN-NEXT:    v_lshrrev_b32_e64 v15, 6, s33
-; GCN-NEXT:    v_add_u32_e32 v15, 0x100, v15
-; GCN-NEXT:    v_add_u32_e32 v0, v15, v0
+; GCN-NEXT:    v_mov_b32_e32 v8, v11
+; GCN-NEXT:    v_mov_b32_e32 v9, v12
+; GCN-NEXT:    v_mov_b32_e32 v10, v13
+; GCN-NEXT:    v_mov_b32_e32 v11, v14
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:496
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:500
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:504
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:508
+; GCN-NEXT:    v_lshrrev_b32_e64 v11, 6, s33
+; GCN-NEXT:    v_add_u32_e32 v11, 0x100, v11
+; GCN-NEXT:    v_add_u32_e32 v0, v11, v0
 ; GCN-NEXT:    buffer_load_dword v0, v0, s[0:3], 0 offen
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_mov_b32 s33, s6
-; GCN-NEXT:    s_waitcnt vmcnt(14)
+; GCN-NEXT:    s_waitcnt vmcnt(12)
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %vec = load <128 x i16>, <128 x i16> addrspace(1)* %ptr
   %elt = extractelement <128 x i16> %vec, i32 %idx
   ret i16 %elt
 }
 
 define i64 @v_extract_v32i64_varidx(<32 x i64> addrspace(1)* %ptr, i32 %idx) {
 ; GCN-LABEL: v_extract_v32i64_varidx:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s6, s33
 ; GCN-NEXT:    s_add_u32 s33, s32, 0x3fc0
 ; GCN-NEXT:    s_and_b32 s33, s33, 0xffffc000
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, 64, v0
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v61, off, s[0:3], s33 ; 4-byte Folded Spill
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s4, 0x80
-; GCN-NEXT:    global_load_dwordx4 v[8:11], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[12:15], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[56:59], v[3:4], off offset:48
+; GCN-NEXT:    v_add_co_u32_e32 v12, vcc, 64, v0
+; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 ; 4-byte Folded Spill
+; GCN-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v1, vcc
+; GCN-NEXT:    global_load_dwordx4 v[4:7], v[12:13], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[12:13], off offset:32
 ; GCN-NEXT:    s_mov_b32 s5, 0
-; GCN-NEXT:    v_mov_b32_e32 v3, s4
-; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e32 v3, vcc, v0, v3
-; GCN-NEXT:    v_addc_co_u32_e32 v4, vcc, v1, v4, vcc
+; GCN-NEXT:    s_movk_i32 s4, 0x80
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    s_movk_i32 s4, 0xc0
+; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    buffer_store_dword v1, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v2, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v3, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
+; GCN-NEXT:    v_add_co_u32_e32 v52, vcc, v0, v16
+; GCN-NEXT:    v_addc_co_u32_e32 v53, vcc, v1, v17, vcc
+; GCN-NEXT:    v_mov_b32_e32 v17, s5
+; GCN-NEXT:    v_mov_b32_e32 v16, s4
+; GCN-NEXT:    v_add_co_u32_e32 v56, vcc, v0, v16
+; GCN-NEXT:    global_load_dwordx4 v[12:15], v[12:13], off offset:48
+; GCN-NEXT:    v_addc_co_u32_e32 v57, vcc, v1, v17, vcc
 ; GCN-NEXT:    global_load_dwordx4 v[16:19], v[0:1], off
 ; GCN-NEXT:    global_load_dwordx4 v[20:23], v[0:1], off offset:16
 ; GCN-NEXT:    global_load_dwordx4 v[24:27], v[0:1], off offset:32
 ; GCN-NEXT:    global_load_dwordx4 v[28:31], v[0:1], off offset:48
 ; GCN-NEXT:    global_load_dwordx4 v[32:35], v[0:1], off offset:64
 ; GCN-NEXT:    global_load_dwordx4 v[36:39], v[0:1], off offset:128
 ; GCN-NEXT:    global_load_dwordx4 v[40:43], v[0:1], off offset:192
-; GCN-NEXT:    global_load_dwordx4 v[44:47], v[3:4], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[48:51], v[3:4], off offset:32
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[3:4], off offset:48
-; GCN-NEXT:    s_movk_i32 s4, 0xc0
-; GCN-NEXT:    v_mov_b32_e32 v6, s5
-; GCN-NEXT:    v_mov_b32_e32 v5, s4
-; GCN-NEXT:    v_add_co_u32_e32 v60, vcc, v0, v5
-; GCN-NEXT:    v_addc_co_u32_e32 v61, vcc, v1, v6, vcc
+; GCN-NEXT:    global_load_dwordx4 v[44:47], v[52:53], off offset:16
+; GCN-NEXT:    global_load_dwordx4 v[8:11], v[52:53], off offset:32
+; GCN-NEXT:    global_load_dwordx4 v[52:55], v[52:53], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:16
 ; GCN-NEXT:    v_and_b32_e32 v0, 31, v2
 ; GCN-NEXT:    v_lshrrev_b32_e64 v2, 6, s33
 ; GCN-NEXT:    v_lshlrev_b32_e32 v0, 3, v0
 ; GCN-NEXT:    v_add_u32_e32 v2, 0x100, v2
 ; GCN-NEXT:    v_add_u32_e32 v1, v2, v0
-; GCN-NEXT:    s_add_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_sub_u32 s32, s32, 0x10000
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:640 ; 4-byte Folded Spill
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:644 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:648 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:652 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:656 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:660 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:664 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:668 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:672 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:676 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:680 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:684 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:688 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:692 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:696 ; 4-byte Folded Spill
-; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:700 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[4:7], v[60:61], off offset:16
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:576 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:580 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:584 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:588 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:592 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:596 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:600 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:604 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:608 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:612 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:616 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:620 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:624 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:628 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:632 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:636 ; 4-byte Folded Spill
-; GCN-NEXT:    global_load_dwordx4 v[52:55], v[60:61], off offset:48
+; GCN-NEXT:    global_load_dwordx4 v[48:51], v[56:57], off offset:32
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:512 ; 4-byte Folded Spill
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:516 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:520 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:524 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:528 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:532 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:536 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:540 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:544 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:548 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:552 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:556 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:560 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:564 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:568 ; 4-byte Folded Spill
 ; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:572 ; 4-byte Folded Spill
+; GCN-NEXT:    global_load_dwordx4 v[56:59], v[56:57], off offset:48
 ; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:256
 ; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:260
 ; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:264
 ; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:268
 ; GCN-NEXT:    buffer_store_dword v20, off, s[0:3], s33 offset:272
 ; GCN-NEXT:    buffer_store_dword v21, off, s[0:3], s33 offset:276
 ; GCN-NEXT:    buffer_store_dword v22, off, s[0:3], s33 offset:280
 ; GCN-NEXT:    buffer_store_dword v23, off, s[0:3], s33 offset:284
 ; GCN-NEXT:    buffer_store_dword v24, off, s[0:3], s33 offset:288
 ; GCN-NEXT:    buffer_store_dword v25, off, s[0:3], s33 offset:292
 ; GCN-NEXT:    buffer_store_dword v26, off, s[0:3], s33 offset:296
 ; GCN-NEXT:    buffer_store_dword v27, off, s[0:3], s33 offset:300
 ; GCN-NEXT:    buffer_store_dword v28, off, s[0:3], s33 offset:304
 ; GCN-NEXT:    buffer_store_dword v29, off, s[0:3], s33 offset:308
 ; GCN-NEXT:    buffer_store_dword v30, off, s[0:3], s33 offset:312
 ; GCN-NEXT:    buffer_store_dword v31, off, s[0:3], s33 offset:316
 ; GCN-NEXT:    buffer_store_dword v32, off, s[0:3], s33 offset:320
 ; GCN-NEXT:    buffer_store_dword v33, off, s[0:3], s33 offset:324
 ; GCN-NEXT:    buffer_store_dword v34, off, s[0:3], s33 offset:328
 ; GCN-NEXT:    buffer_store_dword v35, off, s[0:3], s33 offset:332
 ; GCN-NEXT:    buffer_store_dword v36, off, s[0:3], s33 offset:384
 ; GCN-NEXT:    buffer_store_dword v37, off, s[0:3], s33 offset:388
 ; GCN-NEXT:    buffer_store_dword v38, off, s[0:3], s33 offset:392
 ; GCN-NEXT:    buffer_store_dword v39, off, s[0:3], s33 offset:396
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:336
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:340
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:344
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:348
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:352
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:356
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:360
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:364
-; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:368
-; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:372
-; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:376
-; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:380
-; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
-; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
-; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
-; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
-; GCN-NEXT:    buffer_store_dword v48, off, s[0:3], s33 offset:416
-; GCN-NEXT:    buffer_store_dword v49, off, s[0:3], s33 offset:420
-; GCN-NEXT:    buffer_store_dword v50, off, s[0:3], s33 offset:424
-; GCN-NEXT:    buffer_store_dword v51, off, s[0:3], s33 offset:428
-; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
-; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v20
-; GCN-NEXT:    v_mov_b32_e32 v13, v21
-; GCN-NEXT:    v_mov_b32_e32 v14, v22
-; GCN-NEXT:    v_mov_b32_e32 v15, v23
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:432
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:436
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:440
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:444
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:336
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:340
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:344
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:348
+; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:640 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:644 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:648 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v19, off, s[0:3], s33 offset:652 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v20, off, s[0:3], s33 offset:656 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v21, off, s[0:3], s33 offset:660 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v22, off, s[0:3], s33 offset:664 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v23, off, s[0:3], s33 offset:668 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v24, off, s[0:3], s33 offset:672 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v25, off, s[0:3], s33 offset:676 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v26, off, s[0:3], s33 offset:680 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v27, off, s[0:3], s33 offset:684 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v28, off, s[0:3], s33 offset:688 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v29, off, s[0:3], s33 offset:692 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v30, off, s[0:3], s33 offset:696 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v31, off, s[0:3], s33 offset:700 ; 4-byte Folded Reload
+; GCN-NEXT:    s_waitcnt vmcnt(0)
+; GCN-NEXT:    v_mov_b32_e32 v16, v24
+; GCN-NEXT:    v_mov_b32_e32 v17, v25
+; GCN-NEXT:    v_mov_b32_e32 v18, v26
+; GCN-NEXT:    v_mov_b32_e32 v19, v27
+; GCN-NEXT:    buffer_store_dword v16, off, s[0:3], s33 offset:352
+; GCN-NEXT:    buffer_store_dword v17, off, s[0:3], s33 offset:356
+; GCN-NEXT:    buffer_store_dword v18, off, s[0:3], s33 offset:360
+; GCN-NEXT:    buffer_store_dword v19, off, s[0:3], s33 offset:364
+; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:368
+; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:372
+; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:376
+; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:380
 ; GCN-NEXT:    buffer_store_dword v40, off, s[0:3], s33 offset:448
 ; GCN-NEXT:    buffer_store_dword v41, off, s[0:3], s33 offset:452
 ; GCN-NEXT:    buffer_store_dword v42, off, s[0:3], s33 offset:456
 ; GCN-NEXT:    buffer_store_dword v43, off, s[0:3], s33 offset:460
-; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
-; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
-; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
-; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
+; GCN-NEXT:    buffer_store_dword v44, off, s[0:3], s33 offset:400
+; GCN-NEXT:    buffer_store_dword v45, off, s[0:3], s33 offset:404
+; GCN-NEXT:    buffer_store_dword v46, off, s[0:3], s33 offset:408
+; GCN-NEXT:    buffer_store_dword v47, off, s[0:3], s33 offset:412
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:416
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:420
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:424
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:428
+; GCN-NEXT:    buffer_store_dword v52, off, s[0:3], s33 offset:432
+; GCN-NEXT:    buffer_store_dword v53, off, s[0:3], s33 offset:436
+; GCN-NEXT:    buffer_store_dword v54, off, s[0:3], s33 offset:440
+; GCN-NEXT:    buffer_store_dword v55, off, s[0:3], s33 offset:444
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:576 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:580 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:584 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:588 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:592 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:596 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:600 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:604 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:608 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:612 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:616 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:620 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:624 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:628 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:632 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:636 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v8, v11
-; GCN-NEXT:    v_mov_b32_e32 v9, v12
-; GCN-NEXT:    v_mov_b32_e32 v10, v13
-; GCN-NEXT:    v_mov_b32_e32 v11, v14
-; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
-; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
-; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
-; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    v_mov_b32_e32 v4, v7
+; GCN-NEXT:    v_mov_b32_e32 v5, v8
+; GCN-NEXT:    v_mov_b32_e32 v6, v9
+; GCN-NEXT:    v_mov_b32_e32 v7, v10
+; GCN-NEXT:    buffer_store_dword v4, off, s[0:3], s33 offset:464
+; GCN-NEXT:    buffer_store_dword v5, off, s[0:3], s33 offset:468
+; GCN-NEXT:    buffer_store_dword v6, off, s[0:3], s33 offset:472
+; GCN-NEXT:    buffer_store_dword v7, off, s[0:3], s33 offset:476
 ; GCN-NEXT:    buffer_load_dword v3, off, s[0:3], s33 offset:512 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v4, off, s[0:3], s33 offset:516 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v5, off, s[0:3], s33 offset:520 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v6, off, s[0:3], s33 offset:524 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v7, off, s[0:3], s33 offset:528 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v8, off, s[0:3], s33 offset:532 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v9, off, s[0:3], s33 offset:536 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v10, off, s[0:3], s33 offset:540 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v11, off, s[0:3], s33 offset:544 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v12, off, s[0:3], s33 offset:548 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v13, off, s[0:3], s33 offset:552 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v14, off, s[0:3], s33 offset:556 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v15, off, s[0:3], s33 offset:560 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v16, off, s[0:3], s33 offset:564 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v17, off, s[0:3], s33 offset:568 ; 4-byte Folded Reload
 ; GCN-NEXT:    buffer_load_dword v18, off, s[0:3], s33 offset:572 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_mov_b32_e32 v12, v15
-; GCN-NEXT:    v_mov_b32_e32 v13, v16
-; GCN-NEXT:    v_mov_b32_e32 v14, v17
-; GCN-NEXT:    v_mov_b32_e32 v15, v18
-; GCN-NEXT:    buffer_store_dword v12, off, s[0:3], s33 offset:496
-; GCN-NEXT:    buffer_store_dword v13, off, s[0:3], s33 offset:500
-; GCN-NEXT:    buffer_store_dword v14, off, s[0:3], s33 offset:504
-; GCN-NEXT:    buffer_store_dword v15, off, s[0:3], s33 offset:508
+; GCN-NEXT:    v_mov_b32_e32 v8, v11
+; GCN-NEXT:    v_mov_b32_e32 v9, v12
+; GCN-NEXT:    v_mov_b32_e32 v10, v13
+; GCN-NEXT:    v_mov_b32_e32 v11, v14
+; GCN-NEXT:    buffer_store_dword v8, off, s[0:3], s33 offset:480
+; GCN-NEXT:    buffer_store_dword v9, off, s[0:3], s33 offset:484
+; GCN-NEXT:    buffer_store_dword v10, off, s[0:3], s33 offset:488
+; GCN-NEXT:    buffer_store_dword v11, off, s[0:3], s33 offset:492
+; GCN-NEXT:    buffer_store_dword v56, off, s[0:3], s33 offset:496
+; GCN-NEXT:    buffer_store_dword v57, off, s[0:3], s33 offset:500
+; GCN-NEXT:    buffer_store_dword v58, off, s[0:3], s33 offset:504
+; GCN-NEXT:    buffer_store_dword v59, off, s[0:3], s33 offset:508
 ; GCN-NEXT:    buffer_load_dword v0, v1, s[0:3], 0 offen
 ; GCN-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 offen offset:4
-; GCN-NEXT:    buffer_load_dword v61, off, s[0:3], s33 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v60, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:48 ; 4-byte Folded Reload
-; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:52 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v59, off, s[0:3], s33 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v58, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v57, off, s[0:3], s33 offset:8 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v56, off, s[0:3], s33 offset:12 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v47, off, s[0:3], s33 offset:16 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v46, off, s[0:3], s33 offset:20 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v45, off, s[0:3], s33 offset:24 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v44, off, s[0:3], s33 offset:28 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v43, off, s[0:3], s33 offset:32 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v42, off, s[0:3], s33 offset:36 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v41, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
+; GCN-NEXT:    buffer_load_dword v40, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
 ; GCN-NEXT:    s_mov_b32 s33, s6
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %vec = load <32 x i64>, <32 x i64> addrspace(1)* %ptr
   %elt = extractelement <32 x i64> %vec, i32 %idx
   ret i64 %elt
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v4, v3, v2
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-IEEE-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-IEEE-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v4, v3, v2
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-IEEE-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-IEEE-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v0, v0, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v3, v2, v1
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v0, v1
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v1, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v5, v5
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v5, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-IEEE-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-IEEE-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;

 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
 ; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, s6
 ; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v3, v2, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v5
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v0, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
-; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v5
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v1, v1, 0, 16
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-FLUSH-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-FLUSH-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_rcp_v2f16:

 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v0, v0, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v3, v2, v1
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v0, v1
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v1, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v5, v5
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v5, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-IEEE-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-IEEE-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;

 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
 ; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, s6
 ; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v3, v2, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v5
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v0, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
-; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v5
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v1, v1, 0, 16
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-FLUSH-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-FLUSH-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_rcp_v2f16_arcp:

 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v2, v1
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v0, v0, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v3, v2, v1
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v0, v0, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v1, v0, v1
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v1, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v5, v5
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v5, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, v3
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v5, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v0, v1
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-IEEE-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-IEEE-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;

 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v6, v4, v4
 ; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v3, v6, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
-; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v4, s6
+; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v5, s6
 ; GFX6-FLUSH-NEXT:    v_cvt_f32_f16_e32 v0, v0
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v3, v2, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 0
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v1, v1
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, v5
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, vcc, v4, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, v5, v0, v5
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v6, v3, v3
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v5, v3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v4, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v3, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v6, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v6
-; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v4
+; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, v5
 ; GFX6-FLUSH-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v1, v1, 0, 16
 ; GFX6-FLUSH-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-FLUSH-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-FLUSH-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_rcp_v2f16_ulp25:

 ; GFX6-IEEE-NEXT:    v_cvt_f32_f16_e32 v1, v1
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v1, v1, v0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v2, v4, v3, v2
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, vcc, v0, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v2, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v6, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v5, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v3, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v3, v6, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v5, v6, v3
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v3, v3, v4, v6
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v3, v1, v0
 ; GFX6-IEEE-NEXT:    v_cvt_f16_f32_e32 v0, v0
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v1, v2, 0, 16
 ; GFX6-IEEE-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX6-IEEE-NEXT:    v_lshlrev_b32_e32 v0, 16, v0
 ; GFX6-IEEE-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll

 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-FLUSH-LABEL: v_fdiv_v2f32:
 ; GFX6-FLUSH:       ; %bb.0:
 ; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v5, v5
 ; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v7, v6, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v4, v7, v6
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
-; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v5
+; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-FLUSH-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v5, v6, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-FLUSH-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v6, v5, v2
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX89-IEEE-LABEL: v_fdiv_v2f32:
 ; GFX89-IEEE:       ; %bb.0:
 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v2, v2, v0
 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1

 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
 ; GCN-FLUSH:       ; %bb.0:
 ; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-FLUSH-NEXT:    s_mov_b32 s4, 0x6f800000
 ; GCN-FLUSH-NEXT:    v_mov_b32_e32 v4, 0x2f800000

 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-FLUSH-LABEL: v_rcp_v2f32:
 ; GFX6-FLUSH:       ; %bb.0:
 ; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
 ; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
+; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX89-IEEE-LABEL: v_rcp_v2f32:
 ; GFX89-IEEE:       ; %bb.0:
 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0

 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v3, v5, v3, v3
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v4, v3
 ; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v4, v3
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-IEEE-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v4, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX6-FLUSH-LABEL: v_rcp_v2f32_arcp:
 ; GFX6-FLUSH:       ; %bb.0:
 ; GFX6-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
 ; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v3, v2
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v2, v3, 1.0
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v5, v3, v3
 ; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v4, v3
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v2, v5, v4
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
 ; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v2, v5, v4
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-NEXT:    v_div_scale_f32 v4, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-FLUSH-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v4, v3
+; GFX6-FLUSH-NEXT:    v_rcp_f32_e32 v6, v4
 ; GFX6-FLUSH-NEXT:    v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-FLUSH-NEXT:    v_fma_f32 v4, v5, v4, v4
-; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v4
-; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v3, v5, v2
-; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v4, v5
-; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v3, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, -v4, v6, 1.0
+; GFX6-FLUSH-NEXT:    v_fma_f32 v3, v3, v6, v6
+; GFX6-FLUSH-NEXT:    v_mul_f32_e32 v5, v2, v3
+; GFX6-FLUSH-NEXT:    v_fma_f32 v6, -v4, v5, v2
+; GFX6-FLUSH-NEXT:    v_fma_f32 v5, v6, v3, v5
+; GFX6-FLUSH-NEXT:    v_fma_f32 v2, -v4, v5, v2
 ; GFX6-FLUSH-NEXT:    s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-NEXT:    v_div_fmas_f32 v2, v2, v3, v5
 ; GFX6-FLUSH-NEXT:    v_div_fixup_f32 v1, v2, v1, 1.0
 ; GFX6-FLUSH-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX89-IEEE-LABEL: v_rcp_v2f32_arcp:
 ; GFX89-IEEE:       ; %bb.0:
 ; GFX89-IEEE-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
 ; GFX89-IEEE-NEXT:    v_div_scale_f32 v3, s[4:5], v1, v1, 1.0

 ; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v5, v4
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, vcc, v0, v2, v0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v4, v5, 1.0
 ; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v5, v5
 ; GFX6-IEEE-NEXT:    v_mul_f32_e32 v7, v6, v5
 ; GFX6-IEEE-NEXT:    v_fma_f32 v8, -v4, v7, v6
 ; GFX6-IEEE-NEXT:    v_fma_f32 v7, v8, v5, v7
 ; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-NEXT:    v_div_scale_f32 v6, s[4:5], v3, v3, v1
+; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v8, v6
 ; GFX6-IEEE-NEXT:    v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT:    v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT:    v_rcp_f32_e32 v6, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v0, v4, v2, v0
 ; GFX6-IEEE-NEXT:    v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT:    v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, -v6, v8, 1.0
+; GFX6-IEEE-NEXT:    v_fma_f32 v4, v4, v8, v8
+; GFX6-IEEE-NEXT:    v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-NEXT:    v_fma_f32 v7, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_fma_f32 v5, v7, v4, v5
+; GFX6-IEEE-NEXT:    v_fma_f32 v2, -v6, v5, v2
+; GFX6-IEEE-NEXT:    v_div_fmas_f32 v2, v2, v4, v5
 ; GFX6-IEEE-NEXT:    v_div_fixup_f32 v1, v2, v3, v1
 ; GFX6-IEEE-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
 ; GCN-FLUSH:       ; %bb.0:
 ; GCN-FLUSH-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-FLUSH-NEXT:    s_mov_b32 s4, 0x6f800000
 ; GCN-FLUSH-NEXT:    v_mov_b32_e32 v4, 0x2f800000

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll

; GFX9-NEXT:    s_setpc_b64 s[30:31]
   ret double %fdiv
 }
 
 define <2 x double> @v_fdiv_v2f64(<2 x double> %a, <2 x double> %b) {
 ; GFX6-LABEL: v_fdiv_v2f64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
-; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3]
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1]
 ; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX6-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v9
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v15
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v13
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; GFX6-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
 ; GFX6-NEXT:    v_mul_f64 v[16:17], v[18:19], v[10:11]
 ; GFX6-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19]
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0
 ; GFX6-NEXT:    v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17]
-; GFX6-NEXT:    v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3]
+; GFX6-NEXT:    v_fma_f64 v[8:9], v[14:15], v[8:9], v[14:15]
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], v[2:3], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1]
-; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[8:9]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v13
-; GFX6-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13]
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[14:15], v[8:9]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GFX6-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[16:17], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
 ; GFX6-NEXT:    s_nop 1
 ; GFX6-NEXT:    v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3]
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_fdiv_v2f64:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
 ; GFX8-NEXT:    v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX8-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX8-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX8-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX8-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX8-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX8-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX8-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX8-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_fdiv_v2f64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
 ; GFX9-NEXT:    v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX9-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX9-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX9-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX9-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX9-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX9-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv <2 x double> %a, %b
   ret <2 x double> %fdiv
 }
 
 define <2 x double> @v_fdiv_v2f64_afn(<2 x double> %a, <2 x double> %b) {
; GCN-NEXT:    s_setpc_b64 s[30:31]
   ret <2 x double> %fdiv
 }
 
 define <2 x double> @v_fdiv_v2f64_ulp25(<2 x double> %a, <2 x double> %b) {
 ; GFX6-LABEL: v_fdiv_v2f64_ulp25:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
-; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3]
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1]
 ; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX6-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v9
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v15
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v13
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; GFX6-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
 ; GFX6-NEXT:    v_mul_f64 v[16:17], v[18:19], v[10:11]
 ; GFX6-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19]
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0
 ; GFX6-NEXT:    v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17]
-; GFX6-NEXT:    v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3]
+; GFX6-NEXT:    v_fma_f64 v[8:9], v[14:15], v[8:9], v[14:15]
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], v[2:3], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1]
-; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[8:9]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v13
-; GFX6-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13]
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[14:15], v[8:9]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GFX6-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[16:17], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
 ; GFX6-NEXT:    s_nop 1
 ; GFX6-NEXT:    v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3]
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_fdiv_v2f64_ulp25:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
 ; GFX8-NEXT:    v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX8-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX8-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX8-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX8-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX8-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX8-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX8-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX8-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_fdiv_v2f64_ulp25:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
 ; GFX9-NEXT:    v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX9-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX9-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX9-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX9-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX9-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX9-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv <2 x double> %a, %b, !fpmath !0
   ret <2 x double> %fdiv
 }
 
 define <2 x double> @v_rcp_v2f64(<2 x double> %x) {
 ; GFX6-LABEL: v_rcp_v2f64:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
-; GFX6-NEXT:    v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], 1.0, v[0:1], 1.0
 ; GFX6-NEXT:    v_mov_b32_e32 v18, 0x3ff00000
 ; GFX6-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v11
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
-; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v5
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
-; GFX6-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
-; GFX6-NEXT:    v_mul_f64 v[14:15], v[10:11], v[6:7]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v13
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15]
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v3, v9
-; GFX6-NEXT:    v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v17
-; GFX6-NEXT:    v_mul_f64 v[12:13], v[16:17], v[4:5]
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
+; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[6:7], 1.0
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], 1.0, v[2:3], 1.0
+; GFX6-NEXT:    v_fma_f64 v[4:5], v[10:11], v[4:5], v[10:11]
+; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[12:13], v[6:7], v[16:17]
+; GFX6-NEXT:    v_mul_f64 v[10:11], v[14:15], v[4:5]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v15
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13]
+; GFX6-NEXT:    s_nop 0
+; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[4:5], v[10:11]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_rcp_v2f64:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
 ; GFX8-NEXT:    v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0
; GFX9-NEXT:    s_setpc_b64 s[30:31]
   ret <2 x double> %fdiv
 }
 
 define <2 x double> @v_rcp_v2f64_arcp(<2 x double> %x) {
 ; GFX6-LABEL: v_rcp_v2f64_arcp:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
-; GFX6-NEXT:    v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], 1.0, v[0:1], 1.0
 ; GFX6-NEXT:    v_mov_b32_e32 v18, 0x3ff00000
 ; GFX6-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v11
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
-; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v5
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
-; GFX6-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
-; GFX6-NEXT:    v_mul_f64 v[14:15], v[10:11], v[6:7]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v13
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15]
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v3, v9
-; GFX6-NEXT:    v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v17
-; GFX6-NEXT:    v_mul_f64 v[12:13], v[16:17], v[4:5]
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
+; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[6:7], 1.0
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], 1.0, v[2:3], 1.0
+; GFX6-NEXT:    v_fma_f64 v[4:5], v[10:11], v[4:5], v[10:11]
+; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[12:13], v[6:7], v[16:17]
+; GFX6-NEXT:    v_mul_f64 v[10:11], v[14:15], v[4:5]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v15
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13]
+; GFX6-NEXT:    s_nop 0
+; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[4:5], v[10:11]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_rcp_v2f64_arcp:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
 ; GFX8-NEXT:    v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0
; GCN-NEXT:    s_setpc_b64 s[30:31]
   ret <2 x double> %fdiv
 }
 
 define <2 x double> @v_rcp_v2f64_ulp25(<2 x double> %x) {
 ; GFX6-LABEL: v_rcp_v2f64_ulp25:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
-; GFX6-NEXT:    v_div_scale_f64 v[10:11], s[4:5], 1.0, v[0:1], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], 1.0, v[0:1], 1.0
 ; GFX6-NEXT:    v_mov_b32_e32 v18, 0x3ff00000
 ; GFX6-NEXT:    v_rcp_f64_e32 v[6:7], v[4:5]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v11
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
-; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[2:3], v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v1, v5
-; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[12:13], v[6:7]
-; GFX6-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
-; GFX6-NEXT:    v_mul_f64 v[14:15], v[10:11], v[6:7]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v13
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[14:15], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[10:11], v[6:7], v[14:15]
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[16:17], s[6:7], 1.0, v[2:3], 1.0
-; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], -v[4:5], v[6:7], 1.0
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v3, v9
-; GFX6-NEXT:    v_fma_f64 v[4:5], v[12:13], v[4:5], v[12:13]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v17
-; GFX6-NEXT:    v_mul_f64 v[12:13], v[16:17], v[4:5]
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[10:11], v[6:7]
+; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[4:5], v[6:7], 1.0
+; GFX6-NEXT:    v_fma_f64 v[6:7], v[6:7], v[14:15], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[6:7]
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[16:17], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[4:5], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], 1.0, v[2:3], 1.0
+; GFX6-NEXT:    v_fma_f64 v[4:5], v[10:11], v[4:5], v[10:11]
+; GFX6-NEXT:    v_div_fmas_f64 v[6:7], v[12:13], v[6:7], v[16:17]
+; GFX6-NEXT:    v_mul_f64 v[10:11], v[14:15], v[4:5]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v18, v15
+; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], -v[8:9], v[12:13], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[6:7], v[0:1], 1.0
-; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[10:11], v[4:5], v[12:13]
+; GFX6-NEXT:    s_nop 0
+; GFX6-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[4:5], v[10:11]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[4:5], v[2:3], 1.0
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_rcp_v2f64_ulp25:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_div_scale_f64 v[4:5], s[4:5], v[0:1], v[0:1], 1.0
 ; GFX8-NEXT:    v_div_scale_f64 v[6:7], s[4:5], v[2:3], v[2:3], 1.0
; GCN-NEXT:    s_setpc_b64 s[30:31]
   ret <2 x double> %fdiv
 }
 
 define <2 x double> @v_fdiv_v2f64_arcp_ulp25(<2 x double> %a, <2 x double> %b) {
 ; GFX6-LABEL: v_fdiv_v2f64_arcp_ulp25:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
-; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[4:5], v[6:7], v[6:7], v[2:3]
+; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[0:1], v[4:5], v[0:1]
 ; GFX6-NEXT:    v_rcp_f64_e32 v[10:11], v[8:9]
-; GFX6-NEXT:    v_rcp_f64_e32 v[16:17], v[14:15]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v9
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v19
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v15
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
-; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
-; GFX6-NEXT:    v_fma_f64 v[12:13], -v[14:15], v[16:17], 1.0
-; GFX6-NEXT:    v_fma_f64 v[12:13], v[16:17], v[12:13], v[16:17]
+; GFX6-NEXT:    v_fma_f64 v[14:15], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v13
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[14:15], v[10:11]
+; GFX6-NEXT:    v_rcp_f64_e32 v[14:15], v[12:13]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[10:11], 1.0
+; GFX6-NEXT:    v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
+; GFX6-NEXT:    v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
+; GFX6-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
 ; GFX6-NEXT:    v_mul_f64 v[16:17], v[18:19], v[10:11]
 ; GFX6-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[16:17], v[18:19]
-; GFX6-NEXT:    v_fma_f64 v[8:9], -v[14:15], v[12:13], 1.0
+; GFX6-NEXT:    v_fma_f64 v[8:9], -v[12:13], v[14:15], 1.0
 ; GFX6-NEXT:    v_div_fmas_f64 v[10:11], v[18:19], v[10:11], v[16:17]
-; GFX6-NEXT:    v_fma_f64 v[8:9], v[12:13], v[8:9], v[12:13]
-; GFX6-NEXT:    v_div_scale_f64 v[12:13], s[6:7], v[2:3], v[6:7], v[2:3]
+; GFX6-NEXT:    v_fma_f64 v[8:9], v[14:15], v[8:9], v[14:15]
+; GFX6-NEXT:    v_div_scale_f64 v[14:15], s[6:7], v[2:3], v[6:7], v[2:3]
 ; GFX6-NEXT:    v_div_fixup_f64 v[0:1], v[10:11], v[4:5], v[0:1]
-; GFX6-NEXT:    v_mul_f64 v[16:17], v[12:13], v[8:9]
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v13
-; GFX6-NEXT:    v_fma_f64 v[18:19], -v[14:15], v[16:17], v[12:13]
+; GFX6-NEXT:    v_mul_f64 v[16:17], v[14:15], v[8:9]
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GFX6-NEXT:    v_fma_f64 v[18:19], -v[12:13], v[16:17], v[14:15]
 ; GFX6-NEXT:    s_xor_b64 vcc, vcc, s[4:5]
 ; GFX6-NEXT:    s_nop 1
 ; GFX6-NEXT:    v_div_fmas_f64 v[8:9], v[18:19], v[8:9], v[16:17]
 ; GFX6-NEXT:    v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3]
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_fdiv_v2f64_arcp_ulp25:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
 ; GFX8-NEXT:    v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX8-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX8-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX8-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX8-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX8-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX8-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX8-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX8-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX8-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX8-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX8-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX8-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX8-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX8-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX8-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX8-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX8-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_fdiv_v2f64_arcp_ulp25:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_div_scale_f64 v[8:9], s[4:5], v[4:5], v[4:5], v[0:1]
 ; GFX9-NEXT:    v_div_scale_f64 v[10:11], s[4:5], v[6:7], v[6:7], v[2:3]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[12:13], v[8:9]
 ; GFX9-NEXT:    v_rcp_f64_e32 v[14:15], v[10:11]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
-; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
-; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], vcc, v[0:1], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
 ; GFX9-NEXT:    v_fma_f64 v[16:17], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[8:9], v[12:13], 1.0
 ; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
-; GFX9-NEXT:    v_mul_f64 v[16:17], v[18:19], v[12:13]
-; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[16:17], v[18:19]
-; GFX9-NEXT:    v_div_scale_f64 v[18:19], s[4:5], v[2:3], v[6:7], v[2:3]
-; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], vcc, v[0:1], v[4:5], v[0:1]
+; GFX9-NEXT:    v_fma_f64 v[12:13], v[12:13], v[18:19], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
+; GFX9-NEXT:    v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
+; GFX9-NEXT:    v_mul_f64 v[18:19], v[16:17], v[12:13]
+; GFX9-NEXT:    v_fma_f64 v[8:9], -v[8:9], v[18:19], v[16:17]
+; GFX9-NEXT:    v_div_scale_f64 v[16:17], s[4:5], v[2:3], v[6:7], v[2:3]
+; GFX9-NEXT:    v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
+; GFX9-NEXT:    v_mul_f64 v[20:21], v[16:17], v[14:15]
 ; GFX9-NEXT:    s_mov_b64 vcc, s[4:5]
-; GFX9-NEXT:    v_mul_f64 v[20:21], v[18:19], v[14:15]
 ; GFX9-NEXT:    v_div_fixup_f64 v[0:1], v[8:9], v[4:5], v[0:1]
-; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[18:19]
+; GFX9-NEXT:    v_fma_f64 v[10:11], -v[10:11], v[20:21], v[16:17]
 ; GFX9-NEXT:    v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
 ; GFX9-NEXT:    v_div_fixup_f64 v[2:3], v[10:11], v[6:7], v[2:3]
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   %fdiv = fdiv arcp <2 x double> %a, %b, !fpmath !0
   ret <2 x double> %fdiv
 }
 
 define <2 x double> @v_fdiv_v2f64_arcp_afn_ulp25(<2 x double> %a, <2 x double> %b) {

llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

 
 define <2 x i24> @v_fshl_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
 ; GFX6-LABEL: v_fshl_v2i24:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX6-NEXT:    s_sub_i32 s4, 0, 24
-; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX6-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX6-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v7, v6, v7
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX6-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 23, v4
-; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 23, v4
+; GFX6-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v4, v0
-; GFX6-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX6-NEXT:    v_and_b32_e32 v4, v5, v8
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v6
-; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT:    v_and_b32_e32 v6, v9, v8
+; GFX6-NEXT:    v_mul_lo_u32 v4, v7, 24
+; GFX6-NEXT:    v_and_b32_e32 v6, v6, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, v5, 24
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v4, v5
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v5, v4
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
-; GFX6-NEXT:    v_and_b32_e32 v2, v3, v8
+; GFX6-NEXT:    v_and_b32_e32 v2, v3, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
-; GFX6-NEXT:    v_and_b32_e32 v3, v4, v8
+; GFX6-NEXT:    v_and_b32_e32 v3, v4, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v3, v2
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_fshl_v2i24:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX8-NEXT:    s_sub_i32 s4, 0, 24
-; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX8-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX8-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
 ; GFX8-NEXT:    v_mul_hi_u32 v7, v6, v7
 ; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v7
 ; GFX8-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX8-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX8-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
+; GFX8-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX8-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX8-NEXT:    v_sub_u32_e32 v9, vcc, 23, v4
-; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
+; GFX8-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 23, v4
+; GFX8-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v4, v0
-; GFX8-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX8-NEXT:    v_and_b32_e32 v4, v5, v8
-; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v7, v6
-; GFX8-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX8-NEXT:    v_and_b32_e32 v6, v9, v8
+; GFX8-NEXT:    v_mul_lo_u32 v4, v7, 24
+; GFX8-NEXT:    v_and_b32_e32 v6, v6, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v6, v2
 ; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT:    v_mul_lo_u32 v5, v5, 24
-; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v4, v5
+; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v5, v4
 ; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v1, v2, v1
-; GFX8-NEXT:    v_and_b32_e32 v2, v3, v8
+; GFX8-NEXT:    v_and_b32_e32 v2, v3, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 1, v2
-; GFX8-NEXT:    v_and_b32_e32 v3, v4, v8
+; GFX8-NEXT:    v_and_b32_e32 v3, v4, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v3, v2
 ; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_fshl_v2i24:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24

llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

 ; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
 ; GFX6-NEXT:    s_bfe_u32 s4, s4, 0x100000
 ; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
 ; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
 ; GFX6-NEXT:    s_or_b32 s4, s4, s8
 ; GFX6-NEXT:    s_lshr_b32 s12, s5, 8
 ; GFX6-NEXT:    s_and_b32 s5, s5, s10
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX6-NEXT:    s_lshl_b32 s5, s5, 8
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
 ; GFX6-NEXT:    s_and_b32 s8, s12, s10
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, 24
+; GFX6-NEXT:    s_or_b32 s5, s11, s5
+; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
+; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v1
-; GFX6-NEXT:    s_or_b32 s5, s11, s5
-; GFX6-NEXT:    s_bfe_u32 s8, s8, 0x100000
 ; GFX6-NEXT:    s_bfe_u32 s5, s5, 0x100000
-; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GFX6-NEXT:    s_lshl_b32 s8, s8, 16
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-NEXT:    s_or_b32 s5, s5, s8
-; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX6-NEXT:    s_bfe_u32 s6, s6, 0x100000
 ; GFX6-NEXT:    s_mov_b32 s8, 0xffffff
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 23, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, 24
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v0
 ; GFX6-NEXT:    s_lshl_b32 s4, s6, 17
 ; GFX6-NEXT:    s_lshl_b32 s0, s0, 1
 ; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX6-NEXT:    s_or_b32 s0, s4, s0
-; GFX6-NEXT:    v_and_b32_e32 v2, s8, v3
+; GFX6-NEXT:    v_and_b32_e32 v2, s8, v2
 ; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
 ; GFX6-NEXT:    v_lshr_b32_e32 v0, s2, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
 ; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX6-NEXT:    s_bfe_u32 s1, s1, 0x100000
 ; GFX6-NEXT:    s_bfe_u32 s7, s7, 0x100000
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0xffffff
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0xffffff
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 23, v1
 ; GFX6-NEXT:    s_lshl_b32 s0, s7, 17
 ; GFX6-NEXT:    s_lshl_b32 s1, s1, 1
-; GFX6-NEXT:    v_and_b32_e32 v1, v1, v4
+; GFX6-NEXT:    v_and_b32_e32 v1, v1, v3
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    s_or_b32 s0, s0, s1
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v4
 ; GFX6-NEXT:    v_lshl_b32_e32 v2, s0, v2
 ; GFX6-NEXT:    v_lshr_b32_e32 v1, s3, v1
 ; GFX6-NEXT:    v_or_b32_e32 v1, v2, v1
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
 ; GFX6-NEXT:    v_and_b32_e32 v2, s10, v2
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; GFX6-NEXT:    v_and_b32_e32 v0, s10, v0
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 8, v2

 ; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
 ; GFX8-NEXT:    s_bfe_u32 s4, s4, 0x100000
 ; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
 ; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1
 ; GFX8-NEXT:    s_or_b32 s4, s4, s8
 ; GFX8-NEXT:    s_lshr_b32 s13, s5, 8
 ; GFX8-NEXT:    s_and_b32 s5, s5, s10
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
-; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v1, 24
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX8-NEXT:    s_lshl_b32 s5, s5, s11
-; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
 ; GFX8-NEXT:    s_and_b32 s8, s13, s10
 ; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX8-NEXT:    v_mul_lo_u32 v0, v0, 24
+; GFX8-NEXT:    s_or_b32 s5, s12, s5
+; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
+; GFX8-NEXT:    v_mul_lo_u32 v3, s9, v1
 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s4, v0
 ; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
+; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v0
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v0
-; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX8-NEXT:    v_mul_lo_u32 v2, s9, v1
-; GFX8-NEXT:    s_or_b32 s5, s12, s5
-; GFX8-NEXT:    s_bfe_u32 s8, s8, 0x100000
 ; GFX8-NEXT:    s_bfe_u32 s5, s5, 0x100000
-; GFX8-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GFX8-NEXT:    s_lshl_b32 s8, s8, 16
+; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX8-NEXT:    s_or_b32 s5, s5, s8
-; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX8-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX8-NEXT:    s_bfe_u32 s6, s6, 0x100000
 ; GFX8-NEXT:    s_mov_b32 s8, 0xffffff
-; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, 23, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v1, v1, 24
+; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v0
 ; GFX8-NEXT:    s_lshl_b32 s4, s6, 17
 ; GFX8-NEXT:    s_lshl_b32 s0, s0, 1
 ; GFX8-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX8-NEXT:    s_or_b32 s0, s4, s0
-; GFX8-NEXT:    v_and_b32_e32 v2, s8, v3
+; GFX8-NEXT:    v_and_b32_e32 v2, s8, v2
 ; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
 ; GFX8-NEXT:    v_lshrrev_b32_e64 v0, v0, s2
 ; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s5, v1
 ; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
 ; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, 24, v1
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v1
 ; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX8-NEXT:    s_bfe_u32 s1, s1, 0x100000
 ; GFX8-NEXT:    s_bfe_u32 s7, s7, 0x100000
-; GFX8-NEXT:    v_mov_b32_e32 v4, 0xffffff
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0xffffff
 ; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, 23, v1
 ; GFX8-NEXT:    s_lshl_b32 s0, s7, 17
 ; GFX8-NEXT:    s_lshl_b32 s1, s1, 1
-; GFX8-NEXT:    v_and_b32_e32 v1, v1, v4
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v4
+; GFX8-NEXT:    v_and_b32_e32 v1, v1, v3
 ; GFX8-NEXT:    s_or_b32 s0, s0, s1
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v3
 ; GFX8-NEXT:    v_lshlrev_b32_e64 v2, v2, s0
 ; GFX8-NEXT:    v_lshrrev_b32_e64 v1, v1, s3
 ; GFX8-NEXT:    v_or_b32_e32 v1, v2, v1
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 8, v0
 ; GFX8-NEXT:    v_mov_b32_e32 v4, 8
 ; GFX8-NEXT:    v_lshlrev_b32_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX8-NEXT:    v_mov_b32_e32 v4, s10
 ; GFX8-NEXT:    v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD

 
 define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
 ; GFX6-LABEL: v_fshr_v2i24:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX6-NEXT:    s_sub_i32 s4, 0, 24
-; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX6-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX6-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX6-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX6-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX6-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX6-NEXT:    v_mul_hi_u32 v7, v6, v7
+; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX6-NEXT:    v_and_b32_e32 v3, v3, v9
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX6-NEXT:    v_and_b32_e32 v5, v5, v8
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX6-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, 24, v4
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX6-NEXT:    v_sub_i32_e32 v9, vcc, 23, v4
-; GFX6-NEXT:    v_and_b32_e32 v9, v9, v8
-; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
-; GFX6-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v9, v0
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, 23, v4
+; GFX6-NEXT:    v_and_b32_e32 v6, v6, v9
+; GFX6-NEXT:    v_lshlrev_b32_e32 v0, v6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v6, v7, 24
+; GFX6-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GFX6-NEXT:    v_mul_hi_u32 v6, v5, v6
-; GFX6-NEXT:    v_and_b32_e32 v3, v3, v8
-; GFX6-NEXT:    v_mul_lo_u32 v6, v6, 24
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, v5, v6
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, 24, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 23, v2
-; GFX6-NEXT:    v_and_b32_e32 v2, v2, v8
-; GFX6-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX6-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX6-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
 ; GFX6-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_fshr_v2i24:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v6, 24
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GFX8-NEXT:    s_sub_i32 s4, 0, 24
-; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
 ; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v8, 24
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v8, v8
 ; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
-; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT:    v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT:    v_mul_f32_e32 v8, 0x4f7ffffe, v8
+; GFX8-NEXT:    v_mov_b32_e32 v9, 0xffffff
 ; GFX8-NEXT:    v_mul_lo_u32 v7, s4, v6
+; GFX8-NEXT:    v_and_b32_e32 v5, v5, v9
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
 ; GFX8-NEXT:    v_mul_hi_u32 v7, v6, v7
+; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT:    v_and_b32_e32 v3, v3, v9
 ; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v7
 ; GFX8-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v7, v8
-; GFX8-NEXT:    v_mov_b32_e32 v8, 0xffffff
-; GFX8-NEXT:    v_and_b32_e32 v5, v5, v8
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v8
 ; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
-; GFX8-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v7
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
+; GFX8-NEXT:    v_mul_lo_u32 v8, s4, v7
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, v4, v6
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
+; GFX8-NEXT:    v_mul_hi_u32 v8, v7, v8
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, 24, v4
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v4
 ; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
-; GFX8-NEXT:    v_mul_lo_u32 v6, s4, v7
-; GFX8-NEXT:    v_sub_u32_e32 v9, vcc, 23, v4
-; GFX8-NEXT:    v_and_b32_e32 v9, v9, v8
-; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
-; GFX8-NEXT:    v_mul_hi_u32 v6, v7, v6
-; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v9, v0
+; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v8
+; GFX8-NEXT:    v_mul_hi_u32 v7, v5, v7
+; GFX8-NEXT:    v_sub_u32_e32 v6, vcc, 23, v4
+; GFX8-NEXT:    v_and_b32_e32 v6, v6, v9
+; GFX8-NEXT:    v_lshlrev_b32_e32 v0, v6, v0
+; GFX8-NEXT:    v_mul_lo_u32 v6, v7, 24
+; GFX8-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v4, v2
 ; GFX8-NEXT:    v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v6
-; GFX8-NEXT:    v_mul_hi_u32 v6, v5, v6
-; GFX8-NEXT:    v_and_b32_e32 v3, v3, v8
-; GFX8-NEXT:    v_mul_lo_u32 v6, v6, 24
 ; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v5, v6
 ; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, 24, v2
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, 24, v2
 ; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT:    v_and_b32_e32 v2, v2, v8
-; GFX8-NEXT:    v_and_b32_e32 v4, v4, v8
+; GFX8-NEXT:    v_and_b32_e32 v2, v2, v9
+; GFX8-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v1, v4, v1
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v2, v2, v3
 ; GFX8-NEXT:    v_or_b32_e32 v1, v1, v2
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_fshr_v2i24:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll

; GFX9-NEXT:    s_endpgm
   %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @global_atomic_dec_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
 ; CI-LABEL: global_atomic_dec_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: global_atomic_dec_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ; GFX9-LABEL: global_atomic_dec_ret_i32_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT:    s_endpgm
   %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
 ; CI-LABEL: flat_atomic_dec_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: flat_atomic_dec_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_dec v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ; GFX9-LABEL: flat_atomic_dec_ret_i32_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
 ; CI-LABEL: flat_atomic_dec_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; CI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: flat_atomic_dec_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; VI-NEXT:    s_endpgm
 ; GFX9-LABEL: flat_atomic_dec_ret_i64_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
; GFX9-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
 ; CI-LABEL: global_atomic_dec_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: global_atomic_dec_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_dec_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; VI-NEXT:    s_endpgm
 ; GFX9-LABEL: global_atomic_dec_ret_i64_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v1, 31, v0

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

; GFX9-NEXT:    s_endpgm
   %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 {
 ; CI-LABEL: global_atomic_inc_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: global_atomic_inc_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: global_atomic_inc_ret_i32_offset_addr64:
 ; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 {
 ; CI-LABEL: global_atomic_inc_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0)
 ; CI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: global_atomic_inc_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: global_atomic_inc_ret_i64_offset_addr64:
 ; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_endpgm
   %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
 ; CI-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 20, v5
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
 ; CI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; CI-NEXT:    flat_store_dword v[0:1], v2
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 20, v5
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
 ; VI-NEXT:    flat_atomic_inc v2, v[2:3], v4 glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; VI-NEXT:    flat_store_dword v[0:1], v2
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 2, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 42
 ; GFX9-NEXT:    flat_atomic_inc v0, v[0:1], v4 offset:20 glc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    flat_store_dword v[2:3], v0
 ; GFX9-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
; GFX9-NEXT:    s_endpgm
   %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
   ret void
 }
 
 define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
 ; CI-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
 ; CI:       ; %bb.0:
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; CI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; CI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v0, s2
+; CI-NEXT:    v_mov_b32_e32 v3, s1
 ; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    v_add_i32_e32 v3, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; CI-NEXT:    v_mov_b32_e32 v0, s0
-; CI-NEXT:    v_mov_b32_e32 v1, s1
-; CI-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v3
-; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; CI-NEXT:    v_add_i32_e32 v5, vcc, v0, v4
+; CI-NEXT:    v_mov_b32_e32 v2, s0
+; CI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; CI-NEXT:    v_add_i32_e32 v0, vcc, v2, v4
+; CI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; CI-NEXT:    v_add_i32_e32 v2, vcc, 40, v5
 ; CI-NEXT:    v_mov_b32_e32 v4, 42
+; CI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; CI-NEXT:    v_mov_b32_e32 v5, 0
 ; CI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; CI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; CI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; CI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; VI-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
 ; VI-NEXT:    v_mov_b32_e32 v0, s2
+; VI-NEXT:    v_mov_b32_e32 v3, s1
 ; VI-NEXT:    v_mov_b32_e32 v1, s3
-; VI-NEXT:    v_add_u32_e32 v3, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; VI-NEXT:    v_mov_b32_e32 v0, s0
-; VI-NEXT:    v_mov_b32_e32 v1, s1
-; VI-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v3
-; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
+; VI-NEXT:    v_add_u32_e32 v5, vcc, v0, v4
+; VI-NEXT:    v_mov_b32_e32 v2, s0
+; VI-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
+; VI-NEXT:    v_add_u32_e32 v0, vcc, v2, v4
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    v_add_u32_e32 v2, vcc, 40, v5
 ; VI-NEXT:    v_mov_b32_e32 v4, 42
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v6, vcc
 ; VI-NEXT:    v_mov_b32_e32 v5, 0
 ; VI-NEXT:    flat_atomic_inc_x2 v[2:3], v[2:3], v[4:5] glc
 ; VI-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; VI-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: flat_atomic_inc_ret_i64_offset_addr64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s0
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 42
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[4:5] offset:40 glc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; GFX9-NEXT:    s_endpgm

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    s_nop 0
 ; GFX7-NEXT:    v_div_fmas_f32 v0, v1, v2, v3
 ; GFX7-NEXT:    buffer_store_dword v0, off, s[4:7], 0 offset:8
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: test_div_fmas_f32_i1_phi_vcc:
 ; GFX8:       ; %bb.0: ; %entry
-; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX8-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x4c
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v3, 2, v0
-; GFX8-NEXT:    s_mov_b32 s2, 0
+; GFX8-NEXT:    s_mov_b32 s4, 0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s7
 ; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
 ; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX8-NEXT:    flat_load_dwordx3 v[1:3], v[1:2]
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    s_and_saveexec_b64 s[6:7], vcc
 ; GFX8-NEXT:    s_cbranch_execz BB13_2
 ; GFX8-NEXT:  ; %bb.1: ; %bb
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x74
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_load_dword s0, s[0:1], 0x0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_cmp_lg_u32 s0, 0
-; GFX8-NEXT:    s_cselect_b32 s2, 1, 0
+; GFX8-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX8-NEXT:  BB13_2: ; %exit
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[6:7]
-; GFX8-NEXT:    s_add_u32 s0, s4, 8
-; GFX8-NEXT:    s_addc_u32 s1, s5, 0
-; GFX8-NEXT:    s_and_b32 s2, 1, s2
+; GFX8-NEXT:    s_add_u32 s0, s2, 8
+; GFX8-NEXT:    s_addc_u32 s1, s3, 0
+; GFX8-NEXT:    s_and_b32 s2, 1, s4
 ; GFX8-NEXT:    v_cmp_ne_u32_e64 vcc, 0, s2
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_nop 2
 ; GFX8-NEXT:    v_div_fmas_f32 v2, v1, v2, v3
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
 ; GFX8-NEXT:    flat_store_dword v[0:1], v2
 ; GFX8-NEXT:    s_endpgm

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

; GFX9-NEXT:    ; return to shader part epilog
   %result = mul i64 %num, %den
   ret i64 %result
 }
 
 define i64 @v_mul_i64(i64 %num, i64 %den) {
 ; GFX7-LABEL: v_mul_i64:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX7-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; GFX7-NEXT:    v_mul_lo_u32 v1, v1, v2
-; GFX7-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX7-NEXT:    v_mul_hi_u32 v0, v0, v2
+; GFX7-NEXT:    v_mul_lo_u32 v3, v0, v3
+; GFX7-NEXT:    v_mul_hi_u32 v4, v0, v2
+; GFX7-NEXT:    v_mul_lo_u32 v0, v0, v2
+; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
-; GFX7-NEXT:    v_add_i32_e32 v1, vcc, v1, v0
-; GFX7-NEXT:    v_mov_b32_e32 v0, v3
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX8-LABEL: v_mul_i64:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; GFX8-NEXT:    v_mul_lo_u32 v1, v1, v2
-; GFX8-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX8-NEXT:    v_mul_hi_u32 v0, v0, v2
+; GFX8-NEXT:    v_mul_lo_u32 v3, v0, v3
+; GFX8-NEXT:    v_mul_hi_u32 v4, v0, v2
+; GFX8-NEXT:    v_mul_lo_u32 v0, v0, v2
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3
 ; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v4
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v0
-; GFX8-NEXT:    v_mov_b32_e32 v0, v3
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_mul_i64:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v2

 ; GFX7-NEXT:    v_add_i32_e32 v17, vcc, v17, v18
 ; GFX7-NEXT:    v_mul_lo_u32 v18, v0, v10
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
 ; GFX7-NEXT:    v_mul_hi_u32 v21, v1, v8
 ; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
 ; GFX7-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
+; GFX7-NEXT:    v_mul_hi_u32 v20, v0, v9
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v21
-; GFX7-NEXT:    v_mul_hi_u32 v21, v0, v9
-; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
-; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v11
-; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v21
+; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v21
+; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v18, v20
 ; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v20
 ; GFX7-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
 ; GFX7-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
 ; GFX7-NEXT:    v_mul_lo_u32 v20, v3, v8
 ; GFX7-NEXT:    v_mul_lo_u32 v21, v2, v9
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
 ; GFX7-NEXT:    v_mul_lo_u32 v19, v1, v10
-; GFX7-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v11
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
 ; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
+; GFX7-NEXT:    v_mul_hi_u32 v21, v2, v8
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
-; GFX7-NEXT:    v_mul_hi_u32 v22, v2, v8
-; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
-; GFX7-NEXT:    v_mul_lo_u32 v7, v7, v8
-; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_mul_hi_u32 v22, v1, v9
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
-; GFX7-NEXT:    v_mul_lo_u32 v15, v0, v15
-; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
-; GFX7-NEXT:    v_mul_hi_u32 v22, v0, v10
-; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
+; GFX7-NEXT:    v_mul_hi_u32 v21, v0, v10
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v22
+; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
+; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v19, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v21
 ; GFX7-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
 ; GFX7-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
 ; GFX7-NEXT:    v_mul_lo_u32 v21, v4, v8
 ; GFX7-NEXT:    v_mul_lo_u32 v22, v3, v9
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
 ; GFX7-NEXT:    v_mul_lo_u32 v20, v2, v10
+; GFX7-NEXT:    v_mul_lo_u32 v23, v1, v11
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
 ; GFX7-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
+; GFX7-NEXT:    v_mul_lo_u32 v22, v0, v12
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
-; GFX7-NEXT:    v_mul_lo_u32 v23, v0, v12
-; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
 ; GFX7-NEXT:    v_mul_hi_u32 v23, v3, v8
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_mul_hi_u32 v22, v2, v9
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
-; GFX7-NEXT:    v_mul_hi_u32 v23, v2, v9
-; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
 ; GFX7-NEXT:    v_mul_hi_u32 v23, v1, v10
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
+; GFX7-NEXT:    v_mul_hi_u32 v22, v0, v11
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
-; GFX7-NEXT:    v_mul_hi_u32 v23, v0, v11
-; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
-; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v23
+; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
+; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v20, v22
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v22
 ; GFX7-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
 ; GFX7-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX7-NEXT:    v_mul_lo_u32 v22, v5, v8
 ; GFX7-NEXT:    v_mul_lo_u32 v23, v4, v9
 ; GFX7-NEXT:    v_add_i32_e32 v20, vcc, v21, v20
 ; GFX7-NEXT:    v_mul_lo_u32 v21, v3, v10
+; GFX7-NEXT:    v_mul_lo_u32 v7, v7, v8
 ; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
 ; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v22, v21
 ; GFX7-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v23, v22
 ; GFX7-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX7-NEXT:    v_mul_lo_u32 v15, v0, v15
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
 ; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
 ; GFX7-NEXT:    v_mul_lo_u32 v23, v1, v12
 ; GFX7-NEXT:    v_add_i32_e32 v21, vcc, v21, v23
 ; GFX7-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX7-NEXT:    v_add_i32_e32 v22, vcc, v22, v23
 ; GFX7-NEXT:    v_mul_lo_u32 v23, v0, v13

 ; GFX8-NEXT:    v_add_u32_e32 v17, vcc, v17, v18
 ; GFX8-NEXT:    v_mul_lo_u32 v18, v0, v10
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
 ; GFX8-NEXT:    v_mul_hi_u32 v21, v1, v8
 ; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
 ; GFX8-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
+; GFX8-NEXT:    v_mul_hi_u32 v20, v0, v9
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v21
-; GFX8-NEXT:    v_mul_hi_u32 v21, v0, v9
-; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
-; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v11
-; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v21
+; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v21
+; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v18, v20
 ; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v20
 ; GFX8-NEXT:    v_add_u32_e32 v17, vcc, v18, v17
 ; GFX8-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
 ; GFX8-NEXT:    v_mul_lo_u32 v20, v3, v8
 ; GFX8-NEXT:    v_mul_lo_u32 v21, v2, v9
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
 ; GFX8-NEXT:    v_mul_lo_u32 v19, v1, v10
-; GFX8-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v11
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
 ; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
+; GFX8-NEXT:    v_mul_hi_u32 v21, v2, v8
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
-; GFX8-NEXT:    v_mul_hi_u32 v22, v2, v8
-; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
-; GFX8-NEXT:    v_mul_lo_u32 v7, v7, v8
-; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_mul_hi_u32 v22, v1, v9
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
-; GFX8-NEXT:    v_mul_lo_u32 v15, v0, v15
-; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
-; GFX8-NEXT:    v_mul_hi_u32 v22, v0, v10
-; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
+; GFX8-NEXT:    v_mul_hi_u32 v21, v0, v10
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v22
+; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
+; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v19, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v21
 ; GFX8-NEXT:    v_add_u32_e32 v18, vcc, v19, v18
 ; GFX8-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
 ; GFX8-NEXT:    v_mul_lo_u32 v21, v4, v8
 ; GFX8-NEXT:    v_mul_lo_u32 v22, v3, v9
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
 ; GFX8-NEXT:    v_mul_lo_u32 v20, v2, v10
+; GFX8-NEXT:    v_mul_lo_u32 v23, v1, v11
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
 ; GFX8-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
+; GFX8-NEXT:    v_mul_lo_u32 v22, v0, v12
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
-; GFX8-NEXT:    v_mul_lo_u32 v23, v0, v12
-; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
 ; GFX8-NEXT:    v_mul_hi_u32 v23, v3, v8
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_mul_hi_u32 v22, v2, v9
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
-; GFX8-NEXT:    v_mul_hi_u32 v23, v2, v9
-; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
 ; GFX8-NEXT:    v_mul_hi_u32 v23, v1, v10
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
+; GFX8-NEXT:    v_mul_hi_u32 v22, v0, v11
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
-; GFX8-NEXT:    v_mul_hi_u32 v23, v0, v11
-; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
-; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v23
+; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
+; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v20, v22
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v22
 ; GFX8-NEXT:    v_add_u32_e32 v19, vcc, v20, v19
 ; GFX8-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX8-NEXT:    v_mul_lo_u32 v22, v5, v8
 ; GFX8-NEXT:    v_mul_lo_u32 v23, v4, v9
 ; GFX8-NEXT:    v_add_u32_e32 v20, vcc, v21, v20
 ; GFX8-NEXT:    v_mul_lo_u32 v21, v3, v10
+; GFX8-NEXT:    v_mul_lo_u32 v7, v7, v8
 ; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
 ; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v22, v21
 ; GFX8-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v23, v22
 ; GFX8-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX8-NEXT:    v_mul_lo_u32 v15, v0, v15
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
 ; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
 ; GFX8-NEXT:    v_mul_lo_u32 v23, v1, v12
 ; GFX8-NEXT:    v_add_u32_e32 v21, vcc, v21, v23
 ; GFX8-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v22, vcc, v22, v23
 ; GFX8-NEXT:    v_mul_lo_u32 v23, v0, v13

 ; GFX9-NEXT:    v_add_co_u32_e32 v17, vcc, v19, v17
 ; GFX9-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
 ; GFX9-NEXT:    v_add3_u32 v18, v18, v20, v19
 ; GFX9-NEXT:    v_mul_lo_u32 v19, v1, v10
 ; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v21, v22
 ; GFX9-NEXT:    v_mul_lo_u32 v22, v0, v11
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v20, v19
+; GFX9-NEXT:    v_mul_hi_u32 v23, v2, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v22
-; GFX9-NEXT:    v_mul_hi_u32 v23, v2, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX9-NEXT:    v_add3_u32 v20, v21, v20, v22
 ; GFX9-NEXT:    v_mul_hi_u32 v21, v1, v9
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v23
 ; GFX9-NEXT:    v_mul_hi_u32 v23, v0, v10
 ; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v21
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX9-NEXT:    v_add3_u32 v20, v20, v22, v21
 ; GFX9-NEXT:    v_add_co_u32_e32 v19, vcc, v19, v23
-; GFX9-NEXT:    v_mul_lo_u32 v22, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v23, v3, v9
+; GFX9-NEXT:    v_add3_u32 v20, v20, v22, v21
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v18, vcc, v19, v18
 ; GFX9-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v22, v4, v8
+; GFX9-NEXT:    v_mul_lo_u32 v23, v3, v9
 ; GFX9-NEXT:    v_add3_u32 v19, v20, v21, v19
 ; GFX9-NEXT:    v_mul_lo_u32 v20, v2, v10
-; GFX9-NEXT:    v_add_co_u32_e32 v21, vcc, v22, v23
-; GFX9-NEXT:    v_mul_lo_u32 v23, v1, v11
+; GFX9-NEXT:    v_mul_lo_u32 v21, v1, v11
+; GFX9-NEXT:    v_add_co_u32_e32 v22, vcc, v22, v23
+; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v22, v20
 ; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v21, v20
+; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v21
 ; GFX9-NEXT:    v_cndmask_b32_e64 v21, 0, 1, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v23
-; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
-; GFX9-NEXT:    v_add3_u32 v21, v22, v21, v23
+; GFX9-NEXT:    v_add3_u32 v21, v23, v22, v21
 ; GFX9-NEXT:    v_mul_lo_u32 v22, v0, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v23, v3, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v22
 ; GFX9-NEXT:    v_cndmask_b32_e64 v22, 0, 1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v20, vcc, v20, v23
 ; GFX9-NEXT:    v_cndmask_b32_e64 v23, 0, 1, vcc
 ; GFX9-NEXT:    v_add3_u32 v21, v21, v22, v23

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_add_co_u32_e64 v10, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v11
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s5, v6, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps i64 @s_saddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {

 ; GFX10-LABEL: saddsat_i64_sv:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[0:1]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s1, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 

 ; GFX10-LABEL: saddsat_i64_vs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[0:1], 0
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 

 ; GFX10-NEXT:    v_mov_b32_e32 v15, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v17, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v18, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s4, 0, v[4:5]
 ; GFX10-NEXT:    v_add_co_u32_e64 v8, vcc_lo, v14, v4
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s6, 0, v[6:7]
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
 ; GFX10-NEXT:    v_add_co_u32_e64 v19, vcc_lo, v17, v6
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
 ; GFX10-NEXT:    v_add_co_u32_e64 v1, s5, v12, 0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
+; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_u32_e64 v2, s7, v0, 0
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)

 ;
 ; GFX10-LABEL: saddsat_i128_sv:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_add_co_u32_e64 v4, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s1, 64, s0
-; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s0, v[4:5]
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
+; GFX10-NEXT:    s_sub_i32 s0, 64, s1
+; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s1, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s1, v[6:7]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[6:7]
+; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s0, v[6:7]
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_or_b32_e32 v8, v15, v8
-; GFX10-NEXT:    v_or_b32_e32 v9, v16, v9
-; GFX10-NEXT:    v_ashrrev_i32_e32 v15, 31, v7
+; GFX10-NEXT:    v_or_b32_e32 v0, v15, v8
+; GFX10-NEXT:    v_or_b32_e32 v1, v16, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s1, v[6:7]
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s0, v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc_lo
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[6:7]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v15, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v9, s0
+; GFX10-NEXT:    v_xor_b32_e32 v8, v11, v10
+; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v7
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s0
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo
+; GFX10-NEXT:    v_add_co_u32_e64 v2, s0, v2, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v2, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v9, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v9, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x float> @saddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: saddsat_i128_vs:

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: saddsat_i128_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_mov_b32_e32 v5, v0
-; GFX10-NEXT:    v_mov_b32_e32 v6, v1
-; GFX10-NEXT:    v_mov_b32_e32 v9, v2
-; GFX10-NEXT:    v_mov_b32_e32 v10, v3
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    v_add_co_u32_e64 v15, vcc_lo, v5, s0
+; GFX10-NEXT:    v_add_co_u32_e64 v14, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v16, vcc_lo, s1, v6, vcc_lo
+; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v19, vcc_lo, s2, v9, vcc_lo
-; GFX10-NEXT:    s_and_b32 s1, 1, s4
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, s3, v10, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[15:16], v[5:6]
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v15, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, s[2:3], 0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v20
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10-NEXT:    s_sub_i32 s2, 64, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[0:1]
+; GFX10-NEXT:    s_and_b32 s0, 1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[19:20], v[9:10]
+; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[19:20], v[9:10]
-; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s2, 64, s0
+; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s0, v[15:16]
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[19:20]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s1, v[14:15]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s1, v[19:20]
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
-; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[19:20]
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[7:8], s0, v[4:5]
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_xor_b32_e32 v2, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[4:5]
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v15, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v16, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v7, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v16, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v20, v9, s0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v14, s0
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v15, s0
+; GFX10-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT:    v_add_co_u32_e64 v3, s0, v3, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v2, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v14, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v15, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v5, v7, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.sadd.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define <2 x i128> @v_saddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
 ; GFX6-LABEL: v_saddsat_v2i128:

 ; GFX10-LABEL: v_saddsat_v2i128:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v22, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v23, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v3
-; GFX10-NEXT:    s_movk_i32 s5, 0x7f
+; GFX10-NEXT:    s_movk_i32 s6, 0x7f
 ; GFX10-NEXT:    v_add_co_u32_e64 v16, vcc_lo, v22, v8
-; GFX10-NEXT:    s_sub_i32 s6, 64, s5
+; GFX10-NEXT:    s_sub_i32 s5, 64, s6
+; GFX10-NEXT:    s_sub_i32 s7, s6, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
+; GFX10-NEXT:    v_mov_b32_e32 v26, v4
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v17, vcc_lo, v23, v9, vcc_lo
-; GFX10-NEXT:    s_sub_i32 s7, s5, 64
+; GFX10-NEXT:    v_mov_b32_e32 v27, v5
+; GFX10-NEXT:    v_mov_b32_e32 v4, v6
+; GFX10-NEXT:    v_mov_b32_e32 v5, v7
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v18, vcc_lo, v20, v10, vcc_lo
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v19, vcc_lo, v21, v11, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[22:23]
-; GFX10-NEXT:    v_mov_b32_e32 v26, v4
-; GFX10-NEXT:    v_mov_b32_e32 v27, v5
-; GFX10-NEXT:    v_mov_b32_e32 v24, v6
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s6, v[18:19]
-; GFX10-NEXT:    v_mov_b32_e32 v25, v7
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s5, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v20, v1, v0, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s5, v[16:17]
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s6, v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
 ; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s5, v[18:19]
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s6, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v19
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
 ; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s7, v[18:19]
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX10-NEXT:    s_and_b32 s8, 1, vcc_lo
 ; GFX10-NEXT:    s_and_b32 s4, 1, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s8
-; GFX10-NEXT:    v_xor_b32_e32 v9, v10, v20
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
+; GFX10-NEXT:    v_xor_b32_e32 v10, v10, v20
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v11, v0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v11, v1, s4
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
 ; GFX10-NEXT:    v_add_co_u32_e64 v8, s4, v26, v12
+; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v9, s4, v27, v13, s4
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v10, s4, v24, v14, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v11, s4, v25, v15, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0, v0, vcc_lo
+; GFX10-NEXT:    v_and_b32_e32 v0, 1, v10
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v22, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v10, vcc_lo, v4, v14, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v3, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v20, vcc_lo
-; GFX10-NEXT:    v_lshrrev_b64 v[3:4], s5, v[8:9]
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, v5, v15, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[23:24], s7, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_gt_u64_e64 s4, 0, v[12:13]
-; GFX10-NEXT:    v_lshlrev_b64 v[12:13], s6, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_or_b32_e32 v12, v3, v12
-; GFX10-NEXT:    v_or_b32_e32 v13, v4, v13
-; GFX10-NEXT:    v_ashrrev_i64 v[3:4], s5, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s4
-; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v16, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s4
+; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_lshlrev_b64 v[4:5], s5, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v16, v2, v1, s4
 ; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_ashrrev_i64 v[5:6], s7, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v14, v18, v17, s4
+; GFX10-NEXT:    v_lshrrev_b64 v[2:3], s6, v[8:9]
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v20, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v15, v13, v12, s4
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v12, s4
-; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX10-NEXT:    s_and_b32 s5, 1, s6
-; GFX10-NEXT:    s_and_b32 s6, 1, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
-; GFX10-NEXT:    v_xor_b32_e32 v7, v14, v7
-; GFX10-NEXT:    v_ashrrev_i32_e32 v18, 31, v11
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s6
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s4
-; GFX10-NEXT:    v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v18, v3, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v18, v4, s5
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s4, v5, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v7
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v21, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s5
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
+; GFX10-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX10-NEXT:    s_and_b32 s5, 1, s5
+; GFX10-NEXT:    v_ashrrev_i32_e32 v13, 31, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v23, v2, s4
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v24, v3, s4
+; GFX10-NEXT:    s_and_b32 s4, 1, s4
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s6, v[10:11]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s5
+; GFX10-NEXT:    v_xor_b32_e32 v4, v15, v16
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, v13, v2, s4
+; GFX10-NEXT:    v_add_co_u32_e64 v5, s5, v5, 0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v13, v3, s4
+; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v21, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s5, 0, v6, s5
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s5, 0, v12, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s5, 0x80000000, v3, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s4
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v22, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 define amdgpu_ps <2 x i128> @s_saddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_v2i128:
 ; GFX6:       ; %bb.0:

llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll

 ; CHECK-NEXT:  ; %bb.1:
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v2, v4
 ; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v5, v5, v4
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v5
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v7, v3
-; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, 0, v5
+; CHECK-NEXT:    v_subb_u32_e32 v9, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v14, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v0, v8
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v10, vcc, 0, v5
 ; CHECK-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CHECK-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v6
-; CHECK-NEXT:    v_trunc_f32_e32 v9, v9
-; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v9
+; CHECK-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CHECK-NEXT:    v_trunc_f32_e32 v7, v7
+; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; CHECK-NEXT:    v_subb_u32_e32 v11, vcc, 0, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v7, v7, v8
-; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v13, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v6
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v14
-; CHECK-NEXT:    v_mul_lo_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v14
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v14
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; CHECK-NEXT:    v_mul_lo_u32 v11, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v7
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v6
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v12
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v12
+; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v0, v14
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v14, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CHECK-NEXT:    v_mul_lo_u32 v17, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v16, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; CHECK-NEXT:    v_mul_hi_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v16
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v17, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
 ; CHECK-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; CHECK-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v13
-; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, v10, v6
+; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_mul_hi_u32 v10, v7, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CHECK-NEXT:    v_addc_u32_e64 v11, s[4:5], v7, v10, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v11
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v6
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
 ; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v15
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; CHECK-NEXT:    v_mul_lo_u32 v11, v13, v15
-; CHECK-NEXT:    v_mul_lo_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v15, v13, v15
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v12, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; CHECK-NEXT:    v_mul_hi_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v10, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
+; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v8
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
+; CHECK-NEXT:    v_mul_lo_u32 v16, v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v8, v11, v8
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v16, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v9, v10, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v6
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CHECK-NEXT:    v_mul_hi_u32 v9, v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_xor_b32_e32 v15, v15, v14
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v14
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v15, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v7
 ; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v12, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CHECK-NEXT:    v_mul_hi_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v9
-; CHECK-NEXT:    v_mul_hi_u32 v13, v5, v6
-; CHECK-NEXT:    v_mul_lo_u32 v12, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v12
-; CHECK-NEXT:    v_subb_u32_e64 v11, s[4:5], v1, v10, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v10
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v5, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v15, v11
+; CHECK-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v8, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v3
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v9, v5
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v3
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, 1, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v12, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v12, vcc, 0, v9, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v3
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v3
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v13, v5, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v12, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v12, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v10
+; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v11, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v11, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v11, v5, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v5, v8, v4
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v5, v14, v4
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v5
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v5
 ; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v1, v5
 ; CHECK-NEXT:    v_subb_u32_e32 v5, vcc, v3, v5, vcc
 ; CHECK-NEXT:  BB0_2: ; %Flow
 ; CHECK-NEXT:    s_or_saveexec_b64 s[6:7], s[6:7]
 ; CHECK-NEXT:    s_xor_b64 exec, exec, s[6:7]
 ; CHECK-NEXT:    s_cbranch_execz BB0_4

 ; CHECK-NEXT:    s_cmp_lg_u32 s0, 0
 ; CHECK-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; CHECK-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; CHECK-NEXT:    v_trunc_f32_e32 v1, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; CHECK-NEXT:    s_subb_u32 s5, 0, s11
-; CHECK-NEXT:    v_mov_b32_e32 v6, s11
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s3, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, s3, v0
-; CHECK-NEXT:    v_mul_lo_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v0
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v4
-; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v5
+; CHECK-NEXT:    v_mul_lo_u32 v4, v0, v2
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v5
 ; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, v1, v5
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; CHECK-NEXT:    v_addc_u32_e64 v3, s[0:1], v1, v2, vcc
 ; CHECK-NEXT:    v_mul_lo_u32 v4, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v3
-; CHECK-NEXT:    v_mul_hi_u32 v8, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v6, s3, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; CHECK-NEXT:    v_add_i32_e64 v1, s[0:1], v1, v2
 ; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v8
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v6
 ; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v0, v4
+; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v0, v7
+; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v8, v2
-; CHECK-NEXT:    v_mul_hi_u32 v8, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v7
+; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v6, v2
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v8, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[0:1], v7, v8
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v6, v4
 ; CHECK-NEXT:    v_add_i32_e64 v3, s[0:1], v3, v4
 ; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s13, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s12, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v5, s12, v0
+; CHECK-NEXT:    v_mul_lo_u32 v6, s13, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v0, s13, v0
-; CHECK-NEXT:    v_mov_b32_e32 v4, s13
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, s12, v1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, s13, v1
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, s12, v1
-; CHECK-NEXT:    v_mul_hi_u32 v1, s13, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_mul_hi_u32 v1, s13, v1
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s11, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v1, s10, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, s10, v0
-; CHECK-NEXT:    v_mul_lo_u32 v3, s10, v0
+; CHECK-NEXT:    v_mul_hi_u32 v3, s10, v0
+; CHECK-NEXT:    v_mul_lo_u32 v5, s10, v0
+; CHECK-NEXT:    v_mov_b32_e32 v6, s13
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v5
-; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, s12, v3
-; CHECK-NEXT:    v_subb_u32_e64 v3, s[0:1], v4, v1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
+; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, s12, v5
+; CHECK-NEXT:    v_subb_u32_e64 v3, s[0:1], v6, v1, vcc
 ; CHECK-NEXT:    v_sub_i32_e64 v1, s[0:1], s13, v1
+; CHECK-NEXT:    v_mov_b32_e32 v4, s11
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
 ; CHECK-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, v4, v5, s[0:1]
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v3
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s11, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v5, v6, s[0:1]
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v1
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, 1, v4
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v2, vcc

 ; GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v8, 31, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
 ; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v8
 ; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v8
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v10, v5
-; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v1
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v11
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v11, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v17, 31, v1
 ; GISEL-NEXT:    v_mac_f32_e32 v9, 0x4f800000, v10
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v9, v9
-; GISEL-NEXT:    v_sub_i32_e32 v12, vcc, 0, v4
-; GISEL-NEXT:    v_subb_u32_e32 v13, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v11
+; GISEL-NEXT:    v_xor_b32_e32 v8, v17, v8
 ; GISEL-NEXT:    v_mul_f32_e32 v9, 0x5f7ffffc, v9
 ; GISEL-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v9
 ; GISEL-NEXT:    v_trunc_f32_e32 v10, v10
 ; GISEL-NEXT:    v_mac_f32_e32 v9, 0xcf800000, v10
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v11
-; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v9
-; GISEL-NEXT:    v_mul_lo_u32 v15, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v17, v12, v9
-; GISEL-NEXT:    v_mul_lo_u32 v16, v12, v9
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v16
-; GISEL-NEXT:    v_mul_lo_u32 v17, v9, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v9
+; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v10
+; GISEL-NEXT:    v_mul_hi_u32 v15, v11, v9
+; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v16
+; GISEL-NEXT:    v_mul_lo_u32 v15, v9, v13
 ; GISEL-NEXT:    v_mul_hi_u32 v18, v9, v16
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v17
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v17, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v19, v10, v13
 ; GISEL-NEXT:    v_mul_hi_u32 v16, v10, v16
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v18, v10, v14
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
-; GISEL-NEXT:    v_mul_hi_u32 v17, v9, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v14
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v18
+; GISEL-NEXT:    v_mul_hi_u32 v18, v9, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v19, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
 ; GISEL-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
+; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
+; GISEL-NEXT:    v_mul_hi_u32 v13, v10, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v15
-; GISEL-NEXT:    v_addc_u32_e64 v15, s[4:5], v10, v14, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v13, v9
-; GISEL-NEXT:    v_mul_lo_u32 v16, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v17, v12, v9
-; GISEL-NEXT:    v_mul_hi_u32 v12, v12, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_mul_hi_u32 v14, v9, v17
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_mul_lo_u32 v13, v15, v17
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v14
+; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v9
+; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
+; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v9
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v9
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
+; GISEL-NEXT:    v_mul_lo_u32 v15, v14, v11
 ; GISEL-NEXT:    v_mul_lo_u32 v16, v9, v12
-; GISEL-NEXT:    v_mul_hi_u32 v17, v15, v17
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
+; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v18, v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
 ; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v14, v15, v12
 ; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
-; GISEL-NEXT:    v_mul_hi_u32 v16, v9, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v15, v12
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v18, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; GISEL-NEXT:    v_mul_hi_u32 v12, v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
 ; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, v10, v12, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v17
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v17
 ; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v9
-; GISEL-NEXT:    v_mul_lo_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v14, v0, v9
+; GISEL-NEXT:    v_mul_lo_u32 v11, v1, v9
+; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v10
+; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v9
+; GISEL-NEXT:    v_mul_lo_u32 v14, v1, v10
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v9
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v1, v10
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v10, v1, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v14, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v10
-; GISEL-NEXT:    v_mul_hi_u32 v15, v4, v9
-; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v9
 ; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; GISEL-NEXT:    v_mul_hi_u32 v10, v1, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v10
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v9
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT:    v_subb_u32_e64 v13, s[4:5], v1, v12, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v12
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v5
+; GISEL-NEXT:    v_subb_u32_e64 v12, s[4:5], v1, v11, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v11
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v4
 ; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, 1, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, v12, v14, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e32 v14, vcc, 0, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, 1, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, v11, v13, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v13, vcc, 0, v10, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v5
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v15, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v13
-; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, 0, v14, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v13, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v14, v4, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v12
+; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, 0, v13, vcc
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v5, 31, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v5
 ; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, v7, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v7, v7, v5
 ; GISEL-NEXT:    v_xor_b32_e32 v6, v6, v5
-; GISEL-NEXT:    v_xor_b32_e32 v4, v11, v8
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v7
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v6
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v7, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4
-; GISEL-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
-; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
+; GISEL-NEXT:    v_xor_b32_e32 v7, v7, v5
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v14, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v15, v7
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v12, v1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v13, v4, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v14, 0x4f800000, v15
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v14
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v9, v9
-; GISEL-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v9
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v10
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v10
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v9
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v8
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v4
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v7, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v9
+; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v4
+; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v8
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v12
+; GISEL-NEXT:    v_mul_hi_u32 v17, v4, v15
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v16
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v8, v13
-; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v15
+; GISEL-NEXT:    v_mul_lo_u32 v18, v9, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v17, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_mul_hi_u32 v16, v8, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v4, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v18, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; GISEL-NEXT:    v_mul_hi_u32 v12, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v14
-; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v9, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
-; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v8
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v16
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v14, v16
-; GISEL-NEXT:    v_mul_lo_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v16, v14, v16
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v13
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v4
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v10
+; GISEL-NEXT:    v_mul_lo_u32 v15, v4, v11
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v10
+; GISEL-NEXT:    v_mul_lo_u32 v17, v13, v11
+; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v14, v11
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; GISEL-NEXT:    v_mul_hi_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v17, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v11, v13, v11
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v16
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v16
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v8
-; GISEL-NEXT:    v_mul_lo_u32 v12, v2, v9
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
-; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v8
-; GISEL-NEXT:    v_mul_hi_u32 v8, v3, v8
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v11, v2, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v13, v3, v9
+; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v12, v2, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v9
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v13, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v6, v8
+; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v9
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v6, v9
 ; GISEL-NEXT:    v_mul_hi_u32 v13, v6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v12, v6, v4
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v12
-; GISEL-NEXT:    v_subb_u32_e64 v11, s[4:5], v3, v9, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v9
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v7
+; GISEL-NEXT:    v_mul_lo_u32 v10, v6, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; GISEL-NEXT:    v_subb_u32_e64 v10, s[4:5], v3, v8, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v8
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v7
 ; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v7
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, 1, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v12, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e32 v12, vcc, 0, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v7
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v11, vcc, 0, v9, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v13, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v12, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v12, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v10
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v11, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v11, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v12, v6, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v11, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v4, v10, v5
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v4, v16, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
 ; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
 ; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64:
 ; CGP:       ; %bb.0:

 ; CGP-NEXT:  ; %bb.1:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v0, 31, v5
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v0
 ; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v10, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v11, v5
-; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v5, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v18, 31, v9
 ; CGP-NEXT:    v_mac_f32_e32 v10, 0x4f800000, v11
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v10, v10
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v8, v12
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v12, vcc
-; CGP-NEXT:    v_sub_i32_e32 v14, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v10, 0x5f7ffffc, v10
-; CGP-NEXT:    v_mul_f32_e32 v13, 0x2f800000, v10
-; CGP-NEXT:    v_trunc_f32_e32 v13, v13
-; CGP-NEXT:    v_mac_f32_e32 v10, 0xcf800000, v13
+; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v10
+; CGP-NEXT:    v_trunc_f32_e32 v11, v11
+; CGP-NEXT:    v_mac_f32_e32 v10, 0xcf800000, v11
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; CGP-NEXT:    v_cvt_u32_f32_e32 v13, v13
-; CGP-NEXT:    v_subb_u32_e32 v15, vcc, 0, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v11, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v16, v15, v10
-; CGP-NEXT:    v_mul_lo_u32 v17, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v19, v14, v10
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v10
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v12
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v18
-; CGP-NEXT:    v_mul_lo_u32 v19, v10, v16
-; CGP-NEXT:    v_mul_hi_u32 v20, v10, v18
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v18
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; CGP-NEXT:    v_mul_lo_u32 v15, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v10
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
+; CGP-NEXT:    v_mul_lo_u32 v17, v10, v14
+; CGP-NEXT:    v_mul_hi_u32 v20, v10, v16
+; CGP-NEXT:    v_add_i32_e32 v19, vcc, v8, v18
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v18, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; CGP-NEXT:    v_mul_lo_u32 v21, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v20, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
-; CGP-NEXT:    v_mul_hi_u32 v19, v10, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v20, v18
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v20
+; CGP-NEXT:    v_mul_hi_u32 v20, v10, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v21, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v20
 ; CGP-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v18, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v17
-; CGP-NEXT:    v_addc_u32_e64 v17, s[4:5], v13, v16, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v15, v10
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v19, v14, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, v14, v10
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
+; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
+; CGP-NEXT:    v_mul_lo_u32 v13, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v10
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
 ; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_mul_hi_u32 v16, v10, v19
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CGP-NEXT:    v_mul_lo_u32 v15, v17, v19
-; CGP-NEXT:    v_mul_lo_u32 v18, v10, v14
-; CGP-NEXT:    v_mul_hi_u32 v19, v17, v19
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v16, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v18, v15
-; CGP-NEXT:    v_mul_hi_u32 v18, v10, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v18, s[4:5], v19, v18
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v17
+; CGP-NEXT:    v_mul_lo_u32 v16, v15, v12
+; CGP-NEXT:    v_mul_lo_u32 v17, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v14, v10, v12
+; CGP-NEXT:    v_mul_lo_u32 v20, v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v17
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v20, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v18, v16
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v13, v14, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v9, v10
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v10
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
+; CGP-NEXT:    v_mul_hi_u32 v13, v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v13, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_xor_b32_e32 v19, v19, v18
+; CGP-NEXT:    v_xor_b32_e32 v9, v9, v18
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v13, v19, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v11
 ; CGP-NEXT:    v_mul_hi_u32 v10, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v16, v9, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_mul_hi_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v9, v13
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v16, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v15, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
 ; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_mul_lo_u32 v14, v5, v10
-; CGP-NEXT:    v_mul_lo_u32 v15, v1, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v1, v10
-; CGP-NEXT:    v_mul_lo_u32 v16, v1, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v16
-; CGP-NEXT:    v_subb_u32_e64 v15, s[4:5], v9, v14, vcc
-; CGP-NEXT:    v_sub_i32_e64 v9, s[4:5], v9, v14
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v15, v5
+; CGP-NEXT:    v_mul_hi_u32 v11, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_mul_lo_u32 v12, v5, v10
+; CGP-NEXT:    v_mul_lo_u32 v13, v1, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v1, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v1, v10
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v19, v15
+; CGP-NEXT:    v_subb_u32_e64 v14, s[4:5], v9, v12, vcc
+; CGP-NEXT:    v_sub_i32_e64 v9, s[4:5], v9, v12
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v5
 ; CGP-NEXT:    v_subb_u32_e32 v9, vcc, v9, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v1
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v13, v1
 ; CGP-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v15, v5
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, 1, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v16, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v16, vcc, 0, v13, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v5
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, 1, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v15, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v13, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v9, v5
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v15
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v16, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v14
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v15, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v15, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v16, v9, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v14, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v15, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
 ; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CGP-NEXT:    v_xor_b32_e32 v9, v12, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v13, v5, vcc
+; CGP-NEXT:    v_xor_b32_e32 v9, v18, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v0, v1, v9
 ; CGP-NEXT:    v_xor_b32_e32 v1, v5, v9
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
 ; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; CGP-NEXT:  BB2_2: ; %Flow2
 ; CGP-NEXT:    s_or_saveexec_b64 s[6:7], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[6:7]
 ; CGP-NEXT:    s_cbranch_execz BB2_4

 ; CGP-NEXT:  ; %bb.5:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v7
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v4
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v4
 ; CGP-NEXT:    v_xor_b32_e32 v7, v7, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v8, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v9, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v11, vcc, 0, v7, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v2, v10
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
-; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
-; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v8
-; CGP-NEXT:    v_trunc_f32_e32 v11, v11
-; CGP-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v11
+; CGP-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
+; CGP-NEXT:    v_trunc_f32_e32 v9, v9
+; CGP-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
-; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v10
-; CGP-NEXT:    v_mul_lo_u32 v14, v13, v8
-; CGP-NEXT:    v_mul_lo_u32 v15, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v8
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v8
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
-; CGP-NEXT:    v_mul_lo_u32 v17, v8, v14
-; CGP-NEXT:    v_mul_hi_u32 v18, v8, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_cvt_u32_f32_e32 v9, v9
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v8
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v9
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v8
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v8
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v8, v12
+; CGP-NEXT:    v_mul_hi_u32 v18, v8, v14
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v2, v16
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_mul_lo_u32 v19, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v18, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
-; CGP-NEXT:    v_mul_hi_u32 v17, v8, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v18
+; CGP-NEXT:    v_mul_hi_u32 v18, v8, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v19, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v18
 ; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v15
-; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v13, v8
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
-; CGP-NEXT:    v_mul_lo_u32 v17, v12, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v12, v8
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
+; CGP-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v8
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v8
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v8
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_mul_hi_u32 v14, v8, v17
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v15, v17
-; CGP-NEXT:    v_mul_lo_u32 v16, v8, v12
-; CGP-NEXT:    v_mul_hi_u32 v17, v15, v17
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v14, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v8, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; CGP-NEXT:    v_mul_lo_u32 v14, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v8, v11
+; CGP-NEXT:    v_mul_hi_u32 v12, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v18, v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v10, v13, v10
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v8, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v18, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v12, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v3, v8
-; CGP-NEXT:    v_mul_lo_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v14, v9, v8
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_mul_hi_u32 v11, v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_xor_b32_e32 v17, v17, v16
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v16
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v3, v8
+; CGP-NEXT:    v_mul_lo_u32 v11, v17, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v3, v9
 ; CGP-NEXT:    v_mul_hi_u32 v8, v3, v8
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v14, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
 ; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_mul_lo_u32 v13, v5, v11
-; CGP-NEXT:    v_mul_hi_u32 v15, v5, v8
-; CGP-NEXT:    v_mul_lo_u32 v14, v5, v8
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v14
-; CGP-NEXT:    v_subb_u32_e64 v13, s[4:5], v3, v12, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v12
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v7
+; CGP-NEXT:    v_mul_hi_u32 v9, v3, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v10, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v11, v5, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v5, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v17, v13
+; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v3, v10, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v10
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v7
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v7, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v7
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, 1, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v14, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v14, vcc, 0, v11, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v7
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v13, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v15, v5, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v13
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v14, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v14, v5, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v12
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v13, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v13, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v14, v7, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v13, v7, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v7, v10, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
+; CGP-NEXT:    v_xor_b32_e32 v7, v16, v4
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v7
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v3, v7
 ; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v5, v7, vcc
 ; CGP-NEXT:  BB2_6: ; %Flow
 ; CGP-NEXT:    s_or_saveexec_b64 s[6:7], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[6:7]
 ; CGP-NEXT:    s_cbranch_execz BB2_8
; CGP-NEXT:    s_setpc_b64 s[30:31]
   ret <2 x i64> %result
 }
 
 define i64 @v_sdiv_i64_pow2k_denom(i64 %num) {
 ; CHECK-LABEL: v_sdiv_i64_pow2k_denom:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x1000
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_movk_i32 s6, 0xf000
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_movk_i32 s6, 0x1000
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    s_movk_i32 s6, 0x1000
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CHECK-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
 ; CHECK-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, v5, v7, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v6
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v5
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v6, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv i64 %num, 4096
   ret i64 %result
 }
 
 define <2 x i64> @v_sdiv_v2i64_pow2k_denom(<2 x i64> %num) {
 ; GISEL-LABEL: v_sdiv_v2i64_pow2k_denom:
 ; GISEL:       ; %bb.0:

 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s9
 ; GISEL-NEXT:    s_sub_u32 s11, 0, s8
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v11, s9
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v11, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
 ; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    s_and_b32 s5, s5, 1
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v8
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v7, v1, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v7
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v5, v8, vcc
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GISEL-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v1
+; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v5
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
-; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
-; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v1
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v1, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v1, v6
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v6
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v10, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v6
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v7, v2, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s6, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v10, s7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64_pow2k_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x1000
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_movk_i32 s6, 0xf000
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_movk_i32 s7, 0x1000
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_trunc_f32_e32 v5, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s7, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v9
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, 1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v8, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v10
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v11, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v10, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v11, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, 1, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v7, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v10, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v9, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v9
+; CGP-NEXT:    v_mul_lo_u32 v8, v4, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v5, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
+; CGP-NEXT:    v_mul_hi_u32 v6, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v7, v7, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v8, s7, v5
-; CGP-NEXT:    v_mul_hi_u32 v10, s7, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s7, v4
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v3, v7, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
 ; CGP-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v6, v7, v8, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; CGP-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv <2 x i64> %num, <i64 4096, i64 4096>
   ret <2 x i64> %result
 }
 
 define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
 ; CHECK-LABEL: v_sdiv_i64_oddk_denom:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x12d8fb
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_mov_b32 s6, 0xffed2705
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
-; CHECK-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v5, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CHECK-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
 ; CHECK-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, v5, v7, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v3, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
-; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v6
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, 1, v5
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v6, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v6, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v5, v1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv i64 %num, 1235195
   ret i64 %result
 }
 
 define <2 x i64> @v_sdiv_v2i64_oddk_denom(<2 x i64> %num) {
 ; GISEL-LABEL: v_sdiv_v2i64_oddk_denom:
 ; GISEL:       ; %bb.0:

 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s9
 ; GISEL-NEXT:    s_sub_u32 s11, 0, s8
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v11, s9
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v11, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
 ; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
-; GISEL-NEXT:    s_and_b32 s5, s5, 1
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v8
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v7, v1, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0x4f800000, v7
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v5, v8, vcc
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
+; GISEL-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v1
+; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v5
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
-; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
-; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v1
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v1
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v1, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v1, v6
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v6
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v10, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v6
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v7, v2, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v5
-; GISEL-NEXT:    v_mul_hi_u32 v11, s6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s6, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v10, s7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v3
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64_oddk_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x12d8fb
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_mov_b32 s6, 0xffed2705
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_mov_b32 s7, 0x12d8fb
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_trunc_f32_e32 v5, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s7, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v9
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v10
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, 1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v8, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v10
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v11, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v10, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v11, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s7, v6
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_subrev_i32_e32 v0, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v9
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, 1, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v7, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v10, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v9, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v9
+; CGP-NEXT:    v_mul_lo_u32 v8, v4, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v5, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
+; CGP-NEXT:    v_mul_hi_u32 v6, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v7, v7, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v8, s7, v5
-; CGP-NEXT:    v_mul_hi_u32 v10, s7, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s7, v4
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v3, v7, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
 ; CGP-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, 1, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v6, v7, v8, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v5, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v2
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
-; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v8
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v9, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, 1, v7
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v10, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
 ; CGP-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = sdiv <2 x i64> %num, <i64 1235195, i64 1235195>
   ret <2 x i64> %result
 }
 
 define i64 @v_sdiv_i64_pow2_shl_denom(i64 %x, i64 %y) {
 ; CHECK-LABEL: v_sdiv_i64_pow2_shl_denom:
 ; CHECK:       ; %bb.0:

 ; CHECK-NEXT:  ; %bb.1:
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v2, 31, v5
 ; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v2
 ; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, v5, v2, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v2
 ; CHECK-NEXT:    v_xor_b32_e32 v5, v5, v2
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v3
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v7, v5
-; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, 0, v3
+; CHECK-NEXT:    v_subb_u32_e32 v9, vcc, 0, v5, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v14, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v0, v8
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v10, vcc, 0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CHECK-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v6
-; CHECK-NEXT:    v_trunc_f32_e32 v9, v9
-; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v9
+; CHECK-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CHECK-NEXT:    v_trunc_f32_e32 v7, v7
+; CHECK-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; CHECK-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v7, v7, v8
-; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v13, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v6
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v14
-; CHECK-NEXT:    v_mul_lo_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v14
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v14
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; CHECK-NEXT:    v_mul_lo_u32 v11, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v7
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v6
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v12
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v12
+; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v0, v14
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v14, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CHECK-NEXT:    v_mul_lo_u32 v17, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v16, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; CHECK-NEXT:    v_mul_hi_u32 v15, v6, v12
-; CHECK-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v16
+; CHECK-NEXT:    v_mul_hi_u32 v16, v6, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v17, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
 ; CHECK-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; CHECK-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v11, v6
-; CHECK-NEXT:    v_mul_lo_u32 v14, v10, v13
-; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, v10, v6
+; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CHECK-NEXT:    v_mul_hi_u32 v10, v7, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CHECK-NEXT:    v_addc_u32_e64 v11, s[4:5], v7, v10, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v9, v9, v6
+; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v11
+; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v6
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v6
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
 ; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v15
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; CHECK-NEXT:    v_mul_lo_u32 v11, v13, v15
-; CHECK-NEXT:    v_mul_lo_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v15, v13, v15
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v12, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; CHECK-NEXT:    v_mul_hi_u32 v14, v6, v10
-; CHECK-NEXT:    v_mul_hi_u32 v10, v13, v10
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
+; CHECK-NEXT:    v_mul_lo_u32 v12, v11, v8
+; CHECK-NEXT:    v_mul_lo_u32 v13, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
+; CHECK-NEXT:    v_mul_lo_u32 v16, v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v8, v11, v8
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v6, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v16, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, v9, v10, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v6
+; CHECK-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CHECK-NEXT:    v_mul_hi_u32 v9, v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_xor_b32_e32 v15, v15, v14
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v14
+; CHECK-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v15, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v7
 ; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v12, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CHECK-NEXT:    v_mul_hi_u32 v11, v7, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v1, v9
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_mul_hi_u32 v10, v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_mul_lo_u32 v10, v5, v6
-; CHECK-NEXT:    v_mul_lo_u32 v11, v3, v9
-; CHECK-NEXT:    v_mul_hi_u32 v13, v3, v6
-; CHECK-NEXT:    v_mul_lo_u32 v12, v3, v6
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v12
-; CHECK-NEXT:    v_subb_u32_e64 v11, s[4:5], v1, v10, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v10
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CHECK-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v6
+; CHECK-NEXT:    v_mul_lo_u32 v9, v3, v7
+; CHECK-NEXT:    v_mul_hi_u32 v10, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v11, v3, v6
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v15, v11
+; CHECK-NEXT:    v_subb_u32_e64 v10, s[4:5], v1, v8, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v5
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
-; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, v7, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v9, v3
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, 1, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v12, s[4:5]
-; CHECK-NEXT:    v_addc_u32_e32 v12, vcc, 0, v9, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v5
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
+; CHECK-NEXT:    v_addc_u32_e32 v11, vcc, 0, v7, vcc
 ; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v5
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v13, v3, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v12, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v12, v3, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, 1, v10
+; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, 0, v11, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v11, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v11, v5, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; CHECK-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v5, v8, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v5, v14, v2
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v5
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v5
 ; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v1, v5
 ; CHECK-NEXT:    v_subb_u32_e32 v3, vcc, v3, v5, vcc
 ; CHECK-NEXT:  BB7_2: ; %Flow
 ; CHECK-NEXT:    s_or_saveexec_b64 s[6:7], s[6:7]
 ; CHECK-NEXT:    s_xor_b64 exec, exec, s[6:7]
 ; CHECK-NEXT:    s_cbranch_execz BB7_4

 
 define <2 x i64> @v_sdiv_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
 ; GISEL-LABEL: v_sdiv_v2i64_pow2_shl_denom:
 ; GISEL:       ; %bb.0:
 ; GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-NEXT:    s_movk_i32 s6, 0x1000
 ; GISEL-NEXT:    s_mov_b32 s7, 0
 ; GISEL-NEXT:    v_lshl_b64 v[4:5], s[6:7], v4
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v1
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
 ; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v7
 ; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v4
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GISEL-NEXT:    v_xor_b32_e32 v9, v0, v10
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v17, v1, v10
-; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v8
-; GISEL-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v8, v8
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v8
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; GISEL-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
+; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
+; GISEL-NEXT:    v_trunc_f32_e32 v9, v9
+; GISEL-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v0
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v9
+; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v8
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v12
+; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v15
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v16
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v16, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v1, v0, v15
-; GISEL-NEXT:    v_mul_hi_u32 v15, v8, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v14, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v13
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v16, v1
-; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v18, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v18, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v14, v1
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; GISEL-NEXT:    v_mul_hi_u32 v12, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GISEL-NEXT:    v_addc_u32_e64 v1, s[4:5], v8, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v1
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v0
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v0
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v15
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v15
-; GISEL-NEXT:    v_mul_lo_u32 v14, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v15, v1, v15
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v11
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; GISEL-NEXT:    v_mul_hi_u32 v14, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v1, v1, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v11
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v0, v12
-; GISEL-NEXT:    v_addc_u32_e32 v11, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v17, v8
-; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v11
-; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v9, v8
-; GISEL-NEXT:    v_mul_hi_u32 v8, v17, v8
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v17, v11
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
-; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v17, v11
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v8
+; GISEL-NEXT:    v_xor_b32_e32 v17, v0, v16
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v11, v14
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v15
+; GISEL-NEXT:    v_mul_lo_u32 v11, v13, v10
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v0
+; GISEL-NEXT:    v_xor_b32_e32 v15, v1, v16
+; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v9, v8, v10
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
+; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v0
+; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v14, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v0, v13, v0
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, v15, v1
+; GISEL-NEXT:    v_mul_lo_u32 v9, v17, v0
+; GISEL-NEXT:    v_mul_hi_u32 v10, v17, v1
+; GISEL-NEXT:    v_mul_lo_u32 v11, v15, v0
+; GISEL-NEXT:    v_mul_hi_u32 v1, v15, v1
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_mul_hi_u32 v10, v17, v0
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v8
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v6
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
-; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v6
-; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v6
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v9, v13
-; GISEL-NEXT:    v_subb_u32_e64 v12, s[4:5], v17, v11, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v11, s[4:5], v17, v11
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, v11, v5, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v11, v1
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_hi_u32 v0, v15, v0
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v1, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v0, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v8
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v8
+; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v17, v13
+; GISEL-NEXT:    v_subb_u32_e64 v11, s[4:5], v15, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v6, s[4:5], v15, v6
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; GISEL-NEXT:    v_subb_u32_e32 v6, vcc, v6, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v4
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v9, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_subbrev_u32_e32 v11, vcc, 0, v11, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, v13, v14, s[4:5]
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, 1, v6
-; GISEL-NEXT:    v_addc_u32_e32 v14, vcc, 0, v8, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v4
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
+; GISEL-NEXT:    v_subbrev_u32_e32 v6, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, v12, v13, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
+; GISEL-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v11, v5
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v15, v4, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v13
-; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v14, vcc
+; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v6, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v14, v4, vcc
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v12
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v13, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v14, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v15, v1, v10
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v14
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, v15
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v13, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v14, v9, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v6, v10, v7
-; GISEL-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v8, v0, v7
-; GISEL-NEXT:    v_xor_b32_e32 v9, v1, v7
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v8
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, v9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
-; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v6
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v6
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v12, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v5, v13, v6, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v2, v10
-; GISEL-NEXT:    v_addc_u32_e32 v2, vcc, v3, v10, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v3, v1, v10
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v9, v5, vcc
 ; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GISEL-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v1, v1
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GISEL-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v0
+; GISEL-NEXT:    v_trunc_f32_e32 v6, v6
+; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v6
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v8
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v1
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v0
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v10
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v1, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v17, v0, v15
-; GISEL-NEXT:    v_mul_hi_u32 v15, v1, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v17, v1, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v1, v13
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GISEL-NEXT:    v_xor_b32_e32 v5, v16, v7
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v14
+; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v15, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v0
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v6, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v9
+; GISEL-NEXT:    v_mul_hi_u32 v17, v0, v13
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v16
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v18, v6, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v6, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v0, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v18, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v1, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v0
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
-; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v0
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v0
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v16
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v14, v16
-; GISEL-NEXT:    v_mul_lo_u32 v15, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v16, v14, v16
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v9, v6, v9
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v11
+; GISEL-NEXT:    v_addc_u32_e64 v11, s[4:5], v6, v9, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v0
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v7
+; GISEL-NEXT:    v_mul_lo_u32 v13, v0, v8
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v17, v11, v8
+; GISEL-NEXT:    v_mul_hi_u32 v7, v11, v7
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v13, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v17, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; GISEL-NEXT:    v_mul_hi_u32 v15, v0, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v11, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v0, v12
-; GISEL-NEXT:    v_addc_u32_e32 v12, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v2, v11
-; GISEL-NEXT:    v_mul_lo_u32 v14, v3, v12
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v4, v6
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v11
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v5, v6, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v13, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v5, v2, v12
-; GISEL-NEXT:    v_mul_hi_u32 v11, v2, v11
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v12
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
-; GISEL-NEXT:    v_mul_hi_u32 v11, v2, v12
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; GISEL-NEXT:    v_mul_lo_u32 v6, v9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v4
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; GISEL-NEXT:    v_sub_i32_e32 v3, vcc, v3, v12
-; GISEL-NEXT:    v_subb_u32_e64 v11, s[4:5], v2, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v2, s[4:5], v2, v6
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v9
-; GISEL-NEXT:    v_subb_u32_e32 v2, vcc, v2, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v3, v8
-; GISEL-NEXT:    v_sub_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, 1, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e32 v12, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v9
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v13, v3, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v11
-; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v12, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v8, v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v16
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v16
+; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v0
+; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v6
+; GISEL-NEXT:    v_mul_hi_u32 v0, v3, v0
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v11, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v0, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v0
+; GISEL-NEXT:    v_mul_lo_u32 v9, v15, v7
+; GISEL-NEXT:    v_mul_lo_u32 v11, v14, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v14, v7
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GISEL-NEXT:    v_mul_lo_u32 v8, v14, v7
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v5
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v1, v5
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v5, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v11
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v12
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v15
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v15, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v14
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v15
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[4:5]
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
+; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v15
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, 1, v5
+; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v8, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v11, v3, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v12, v8, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v4, v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v5, v3, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v7, v2, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v4, v16, v10
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
 ; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
 ; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64_pow2_shl_denom:
 ; CGP:       ; %bb.0:

 ; CGP-NEXT:  ; %bb.1:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v0, 31, v11
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v10, v0
 ; CGP-NEXT:    v_addc_u32_e32 v4, vcc, v11, v0, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; CGP-NEXT:    v_xor_b32_e32 v4, v4, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v11, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v7
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v4, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v18, 31, v7
 ; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v11
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v5, v12
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v12, vcc
-; CGP-NEXT:    v_sub_i32_e32 v14, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CGP-NEXT:    v_mul_f32_e32 v13, 0x2f800000, v6
-; CGP-NEXT:    v_trunc_f32_e32 v13, v13
-; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v13
+; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v11, v11
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v11
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT:    v_cvt_u32_f32_e32 v13, v13
-; CGP-NEXT:    v_subb_u32_e32 v15, vcc, 0, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v11, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v16, v15, v6
-; CGP-NEXT:    v_mul_lo_u32 v17, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v19, v14, v6
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v6
-; CGP-NEXT:    v_xor_b32_e32 v7, v7, v12
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v18
-; CGP-NEXT:    v_mul_lo_u32 v19, v6, v16
-; CGP-NEXT:    v_mul_hi_u32 v20, v6, v18
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v18
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; CGP-NEXT:    v_mul_lo_u32 v15, v13, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v6
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v6
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
+; CGP-NEXT:    v_mul_lo_u32 v17, v6, v14
+; CGP-NEXT:    v_mul_hi_u32 v20, v6, v16
+; CGP-NEXT:    v_add_i32_e32 v19, vcc, v5, v18
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v18, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; CGP-NEXT:    v_mul_lo_u32 v21, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v20
+; CGP-NEXT:    v_mul_hi_u32 v20, v6, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v21, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v20, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
-; CGP-NEXT:    v_mul_hi_u32 v19, v6, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v13, v16
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v20, v18
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v20
 ; CGP-NEXT:    v_cndmask_b32_e64 v20, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v18, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v19, vcc, v20, v19
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v17
-; CGP-NEXT:    v_addc_u32_e64 v17, s[4:5], v13, v16, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v15, v6
-; CGP-NEXT:    v_mul_lo_u32 v18, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v19, v14, v6
-; CGP-NEXT:    v_mul_hi_u32 v14, v14, v6
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v20
+; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v15
+; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
+; CGP-NEXT:    v_mul_lo_u32 v13, v13, v6
+; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
+; CGP-NEXT:    v_mul_hi_u32 v17, v12, v6
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v6
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
 ; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_mul_hi_u32 v16, v6, v19
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; CGP-NEXT:    v_mul_lo_u32 v15, v17, v19
-; CGP-NEXT:    v_mul_lo_u32 v18, v6, v14
-; CGP-NEXT:    v_mul_hi_u32 v19, v17, v19
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v16, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v18, v15
-; CGP-NEXT:    v_mul_hi_u32 v18, v6, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v17, v14
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v19
-; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v18, s[4:5], v19, v18
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v17
+; CGP-NEXT:    v_mul_lo_u32 v16, v15, v12
+; CGP-NEXT:    v_mul_lo_u32 v17, v6, v13
+; CGP-NEXT:    v_mul_hi_u32 v14, v6, v12
+; CGP-NEXT:    v_mul_lo_u32 v20, v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v16, v17
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v6, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v20, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v18, v16
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, v13, v14, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v15
-; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v6
+; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
+; CGP-NEXT:    v_mul_hi_u32 v13, v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v13, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_xor_b32_e32 v19, v19, v18
+; CGP-NEXT:    v_xor_b32_e32 v7, v7, v18
+; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v7, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v19, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v6
+; CGP-NEXT:    v_mul_lo_u32 v15, v7, v11
 ; CGP-NEXT:    v_mul_hi_u32 v6, v7, v6
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v16, v7, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_mul_hi_u32 v15, v11, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v16, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_hi_u32 v14, v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v15, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
 ; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_mul_lo_u32 v14, v4, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v1, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v1, v6
-; CGP-NEXT:    v_mul_lo_u32 v16, v1, v6
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v16
-; CGP-NEXT:    v_subb_u32_e64 v15, s[4:5], v7, v14, vcc
-; CGP-NEXT:    v_sub_i32_e64 v7, s[4:5], v7, v14
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v15, v4
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_mul_lo_u32 v12, v4, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v1, v11
+; CGP-NEXT:    v_mul_hi_u32 v14, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v15, v1, v6
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v19, v15
+; CGP-NEXT:    v_subb_u32_e64 v14, s[4:5], v7, v12, vcc
+; CGP-NEXT:    v_sub_i32_e64 v7, s[4:5], v7, v12
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v4
 ; CGP-NEXT:    v_subb_u32_e32 v7, vcc, v7, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v1
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
+; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v13, v1
 ; CGP-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v15, v4
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, 1, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v16, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v16, vcc, 0, v13, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v4
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, 1, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v15, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v15, vcc, 0, v11, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v13, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, 1, v15
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v16, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, 1, v14
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v15, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v15, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v16, v7, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v14, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v15, v7, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
 ; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CGP-NEXT:    v_xor_b32_e32 v6, v12, v0
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v13, v4, vcc
+; CGP-NEXT:    v_xor_b32_e32 v6, v18, v0
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v0, v1, v6
 ; CGP-NEXT:    v_xor_b32_e32 v1, v4, v6
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
 ; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
 ; CGP-NEXT:  BB8_2: ; %Flow2
 ; CGP-NEXT:    s_or_saveexec_b64 s[6:7], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[6:7]
 ; CGP-NEXT:    s_cbranch_execz BB8_4

 ; CGP-NEXT:  ; %bb.5:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v9
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v4
 ; CGP-NEXT:    v_addc_u32_e32 v6, vcc, v9, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v4
 ; CGP-NEXT:    v_xor_b32_e32 v6, v6, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v9, v6
-; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v11, vcc, 0, v6, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v16, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v9
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v2, v10
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
-; CGP-NEXT:    v_sub_i32_e32 v12, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v11, v11
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v11
+; CGP-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v7
+; CGP-NEXT:    v_trunc_f32_e32 v9, v9
+; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v9
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v11, v11
-; CGP-NEXT:    v_subb_u32_e32 v13, vcc, 0, v6, vcc
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v10
-; CGP-NEXT:    v_mul_lo_u32 v14, v13, v7
-; CGP-NEXT:    v_mul_lo_u32 v15, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v7
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v7
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v16
-; CGP-NEXT:    v_mul_lo_u32 v17, v7, v14
-; CGP-NEXT:    v_mul_hi_u32 v18, v7, v16
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_cvt_u32_f32_e32 v9, v9
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v7
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v9
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v7
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v7, v12
+; CGP-NEXT:    v_mul_hi_u32 v18, v7, v14
+; CGP-NEXT:    v_add_i32_e32 v17, vcc, v2, v16
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v16, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_mul_lo_u32 v19, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v18, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
-; CGP-NEXT:    v_mul_hi_u32 v17, v7, v14
-; CGP-NEXT:    v_mul_hi_u32 v14, v11, v14
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v18
+; CGP-NEXT:    v_mul_hi_u32 v18, v7, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v19, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v18
 ; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v15
-; CGP-NEXT:    v_addc_u32_e64 v15, s[4:5], v11, v14, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v13, v7
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v15
-; CGP-NEXT:    v_mul_lo_u32 v17, v12, v7
-; CGP-NEXT:    v_mul_hi_u32 v12, v12, v7
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
+; CGP-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v7
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v7
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v17
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v15, v17
-; CGP-NEXT:    v_mul_lo_u32 v16, v7, v12
-; CGP-NEXT:    v_mul_hi_u32 v17, v15, v17
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v14, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
-; CGP-NEXT:    v_mul_hi_u32 v16, v7, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v15, v12
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v16, s[4:5], v17, v16
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; CGP-NEXT:    v_mul_lo_u32 v14, v13, v10
+; CGP-NEXT:    v_mul_lo_u32 v15, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v12, v7, v10
+; CGP-NEXT:    v_mul_lo_u32 v18, v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v10, v13, v10
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v18, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v16, v14
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, v11, v12, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
-; CGP-NEXT:    v_addc_u32_e32 v11, vcc, 0, v11, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v3, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v14, v9, v7
+; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_mul_hi_u32 v11, v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CGP-NEXT:    v_xor_b32_e32 v17, v17, v16
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v16
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v3, v7
+; CGP-NEXT:    v_mul_lo_u32 v11, v17, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v3, v9
 ; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v13, v9, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v3, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v14, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_mul_hi_u32 v12, v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
 ; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_mul_lo_u32 v12, v6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, v5, v11
-; CGP-NEXT:    v_mul_hi_u32 v15, v5, v7
-; CGP-NEXT:    v_mul_lo_u32 v14, v5, v7
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v14
-; CGP-NEXT:    v_subb_u32_e64 v13, s[4:5], v3, v12, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v12
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v6
+; CGP-NEXT:    v_mul_hi_u32 v9, v3, v9
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v7
+; CGP-NEXT:    v_mul_lo_u32 v11, v5, v9
+; CGP-NEXT:    v_mul_hi_u32 v12, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v17, v13
+; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v3, v10, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v10
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v6
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; CGP-NEXT:    v_sub_i32_e32 v9, vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v11, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v6
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, 1, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v14, s[4:5]
-; CGP-NEXT:    v_addc_u32_e32 v14, vcc, 0, v11, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v6
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, 1, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v13, s[4:5]
+; CGP-NEXT:    v_addc_u32_e32 v13, vcc, 0, v9, vcc
 ; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v9, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e32 vcc, v11, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v6
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v15, v5, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v13
-; CGP-NEXT:    v_addc_u32_e32 v6, vcc, 0, v14, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v14, v5, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, 1, v12
+; CGP-NEXT:    v_addc_u32_e32 v6, vcc, 0, v13, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v13, v5, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v14, v6, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v13, v6, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v6, v10, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
+; CGP-NEXT:    v_xor_b32_e32 v6, v16, v4
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v6
 ; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v3, v6
 ; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v5, v6, vcc
 ; CGP-NEXT:  BB8_6: ; %Flow
 ; CGP-NEXT:    s_or_saveexec_b64 s[6:7], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[6:7]
 ; CGP-NEXT:    s_cbranch_execz BB8_8

 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff
 ; CGP-NEXT:    v_and_b32_e32 v1, s4, v2
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v1, v1
 ; CGP-NEXT:    v_and_b32_e32 v0, s4, v0
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v0, v0
 ; CGP-NEXT:    v_rcp_f32_e32 v2, v1
 ; CGP-NEXT:    v_mul_f32_e32 v2, v0, v2
 ; CGP-NEXT:    v_trunc_f32_e32 v2, v2
+; CGP-NEXT:    v_cvt_i32_f32_e32 v3, v2
 ; CGP-NEXT:    v_mad_f32 v0, -v2, v1, v0
-; CGP-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
 ; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and i64 %num, 16777215
   %den.mask = and i64 %den, 16777215
   %result = sdiv i64 %num.mask, %den.mask
   ret i64 %result
 }

 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v11
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v12
 ; GISEL-NEXT:    v_mul_lo_u32 v14, v5, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v12
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
 ; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
 ; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v8, v7
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], 0, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v14, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; GISEL-NEXT:    v_mul_hi_u32 v8, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v13, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v13, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
 ; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v13, v7, vcc
 ; GISEL-NEXT:    v_sub_i32_e64 v7, s[4:5], v13, v7
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v3
 ; GISEL-NEXT:    v_subb_u32_e32 v7, vcc, v7, v3, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v1
 ; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
+; GISEL-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v3
-; GISEL-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, 0, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, v9, v10, s[4:5]
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, 1, v4
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, 0, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v10, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, 1, v4
+; GISEL-NEXT:    v_addc_u32_e32 v13, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v10, 0x4f800000, v11
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v10, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v10
 ; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v3
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, 0, v10, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, 0, v6
-; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v12, v7
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v9, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v10, v3, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v11, 0x4f800000, v12
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v3, v11
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
-; GISEL-NEXT:    v_trunc_f32_e32 v4, v4
-; GISEL-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
+; GISEL-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v1
+; GISEL-NEXT:    v_trunc_f32_e32 v3, v3
+; GISEL-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v3
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GISEL-NEXT:    v_sub_i32_e32 v5, vcc, 0, v6
-; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v4
-; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v3
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v3, v11
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v10, vcc, 0, v9, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v1
+; GISEL-NEXT:    v_mul_lo_u32 v15, v7, v3
+; GISEL-NEXT:    v_mul_hi_u32 v16, v7, v1
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v1
+; GISEL-NEXT:    v_add_i32_e32 v17, vcc, 1, v12
+; GISEL-NEXT:    v_addc_u32_e32 v18, vcc, 0, v13, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; GISEL-NEXT:    v_mul_lo_u32 v15, v3, v11
+; GISEL-NEXT:    v_mul_lo_u32 v16, v1, v14
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v12, v17, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v11
+; GISEL-NEXT:    v_mul_lo_u32 v17, v3, v14
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
+; GISEL-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_mul_hi_u32 v15, v1, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v16, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v17, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; GISEL-NEXT:    v_mul_hi_u32 v14, v3, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v11
+; GISEL-NEXT:    v_addc_u32_e64 v11, s[6:7], v3, v12, s[4:5]
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v1
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v15, v7, v1
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v1
+; GISEL-NEXT:    v_cndmask_b32_e32 v13, v13, v18, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
 ; GISEL-NEXT:    v_add_i32_e32 v2, vcc, 0, v2
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v7
+; GISEL-NEXT:    v_mul_lo_u32 v15, v1, v10
+; GISEL-NEXT:    v_addc_u32_e64 v16, s[6:7], 0, 0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v7
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v17, v11, v10
+; GISEL-NEXT:    v_mul_hi_u32 v7, v11, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v1, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v17, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v14
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v10, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
-; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v4, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v3
-; GISEL-NEXT:    v_mul_hi_u32 v5, v5, v3
-; GISEL-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v12
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v5
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v3, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v10, v5
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, v4, v5, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v5, v13, v3
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_addc_u32_e64 v3, vcc, v3, v10, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v16, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v2, v3
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v5, v13, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v5, v2, v1
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_mul_lo_u32 v10, v16, v3
+; GISEL-NEXT:    v_mul_hi_u32 v1, v16, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GISEL-NEXT:    v_mul_hi_u32 v7, v2, v3
 ; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v4
-; GISEL-NEXT:    v_mul_hi_u32 v3, v13, v3
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v13, v4
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT:    v_mul_lo_u32 v5, v7, v3
-; GISEL-NEXT:    v_mul_lo_u32 v8, v6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v10, v6, v3
-; GISEL-NEXT:    v_mul_lo_u32 v9, v6, v3
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v9
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v13, v5, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v5, s[4:5], v13, v5
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v7
-; GISEL-NEXT:    v_subb_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v3, v16, v3
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v1, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v7, v1
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v1
+; GISEL-NEXT:    v_mul_lo_u32 v8, v9, v5
+; GISEL-NEXT:    v_mul_lo_u32 v10, v6, v3
+; GISEL-NEXT:    v_mul_hi_u32 v11, v6, v5
+; GISEL-NEXT:    v_mul_lo_u32 v7, v6, v5
+; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
+; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v4, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v10
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v16, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v4, s[4:5], v16, v4
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v9
+; GISEL-NEXT:    v_subb_u32_e32 v4, vcc, v4, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
 ; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v7
-; GISEL-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, v9, v10, s[4:5]
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, 1, v3
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v4, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v7
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v9
+; GISEL-NEXT:    v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, v8, v10, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, 1, v5
+; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v2, 0, -1, vcc
-; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v7
+; GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v4, v9
 ; GISEL-NEXT:    v_cndmask_b32_e32 v2, v11, v2, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, 1, v9
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, 1, v8
 ; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, 0, v10, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v9, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v10, v6, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v8, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v10, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, 0, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_sdiv_v2i64_24bit:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff

 ; CGP-NEXT:    v_mad_f32 v0, -v3, v1, v0
 ; CGP-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; CGP-NEXT:    v_rcp_f32_e32 v5, v4
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
 ; CGP-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; CGP-NEXT:    v_mul_f32_e32 v3, v2, v5
 ; CGP-NEXT:    v_trunc_f32_e32 v3, v3
+; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v3
 ; CGP-NEXT:    v_mad_f32 v2, -v3, v4, v2
-; CGP-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v2|, |v4|
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CGP-NEXT:    v_bfe_i32 v2, v2, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and <2 x i64> %num, <i64 16777215, i64 16777215>
   %den.mask = and <2 x i64> %den, <i64 16777215, i64 16777215>
   %result = sdiv <2 x i64> %num.mask, %den.mask
   ret <2 x i64> %result
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

 ; CHECK-NEXT:    ; implicit-def: $vgpr4_vgpr5
 ; CHECK-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; CHECK-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
 ; CHECK-NEXT:    s_cbranch_execz BB0_2
 ; CHECK-NEXT:  ; %bb.1:
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v2, v4
 ; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; CHECK-NEXT:    v_xor_b32_e32 v5, v5, v4
+; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v4
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v4, v5
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v3
-; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
+; CHECK-NEXT:    v_subb_u32_e32 v8, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v13, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v0, v7
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
 ; CHECK-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CHECK-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v4
-; CHECK-NEXT:    v_trunc_f32_e32 v8, v8
-; CHECK-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v8
+; CHECK-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v4
+; CHECK-NEXT:    v_trunc_f32_e32 v6, v6
+; CHECK-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v6
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CHECK-NEXT:    v_subb_u32_e32 v10, vcc, 0, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v6, v6, v7
-; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v4
-; CHECK-NEXT:    v_mul_lo_u32 v12, v9, v8
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v4
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
-; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v13
-; CHECK-NEXT:    v_mul_lo_u32 v14, v4, v11
-; CHECK-NEXT:    v_mul_hi_u32 v15, v4, v13
-; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v4
+; CHECK-NEXT:    v_mul_lo_u32 v9, v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v4
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v4
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v11
+; CHECK-NEXT:    v_mul_lo_u32 v12, v4, v9
+; CHECK-NEXT:    v_mul_hi_u32 v15, v4, v11
+; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v0, v13
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v13, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_mul_lo_u32 v16, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v15, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; CHECK-NEXT:    v_mul_hi_u32 v14, v4, v11
-; CHECK-NEXT:    v_mul_hi_u32 v11, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
+; CHECK-NEXT:    v_mul_hi_u32 v15, v4, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v16, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v15
 ; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v12
-; CHECK-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v10, v4
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v12
-; CHECK-NEXT:    v_mul_lo_u32 v14, v9, v4
-; CHECK-NEXT:    v_mul_hi_u32 v9, v9, v4
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; CHECK-NEXT:    v_addc_u32_e64 v10, s[4:5], v6, v9, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v4
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v4
+; CHECK-NEXT:    v_mul_lo_u32 v7, v7, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
 ; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_mul_hi_u32 v11, v4, v14
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v12, v14
-; CHECK-NEXT:    v_mul_lo_u32 v13, v4, v9
-; CHECK-NEXT:    v_mul_hi_u32 v14, v12, v14
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v11, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
-; CHECK-NEXT:    v_mul_hi_u32 v13, v4, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v7
+; CHECK-NEXT:    v_mul_lo_u32 v12, v4, v8
+; CHECK-NEXT:    v_mul_hi_u32 v9, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v8
+; CHECK-NEXT:    v_mul_hi_u32 v7, v10, v7
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, v8, v9, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v1, v4
-; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v4
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_mul_hi_u32 v8, v10, v8
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_xor_b32_e32 v14, v14, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
+; CHECK-NEXT:    v_mul_lo_u32 v8, v14, v6
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v4
+; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
 ; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v11, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CHECK-NEXT:    v_mul_lo_u32 v9, v3, v4
-; CHECK-NEXT:    v_mul_lo_u32 v8, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v10, v5, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v5, v4
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; CHECK-NEXT:    v_sub_i32_e32 v6, vcc, v6, v10
-; CHECK-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v4, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CHECK-NEXT:    v_mul_lo_u32 v7, v3, v4
+; CHECK-NEXT:    v_mul_lo_u32 v6, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v8, v5, v4
+; CHECK-NEXT:    v_mul_lo_u32 v4, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v14, v4
+; CHECK-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, v4, v9, s[4:5]
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v6, v5
-; CHECK-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, v4, v5
+; CHECK-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v3
-; CHECK-NEXT:    v_sub_i32_e32 v3, vcc, v9, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_sub_i32_e32 v3, vcc, v8, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e32 v3, v6, v3, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v7
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v3, v7
-; CHECK-NEXT:    v_subb_u32_e32 v5, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
+; CHECK-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_sub_i32_e32 v4, vcc, v3, v13
+; CHECK-NEXT:    v_subb_u32_e32 v5, vcc, v1, v13, vcc
 ; CHECK-NEXT:  BB0_2: ; %Flow
 ; CHECK-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CHECK-NEXT:    s_xor_b64 exec, exec, s[4:5]
 ; CHECK-NEXT:    s_cbranch_execz BB0_4
 ; CHECK-NEXT:  ; %bb.3:
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v1, v2
 ; CHECK-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
 ; CHECK-NEXT:    v_mov_b32_e32 v5, 0

 ; CHECK-NEXT:    s_cmp_lg_u32 s0, 0
 ; CHECK-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; CHECK-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; CHECK-NEXT:    v_trunc_f32_e32 v1, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; CHECK-NEXT:    s_subb_u32 s5, 0, s11
-; CHECK-NEXT:    v_mov_b32_e32 v6, s11
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s3, v1
-; CHECK-NEXT:    v_mul_hi_u32 v5, s3, v0
-; CHECK-NEXT:    v_mul_lo_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v4, s3, v0
+; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v0
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v4
-; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
-; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_mul_lo_u32 v3, v1, v5
+; CHECK-NEXT:    v_mul_lo_u32 v4, v0, v2
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v5
 ; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, v1, v5
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v7, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; CHECK-NEXT:    v_addc_u32_e64 v3, s[0:1], v1, v2, vcc
 ; CHECK-NEXT:    v_mul_lo_u32 v4, s5, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v5, s3, v3
-; CHECK-NEXT:    v_mul_hi_u32 v8, s3, v0
+; CHECK-NEXT:    v_mul_hi_u32 v6, s3, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; CHECK-NEXT:    v_add_i32_e64 v1, s[0:1], v1, v2
 ; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v8
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v4, v6
 ; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v0, v4
+; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v0, v7
+; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v4
 ; CHECK-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
+; CHECK-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v8, v2
-; CHECK-NEXT:    v_mul_hi_u32 v8, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v7
+; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v6, v2
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v8, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v5, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[0:1], v7, v8
+; CHECK-NEXT:    v_add_i32_e64 v5, s[0:1], v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[0:1], v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v3, v4
 ; CHECK-NEXT:    v_add_i32_e64 v2, s[0:1], v5, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]
-; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v7, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[0:1]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[0:1], v6, v4
 ; CHECK-NEXT:    v_add_i32_e64 v3, s[0:1], v3, v4
 ; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s9, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v3, s8, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v5, s8, v0
+; CHECK-NEXT:    v_mul_lo_u32 v6, s9, v1
 ; CHECK-NEXT:    v_mul_hi_u32 v0, s9, v0
-; CHECK-NEXT:    v_mov_b32_e32 v4, s9
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_mul_hi_u32 v5, s8, v1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, s9, v1
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; CHECK-NEXT:    v_mul_hi_u32 v3, s8, v1
-; CHECK-NEXT:    v_mul_hi_u32 v1, s9, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v5, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v6, v0
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_mul_hi_u32 v1, s9, v1
 ; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
 ; CHECK-NEXT:    v_mul_lo_u32 v2, s11, v0
 ; CHECK-NEXT:    v_mul_lo_u32 v1, s10, v1
-; CHECK-NEXT:    v_mul_lo_u32 v3, s10, v0
-; CHECK-NEXT:    v_mul_hi_u32 v0, s10, v0
+; CHECK-NEXT:    v_mul_hi_u32 v3, s10, v0
+; CHECK-NEXT:    v_mul_lo_u32 v0, s10, v0
+; CHECK-NEXT:    v_mov_b32_e32 v5, s9
 ; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; CHECK-NEXT:    v_sub_i32_e32 v1, vcc, s8, v3
-; CHECK-NEXT:    v_subb_u32_e64 v2, s[0:1], v4, v0, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v0, s[0:1], s9, v0
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, s8, v0
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[0:1], v5, v1, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[0:1], s9, v1
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v2
+; CHECK-NEXT:    v_mov_b32_e32 v4, s11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v1
-; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
 ; CHECK-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v2
-; CHECK-NEXT:    v_subb_u32_e32 v0, vcc, v0, v6, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v3, v4, s[0:1]
-; CHECK-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v1
-; CHECK-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s11, v0
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, v3, v5, s[0:1]
+; CHECK-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v0
+; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s11, v1
 ; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v4, v5, vcc
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v1
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v5, vcc
 ; CHECK-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v3
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v3, v4, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
 ; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v0, s6, v0
 ; CHECK-NEXT:    v_subrev_i32_e32 v0, vcc, s6, v0
 ; CHECK-NEXT:    s_mov_b32 s1, 0
 ; CHECK-NEXT:    s_branch BB1_3
 ; CHECK-NEXT:  BB1_2:
 ; CHECK-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; CHECK-NEXT:  BB1_3: ; %Flow
 ; CHECK-NEXT:    s_xor_b32 s0, s1, -1

 
 define <2 x i64> @v_srem_v2i64(<2 x i64> %num, <2 x i64> %den) {
 ; GISEL-LABEL: v_srem_v2i64:
 ; GISEL:       ; %bb.0:
 ; GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v8, 31, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v8
 ; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v8
+; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v8
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, v5
-; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v16, 31, v1
 ; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, 0, v4
-; GISEL-NEXT:    v_subb_u32_e32 v12, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
 ; GISEL-NEXT:    v_mul_f32_e32 v8, 0x5f7ffffc, v8
 ; GISEL-NEXT:    v_mul_f32_e32 v9, 0x2f800000, v8
 ; GISEL-NEXT:    v_trunc_f32_e32 v9, v9
 ; GISEL-NEXT:    v_mac_f32_e32 v8, 0xcf800000, v9
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v9, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
-; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v14, v11, v9
-; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v8
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v15
-; GISEL-NEXT:    v_mul_lo_u32 v16, v8, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v9
+; GISEL-NEXT:    v_mul_hi_u32 v14, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v8
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v15
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v16
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v16, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT:    v_mul_lo_u32 v18, v9, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v15
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v17, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_mul_hi_u32 v16, v8, v13
-; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v13
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT:    v_mul_hi_u32 v17, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v18, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
 ; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
+; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
+; GISEL-NEXT:    v_mul_hi_u32 v12, v9, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v14
-; GISEL-NEXT:    v_addc_u32_e64 v14, s[4:5], v9, v13, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v12, v8
-; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v14
-; GISEL-NEXT:    v_mul_lo_u32 v16, v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v11, v8
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v16
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v14, v16
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v13
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v9, v12, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
+; GISEL-NEXT:    v_mul_lo_u32 v14, v13, v10
 ; GISEL-NEXT:    v_mul_lo_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v16, v14, v16
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
+; GISEL-NEXT:    v_mul_hi_u32 v12, v8, v10
+; GISEL-NEXT:    v_mul_lo_u32 v17, v13, v11
+; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v13, v14, v11
 ; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; GISEL-NEXT:    v_mul_hi_u32 v15, v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v14, v11
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v17, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v11, v13, v11
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v16
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v16
 ; GISEL-NEXT:    v_addc_u32_e32 v9, vcc, 0, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v1, v8
-; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v9
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v8
+; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v8
+; GISEL-NEXT:    v_mul_lo_u32 v11, v0, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v9
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v1, v8
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
 ; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v8
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v9, v1, v9
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v8
 ; GISEL-NEXT:    v_mul_lo_u32 v9, v4, v9
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
-; GISEL-NEXT:    v_mul_hi_u32 v8, v4, v8
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
-; GISEL-NEXT:    v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v8
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v8
+; GISEL-NEXT:    v_ashrrev_i32_e32 v14, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v9, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v9
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, v8, v11, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, v0, v4
-; GISEL-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v0, v4
+; GISEL-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v1, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
+; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v10, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; GISEL-NEXT:    v_ashrrev_i32_e32 v5, 31, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v5
+; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, v7, v5, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v6, v6, v5
+; GISEL-NEXT:    v_xor_b32_e32 v5, v7, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v13, v5
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v13
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v7, v7
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
 ; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v4, 31, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v4
-; GISEL-NEXT:    v_addc_u32_e32 v6, vcc, v7, v4, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v4
-; GISEL-NEXT:    v_xor_b32_e32 v4, v6, v4
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v6, v5
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, v4
-; GISEL-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v4, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
-; GISEL-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; GISEL-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v7
+; GISEL-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v7, v7
-; GISEL-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v8
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v8
-; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v6
-; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v7
-; GISEL-NEXT:    v_mul_hi_u32 v15, v9, v6
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v6
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v14
-; GISEL-NEXT:    v_mul_lo_u32 v15, v6, v12
-; GISEL-NEXT:    v_mul_hi_u32 v16, v6, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v7, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v9, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v10, v9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v11, v8, v7
+; GISEL-NEXT:    v_mul_hi_u32 v12, v8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v13, v8, v4
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v16
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v10
+; GISEL-NEXT:    v_mul_hi_u32 v15, v4, v13
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v14, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v17, v7, v10
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v15
+; GISEL-NEXT:    v_mul_hi_u32 v15, v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v17, v13
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v16, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; GISEL-NEXT:    v_mul_hi_u32 v15, v6, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
 ; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v13
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v7, v12, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v6
-; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v13
-; GISEL-NEXT:    v_mul_lo_u32 v15, v9, v6
-; GISEL-NEXT:    v_mul_hi_u32 v9, v9, v6
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v12
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_mul_hi_u32 v12, v6, v15
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_mul_lo_u32 v11, v13, v15
-; GISEL-NEXT:    v_mul_lo_u32 v14, v6, v9
-; GISEL-NEXT:    v_mul_hi_u32 v15, v13, v15
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v12, v13, v9
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; GISEL-NEXT:    v_mul_hi_u32 v14, v6, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v13, v9
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; GISEL-NEXT:    v_mul_hi_u32 v10, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; GISEL-NEXT:    v_addc_u32_e64 v11, s[4:5], v7, v10, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v9, v9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v11
+; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v4
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v8
+; GISEL-NEXT:    v_mul_lo_u32 v13, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v8
+; GISEL-NEXT:    v_mul_lo_u32 v15, v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v8, v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v15, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v9, v11, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v10
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
 ; GISEL-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v6
-; GISEL-NEXT:    v_mul_lo_u32 v11, v2, v7
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v10, vcc
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v3, v6
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v8, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v2, v7
+; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v7
+; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v2, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v3, v7
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v11, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_mul_lo_u32 v9, v4, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_mul_hi_u32 v7, v3, v7
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v9, v5, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v6, v7
+; GISEL-NEXT:    v_mul_lo_u32 v8, v6, v4
+; GISEL-NEXT:    v_mul_hi_u32 v4, v6, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v16
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v16, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v4
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v2, v5
-; GISEL-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
+; GISEL-NEXT:    v_subb_u32_e64 v7, s[4:5], v3, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v5
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, v2, v6
+; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v3, vcc
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v5
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v4
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v6
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v5
+; GISEL-NEXT:    v_sub_i32_e32 v5, vcc, v8, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v10, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; GISEL-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v8
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v8
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v14, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_mov_b32_e32 v9, v1
 ; CGP-NEXT:    v_mov_b32_e32 v8, v0
 ; CGP-NEXT:    v_or_b32_e32 v1, v9, v5
 ; CGP-NEXT:    v_mov_b32_e32 v0, 0
 ; CGP-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[0:1]
 ; CGP-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; CGP-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; CGP-NEXT:    s_xor_b64 s[6:7], exec, s[4:5]
 ; CGP-NEXT:    s_cbranch_execz BB2_2
 ; CGP-NEXT:  ; %bb.1:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v0, 31, v5
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v4, v0
 ; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v0, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; CGP-NEXT:    v_xor_b32_e32 v0, v5, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v5, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v10, v0
-; CGP-NEXT:    v_ashrrev_i32_e32 v11, 31, v9
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v0, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v17, 31, v9
 ; CGP-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v10
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v5, v5
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v8, v11
-; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
-; CGP-NEXT:    v_mul_f32_e32 v12, 0x2f800000, v5
-; CGP-NEXT:    v_trunc_f32_e32 v12, v12
-; CGP-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v12
+; CGP-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v5
+; CGP-NEXT:    v_trunc_f32_e32 v10, v10
+; CGP-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v10
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; CGP-NEXT:    v_cvt_u32_f32_e32 v12, v12
-; CGP-NEXT:    v_subb_u32_e32 v14, vcc, 0, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v10, v10, v11
-; CGP-NEXT:    v_mul_lo_u32 v15, v14, v5
-; CGP-NEXT:    v_mul_lo_u32 v16, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v5
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v5
-; CGP-NEXT:    v_xor_b32_e32 v9, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v17
-; CGP-NEXT:    v_mul_lo_u32 v18, v5, v15
-; CGP-NEXT:    v_mul_hi_u32 v19, v5, v17
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v5
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v10
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v5
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v5
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CGP-NEXT:    v_mul_lo_u32 v14, v10, v15
+; CGP-NEXT:    v_mul_lo_u32 v16, v5, v13
+; CGP-NEXT:    v_mul_hi_u32 v19, v5, v15
+; CGP-NEXT:    v_add_i32_e32 v18, vcc, v8, v17
+; CGP-NEXT:    v_addc_u32_e32 v9, vcc, v9, v17, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_mul_lo_u32 v20, v10, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v10, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v19
+; CGP-NEXT:    v_mul_hi_u32 v19, v5, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v20, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v19, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
-; CGP-NEXT:    v_mul_hi_u32 v18, v5, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v19
 ; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v16
-; CGP-NEXT:    v_addc_u32_e64 v16, s[4:5], v12, v15, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v14, v5
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v18, v13, v5
-; CGP-NEXT:    v_mul_hi_u32 v13, v13, v5
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v14
+; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v5
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v5
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v5
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
 ; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_mul_hi_u32 v15, v5, v18
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v16, v18
-; CGP-NEXT:    v_mul_lo_u32 v17, v5, v13
-; CGP-NEXT:    v_mul_hi_u32 v18, v16, v18
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v15, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
-; CGP-NEXT:    v_mul_hi_u32 v17, v5, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v17, s[4:5], v18, v17
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
+; CGP-NEXT:    v_mul_lo_u32 v15, v14, v11
+; CGP-NEXT:    v_mul_lo_u32 v16, v5, v12
+; CGP-NEXT:    v_mul_hi_u32 v13, v5, v11
+; CGP-NEXT:    v_mul_lo_u32 v19, v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v5, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v17, v15
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, v12, v13, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v14
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v12, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v9, v5
-; CGP-NEXT:    v_mul_lo_u32 v14, v10, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v10, v5
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_mul_hi_u32 v12, v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v10, v12, vcc
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
+; CGP-NEXT:    v_xor_b32_e32 v18, v18, v17
+; CGP-NEXT:    v_xor_b32_e32 v9, v9, v17
+; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v5
+; CGP-NEXT:    v_mul_lo_u32 v12, v18, v10
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v5
+; CGP-NEXT:    v_mul_lo_u32 v14, v9, v10
 ; CGP-NEXT:    v_mul_hi_u32 v5, v9, v5
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v9, v12
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v14, v10, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v15, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v14, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
 ; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_mul_lo_u32 v13, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v12, v1, v12
-; CGP-NEXT:    v_mul_lo_u32 v14, v1, v5
-; CGP-NEXT:    v_mul_hi_u32 v5, v1, v5
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v12, v5
-; CGP-NEXT:    v_sub_i32_e32 v10, vcc, v10, v14
-; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v9, v5, vcc
-; CGP-NEXT:    v_sub_i32_e64 v5, s[4:5], v9, v5
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v0
-; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v5, v0, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v9, v9, v13, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v10, v1
-; CGP-NEXT:    v_subbrev_u32_e64 v14, s[4:5], 0, v5, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v0
+; CGP-NEXT:    v_mul_hi_u32 v10, v9, v10
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; CGP-NEXT:    v_mul_lo_u32 v11, v0, v5
+; CGP-NEXT:    v_mul_lo_u32 v10, v1, v10
+; CGP-NEXT:    v_mul_hi_u32 v12, v1, v5
+; CGP-NEXT:    v_mul_lo_u32 v5, v1, v5
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT:    v_sub_i32_e32 v5, vcc, v18, v5
+; CGP-NEXT:    v_subb_u32_e64 v11, s[4:5], v9, v10, vcc
+; CGP-NEXT:    v_sub_i32_e64 v9, s[4:5], v9, v10
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v0
+; CGP-NEXT:    v_subb_u32_e32 v9, vcc, v9, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v10, v10, v12, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, v5, v1
+; CGP-NEXT:    v_subbrev_u32_e64 v13, s[4:5], 0, v9, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v0
-; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v5, v0, vcc
-; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v15, v15, v16, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v9, v0, vcc
+; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v15, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v11
-; CGP-NEXT:    v_xor_b32_e32 v5, v0, v11
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v11
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v5, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v13, v0, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v17
+; CGP-NEXT:    v_xor_b32_e32 v5, v0, v17
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v17
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v5, v17, vcc
 ; CGP-NEXT:  BB2_2: ; %Flow2
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
 ; CGP-NEXT:    s_cbranch_execz BB2_4
 ; CGP-NEXT:  ; %bb.3:
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v0, v4
 ; CGP-NEXT:    v_sub_i32_e32 v1, vcc, 0, v4
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v0, v0

 ; CGP-NEXT:  ; %bb.5:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v7
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v6, v4
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v4
 ; CGP-NEXT:    v_xor_b32_e32 v4, v7, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v8, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v10, vcc, 0, v4, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v15, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v8
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v2, v9
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v9, vcc
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v10, v10
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v10
+; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
+; CGP-NEXT:    v_trunc_f32_e32 v8, v8
+; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v8, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v13, v12, v7
-; CGP-NEXT:    v_mul_lo_u32 v14, v11, v10
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v7
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v7
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v14, v10, v15
-; CGP-NEXT:    v_mul_lo_u32 v16, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v7, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v10, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v8
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
+; CGP-NEXT:    v_mul_lo_u32 v12, v8, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v7, v13
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v2, v15
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v15, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_lo_u32 v18, v8, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v8, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v17, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; CGP-NEXT:    v_mul_hi_u32 v16, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v17
+; CGP-NEXT:    v_mul_hi_u32 v17, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v18, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v14
-; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v12, v7
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v16, v11, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, v11, v7
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; CGP-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v7
+; CGP-NEXT:    v_mul_lo_u32 v9, v9, v7
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v16
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v14, v16
-; CGP-NEXT:    v_mul_lo_u32 v15, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v16, v14, v16
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v13, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v12, v9
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v10
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v9
+; CGP-NEXT:    v_mul_lo_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_hi_u32 v9, v12, v9
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v10, v11, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v3, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, v8, v10
-; CGP-NEXT:    v_mul_hi_u32 v13, v8, v7
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v10, v12, v10
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_xor_b32_e32 v16, v16, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v7
+; CGP-NEXT:    v_mul_lo_u32 v10, v16, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v7
+; CGP-NEXT:    v_mul_lo_u32 v12, v3, v8
 ; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v12, v8, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v12, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v5, v10
-; CGP-NEXT:    v_mul_lo_u32 v12, v5, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v5, v7
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; CGP-NEXT:    v_sub_i32_e32 v8, vcc, v8, v12
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v3, v7, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v4
+; CGP-NEXT:    v_mul_hi_u32 v8, v3, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; CGP-NEXT:    v_mul_lo_u32 v9, v4, v7
+; CGP-NEXT:    v_mul_lo_u32 v8, v5, v8
+; CGP-NEXT:    v_mul_hi_u32 v10, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v16, v7
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v3, v8, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v8
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v4
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v8, v5
-; CGP-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v3, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v8, v8, v10, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, v7, v5
+; CGP-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v3, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v5
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v11, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v10, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v10, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v4, v4, v9
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v9
-; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CGP-NEXT:    v_xor_b32_e32 v4, v4, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v15
+; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v15, vcc
 ; CGP-NEXT:  BB2_6: ; %Flow
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
 ; CGP-NEXT:    s_cbranch_execz BB2_8
 ; CGP-NEXT:  ; %bb.7:
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v3, v6
 ; CGP-NEXT:    v_sub_i32_e32 v4, vcc, 0, v6
 ; CGP-NEXT:    v_mov_b32_e32 v5, 0
; CGP-NEXT:    s_setpc_b64 s[30:31]
   ret <2 x i64> %result
 }
 
 define i64 @v_srem_i64_pow2k_denom(i64 %num) {
 ; CHECK-LABEL: v_srem_i64_pow2k_denom:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x1000
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_movk_i32 s6, 0xf000
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_movk_i32 s6, 0x1000
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v4
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; CHECK-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    s_movk_i32 s6, 0x1000
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v3, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v5, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v1, v3, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v3
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[4:5]
-; CHECK-NEXT:    v_subrev_i32_e32 v5, vcc, s6, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[4:5]
+; CHECK-NEXT:    v_subrev_i32_e32 v4, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
-; CHECK-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v5
-; CHECK-NEXT:    v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
+; CHECK-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v4
+; CHECK-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = srem i64 %num, 4096
   ret i64 %result
 }
 
 define <2 x i64> @v_srem_v2i64_pow2k_denom(<2 x i64> %num) {
 ; GISEL-LABEL: v_srem_v2i64_pow2k_denom:
 ; GISEL:       ; %bb.0:

 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s9
 ; GISEL-NEXT:    s_sub_u32 s11, 0, s8
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s8, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s9
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s8, v0
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s8, v0
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s8, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s8, v6
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v5, v8
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
-; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v5
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
+; GISEL-NEXT:    s_subb_u32 s9, 0, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
 ; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v2, v5
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s6, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s7
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v3, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v2
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v2
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v6
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s6, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v7
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s6, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64_pow2k_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x1000
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_movk_i32 s6, 0xf000
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_movk_i32 s7, 0x1000
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v8
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v11, vcc, s7, v9
-; CGP-NEXT:    v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v7, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v10, vcc, s7, v8
+; CGP-NEXT:    v_subbrev_u32_e32 v11, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v8, v10, vcc
+; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v4
+; CGP-NEXT:    v_trunc_f32_e32 v8, v8
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v8
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v5, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s6, v8
+; CGP-NEXT:    v_mul_hi_u32 v7, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v6, v8, v9
+; CGP-NEXT:    v_mul_lo_u32 v7, v4, v5
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v8, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_addc_u32_e64 v6, s[4:5], v8, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v7, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v6, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v7
+; CGP-NEXT:    v_mul_hi_u32 v8, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v7
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v6, v7
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v5, s7, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; CGP-NEXT:    v_mul_hi_u32 v4, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; CGP-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; CGP-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v7, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v6, vcc, s7, v2
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v7
-; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = srem <2 x i64> %num, <i64 4096, i64 4096>
   ret <2 x i64> %result
 }
 
 define i64 @v_srem_i64_oddk_denom(i64 %num) {
 ; CHECK-LABEL: v_srem_i64_oddk_denom:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v2, 0x12d8fb
-; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v4, 0
+; CHECK-NEXT:    v_cvt_f32_ubyte0_e32 v3, 0
 ; CHECK-NEXT:    s_mov_b32 s6, 0xffed2705
-; CHECK-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v4
+; CHECK-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
-; CHECK-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v2
-; CHECK-NEXT:    v_trunc_f32_e32 v4, v4
-; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v4
+; CHECK-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
+; CHECK-NEXT:    v_trunc_f32_e32 v3, v3
+; CHECK-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; CHECK-NEXT:    v_mul_lo_u32 v5, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v4
-; CHECK-NEXT:    v_mul_hi_u32 v8, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
-; CHECK-NEXT:    v_mul_lo_u32 v6, v4, v7
-; CHECK-NEXT:    v_mul_lo_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v7, v4, v7
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v7, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v6
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v4
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v6
+; CHECK-NEXT:    v_add_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v4
+; CHECK-NEXT:    v_mul_hi_u32 v6, v3, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; CHECK-NEXT:    v_mul_hi_u32 v8, v2, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v4, v5
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CHECK-NEXT:    v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, -1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v8, s6, v6
-; CHECK-NEXT:    v_mul_hi_u32 v10, s6, v2
-; CHECK-NEXT:    v_mul_lo_u32 v9, s6, v2
-; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v5
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v10
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v5, v2, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
-; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v8, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v10, v5
-; CHECK-NEXT:    v_mul_hi_u32 v10, v2, v7
-; CHECK-NEXT:    v_mul_hi_u32 v6, v6, v7
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; CHECK-NEXT:    v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v6, -1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, s6, v5
+; CHECK-NEXT:    v_mul_hi_u32 v9, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v10, s6, v2
+; CHECK-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v4
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
+; CHECK-NEXT:    v_mul_lo_u32 v7, v5, v10
+; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v6
+; CHECK-NEXT:    v_mul_hi_u32 v4, v2, v10
+; CHECK-NEXT:    v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v10, v5, v10
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v10
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_mul_hi_u32 v7, v2, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v9, v4
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
 ; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
-; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v7
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, v4, v6, vcc
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v5, v1, v2
-; CHECK-NEXT:    v_mul_lo_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v7, v0, v2
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; CHECK-NEXT:    v_mul_hi_u32 v5, v5, v6
+; CHECK-NEXT:    v_add_i32_e64 v4, s[4:5], v7, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; CHECK-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v4, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v5, v0, v3
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v3
 ; CHECK-NEXT:    v_mul_hi_u32 v2, v1, v2
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v4
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v4
-; CHECK-NEXT:    v_mul_hi_u32 v4, v1, v4
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CHECK-NEXT:    v_mul_hi_u32 v6, v0, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CHECK-NEXT:    v_mul_lo_u32 v5, 0, v2
-; CHECK-NEXT:    v_mul_lo_u32 v4, s6, v4
-; CHECK-NEXT:    v_mul_lo_u32 v6, s6, v2
-; CHECK-NEXT:    v_mul_hi_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CHECK-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; CHECK-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v2, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v2
-; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v4
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
+; CHECK-NEXT:    s_mov_b32 s6, 0x12d8fb
+; CHECK-NEXT:    v_mul_lo_u32 v4, 0, v2
+; CHECK-NEXT:    v_mul_lo_u32 v3, s6, v3
+; CHECK-NEXT:    v_mul_hi_u32 v5, s6, v2
+; CHECK-NEXT:    v_mul_lo_u32 v2, s6, v2
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
+; CHECK-NEXT:    v_subb_u32_e64 v2, s[4:5], v1, v3, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v3
+; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[4:5]
 ; CHECK-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v0
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CHECK-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v2
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[4:5]
-; CHECK-NEXT:    v_subrev_i32_e32 v5, vcc, s6, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[4:5]
+; CHECK-NEXT:    v_subrev_i32_e32 v4, vcc, s6, v0
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
+; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v4
 ; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; CHECK-NEXT:    v_cmp_le_u32_e32 vcc, s6, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
 ; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc
-; CHECK-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v5
-; CHECK-NEXT:    v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v8, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v3
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v3
-; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v3
-; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
+; CHECK-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v4
+; CHECK-NEXT:    v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
+; CHECK-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v0, v0, v8
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v8
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
+; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; CHECK-NEXT:    s_setpc_b64 s[30:31]
   %result = srem i64 %num, 1235195
   ret i64 %result
 }
 
 define <2 x i64> @v_srem_v2i64_oddk_denom(<2 x i64> %num) {
 ; GISEL-LABEL: v_srem_v2i64_oddk_denom:
 ; GISEL:       ; %bb.0:

 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s9
 ; GISEL-NEXT:    s_sub_u32 s11, 0, s8
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
 ; GISEL-NEXT:    s_subb_u32 s12, 0, s9
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s11, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s11, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s11, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v4
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_lo_u32 v12, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s12, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v12, s11, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s11, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s12, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s11, v7
+; GISEL-NEXT:    v_mul_hi_u32 v11, s11, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, s11, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v12
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v11, v6
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v1, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, v1, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s8, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s8, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s8, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s9
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v1, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v0
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v5
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s8, v0
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v1, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v4
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s8, v0
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v1, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s8, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s9, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
 ; GISEL-NEXT:    s_add_u32 s4, s10, 0
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GISEL-NEXT:    s_cselect_b32 s5, 1, 0
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s8, v7
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
 ; GISEL-NEXT:    s_and_b32 s5, s5, 1
 ; GISEL-NEXT:    s_cmp_lg_u32 s5, 0
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s8, v6
 ; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GISEL-NEXT:    s_addc_u32 s5, 0, 0
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
 ; GISEL-NEXT:    s_xor_b64 s[6:7], s[4:5], s[6:7]
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v4, s6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v5, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, s6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v9, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
+; GISEL-NEXT:    v_mac_f32_e32 v8, 0x4f800000, v9
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v5, v8
 ; GISEL-NEXT:    s_sub_u32 s8, 0, s6
 ; GISEL-NEXT:    s_cselect_b32 s4, 1, 0
 ; GISEL-NEXT:    s_and_b32 s4, s4, 1
-; GISEL-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v7, vcc
-; GISEL-NEXT:    s_subb_u32 s9, 0, s7
-; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
+; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v5
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v6
-; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, s8, v5
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
-; GISEL-NEXT:    v_mul_hi_u32 v10, s8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; GISEL-NEXT:    s_cmp_lg_u32 s4, 0
+; GISEL-NEXT:    s_subb_u32 s9, 0, s7
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v6, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, s8, v5
+; GISEL-NEXT:    v_mul_hi_u32 v8, s8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v4
-; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_ashrrev_i32_e32 v11, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v9
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v6
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v8, v5, v9
-; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v5, v6
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_mul_hi_u32 v10, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v13, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
-; GISEL-NEXT:    v_addc_u32_e64 v8, s[4:5], v5, v7, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, s9, v4
-; GISEL-NEXT:    v_mul_lo_u32 v10, s8, v8
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v6, v5, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_addc_u32_e64 v7, s[4:5], v5, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, s9, v4
+; GISEL-NEXT:    v_mul_lo_u32 v9, s8, v7
 ; GISEL-NEXT:    v_mul_hi_u32 v12, s8, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, s8, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_mul_lo_u32 v13, s8, v4
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v6
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v9, v7, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v13
+; GISEL-NEXT:    v_mul_lo_u32 v14, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v7, v4, v11
-; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v10, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v12, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v12, v6
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v10
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v8
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], v9, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GISEL-NEXT:    v_mul_lo_u32 v6, v3, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v2, v5
+; GISEL-NEXT:    v_xor_b32_e32 v0, v0, v10
+; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v10
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v1, v10, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v3, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v4
-; GISEL-NEXT:    v_mov_b32_e32 v9, s7
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, s7, v4
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; GISEL-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, s6, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, s6, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, s6, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mul_hi_u32 v7, s6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, s6, v4
+; GISEL-NEXT:    v_mov_b32_e32 v8, s7
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v3, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v5
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v2
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v5
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; GISEL-NEXT:    v_subrev_i32_e32 v7, vcc, s6, v2
-; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v9, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v4
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[4:5]
+; GISEL-NEXT:    v_subrev_i32_e32 v6, vcc, s6, v2
+; GISEL-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v6
+; GISEL-NEXT:    v_subrev_i32_e32 v8, vcc, s6, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_le_u32_e64 s[4:5], s6, v7
-; GISEL-NEXT:    v_subrev_i32_e32 v9, vcc, s6, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], s7, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v6
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v11
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v11
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v11
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v11, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64_oddk_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, 0x12d8fb
-; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v6, 0
+; CGP-NEXT:    v_cvt_f32_ubyte0_e32 v5, 0
 ; CGP-NEXT:    s_mov_b32 s6, 0xffed2705
-; CGP-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; CGP-NEXT:    v_mov_b32_e32 v7, v4
-; CGP-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v6
-; CGP-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
-; CGP-NEXT:    v_trunc_f32_e32 v8, v8
-; CGP-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
+; CGP-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
+; CGP-NEXT:    v_mov_b32_e32 v6, v4
+; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; CGP-NEXT:    s_mov_b32 s7, 0x12d8fb
-; CGP-NEXT:    v_mul_lo_u32 v9, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v11, s6, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v10, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v8, v11
+; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v5
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v9
-; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, -1, v7
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v10
-; CGP-NEXT:    v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT:    v_mul_lo_u32 v13, s6, v7
-; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v9, v7, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v12, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v14, v9
-; CGP-NEXT:    v_mul_hi_u32 v14, v7, v11
-; CGP-NEXT:    v_mul_hi_u32 v10, v10, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
-; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v12
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, v8, v10, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v9, v1, v7
-; CGP-NEXT:    v_mul_lo_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v11, v0, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
-; CGP-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
+; CGP-NEXT:    v_mul_lo_u32 v9, -1, v6
+; CGP-NEXT:    v_mul_lo_u32 v8, s6, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, s6, v6
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_lo_u32 v9, v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v10, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v11
+; CGP-NEXT:    v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_addc_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v8
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v1, v8
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_mul_hi_u32 v10, v0, v8
-; CGP-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_mul_lo_u32 v9, 0, v7
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v8
-; CGP-NEXT:    v_mul_lo_u32 v10, s7, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, s7, v7
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v10
-; CGP-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
-; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v8
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v9, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v0
-; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v9
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
-; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT:    v_cndmask_b32_e32 v10, v10, v11, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v11, vcc, s7, v9
-; CGP-NEXT:    v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v11, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v12, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v7, v7
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
-; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, -1, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, s6, v7
-; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v10, s6, v4
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v6, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
-; CGP-NEXT:    v_mul_lo_u32 v9, v7, v10
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v8
-; CGP-NEXT:    v_mul_hi_u32 v12, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v7, v10
-; CGP-NEXT:    v_xor_b32_e32 v0, v0, v5
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v14, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
-; CGP-NEXT:    v_mul_hi_u32 v11, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; CGP-NEXT:    v_mul_hi_u32 v8, v7, v8
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
 ; CGP-NEXT:    v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
-; CGP-NEXT:    v_mul_lo_u32 v10, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v10, -1, v6
 ; CGP-NEXT:    v_mul_lo_u32 v11, s6, v9
-; CGP-NEXT:    v_mul_hi_u32 v13, s6, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, s6, v4
+; CGP-NEXT:    v_mul_hi_u32 v13, s6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, s6, v6
 ; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v8
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v12
-; CGP-NEXT:    v_mul_lo_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v8, v4, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v9, v12
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v8, v6, v14
+; CGP-NEXT:    v_mul_lo_u32 v15, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v14
 ; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v10
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v11, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v13, v8
-; CGP-NEXT:    v_mul_hi_u32 v13, v4, v10
-; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v9, v9, v10
 ; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v12, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
 ; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
 ; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v5
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v4
-; CGP-NEXT:    v_mul_lo_u32 v9, v2, v7
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v5, vcc
-; CGP-NEXT:    v_mul_hi_u32 v5, v2, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v8, v1, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v0, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v1, v7
+; CGP-NEXT:    v_mul_hi_u32 v6, v1, v6
 ; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v8, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; CGP-NEXT:    v_mul_hi_u32 v9, v2, v7
-; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT:    v_mul_hi_u32 v10, v0, v7
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_mul_hi_u32 v7, v1, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_lo_u32 v8, 0, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, s7, v7
+; CGP-NEXT:    v_mul_hi_u32 v9, s7, v6
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v6
+; CGP-NEXT:    v_subb_u32_e64 v6, s[4:5], v1, v7, vcc
+; CGP-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v7
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v0
+; CGP-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v1
+; CGP-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v10, vcc, s7, v8
+; CGP-NEXT:    v_subbrev_u32_e32 v11, vcc, 0, v1, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; CGP-NEXT:    v_cndmask_b32_e32 v5, v8, v10, vcc
+; CGP-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v4
+; CGP-NEXT:    v_trunc_f32_e32 v8, v8
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v8
+; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v1, v11, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
+; CGP-NEXT:    v_mul_lo_u32 v5, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s6, v8
+; CGP-NEXT:    v_mul_hi_u32 v7, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v4
+; CGP-NEXT:    v_ashrrev_i32_e32 v10, 31, v3
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_mul_lo_u32 v6, v8, v9
+; CGP-NEXT:    v_mul_lo_u32 v7, v4, v5
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v9
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_mul_lo_u32 v13, v8, v5
+; CGP-NEXT:    v_mul_hi_u32 v9, v8, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v4, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v13, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v5, v8, v5
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_addc_u32_e64 v6, s[4:5], v8, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v7, -1, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, s6, v6
+; CGP-NEXT:    v_mul_hi_u32 v11, s6, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, s6, v4
+; CGP-NEXT:    v_add_i32_e64 v5, s[4:5], v8, v5
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
+; CGP-NEXT:    v_mul_lo_u32 v9, v6, v13
+; CGP-NEXT:    v_mul_lo_u32 v11, v4, v7
+; CGP-NEXT:    v_mul_hi_u32 v8, v4, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v7
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v13
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; CGP-NEXT:    v_mul_hi_u32 v9, v4, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v6, v6, v7
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v9, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v8
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; CGP-NEXT:    v_mul_lo_u32 v6, v3, v4
+; CGP-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v4
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v5
+; CGP-NEXT:    v_mul_hi_u32 v4, v3, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CGP-NEXT:    v_mul_hi_u32 v8, v2, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CGP-NEXT:    v_mul_hi_u32 v5, v3, v5
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; CGP-NEXT:    v_mul_lo_u32 v7, 0, v4
 ; CGP-NEXT:    v_mul_lo_u32 v5, s7, v5
-; CGP-NEXT:    v_mul_lo_u32 v8, s7, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, s7, v4
 ; CGP-NEXT:    v_mul_hi_u32 v4, s7, v4
+; CGP-NEXT:    v_xor_b32_e32 v0, v0, v12
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v12
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v1, v12, vcc
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
 ; CGP-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
 ; CGP-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
 ; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_le_u32_e64 s[4:5], s7, v2
-; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
 ; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], 0, v5
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
-; CGP-NEXT:    v_subrev_i32_e32 v7, vcc, s7, v2
+; CGP-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[4:5]
+; CGP-NEXT:    v_subrev_i32_e32 v6, vcc, s7, v2
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; CGP-NEXT:    v_cmp_le_u32_e32 vcc, 0, v3
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; CGP-NEXT:    v_cmp_le_u32_e32 vcc, s7, v7
-; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; CGP-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
-; CGP-NEXT:    v_subrev_i32_e32 v9, vcc, s7, v7
-; CGP-NEXT:    v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
-; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
+; CGP-NEXT:    v_subrev_i32_e32 v8, vcc, s7, v6
+; CGP-NEXT:    v_subbrev_u32_e32 v9, vcc, 0, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
 ; CGP-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v2, v2, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v6
-; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v6
-; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; CGP-NEXT:    v_xor_b32_e32 v2, v2, v10
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v10
+; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
+; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %result = srem <2 x i64> %num, <i64 1235195, i64 1235195>
   ret <2 x i64> %result
 }
 
 define i64 @v_srem_i64_pow2_shl_denom(i64 %x, i64 %y) {
 ; CHECK-LABEL: v_srem_i64_pow2_shl_denom:
 ; CHECK:       ; %bb.0:

 ; CHECK-NEXT:  ; %bb.1:
 ; CHECK-NEXT:    v_ashrrev_i32_e32 v2, 31, v5
 ; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v4, v2
 ; CHECK-NEXT:    v_addc_u32_e32 v5, vcc, v5, v2, vcc
 ; CHECK-NEXT:    v_xor_b32_e32 v3, v3, v2
 ; CHECK-NEXT:    v_xor_b32_e32 v2, v5, v2
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v6, v2
-; CHECK-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
+; CHECK-NEXT:    v_sub_i32_e32 v7, vcc, 0, v3
+; CHECK-NEXT:    v_subb_u32_e32 v8, vcc, 0, v2, vcc
+; CHECK-NEXT:    v_ashrrev_i32_e32 v13, 31, v1
 ; CHECK-NEXT:    v_mac_f32_e32 v5, 0x4f800000, v6
 ; CHECK-NEXT:    v_rcp_iflag_f32_e32 v5, v5
-; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v0, v7
-; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v7, vcc
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, 0, v3
 ; CHECK-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v5
-; CHECK-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v5
-; CHECK-NEXT:    v_trunc_f32_e32 v8, v8
-; CHECK-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v8
+; CHECK-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
+; CHECK-NEXT:    v_trunc_f32_e32 v6, v6
+; CHECK-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; CHECK-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; CHECK-NEXT:    v_subb_u32_e32 v10, vcc, 0, v2, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v6, v6, v7
-; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v5
-; CHECK-NEXT:    v_mul_lo_u32 v12, v9, v8
-; CHECK-NEXT:    v_mul_hi_u32 v14, v9, v5
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v5
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
-; CHECK-NEXT:    v_mul_lo_u32 v12, v8, v13
-; CHECK-NEXT:    v_mul_lo_u32 v14, v5, v11
-; CHECK-NEXT:    v_mul_hi_u32 v15, v5, v13
-; CHECK-NEXT:    v_mul_hi_u32 v13, v8, v13
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CHECK-NEXT:    v_mul_lo_u32 v10, v8, v5
+; CHECK-NEXT:    v_mul_lo_u32 v9, v7, v6
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v5
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v5
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v11
+; CHECK-NEXT:    v_mul_lo_u32 v12, v5, v9
+; CHECK-NEXT:    v_mul_hi_u32 v15, v5, v11
+; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v0, v13
+; CHECK-NEXT:    v_addc_u32_e32 v1, vcc, v1, v13, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; CHECK-NEXT:    v_mul_lo_u32 v16, v6, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v11
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v10, v15
+; CHECK-NEXT:    v_mul_hi_u32 v15, v5, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v16, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v15, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; CHECK-NEXT:    v_mul_hi_u32 v14, v5, v11
-; CHECK-NEXT:    v_mul_hi_u32 v11, v8, v11
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v15
 ; CHECK-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v12
-; CHECK-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v10, v10, v5
-; CHECK-NEXT:    v_mul_lo_u32 v13, v9, v12
-; CHECK-NEXT:    v_mul_lo_u32 v14, v9, v5
-; CHECK-NEXT:    v_mul_hi_u32 v9, v9, v5
+; CHECK-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
+; CHECK-NEXT:    v_mul_hi_u32 v9, v6, v9
+; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
+; CHECK-NEXT:    v_addc_u32_e64 v10, s[4:5], v6, v9, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v8, v8, v5
+; CHECK-NEXT:    v_mul_lo_u32 v11, v7, v10
+; CHECK-NEXT:    v_mul_hi_u32 v12, v7, v5
+; CHECK-NEXT:    v_mul_lo_u32 v7, v7, v5
+; CHECK-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v9
 ; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_mul_hi_u32 v11, v5, v14
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
-; CHECK-NEXT:    v_mul_lo_u32 v10, v12, v14
-; CHECK-NEXT:    v_mul_lo_u32 v13, v5, v9
-; CHECK-NEXT:    v_mul_hi_u32 v14, v12, v14
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; CHECK-NEXT:    v_mul_lo_u32 v11, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v10
-; CHECK-NEXT:    v_mul_hi_u32 v13, v5, v9
-; CHECK-NEXT:    v_mul_hi_u32 v9, v12, v9
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; CHECK-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CHECK-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CHECK-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; CHECK-NEXT:    v_mul_lo_u32 v11, v10, v7
+; CHECK-NEXT:    v_mul_lo_u32 v12, v5, v8
+; CHECK-NEXT:    v_mul_hi_u32 v9, v5, v7
+; CHECK-NEXT:    v_mul_lo_u32 v15, v10, v8
+; CHECK-NEXT:    v_mul_hi_u32 v7, v10, v7
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_mul_hi_u32 v11, v5, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v15, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
-; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, v8, v9, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; CHECK-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v9, v1, v5
-; CHECK-NEXT:    v_mul_lo_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v11, v6, v5
+; CHECK-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
+; CHECK-NEXT:    v_mul_hi_u32 v8, v10, v8
+; CHECK-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; CHECK-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; CHECK-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, v6, v8, vcc
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_xor_b32_e32 v14, v14, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; CHECK-NEXT:    v_mul_lo_u32 v7, v1, v5
+; CHECK-NEXT:    v_mul_lo_u32 v8, v14, v6
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v5
+; CHECK-NEXT:    v_mul_lo_u32 v10, v1, v6
 ; CHECK-NEXT:    v_mul_hi_u32 v5, v1, v5
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_mul_lo_u32 v11, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; CHECK-NEXT:    v_mul_hi_u32 v10, v6, v8
-; CHECK-NEXT:    v_mul_hi_u32 v8, v1, v8
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT:    v_mul_hi_u32 v9, v14, v6
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
 ; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; CHECK-NEXT:    v_mul_lo_u32 v9, v2, v5
-; CHECK-NEXT:    v_mul_lo_u32 v8, v3, v8
-; CHECK-NEXT:    v_mul_lo_u32 v10, v3, v5
-; CHECK-NEXT:    v_mul_hi_u32 v5, v3, v5
-; CHECK-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; CHECK-NEXT:    v_sub_i32_e32 v6, vcc, v6, v10
-; CHECK-NEXT:    v_subb_u32_e64 v8, s[4:5], v1, v5, vcc
-; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v5
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v2
+; CHECK-NEXT:    v_mul_hi_u32 v6, v1, v6
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; CHECK-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; CHECK-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; CHECK-NEXT:    v_mul_lo_u32 v7, v2, v5
+; CHECK-NEXT:    v_mul_lo_u32 v6, v3, v6
+; CHECK-NEXT:    v_mul_hi_u32 v8, v3, v5
+; CHECK-NEXT:    v_mul_lo_u32 v5, v3, v5
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; CHECK-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT:    v_sub_i32_e32 v5, vcc, v14, v5
+; CHECK-NEXT:    v_subb_u32_e64 v7, s[4:5], v1, v6, vcc
+; CHECK-NEXT:    v_sub_i32_e64 v1, s[4:5], v1, v6
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v2
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s[4:5]
-; CHECK-NEXT:    v_sub_i32_e32 v9, vcc, v6, v3
-; CHECK-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v6, v6, v8, s[4:5]
+; CHECK-NEXT:    v_sub_i32_e32 v8, vcc, v5, v3
+; CHECK-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v1, vcc
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v3
 ; CHECK-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v2
-; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v9, v3
-; CHECK-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
+; CHECK-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; CHECK-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v2
+; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v8, v3
+; CHECK-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
 ; CHECK-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; CHECK-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v10, v1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
-; CHECK-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
-; CHECK-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
-; CHECK-NEXT:    v_xor_b32_e32 v2, v2, v7
-; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v7
-; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
-; CHECK-NEXT:    v_subb_u32_e32 v3, vcc, v1, v7, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; CHECK-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
+; CHECK-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
+; CHECK-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc
+; CHECK-NEXT:    v_xor_b32_e32 v2, v2, v13
+; CHECK-NEXT:    v_xor_b32_e32 v1, v1, v13
+; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v2, v13
+; CHECK-NEXT:    v_subb_u32_e32 v3, vcc, v1, v13, vcc
 ; CHECK-NEXT:  BB7_2: ; %Flow
 ; CHECK-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CHECK-NEXT:    s_xor_b64 exec, exec, s[4:5]
 ; CHECK-NEXT:    s_cbranch_execz BB7_4
 ; CHECK-NEXT:  ; %bb.3:
 ; CHECK-NEXT:    v_cvt_f32_u32_e32 v1, v4
 ; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, 0, v4
 ; CHECK-NEXT:    v_mov_b32_e32 v3, 0

 
 define <2 x i64> @v_srem_v2i64_pow2_shl_denom(<2 x i64> %x, <2 x i64> %y) {
 ; GISEL-LABEL: v_srem_v2i64_pow2_shl_denom:
 ; GISEL:       ; %bb.0:
 ; GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GISEL-NEXT:    s_movk_i32 s6, 0x1000
 ; GISEL-NEXT:    s_mov_b32 s7, 0
 ; GISEL-NEXT:    v_lshl_b64 v[4:5], s[6:7], v4
-; GISEL-NEXT:    v_ashrrev_i32_e32 v9, 31, v1
+; GISEL-NEXT:    v_ashrrev_i32_e32 v15, 31, v1
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v7
+; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v7
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v7, v4
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v8, v5
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v9
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v9, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
+; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, 0, v4
+; GISEL-NEXT:    v_subb_u32_e32 v10, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v7, 0x4f800000, v8
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; GISEL-NEXT:    v_xor_b32_e32 v8, v0, v9
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v16, v1, v9
-; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v7
-; GISEL-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v7, v7
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v7
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; GISEL-NEXT:    v_mul_f32_e32 v7, 0x5f7ffffc, v7
+; GISEL-NEXT:    v_mul_f32_e32 v8, 0x2f800000, v7
+; GISEL-NEXT:    v_trunc_f32_e32 v8, v8
+; GISEL-NEXT:    v_mac_f32_e32 v7, 0xcf800000, v8
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v7
-; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v0
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v9, v8
+; GISEL-NEXT:    v_mul_hi_u32 v13, v9, v7
+; GISEL-NEXT:    v_mul_lo_u32 v14, v9, v7
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v14
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v11
+; GISEL-NEXT:    v_mul_hi_u32 v16, v7, v14
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v15
+; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v15, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v14
-; GISEL-NEXT:    v_mul_lo_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v1, v0, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v7, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v13, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v15, v1
-; GISEL-NEXT:    v_mul_hi_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v12
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT:    v_mul_lo_u32 v17, v8, v11
+; GISEL-NEXT:    v_mul_hi_u32 v14, v8, v14
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
+; GISEL-NEXT:    v_mul_hi_u32 v16, v7, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v17, v14
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v13, v1
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; GISEL-NEXT:    v_mul_hi_u32 v11, v8, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GISEL-NEXT:    v_addc_u32_e64 v1, s[4:5], v7, v12, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v1
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v0
-; GISEL-NEXT:    v_mul_hi_u32 v10, v10, v0
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v12
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v14
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; GISEL-NEXT:    v_mul_lo_u32 v11, v1, v14
-; GISEL-NEXT:    v_mul_lo_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v14, v1, v14
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v12, v1, v10
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
-; GISEL-NEXT:    v_mul_hi_u32 v13, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v1, v1, v10
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v13, v12
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v10
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v0, v11
-; GISEL-NEXT:    v_addc_u32_e32 v10, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v16, v7
-; GISEL-NEXT:    v_mul_lo_u32 v12, v8, v10
-; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v16, v7
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v16, v10
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GISEL-NEXT:    v_mul_hi_u32 v12, v8, v10
-; GISEL-NEXT:    v_mul_hi_u32 v10, v16, v10
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GISEL-NEXT:    v_addc_u32_e64 v12, s[4:5], v8, v11, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v10, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v13, v9, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v9, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v9, v7
+; GISEL-NEXT:    v_xor_b32_e32 v16, v0, v15
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v10, v13
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v14
+; GISEL-NEXT:    v_mul_lo_u32 v10, v12, v9
+; GISEL-NEXT:    v_mul_lo_u32 v13, v7, v0
+; GISEL-NEXT:    v_xor_b32_e32 v14, v1, v15
+; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v8, v11
+; GISEL-NEXT:    v_mul_hi_u32 v8, v7, v9
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
+; GISEL-NEXT:    v_mul_lo_u32 v13, v12, v0
+; GISEL-NEXT:    v_mul_hi_u32 v9, v12, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v10, v8
+; GISEL-NEXT:    v_mul_hi_u32 v10, v7, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v13, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
+; GISEL-NEXT:    v_mul_hi_u32 v0, v12, v0
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v10, v9
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], v0, v9
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, v1, v0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v7, v8
+; GISEL-NEXT:    v_addc_u32_e32 v0, vcc, 0, v0, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v7, v14, v1
+; GISEL-NEXT:    v_mul_lo_u32 v8, v16, v0
+; GISEL-NEXT:    v_mul_hi_u32 v9, v16, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v14, v0
+; GISEL-NEXT:    v_mul_hi_u32 v1, v14, v1
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v16, v0
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v6
-; GISEL-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v6
-; GISEL-NEXT:    v_mul_hi_u32 v6, v4, v6
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v8, v11
-; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v16, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v6, s[4:5], v16, v6
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v0, v14, v0
+; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v1, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v7, v5, v1
+; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v0
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v1
+; GISEL-NEXT:    v_mul_lo_u32 v10, v4, v1
+; GISEL-NEXT:    v_lshl_b64 v[0:1], s[6:7], v6
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v7, v8
+; GISEL-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v16, v10
+; GISEL-NEXT:    v_subb_u32_e64 v8, s[4:5], v14, v6, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v6, s[4:5], v14, v6
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v5
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v6, vcc, v6, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v11, vcc, v7, v4
-; GISEL-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v6, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, v7, v4
+; GISEL-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v6, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v5
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v5
 ; GISEL-NEXT:    v_subb_u32_e32 v5, vcc, v6, v5, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v11, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v10, v4
 ; GISEL-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v12, v5, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
 ; GISEL-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
-; GISEL-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v6, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v7, v0, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
+; GISEL-NEXT:    v_xor_b32_e32 v13, v0, v6
 ; GISEL-NEXT:    v_xor_b32_e32 v6, v1, v6
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v7
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v0, v13
 ; GISEL-NEXT:    v_cvt_f32_u32_e32 v1, v6
-; GISEL-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
-; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v9
-; GISEL-NEXT:    v_xor_b32_e32 v5, v5, v9
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v5, v11, v5, vcc
 ; GISEL-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GISEL-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GISEL-NEXT:    v_add_i32_e32 v1, vcc, v2, v8
-; GISEL-NEXT:    v_addc_u32_e32 v2, vcc, v3, v8, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v3, v1, v8
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v7, v4, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v4, v8, v5, vcc
 ; GISEL-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GISEL-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GISEL-NEXT:    v_trunc_f32_e32 v1, v1
-; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v0
+; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
+; GISEL-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GISEL-NEXT:    v_sub_i32_e32 v10, vcc, 0, v7
-; GISEL-NEXT:    v_subb_u32_e32 v11, vcc, 0, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v13, v10, v1
-; GISEL-NEXT:    v_mul_hi_u32 v15, v10, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v0
-; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v8
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT:    v_mul_lo_u32 v13, v1, v14
-; GISEL-NEXT:    v_mul_lo_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v14
-; GISEL-NEXT:    v_mul_hi_u32 v14, v1, v14
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v16, v1, v12
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v15, v13
-; GISEL-NEXT:    v_mul_hi_u32 v15, v0, v12
-; GISEL-NEXT:    v_mul_hi_u32 v12, v1, v12
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v13
+; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v6, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
+; GISEL-NEXT:    v_mul_hi_u32 v11, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v0
+; GISEL-NEXT:    v_ashrrev_i32_e32 v14, 31, v3
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v0, v9
+; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v12
+; GISEL-NEXT:    v_add_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_addc_u32_e32 v3, vcc, v3, v14, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_mul_lo_u32 v17, v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v16
+; GISEL-NEXT:    v_mul_hi_u32 v16, v0, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v17, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v16
 ; GISEL-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v13
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], v1, v12, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v11, v11, v0
-; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v13
-; GISEL-NEXT:    v_mul_lo_u32 v15, v10, v0
-; GISEL-NEXT:    v_mul_hi_u32 v10, v10, v0
-; GISEL-NEXT:    v_add_i32_e64 v1, s[4:5], v1, v12
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_mul_hi_u32 v12, v0, v15
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v11, v10
-; GISEL-NEXT:    v_mul_lo_u32 v11, v13, v15
-; GISEL-NEXT:    v_mul_lo_u32 v14, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v15, v13, v15
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v16
+; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v0
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v0
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v0, v8
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v16, v10, v8
+; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v0, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v16, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v12, v13, v10
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
-; GISEL-NEXT:    v_mul_hi_u32 v14, v0, v10
-; GISEL-NEXT:    v_mul_hi_u32 v10, v13, v10
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v14, v12
-; GISEL-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v12
-; GISEL-NEXT:    v_addc_u32_e32 v1, vcc, v1, v10, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v0, v11
-; GISEL-NEXT:    v_addc_u32_e32 v11, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v12, v2, v10
-; GISEL-NEXT:    v_mul_lo_u32 v13, v3, v11
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v4, v3, v10
-; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v5, v9, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v12, v13
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v5, v2, v11
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v10
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v11
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v8, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v0
+; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v0
+; GISEL-NEXT:    v_mul_lo_u32 v10, v3, v5
+; GISEL-NEXT:    v_mul_hi_u32 v0, v3, v0
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v5
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v10, v0
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT:    v_mul_hi_u32 v10, v2, v11
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
-; GISEL-NEXT:    v_mul_lo_u32 v9, v6, v4
-; GISEL-NEXT:    v_mul_lo_u32 v5, v7, v5
-; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v7, v4
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v3, vcc, v3, v10
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v2, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v2, s[4:5], v2, v4
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GISEL-NEXT:    v_add_i32_e32 v0, vcc, v0, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GISEL-NEXT:    v_mul_lo_u32 v8, v6, v0
+; GISEL-NEXT:    v_mul_lo_u32 v5, v13, v5
+; GISEL-NEXT:    v_mul_hi_u32 v9, v13, v0
+; GISEL-NEXT:    v_xor_b32_e32 v1, v1, v15
+; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v0
+; GISEL-NEXT:    v_xor_b32_e32 v4, v4, v15
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v1, v15
+; GISEL-NEXT:    v_subb_u32_e32 v1, vcc, v4, v15, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v8, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v7
+; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v4
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v3, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v6
-; GISEL-NEXT:    v_subb_u32_e32 v2, vcc, v2, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v9, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v9, vcc, v3, v7
-; GISEL-NEXT:    v_subbrev_u32_e64 v10, s[4:5], 0, v2, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v7
-; GISEL-NEXT:    v_subb_u32_e32 v2, vcc, v2, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v6
-; GISEL-NEXT:    v_sub_i32_e32 v6, vcc, v9, v7
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[4:5]
-; GISEL-NEXT:    v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11
-; GISEL-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v10, v2, vcc
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v2, v13
+; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v6
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v13
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v6
+; GISEL-NEXT:    v_sub_i32_e32 v6, vcc, v7, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[4:5]
+; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
 ; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
-; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v8
-; GISEL-NEXT:    v_xor_b32_e32 v4, v2, v8
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v3, v8
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v4, v8, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT:    v_xor_b32_e32 v2, v2, v14
+; GISEL-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v14
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v14, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64_pow2_shl_denom:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    s_movk_i32 s4, 0x1000
 ; CGP-NEXT:    s_mov_b32 s5, 0
 ; CGP-NEXT:    v_lshl_b64 v[10:11], s[4:5], v4

 ; CGP-NEXT:  ; %bb.1:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v0, 31, v11
 ; CGP-NEXT:    v_add_i32_e32 v1, vcc, v10, v0
 ; CGP-NEXT:    v_addc_u32_e32 v4, vcc, v11, v0, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; CGP-NEXT:    v_xor_b32_e32 v0, v4, v0
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v4, v1
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, v0
-; CGP-NEXT:    v_ashrrev_i32_e32 v11, 31, v7
+; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v1
+; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v0, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v17, 31, v7
 ; CGP-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v5, v11
-; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v11, vcc
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, 0, v1
 ; CGP-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
-; CGP-NEXT:    v_mul_f32_e32 v12, 0x2f800000, v4
-; CGP-NEXT:    v_trunc_f32_e32 v12, v12
-; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v12
+; CGP-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v4
+; CGP-NEXT:    v_trunc_f32_e32 v6, v6
+; CGP-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v6
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; CGP-NEXT:    v_cvt_u32_f32_e32 v12, v12
-; CGP-NEXT:    v_subb_u32_e32 v14, vcc, 0, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v6, v6, v11
-; CGP-NEXT:    v_mul_lo_u32 v15, v14, v4
-; CGP-NEXT:    v_mul_lo_u32 v16, v13, v12
-; CGP-NEXT:    v_mul_hi_u32 v18, v13, v4
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v4
-; CGP-NEXT:    v_xor_b32_e32 v7, v7, v11
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v18
-; CGP-NEXT:    v_mul_lo_u32 v16, v12, v17
-; CGP-NEXT:    v_mul_lo_u32 v18, v4, v15
-; CGP-NEXT:    v_mul_hi_u32 v19, v4, v17
-; CGP-NEXT:    v_mul_hi_u32 v17, v12, v17
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT:    v_mul_lo_u32 v14, v12, v4
+; CGP-NEXT:    v_mul_lo_u32 v13, v11, v6
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v4
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v4
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v15
+; CGP-NEXT:    v_mul_lo_u32 v16, v4, v13
+; CGP-NEXT:    v_mul_hi_u32 v19, v4, v15
+; CGP-NEXT:    v_add_i32_e32 v18, vcc, v5, v17
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v17, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT:    v_mul_lo_u32 v20, v6, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v6, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v19, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v18, v16
-; CGP-NEXT:    v_mul_hi_u32 v18, v4, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v12, v15
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v19, v17
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v19
+; CGP-NEXT:    v_mul_hi_u32 v19, v4, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v20, v15
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v19
 ; CGP-NEXT:    v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v17, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v17, vcc, v18, v17
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v16
-; CGP-NEXT:    v_addc_u32_e64 v16, s[4:5], v12, v15, vcc
-; CGP-NEXT:    v_mul_lo_u32 v14, v14, v4
-; CGP-NEXT:    v_mul_lo_u32 v17, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v18, v13, v4
-; CGP-NEXT:    v_mul_hi_u32 v13, v13, v4
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v13
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v14
+; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v6, v13, vcc
+; CGP-NEXT:    v_mul_lo_u32 v12, v12, v4
+; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
+; CGP-NEXT:    v_mul_hi_u32 v16, v11, v4
+; CGP-NEXT:    v_mul_lo_u32 v11, v11, v4
+; CGP-NEXT:    v_add_i32_e64 v6, s[4:5], v6, v13
 ; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_mul_hi_u32 v15, v4, v18
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
-; CGP-NEXT:    v_mul_lo_u32 v14, v16, v18
-; CGP-NEXT:    v_mul_lo_u32 v17, v4, v13
-; CGP-NEXT:    v_mul_hi_u32 v18, v16, v18
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v14, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v15, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v17, v14
-; CGP-NEXT:    v_mul_hi_u32 v17, v4, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v16, v13
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v18
-; CGP-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v17
-; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v17, s[4:5], v18, v17
-; CGP-NEXT:    v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v16
+; CGP-NEXT:    v_mul_lo_u32 v15, v14, v11
+; CGP-NEXT:    v_mul_lo_u32 v16, v4, v12
+; CGP-NEXT:    v_mul_hi_u32 v13, v4, v11
+; CGP-NEXT:    v_mul_lo_u32 v19, v14, v12
+; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v15, v16
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_mul_hi_u32 v15, v4, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v16, v13
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v19, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v15
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v17, v15
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, v12, v13, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v14
-; CGP-NEXT:    v_addc_u32_e32 v12, vcc, 0, v12, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v7, v4
-; CGP-NEXT:    v_mul_lo_u32 v14, v6, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v6, v4
+; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT:    v_mul_hi_u32 v12, v14, v12
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
+; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
+; CGP-NEXT:    v_addc_u32_e32 v6, vcc, v6, v12, vcc
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT:    v_xor_b32_e32 v18, v18, v17
+; CGP-NEXT:    v_xor_b32_e32 v7, v7, v17
+; CGP-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
+; CGP-NEXT:    v_mul_lo_u32 v11, v7, v4
+; CGP-NEXT:    v_mul_lo_u32 v12, v18, v6
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v4
+; CGP-NEXT:    v_mul_lo_u32 v14, v7, v6
 ; CGP-NEXT:    v_mul_hi_u32 v4, v7, v4
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v15, v7, v12
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT:    v_mul_hi_u32 v14, v6, v12
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v12
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v15, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_mul_hi_u32 v13, v18, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v14, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
 ; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; CGP-NEXT:    v_mul_lo_u32 v13, v0, v4
-; CGP-NEXT:    v_mul_lo_u32 v12, v1, v12
-; CGP-NEXT:    v_mul_lo_u32 v14, v1, v4
-; CGP-NEXT:    v_mul_hi_u32 v4, v1, v4
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; CGP-NEXT:    v_add_i32_e32 v4, vcc, v12, v4
-; CGP-NEXT:    v_sub_i32_e32 v6, vcc, v6, v14
-; CGP-NEXT:    v_subb_u32_e64 v12, s[4:5], v7, v4, vcc
-; CGP-NEXT:    v_sub_i32_e64 v4, s[4:5], v7, v4
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v0
+; CGP-NEXT:    v_mul_hi_u32 v6, v7, v6
+; CGP-NEXT:    v_add_i32_e32 v4, vcc, v4, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
+; CGP-NEXT:    v_mul_lo_u32 v11, v0, v4
+; CGP-NEXT:    v_mul_lo_u32 v6, v1, v6
+; CGP-NEXT:    v_mul_hi_u32 v12, v1, v4
+; CGP-NEXT:    v_mul_lo_u32 v4, v1, v4
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v18, v4
+; CGP-NEXT:    v_subb_u32_e64 v11, s[4:5], v7, v6, vcc
+; CGP-NEXT:    v_sub_i32_e64 v6, s[4:5], v7, v6
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v0
 ; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v0
-; CGP-NEXT:    v_subb_u32_e32 v4, vcc, v4, v0, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v13, vcc, v6, v1
-; CGP-NEXT:    v_subbrev_u32_e64 v14, s[4:5], 0, v4, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v14, v0
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v0
+; CGP-NEXT:    v_subb_u32_e32 v6, vcc, v6, v0, vcc
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v12, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v12, vcc, v4, v1
+; CGP-NEXT:    v_subbrev_u32_e64 v13, s[4:5], 0, v6, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v1
 ; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v14, v0
-; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v4, v0, vcc
-; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v13, v1
-; CGP-NEXT:    v_cndmask_b32_e64 v15, v15, v16, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v13, v0
+; CGP-NEXT:    v_subb_u32_e32 v0, vcc, v6, v0, vcc
+; CGP-NEXT:    v_sub_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT:    v_cndmask_b32_e64 v14, v14, v15, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v13, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v14, v0, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v12, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v13, v0, vcc
 ; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; CGP-NEXT:    v_cndmask_b32_e32 v1, v6, v1, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v0, v12, v0, vcc
-; CGP-NEXT:    v_xor_b32_e32 v1, v1, v11
-; CGP-NEXT:    v_xor_b32_e32 v4, v0, v11
-; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v11
-; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v4, v11, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc
+; CGP-NEXT:    v_xor_b32_e32 v1, v1, v17
+; CGP-NEXT:    v_xor_b32_e32 v4, v0, v17
+; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v1, v17
+; CGP-NEXT:    v_subb_u32_e32 v1, vcc, v4, v17, vcc
 ; CGP-NEXT:  BB8_2: ; %Flow2
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
 ; CGP-NEXT:    s_cbranch_execz BB8_4
 ; CGP-NEXT:  ; %bb.3:
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v0, v10
 ; CGP-NEXT:    v_sub_i32_e32 v1, vcc, 0, v10
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v0, v0

 ; CGP-NEXT:  ; %bb.5:
 ; CGP-NEXT:    v_ashrrev_i32_e32 v4, 31, v9
 ; CGP-NEXT:    v_add_i32_e32 v5, vcc, v8, v4
 ; CGP-NEXT:    v_addc_u32_e32 v6, vcc, v9, v4, vcc
 ; CGP-NEXT:    v_xor_b32_e32 v5, v5, v4
 ; CGP-NEXT:    v_xor_b32_e32 v4, v6, v4
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v6, v5
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v7, v4
-; CGP-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
+; CGP-NEXT:    v_sub_i32_e32 v9, vcc, 0, v5
+; CGP-NEXT:    v_subb_u32_e32 v10, vcc, 0, v4, vcc
+; CGP-NEXT:    v_ashrrev_i32_e32 v15, 31, v3
 ; CGP-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; CGP-NEXT:    v_rcp_iflag_f32_e32 v6, v6
-; CGP-NEXT:    v_add_i32_e32 v7, vcc, v2, v9
-; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v9, vcc
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, 0, v5
 ; CGP-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
-; CGP-NEXT:    v_mul_f32_e32 v10, 0x2f800000, v6
-; CGP-NEXT:    v_trunc_f32_e32 v10, v10
-; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v10
+; CGP-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
+; CGP-NEXT:    v_trunc_f32_e32 v7, v7
+; CGP-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; CGP-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; CGP-NEXT:    v_cvt_u32_f32_e32 v10, v10
-; CGP-NEXT:    v_subb_u32_e32 v12, vcc, 0, v4, vcc
-; CGP-NEXT:    v_xor_b32_e32 v7, v7, v9
-; CGP-NEXT:    v_mul_lo_u32 v13, v12, v6
-; CGP-NEXT:    v_mul_lo_u32 v14, v11, v10
-; CGP-NEXT:    v_mul_hi_u32 v16, v11, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v6
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v16
-; CGP-NEXT:    v_mul_lo_u32 v14, v10, v15
-; CGP-NEXT:    v_mul_lo_u32 v16, v6, v13
-; CGP-NEXT:    v_mul_hi_u32 v17, v6, v15
-; CGP-NEXT:    v_mul_hi_u32 v15, v10, v15
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; CGP-NEXT:    v_mul_lo_u32 v12, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v11, v9, v7
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v6
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v14
+; CGP-NEXT:    v_mul_lo_u32 v12, v7, v13
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v11
+; CGP-NEXT:    v_mul_hi_u32 v17, v6, v13
+; CGP-NEXT:    v_add_i32_e32 v16, vcc, v2, v15
+; CGP-NEXT:    v_addc_u32_e32 v3, vcc, v3, v15, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v14
+; CGP-NEXT:    v_mul_lo_u32 v18, v7, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v7, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v17, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v16, v14
-; CGP-NEXT:    v_mul_hi_u32 v16, v6, v13
-; CGP-NEXT:    v_mul_hi_u32 v13, v10, v13
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v12, v17
+; CGP-NEXT:    v_mul_hi_u32 v17, v6, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v18, v13
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v17
 ; CGP-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v16, vcc, v17, v16
-; CGP-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v15, vcc, v16, v15
-; CGP-NEXT:    v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v14
-; CGP-NEXT:    v_addc_u32_e64 v14, s[4:5], v10, v13, vcc
-; CGP-NEXT:    v_mul_lo_u32 v12, v12, v6
-; CGP-NEXT:    v_mul_lo_u32 v15, v11, v14
-; CGP-NEXT:    v_mul_lo_u32 v16, v11, v6
-; CGP-NEXT:    v_mul_hi_u32 v11, v11, v6
+; CGP-NEXT:    v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT:    v_mul_hi_u32 v11, v7, v11
+; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v13, vcc, v14, v13
+; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT:    v_addc_u32_e64 v12, s[4:5], v7, v11, vcc
+; CGP-NEXT:    v_mul_lo_u32 v10, v10, v6
+; CGP-NEXT:    v_mul_lo_u32 v13, v9, v12
+; CGP-NEXT:    v_mul_hi_u32 v14, v9, v6
+; CGP-NEXT:    v_mul_lo_u32 v9, v9, v6
+; CGP-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v13
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_mul_hi_u32 v13, v6, v16
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; CGP-NEXT:    v_mul_lo_u32 v12, v14, v16
-; CGP-NEXT:    v_mul_lo_u32 v15, v6, v11
-; CGP-NEXT:    v_mul_hi_u32 v16, v14, v16
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v12, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT:    v_mul_lo_u32 v13, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
-; CGP-NEXT:    v_mul_hi_u32 v15, v6, v11
-; CGP-NEXT:    v_mul_hi_u32 v11, v14, v11
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v16
-; CGP-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v15
-; CGP-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v15, s[4:5], v16, v15
-; CGP-NEXT:    v_add_i32_e64 v12, s[4:5], v13, v12
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v14
+; CGP-NEXT:    v_mul_lo_u32 v13, v12, v9
+; CGP-NEXT:    v_mul_lo_u32 v14, v6, v10
+; CGP-NEXT:    v_mul_hi_u32 v11, v6, v9
+; CGP-NEXT:    v_mul_lo_u32 v17, v12, v10
+; CGP-NEXT:    v_mul_hi_u32 v9, v12, v9
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v13, v14
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_mul_hi_u32 v13, v6, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v14, v11
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v17, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v13
 ; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v15, v13
-; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v13
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, v10, v11, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
-; CGP-NEXT:    v_addc_u32_e32 v10, vcc, 0, v10, vcc
-; CGP-NEXT:    v_mul_lo_u32 v11, v3, v6
-; CGP-NEXT:    v_mul_lo_u32 v12, v7, v10
-; CGP-NEXT:    v_mul_hi_u32 v13, v7, v6
+; CGP-NEXT:    v_add_i32_e64 v13, s[4:5], v14, v13
+; CGP-NEXT:    v_mul_hi_u32 v10, v12, v10
+; CGP-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e64 v11, s[4:5], v13, v11
+; CGP-NEXT:    v_add_i32_e64 v10, s[4:5], v10, v11
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, v7, v10, vcc
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_xor_b32_e32 v16, v16, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_addc_u32_e32 v7, vcc, 0, v7, vcc
+; CGP-NEXT:    v_mul_lo_u32 v9, v3, v6
+; CGP-NEXT:    v_mul_lo_u32 v10, v16, v7
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v6
+; CGP-NEXT:    v_mul_lo_u32 v12, v3, v7
 ; CGP-NEXT:    v_mul_hi_u32 v6, v3, v6
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_mul_lo_u32 v13, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; CGP-NEXT:    v_mul_hi_u32 v12, v7, v10
-; CGP-NEXT:    v_mul_hi_u32 v10, v3, v10
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v12
-; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT:    v_mul_hi_u32 v11, v16, v7
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
 ; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v11
 ; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; CGP-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT:    v_mul_lo_u32 v11, v4, v6
-; CGP-NEXT:    v_mul_lo_u32 v10, v5, v10
-; CGP-NEXT:    v_mul_lo_u32 v12, v5, v6
-; CGP-NEXT:    v_mul_hi_u32 v6, v5, v6
-; CGP-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; CGP-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; CGP-NEXT:    v_sub_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT:    v_subb_u32_e64 v10, s[4:5], v3, v6, vcc
-; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v6
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v10, v4
+; CGP-NEXT:    v_mul_hi_u32 v7, v3, v7
+; CGP-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; CGP-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; CGP-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; CGP-NEXT:    v_mul_lo_u32 v9, v4, v6
+; CGP-NEXT:    v_mul_lo_u32 v7, v5, v7
+; CGP-NEXT:    v_mul_hi_u32 v10, v5, v6
+; CGP-NEXT:    v_mul_lo_u32 v6, v5, v6
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; CGP-NEXT:    v_sub_i32_e32 v6, vcc, v16, v6
+; CGP-NEXT:    v_subb_u32_e64 v9, s[4:5], v3, v7, vcc
+; CGP-NEXT:    v_sub_i32_e64 v3, s[4:5], v3, v7
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v4
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v6, v6, v11, s[4:5]
-; CGP-NEXT:    v_sub_i32_e32 v11, vcc, v7, v5
-; CGP-NEXT:    v_subbrev_u32_e64 v12, s[4:5], 0, v3, vcc
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[4:5]
+; CGP-NEXT:    v_sub_i32_e32 v10, vcc, v6, v5
+; CGP-NEXT:    v_subbrev_u32_e64 v11, s[4:5], 0, v3, vcc
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v5
 ; CGP-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
-; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v12, v4
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v11, v5
-; CGP-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[4:5]
+; CGP-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
+; CGP-NEXT:    v_cmp_eq_u32_e64 s[4:5], v11, v4
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v10, v5
+; CGP-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[4:5]
 ; CGP-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v11, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc
-; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v6
-; CGP-NEXT:    v_cndmask_b32_e32 v4, v7, v4, vcc
-; CGP-NEXT:    v_cndmask_b32_e32 v3, v10, v3, vcc
-; CGP-NEXT:    v_xor_b32_e32 v4, v4, v9
-; CGP-NEXT:    v_xor_b32_e32 v3, v3, v9
-; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v9
-; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v9, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v10, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v11, v3, vcc
+; CGP-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; CGP-NEXT:    v_cndmask_b32_e32 v4, v6, v4, vcc
+; CGP-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
+; CGP-NEXT:    v_xor_b32_e32 v4, v4, v15
+; CGP-NEXT:    v_xor_b32_e32 v3, v3, v15
+; CGP-NEXT:    v_sub_i32_e32 v4, vcc, v4, v15
+; CGP-NEXT:    v_subb_u32_e32 v5, vcc, v3, v15, vcc
 ; CGP-NEXT:  BB8_6: ; %Flow
 ; CGP-NEXT:    s_or_saveexec_b64 s[4:5], s[6:7]
 ; CGP-NEXT:    s_xor_b64 exec, exec, s[4:5]
 ; CGP-NEXT:    s_cbranch_execz BB8_8
 ; CGP-NEXT:  ; %bb.7:
 ; CGP-NEXT:    v_cvt_f32_u32_e32 v3, v8
 ; CGP-NEXT:    v_sub_i32_e32 v4, vcc, 0, v8
 ; CGP-NEXT:    v_mov_b32_e32 v5, 0

 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff
 ; CGP-NEXT:    v_and_b32_e32 v1, s4, v2
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v2, v1
 ; CGP-NEXT:    v_and_b32_e32 v0, s4, v0
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v0
 ; CGP-NEXT:    v_rcp_f32_e32 v4, v2
 ; CGP-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; CGP-NEXT:    v_trunc_f32_e32 v4, v4
+; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v4
 ; CGP-NEXT:    v_mad_f32 v3, -v4, v2, v3
-; CGP-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v2|
 ; CGP-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; CGP-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; CGP-NEXT:    v_mul_lo_u32 v1, v2, v1
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and i64 %num, 16777215
   %den.mask = and i64 %den, 16777215
   %result = srem i64 %num.mask, %den.mask

 ; GISEL-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_hi_u32 v11, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v4, v11
-; GISEL-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v12
+; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v12
 ; GISEL-NEXT:    v_mul_lo_u32 v14, v5, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v4, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v12
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; GISEL-NEXT:    v_mul_hi_u32 v13, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
+; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
 ; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v10
 ; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v4
-; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v4
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v8, v7
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v4, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v12
+; GISEL-NEXT:    v_add_i32_e64 v0, s[4:5], 0, v0
+; GISEL-NEXT:    v_mul_lo_u32 v11, v10, v7
+; GISEL-NEXT:    v_mul_lo_u32 v12, v4, v8
+; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v11, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v10, v8
 ; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
+; GISEL-NEXT:    v_mul_hi_u32 v11, v4, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v12, v9
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v14, v7
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v11
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
+; GISEL-NEXT:    v_mul_hi_u32 v8, v10, v8
+; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
 ; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
+; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v8, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v8, v0, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GISEL-NEXT:    v_mul_lo_u32 v10, v13, v5
 ; GISEL-NEXT:    v_mul_hi_u32 v4, v13, v4
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v0, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v9
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
 ; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GISEL-NEXT:    v_mul_lo_u32 v7, v3, v4
 ; GISEL-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GISEL-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GISEL-NEXT:    v_mul_hi_u32 v8, v1, v4
+; GISEL-NEXT:    v_mul_lo_u32 v4, v1, v4
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v13, v4, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v4, s[4:5], v13, v4
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v3
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v8
+; GISEL-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v13, v5, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v5, s[4:5], v13, v5
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v3
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v0, v1
 ; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v3
-; GISEL-NEXT:    v_subb_u32_e32 v4, vcc, v4, v3, vcc
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v4, v3
+; GISEL-NEXT:    v_subb_u32_e32 v5, vcc, v5, v3, vcc
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
 ; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, v0, v1
-; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v4, vcc
+; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v5, vcc
+; GISEL-NEXT:    v_add_i32_e64 v6, s[4:5], 0, v6
+; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], 0, 0, s[4:5]
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v6
+; GISEL-NEXT:    v_cvt_f32_u32_e32 v12, v10
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v1
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
+; GISEL-NEXT:    v_mac_f32_e32 v11, 0x4f800000, v12
+; GISEL-NEXT:    v_rcp_iflag_f32_e32 v11, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[4:5]
 ; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v4, v3, vcc
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v5, v3, vcc
+; GISEL-NEXT:    v_mul_f32_e32 v5, 0x5f7ffffc, v11
+; GISEL-NEXT:    v_mul_f32_e32 v11, 0x2f800000, v5
+; GISEL-NEXT:    v_trunc_f32_e32 v11, v11
+; GISEL-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v11
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GISEL-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, v13, v14, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v13, vcc, 0, v6
+; GISEL-NEXT:    v_subb_u32_e32 v14, vcc, 0, v10, vcc
+; GISEL-NEXT:    v_mul_lo_u32 v16, v14, v5
+; GISEL-NEXT:    v_mul_lo_u32 v17, v13, v11
+; GISEL-NEXT:    v_mul_hi_u32 v18, v13, v5
+; GISEL-NEXT:    v_mul_lo_u32 v15, v13, v5
 ; GISEL-NEXT:    v_sub_i32_e32 v1, vcc, v8, v1
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_add_i32_e32 v4, vcc, 0, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
-; GISEL-NEXT:    v_addc_u32_e64 v6, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v11, v4
-; GISEL-NEXT:    v_cvt_f32_u32_e32 v12, v6
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
+; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v17
+; GISEL-NEXT:    v_add_i32_e32 v16, vcc, v16, v18
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12
+; GISEL-NEXT:    v_mul_lo_u32 v17, v11, v15
+; GISEL-NEXT:    v_mul_lo_u32 v18, v5, v16
 ; GISEL-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v8, v5, v15
+; GISEL-NEXT:    v_mul_hi_u32 v15, v11, v15
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v17, v18
+; GISEL-NEXT:    v_mul_lo_u32 v18, v11, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v16
+; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v17, v8
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v18, v15
+; GISEL-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v15, s[4:5], v17, v15
+; GISEL-NEXT:    v_mul_hi_u32 v16, v11, v16
+; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v12, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v15, v12
+; GISEL-NEXT:    v_add_i32_e64 v12, s[4:5], v16, v12
+; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v8
+; GISEL-NEXT:    v_addc_u32_e64 v8, s[6:7], v11, v12, s[4:5]
+; GISEL-NEXT:    v_mul_lo_u32 v14, v14, v5
+; GISEL-NEXT:    v_mul_lo_u32 v15, v13, v8
+; GISEL-NEXT:    v_mul_hi_u32 v16, v13, v5
+; GISEL-NEXT:    v_mul_lo_u32 v13, v13, v5
 ; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
-; GISEL-NEXT:    v_mac_f32_e32 v11, 0x4f800000, v12
-; GISEL-NEXT:    v_rcp_iflag_f32_e32 v8, v11
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc
-; GISEL-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v8
-; GISEL-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v3
-; GISEL-NEXT:    v_trunc_f32_e32 v5, v5
-; GISEL-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v5
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GISEL-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, 0, v4
-; GISEL-NEXT:    v_subb_u32_e32 v8, vcc, 0, v6, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v10, v7, v5
-; GISEL-NEXT:    v_mul_hi_u32 v12, v7, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v3
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT:    v_mul_lo_u32 v10, v5, v11
-; GISEL-NEXT:    v_mul_lo_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v14, v3, v11
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v14, v15
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v16
 ; GISEL-NEXT:    v_add_i32_e32 v2, vcc, 0, v2
-; GISEL-NEXT:    v_addc_u32_e64 v13, s[4:5], 0, 0, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v12
+; GISEL-NEXT:    v_mul_lo_u32 v14, v8, v13
+; GISEL-NEXT:    v_mul_lo_u32 v15, v5, v9
+; GISEL-NEXT:    v_addc_u32_e64 v16, s[6:7], 0, 0, vcc
+; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_mul_hi_u32 v12, v5, v13
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v14, v15
+; GISEL-NEXT:    v_mul_lo_u32 v17, v8, v9
+; GISEL-NEXT:    v_mul_hi_u32 v13, v8, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
+; GISEL-NEXT:    v_mul_hi_u32 v14, v5, v9
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v14, v5, v9
-; GISEL-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT:    v_mul_hi_u32 v12, v3, v9
-; GISEL-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v17, v13
+; GISEL-NEXT:    v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v13, vcc, v13, v14
 ; GISEL-NEXT:    v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
+; GISEL-NEXT:    v_add_i32_e32 v14, vcc, v15, v14
+; GISEL-NEXT:    v_mul_hi_u32 v8, v8, v9
+; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v13, v12
 ; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v12, vcc, v14, v12
-; GISEL-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GISEL-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v10
-; GISEL-NEXT:    v_addc_u32_e64 v10, s[4:5], v5, v9, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v8, v8, v3
-; GISEL-NEXT:    v_mul_lo_u32 v11, v7, v10
-; GISEL-NEXT:    v_mul_lo_u32 v12, v7, v3
-; GISEL-NEXT:    v_mul_hi_u32 v7, v7, v3
-; GISEL-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_mul_hi_u32 v9, v3, v12
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v8, v7
-; GISEL-NEXT:    v_mul_lo_u32 v8, v10, v12
-; GISEL-NEXT:    v_mul_lo_u32 v11, v3, v7
-; GISEL-NEXT:    v_mul_hi_u32 v12, v10, v12
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v8, v9
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT:    v_mul_lo_u32 v9, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v11, v8
-; GISEL-NEXT:    v_mul_hi_u32 v11, v3, v7
-; GISEL-NEXT:    v_mul_hi_u32 v7, v10, v7
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v12
-; GISEL-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v9, v11
-; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT:    v_add_i32_e64 v8, s[4:5], v9, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s[4:5]
-; GISEL-NEXT:    v_add_i32_e64 v9, s[4:5], v11, v9
-; GISEL-NEXT:    v_add_i32_e64 v7, s[4:5], v7, v9
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, v5, v7, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v7, v13, v3
-; GISEL-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
-; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT:    v_addc_u32_e64 v8, vcc, v11, v8, s[4:5]
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
+; GISEL-NEXT:    v_addc_u32_e32 v8, vcc, 0, v8, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
+; GISEL-NEXT:    v_mul_lo_u32 v9, v16, v5
+; GISEL-NEXT:    v_mul_lo_u32 v11, v2, v8
+; GISEL-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v1, v4, v3, vcc
+; GISEL-NEXT:    v_mul_hi_u32 v3, v2, v5
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v9, v11
+; GISEL-NEXT:    v_mul_lo_u32 v9, v16, v8
+; GISEL-NEXT:    v_mul_hi_u32 v5, v16, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_mul_lo_u32 v9, v13, v5
-; GISEL-NEXT:    v_mul_hi_u32 v3, v13, v3
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GISEL-NEXT:    v_mul_hi_u32 v5, v13, v5
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT:    v_mul_hi_u32 v4, v2, v8
+; GISEL-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
+; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc
-; GISEL-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GISEL-NEXT:    v_mul_lo_u32 v7, v6, v3
-; GISEL-NEXT:    v_mul_lo_u32 v5, v4, v5
-; GISEL-NEXT:    v_mul_lo_u32 v8, v4, v3
-; GISEL-NEXT:    v_mul_hi_u32 v3, v4, v3
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc
 ; GISEL-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v8
-; GISEL-NEXT:    v_subb_u32_e64 v5, s[4:5], v13, v3, vcc
-; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v13, v3
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v6
+; GISEL-NEXT:    v_mul_hi_u32 v7, v16, v8
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_mul_lo_u32 v7, v10, v3
+; GISEL-NEXT:    v_mul_lo_u32 v4, v6, v4
+; GISEL-NEXT:    v_mul_lo_u32 v5, v6, v3
+; GISEL-NEXT:    v_mul_hi_u32 v3, v6, v3
+; GISEL-NEXT:    v_subrev_i32_e32 v0, vcc, 0, v0
+; GISEL-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; GISEL-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GISEL-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GISEL-NEXT:    v_sub_i32_e32 v2, vcc, v2, v5
+; GISEL-NEXT:    v_subb_u32_e64 v4, s[4:5], v16, v3, vcc
+; GISEL-NEXT:    v_sub_i32_e64 v3, s[4:5], v16, v3
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v4
-; GISEL-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v6
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT:    v_cndmask_b32_e64 v7, v7, v8, s[4:5]
-; GISEL-NEXT:    v_sub_i32_e32 v8, vcc, v2, v4
-; GISEL-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v4
-; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v6, vcc
-; GISEL-NEXT:    v_sub_i32_e32 v4, vcc, v8, v4
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v4, v10
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_cndmask_b32_e64 v5, v5, v7, s[4:5]
+; GISEL-NEXT:    v_sub_i32_e32 v7, vcc, v2, v6
+; GISEL-NEXT:    v_subbrev_u32_e64 v8, s[4:5], 0, v3, vcc
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
+; GISEL-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v6
+; GISEL-NEXT:    v_subb_u32_e32 v3, vcc, v3, v10, vcc
+; GISEL-NEXT:    v_sub_i32_e32 v6, vcc, v7, v6
 ; GISEL-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
-; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v6
-; GISEL-NEXT:    v_cndmask_b32_e64 v10, v10, v11, s[4:5]
+; GISEL-NEXT:    v_cmp_eq_u32_e64 s[4:5], v8, v10
+; GISEL-NEXT:    v_cndmask_b32_e64 v9, v9, v11, s[4:5]
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10
-; GISEL-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc
-; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GISEL-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v9
+; GISEL-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
+; GISEL-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
+; GISEL-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
 ; GISEL-NEXT:    v_subrev_i32_e32 v2, vcc, 0, v2
 ; GISEL-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
 ; GISEL-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; CGP-LABEL: v_srem_v2i64_24bit:
 ; CGP:       ; %bb.0:
 ; CGP-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; CGP-NEXT:    s_mov_b32 s4, 0xffffff
 ; CGP-NEXT:    v_and_b32_e32 v1, s4, v4
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v1
 ; CGP-NEXT:    v_and_b32_e32 v0, s4, v0
 ; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v0
 ; CGP-NEXT:    v_and_b32_e32 v6, s4, v6
 ; CGP-NEXT:    v_rcp_f32_e32 v5, v3
+; CGP-NEXT:    v_cvt_f32_i32_e32 v7, v6
 ; CGP-NEXT:    v_and_b32_e32 v2, s4, v2
+; CGP-NEXT:    v_cvt_f32_i32_e32 v8, v2
 ; CGP-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; CGP-NEXT:    v_trunc_f32_e32 v5, v5
 ; CGP-NEXT:    v_mad_f32 v4, -v5, v3, v4
 ; CGP-NEXT:    v_cvt_i32_f32_e32 v5, v5
+; CGP-NEXT:    v_rcp_f32_e32 v9, v7
 ; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v4|, |v3|
-; CGP-NEXT:    v_cvt_f32_i32_e32 v4, v6
 ; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
 ; CGP-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; CGP-NEXT:    v_mul_lo_u32 v1, v3, v1
-; CGP-NEXT:    v_cvt_f32_i32_e32 v3, v2
-; CGP-NEXT:    v_rcp_f32_e32 v5, v4
+; CGP-NEXT:    v_mul_f32_e32 v3, v8, v9
+; CGP-NEXT:    v_trunc_f32_e32 v3, v3
+; CGP-NEXT:    v_cvt_i32_f32_e32 v4, v3
+; CGP-NEXT:    v_mad_f32 v3, -v3, v7, v8
+; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v7|
+; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
+; CGP-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; CGP-NEXT:    v_mul_lo_u32 v3, v3, v6
 ; CGP-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; CGP-NEXT:    v_bfe_i32 v0, v0, 0, 25
-; CGP-NEXT:    v_mul_f32_e32 v1, v3, v5
-; CGP-NEXT:    v_trunc_f32_e32 v1, v1
-; CGP-NEXT:    v_mad_f32 v3, -v1, v4, v3
-; CGP-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; CGP-NEXT:    v_cmp_ge_f32_e64 s[4:5], |v3|, |v4|
-; CGP-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s[4:5]
-; CGP-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; CGP-NEXT:    v_mul_lo_u32 v3, v1, v6
 ; CGP-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; CGP-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
 ; CGP-NEXT:    v_bfe_i32 v2, v2, 0, 25
 ; CGP-NEXT:    v_ashrrev_i32_e32 v3, 31, v2
 ; CGP-NEXT:    s_setpc_b64 s[30:31]
   %num.mask = and <2 x i64> %num, <i64 16777215, i64 16777215>
   %den.mask = and <2 x i64> %den, <i64 16777215, i64 16777215>
   %result = srem <2 x i64> %num.mask, %den.mask
   ret <2 x i64> %result
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_sub_co_u32_e64 v10, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v11
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s5, v6, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }
 
 define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {

 ; GFX10-LABEL: ssubsat_i64_sv:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[0:1]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s1, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 

 ; GFX10-LABEL: ssubsat_i64_vs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s1, s[0:1], 0
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, v4, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast
 }
 

 ; GFX10-NEXT:    v_mov_b32_e32 v15, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v17, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v18, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, 0, v[4:5]
 ; GFX10-NEXT:    v_sub_co_u32_e64 v8, vcc_lo, v14, v4
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s6, 0, v[6:7]
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v19, vcc_lo, v17, v6
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
-; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
 ; GFX10-NEXT:    v_add_co_u32_e64 v1, s5, v12, 0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
+; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_u32_e64 v2, s7, v0, 0
-; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)

 ;
 ; GFX10-LABEL: ssubsat_i128_sv:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_sub_co_u32_e64 v4, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s1, 64, s0
-; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s0, v[4:5]
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
+; GFX10-NEXT:    s_sub_i32 s0, 64, s1
+; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s1, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
-; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s1, v[6:7]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[6:7]
+; GFX10-NEXT:    v_lshlrev_b64 v[8:9], s0, v[6:7]
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_or_b32_e32 v8, v15, v8
-; GFX10-NEXT:    v_or_b32_e32 v9, v16, v9
-; GFX10-NEXT:    v_ashrrev_i32_e32 v15, 31, v7
+; GFX10-NEXT:    v_or_b32_e32 v0, v15, v8
+; GFX10-NEXT:    v_or_b32_e32 v1, v16, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
-; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s1, v[6:7]
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s0, v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v12, v11, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v9, vcc_lo
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v1, vcc_lo
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[6:7]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v15, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v9, s0
+; GFX10-NEXT:    v_xor_b32_e32 v8, v11, v10
+; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v7
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s0
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v11, v0, vcc_lo
+; GFX10-NEXT:    v_add_co_u32_e64 v2, s0, v2, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v2, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v9, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v3, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v6, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v9, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
 ; GFX6-LABEL: ssubsat_i128_vs:

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: ssubsat_i128_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_mov_b32_e32 v5, v0
-; GFX10-NEXT:    v_mov_b32_e32 v6, v1
-; GFX10-NEXT:    v_mov_b32_e32 v9, v2
-; GFX10-NEXT:    v_mov_b32_e32 v10, v3
-; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    v_sub_co_u32_e64 v15, vcc_lo, v5, s0
+; GFX10-NEXT:    v_sub_co_u32_e64 v14, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_cmp_gt_u64_e64 s0, s[0:1], 0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v16, vcc_lo, s1, v6, vcc_lo
+; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v19, vcc_lo, s2, v9, vcc_lo
-; GFX10-NEXT:    s_and_b32 s1, 1, s4
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v20, vcc_lo, s3, v10, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[15:16], v[5:6]
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v15, vcc_lo, s1, v1, vcc_lo
+; GFX10-NEXT:    s_movk_i32 s1, 0x7f
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[2:3], 0
-; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v20
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
+; GFX10-NEXT:    s_sub_i32 s2, 64, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[14:15], v[0:1]
+; GFX10-NEXT:    s_and_b32 s0, 1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[19:20], v[9:10]
+; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[19:20], v[9:10]
-; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX10-NEXT:    s_movk_i32 s0, 0x7f
-; GFX10-NEXT:    s_sub_i32 s2, 64, s0
+; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v1, v0, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s0, v[15:16]
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s2, v[19:20]
-; GFX10-NEXT:    s_sub_i32 s1, s0, 64
-; GFX10-NEXT:    s_cmp_lt_u32 s0, 64
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s1, v[14:15]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
+; GFX10-NEXT:    s_sub_i32 s0, s1, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s1, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v11, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s1, v[19:20]
-; GFX10-NEXT:    s_cmp_eq_u32 s0, 0
-; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
-; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    s_cselect_b32 s1, 1, 0
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s0, v[19:20]
-; GFX10-NEXT:    s_and_b32 s0, 1, s1
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[7:8], s0, v[4:5]
+; GFX10-NEXT:    s_cmp_eq_u32 s1, 0
+; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX10-NEXT:    s_cselect_b32 s0, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
+; GFX10-NEXT:    s_and_b32 s0, 1, s0
+; GFX10-NEXT:    v_xor_b32_e32 v2, v11, v10
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s1, v[4:5]
 ; GFX10-NEXT:    s_and_b32 s1, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
-; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v15, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v16, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v7, v0, s0
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v2, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v16, v3, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v8, s0
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v20, v9, s0
+; GFX10-NEXT:    v_ashrrev_i32_e32 v7, 31, v5
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v14, s0
+; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s1
+; GFX10-NEXT:    v_cndmask_b32_e64 v8, v8, v15, s0
+; GFX10-NEXT:    v_and_b32_e32 v2, 1, v2
+; GFX10-NEXT:    v_add_co_u32_e64 v3, s0, v3, 0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v7, v0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v2, s0, 0, v0, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v14, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s0, 0x80000000, v1, s0
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v15, v8, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v5, v7, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }
 
 define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
 ; GFX6-LABEL: v_ssubsat_v2i128:

 ; GFX10-LABEL: v_ssubsat_v2i128:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v22, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v23, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v3
-; GFX10-NEXT:    s_movk_i32 s5, 0x7f
+; GFX10-NEXT:    s_movk_i32 s6, 0x7f
 ; GFX10-NEXT:    v_sub_co_u32_e64 v16, vcc_lo, v22, v8
-; GFX10-NEXT:    s_sub_i32 s6, 64, s5
+; GFX10-NEXT:    s_sub_i32 s5, 64, s6
+; GFX10-NEXT:    s_sub_i32 s7, s6, 64
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
+; GFX10-NEXT:    v_mov_b32_e32 v26, v4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v17, vcc_lo, v23, v9, vcc_lo
-; GFX10-NEXT:    s_sub_i32 s7, s5, 64
+; GFX10-NEXT:    v_mov_b32_e32 v27, v5
+; GFX10-NEXT:    v_mov_b32_e32 v4, v6
+; GFX10-NEXT:    v_mov_b32_e32 v5, v7
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v18, vcc_lo, v20, v10, vcc_lo
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v19, vcc_lo, v21, v11, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[22:23]
-; GFX10-NEXT:    v_mov_b32_e32 v26, v4
-; GFX10-NEXT:    v_mov_b32_e32 v27, v5
-; GFX10-NEXT:    v_mov_b32_e32 v24, v6
-; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s6, v[18:19]
-; GFX10-NEXT:    v_mov_b32_e32 v25, v7
+; GFX10-NEXT:    v_lshlrev_b64 v[2:3], s5, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v20, v1, v0, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
-; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s5, v[16:17]
+; GFX10-NEXT:    v_lshrrev_b64 v[0:1], s6, v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_or_b32_e32 v2, v0, v2
 ; GFX10-NEXT:    v_or_b32_e32 v3, v1, v3
-; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s5, v[18:19]
+; GFX10-NEXT:    v_ashrrev_i64 v[0:1], s6, v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v11, 31, v19
 ; GFX10-NEXT:    v_cndmask_b32_e32 v10, v9, v8, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, 1, 0
 ; GFX10-NEXT:    v_ashrrev_i64 v[8:9], s7, v[18:19]
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX10-NEXT:    s_and_b32 s8, 1, vcc_lo
 ; GFX10-NEXT:    s_and_b32 s4, 1, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s8
-; GFX10-NEXT:    v_xor_b32_e32 v9, v10, v20
-; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
+; GFX10-NEXT:    v_xor_b32_e32 v10, v10, v20
+; GFX10-NEXT:    s_cmp_lt_u32 s6, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v11, v0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v11, v1, s4
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
-; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
 ; GFX10-NEXT:    v_sub_co_u32_e64 v8, s4, v26, v12
+; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e64 v9, s4, v27, v13, s4
-; GFX10-NEXT:    v_sub_co_ci_u32_e64 v10, s4, v24, v14, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
-; GFX10-NEXT:    v_sub_co_ci_u32_e64 v11, s4, v25, v15, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v3, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0, v0, vcc_lo
+; GFX10-NEXT:    v_and_b32_e32 v0, 1, v10
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v22, vcc_lo, 0x80000000, v1, vcc_lo
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v10, vcc_lo, v4, v14, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
-; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v3, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v20, vcc_lo
-; GFX10-NEXT:    v_lshrrev_b64 v[3:4], s5, v[8:9]
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s4
-; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s4
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v5, v15, vcc_lo
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
+; GFX10-NEXT:    v_ashrrev_i64 v[23:24], s7, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, 0, v[12:13]
-; GFX10-NEXT:    v_lshlrev_b64 v[12:13], s6, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s4
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_or_b32_e32 v12, v3, v12
-; GFX10-NEXT:    v_or_b32_e32 v13, v4, v13
-; GFX10-NEXT:    v_ashrrev_i64 v[3:4], s5, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s4
-; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[24:25]
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v16, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s4
+; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[10:11], v[4:5]
+; GFX10-NEXT:    v_lshlrev_b64 v[4:5], s5, v[10:11]
+; GFX10-NEXT:    v_cndmask_b32_e64 v16, v2, v1, s4
 ; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, 0, v[14:15]
-; GFX10-NEXT:    v_ashrrev_i64 v[5:6], s7, v[10:11]
-; GFX10-NEXT:    v_cndmask_b32_e64 v14, v18, v17, s4
+; GFX10-NEXT:    v_lshrrev_b64 v[2:3], s6, v[8:9]
+; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v20, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v15, v13, v12, s4
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
-; GFX10-NEXT:    s_cmp_eq_u32 s5, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v12, s4
-; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v13, s4
-; GFX10-NEXT:    s_and_b32 s5, 1, s6
-; GFX10-NEXT:    s_and_b32 s6, 1, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s5
-; GFX10-NEXT:    v_xor_b32_e32 v7, v14, v7
-; GFX10-NEXT:    v_ashrrev_i32_e32 v18, 31, v11
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s6
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s4
-; GFX10-NEXT:    v_and_b32_e32 v7, 1, v7
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v18, v3, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v18, v4, s5
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s4, v5, 0
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v7
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
-; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v21, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
-; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s5
-; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s5
+; GFX10-NEXT:    s_cmp_eq_u32 s6, 0
+; GFX10-NEXT:    v_or_b32_e32 v2, v2, v4
+; GFX10-NEXT:    s_cselect_b32 s5, 1, 0
+; GFX10-NEXT:    v_or_b32_e32 v3, v3, v5
+; GFX10-NEXT:    s_and_b32 s5, 1, s5
+; GFX10-NEXT:    v_ashrrev_i32_e32 v13, 31, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v23, v2, s4
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v24, v3, s4
+; GFX10-NEXT:    s_and_b32 s4, 1, s4
+; GFX10-NEXT:    v_ashrrev_i64 v[2:3], s6, v[10:11]
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s5
+; GFX10-NEXT:    v_xor_b32_e32 v4, v15, v16
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, v13, v2, s4
+; GFX10-NEXT:    v_add_co_u32_e64 v5, s5, v5, 0
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v13, v3, s4
+; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v21, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s5, 0, v6, s5
+; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s5, 0, v12, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s5, 0x80000000, v3, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s4
+; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v22, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v7, v11, v12, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }
 
 define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_v2i128:
 ; GFX6:       ; %bb.0:

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

 ;
 ; GFX10-LABEL: v_uaddsat_v2i128:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v18, v8
 ; GFX10-NEXT:    v_mov_b32_e32 v19, v9
 ; GFX10-NEXT:    v_mov_b32_e32 v16, v10
+; GFX10-NEXT:    v_mov_b32_e32 v22, v12
 ; GFX10-NEXT:    v_mov_b32_e32 v17, v11
-; GFX10-NEXT:    v_mov_b32_e32 v10, v12
 ; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v18
-; GFX10-NEXT:    v_mov_b32_e32 v11, v13
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v19, vcc_lo
+; GFX10-NEXT:    v_mov_b32_e32 v23, v13
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v14
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v16, vcc_lo
+; GFX10-NEXT:    v_add_co_u32_e64 v4, s4, v4, v22
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v15
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v19, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v5, s4, v5, v23, s4
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v4, vcc_lo, v4, v10
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, v5, v11, vcc_lo
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, v6, v20, vcc_lo
+; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, vcc_lo, v6, v20, s4
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, v7, v21, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[10:11]
+; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[22:23]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[20:21]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[20:21]
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
 ; GFX10-NEXT:    v_cndmask_b32_e32 v9, v13, v12, vcc_lo

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, s0, v0
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, v0, s0
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
-; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
+; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)
   %cast = bitcast i128 %result to <4 x float>
   ret <4 x float> %cast
 }

 ; GFX10-NEXT:    v_mov_b32_e32 v21, v3
 ; GFX10-NEXT:    v_mov_b32_e32 v26, v4
 ; GFX10-NEXT:    v_mov_b32_e32 v27, v5
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[22:23], v[8:9]
 ; GFX10-NEXT:    v_mov_b32_e32 v24, v6
 ; GFX10-NEXT:    v_mov_b32_e32 v25, v7
 ; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[20:21], v[10:11]
-; GFX10-NEXT:    v_cmp_eq_u64_e64 s5, v[24:25], v[14:15]
+; GFX10-NEXT:    v_cmp_eq_u64_e64 s4, v[24:25], v[14:15]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[10:11]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[26:27], v[12:13]
-; GFX10-NEXT:    v_and_b32_e32 v16, 1, v16
 ; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[24:25], v[14:15]
-; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v16
 ; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, v22, v8
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v16
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v23, v9, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v8, v18, v17, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v9, v18, v17, s4
+; GFX10-NEXT:    v_sub_co_u32_e64 v4, s4, v26, v12
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, v20, v10, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s4
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v5, s4, v27, v13, s4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v21, v11, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v4, vcc_lo, v26, v12
-; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v27, v13, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s4
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, v24, v14, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s4
+; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v6, s4, v24, v14, s4
+; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
+; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, vcc_lo
+; GFX10-NEXT:    v_sub_co_ci_u32_e64 v7, s4, v25, v15, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v8
-; GFX10-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, v25, v15, vcc_lo
-; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, vcc_lo
+; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v4, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, 0, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, 0, s5
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
   ret <2 x i128> %result
 }

llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
 ; GFX6-NEXT:    s_add_i32 s3, s3, s8
 ; GFX6-NEXT:    s_xor_b32 s9, s3, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
 ; GFX6-NEXT:    s_sub_i32 s3, 0, s9
-; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
-; GFX6-NEXT:    s_add_i32 s1, s2, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
-; GFX6-NEXT:    s_xor_b32 s2, s0, s8
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
+; GFX6-NEXT:    s_ashr_i32 s3, s2, 31
+; GFX6-NEXT:    s_add_i32 s2, s2, s3
+; GFX6-NEXT:    s_xor_b32 s2, s2, s3
 ; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
+; GFX6-NEXT:    s_xor_b32 s3, s3, s8
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; GFX9-NEXT:    v_mov_b32_e32 v3, 0
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshr_b32 s3, s2, 16
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s3
 ; GFX9-NEXT:    s_and_b32 s2, s2, 0xffff
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s2
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GFX9-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
-; GFX9-NEXT:    global_store_short v3, v0, s[0:1]
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT:    global_store_short v4, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i16 %x, %y
   store i16 %r, i16 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @urem_i16(i16 addrspace(1)* %out, i16 %x, i16 %y) {
 ; CHECK-LABEL: @urem_i16(

 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s2, s4, 16
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
 ; GFX6-NEXT:    s_sext_i32_i16 s3, s4
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
-; GFX6-NEXT:    s_xor_b32 s3, s3, s2
+; GFX6-NEXT:    s_xor_b32 s5, s3, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
+; GFX6-NEXT:    s_ashr_i32 s3, s5, 30
 ; GFX6-NEXT:    s_or_b32 s3, s3, 1
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    buffer_store_short v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c

 ; CHECK-NEXT:    [[TMP15:%.*]] = add i32 [[TMP10]], [[TMP14]]
 ; CHECK-NEXT:    [[TMP16:%.*]] = and i32 [[TMP15]], 255
 ; CHECK-NEXT:    [[TMP17:%.*]] = trunc i32 [[TMP16]] to i8
 ; CHECK-NEXT:    store i8 [[TMP17]], i8 addrspace(1)* [[OUT:%.*]], align 1
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: udiv_i8:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s2, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s0
+; GFX6-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s0
+; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
 ; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_i8:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
-; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_cvt_f32_ubyte1_e32 v0, s2
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s2
-; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
+; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
-; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
+; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
-; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
+; GFX9-NEXT:    global_store_byte v4, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i8 %x, %y
   store i8 %r, i8 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @urem_i8(i8 addrspace(1)* %out, i8 %x, i8 %y) {
 ; CHECK-LABEL: @urem_i8(

 ; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 24
 ; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 24
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i8
 ; CHECK-NEXT:    store i8 [[TMP23]], i8 addrspace(1)* [[OUT:%.*]], align 1
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: srem_i8:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x80008
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
-; GFX6-NEXT:    s_sext_i32_i8 s3, s0
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
-; GFX6-NEXT:    s_xor_b32 s1, s3, s1
+; GFX6-NEXT:    s_bfe_i32 s3, s4, 0x80008
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s3
+; GFX6-NEXT:    s_sext_i32_i8 s5, s4
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
+; GFX6-NEXT:    s_xor_b32 s3, s5, s3
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
-; GFX6-NEXT:    s_or_b32 s1, s1, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s1
+; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
+; GFX6-NEXT:    s_or_b32 s3, s3, 1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s3
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    s_lshr_b32 s2, s0, 8
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i8:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)

 ; CHECK-NEXT:    [[TMP127:%.*]] = select i1 [[TMP125]], i32 [[TMP126]], i32 [[TMP122]]
 ; CHECK-NEXT:    [[TMP128:%.*]] = insertelement <4 x i32> [[TMP96]], i32 [[TMP127]], i64 3
 ; CHECK-NEXT:    store <4 x i32> [[TMP128]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: udiv_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s3, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s16, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s15, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s14, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s10
+; GFX6-NEXT:    s_sub_i32 s3, 0, s9
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s11
-; GFX6-NEXT:    v_mul_f32_e32 v0, s3, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s10
+; GFX6-NEXT:    v_mul_f32_e32 v0, s16, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s3, v1
+; GFX6-NEXT:    v_mul_f32_e32 v1, s16, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX6-NEXT:    s_sub_i32 s2, 0, s10
+; GFX6-NEXT:    s_sub_i32 s2, 0, s11
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s9
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s4, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s5, v5
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, s3, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s16, v4
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s8
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
-; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s4, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v5, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s5, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s11
+; GFX6-NEXT:    s_sub_i32 s0, 0, s10
+; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v1
-; GFX6-NEXT:    s_sub_i32 s0, 0, s11
-; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v6
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX6-NEXT:    v_mul_f32_e32 v3, s16, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
-; GFX6-NEXT:    v_mul_f32_e32 v4, s3, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s10
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
+; GFX6-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GFX6-NEXT:    v_mul_lo_u32 v7, v2, s10
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v6, vcc, s10, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v6, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, s7, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v4, s11
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v6
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s6, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v4
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, v3, s11
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s7, v5
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s11, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[12:15], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v4i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
 ; GFX9-NEXT:    s_mov_b32 s12, 0x4f7ffffe
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

 ; CHECK-NEXT:    [[TMP119:%.*]] = select i1 [[TMP117]], i32 [[TMP118]], i32 [[TMP116]]
 ; CHECK-NEXT:    [[TMP120:%.*]] = insertelement <4 x i32> [[TMP90]], i32 [[TMP119]], i64 3
 ; CHECK-NEXT:    store <4 x i32> [[TMP120]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: urem_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s14, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    s_sub_i32 s12, 0, s9
+; GFX6-NEXT:    s_sub_i32 s12, 0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
-; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT:    s_sub_i32 s13, 0, s9
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_f32_e32 v0, s14, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT:    v_mul_f32_e32 v1, s14, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_mov_b32 s2, -1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s14, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, s12, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
+; GFX6-NEXT:    v_mul_lo_u32 v4, s13, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v3
+; GFX6-NEXT:    s_sub_i32 s12, 0, s10
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v5
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    v_mul_f32_e32 v3, s14, v3
+; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    s_sub_i32 s4, 0, s10
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
 ; GFX6-NEXT:    s_sub_i32 s4, 0, s11
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
-; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v5
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s11
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3

 ; CHECK-NEXT:    [[TMP163:%.*]] = sub i32 [[TMP162]], [[TMP128]]
 ; CHECK-NEXT:    [[TMP164:%.*]] = insertelement <4 x i32> [[TMP123]], i32 [[TMP163]], i64 3
 ; CHECK-NEXT:    store <4 x i32> [[TMP164]], <4 x i32> addrspace(1)* [[OUT:%.*]], align 16
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: sdiv_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[8:15], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s16, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s17, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_ashr_i32 s2, s12, 31
 ; GFX6-NEXT:    s_add_i32 s3, s12, s2
-; GFX6-NEXT:    s_xor_b32 s12, s3, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GFX6-NEXT:    s_ashr_i32 s3, s13, 31
-; GFX6-NEXT:    s_add_i32 s0, s13, s3
-; GFX6-NEXT:    s_xor_b32 s13, s0, s3
+; GFX6-NEXT:    s_xor_b32 s16, s3, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s16
+; GFX6-NEXT:    s_ashr_i32 s12, s13, 31
+; GFX6-NEXT:    s_add_i32 s1, s13, s12
+; GFX6-NEXT:    s_xor_b32 s13, s1, s12
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GFX6-NEXT:    s_sub_i32 s1, 0, s12
+; GFX6-NEXT:    s_sub_i32 s1, 0, s16
 ; GFX6-NEXT:    s_ashr_i32 s0, s8, 31
-; GFX6-NEXT:    v_mul_f32_e32 v0, s16, v0
+; GFX6-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
 ; GFX6-NEXT:    s_xor_b32 s2, s0, s2
+; GFX6-NEXT:    s_ashr_i32 s3, s9, 31
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v0
 ; GFX6-NEXT:    s_add_i32 s1, s8, s0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s16, v1
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s17, v1
+; GFX6-NEXT:    s_xor_b32 s0, s1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_sub_i32 s0, 0, s13
+; GFX6-NEXT:    s_sub_i32 s1, 0, s13
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s12
+; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v1
+; GFX6-NEXT:    s_add_i32 s1, s9, s3
+; GFX6-NEXT:    s_xor_b32 s8, s1, s3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s16
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s16, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s12, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s16, v3
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
-; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
-; GFX6-NEXT:    s_add_i32 s1, s9, s0
 ; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    s_xor_b32 s2, s0, s3
+; GFX6-NEXT:    s_xor_b32 s2, s3, s12
 ; GFX6-NEXT:    s_ashr_i32 s3, s14, 31
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
 ; GFX6-NEXT:    s_add_i32 s0, s14, s3
-; GFX6-NEXT:    s_xor_b32 s9, s0, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
-; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT:    s_xor_b32 s12, s0, s3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s12
+; GFX6-NEXT:    v_mul_hi_u32 v1, s8, v1
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s13
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v3, s16, v3
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GFX6-NEXT:    v_mul_f32_e32 v3, s17, v3
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s8, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
-; GFX6-NEXT:    s_sub_i32 s0, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
+; GFX6-NEXT:    s_sub_i32 s0, 0, s12
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v3
+; GFX6-NEXT:    s_ashr_i32 s8, s15, 31
+; GFX6-NEXT:    s_add_i32 s9, s15, s8
+; GFX6-NEXT:    s_xor_b32 s9, s9, s8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v2, v3, v5
-; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
-; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
+; GFX6-NEXT:    v_mul_hi_u32 v2, v3, v2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
 ; GFX6-NEXT:    s_ashr_i32 s0, s10, 31
-; GFX6-NEXT:    s_add_i32 s8, s15, s2
 ; GFX6-NEXT:    s_add_i32 s1, s10, s0
-; GFX6-NEXT:    s_xor_b32 s8, s8, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s8
-; GFX6-NEXT:    s_xor_b32 s1, s1, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v4
+; GFX6-NEXT:    s_xor_b32 s1, s1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s1, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; GFX6-NEXT:    s_xor_b32 s3, s0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v2, s9
-; GFX6-NEXT:    v_mul_f32_e32 v4, s16, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
+; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT:    v_mul_f32_e32 v3, s17, v3
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s12
+; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
+; GFX6-NEXT:    s_xor_b32 s2, s0, s3
+; GFX6-NEXT:    s_sub_i32 s0, 0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v6, s0, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s1, v4
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v5, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GFX6-NEXT:    s_sub_i32 s0, 0, s8
-; GFX6-NEXT:    v_mul_lo_u32 v5, s0, v4
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s12, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT:    v_mul_hi_u32 v5, v3, v6
 ; GFX6-NEXT:    s_ashr_i32 s0, s11, 31
 ; GFX6-NEXT:    s_add_i32 s1, s11, s0
 ; GFX6-NEXT:    s_xor_b32 s1, s1, s0
-; GFX6-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, 1, v2
-; GFX6-NEXT:    s_xor_b32 s2, s0, s2
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, s1, v4
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v2, s3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v4, s8
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v3
-; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_mul_hi_u32 v3, s1, v3
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v3, s9
+; GFX6-NEXT:    v_xor_b32_e32 v2, s2, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT:    s_xor_b32 s2, s0, s8
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s1, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v3, s2, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s2, v3
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_v4i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34

 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: srem_v4i32:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s2, s8, 31
-; GFX6-NEXT:    s_add_i32 s8, s8, s2
-; GFX6-NEXT:    s_xor_b32 s12, s8, s2
+; GFX6-NEXT:    s_ashr_i32 s12, s8, 31
+; GFX6-NEXT:    s_add_i32 s8, s8, s12
+; GFX6-NEXT:    s_xor_b32 s12, s8, s12
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GFX6-NEXT:    s_ashr_i32 s8, s9, 31
 ; GFX6-NEXT:    s_add_i32 s9, s9, s8
 ; GFX6-NEXT:    s_xor_b32 s14, s9, s8
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s14
 ; GFX6-NEXT:    s_sub_i32 s9, 0, s12
 ; GFX6-NEXT:    s_ashr_i32 s8, s4, 31
 ; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
 ; GFX6-NEXT:    s_add_i32 s4, s4, s8
 ; GFX6-NEXT:    s_xor_b32 s4, s4, s8
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_sub_i32 s9, 0, s14
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
-; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v1
+; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s9, v1
-; GFX6-NEXT:    s_ashr_i32 s9, s5, 31
+; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v3
 ; GFX6-NEXT:    s_add_i32 s5, s5, s9
+; GFX6-NEXT:    s_xor_b32 s5, s5, s9
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s12
-; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    s_xor_b32 s4, s5, s9
-; GFX6-NEXT:    s_ashr_i32 s5, s10, 31
-; GFX6-NEXT:    s_add_i32 s10, s10, s5
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s12, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
-; GFX6-NEXT:    s_xor_b32 s10, s10, s5
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
-; GFX6-NEXT:    v_mul_hi_u32 v1, s4, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    s_ashr_i32 s4, s10, 31
+; GFX6-NEXT:    s_add_i32 s10, s10, s4
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s12, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    s_xor_b32 s10, s10, s4
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s14
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v1
-; GFX6-NEXT:    s_sub_i32 s4, 0, s10
 ; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s14, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s14, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v1
+; GFX6-NEXT:    s_sub_i32 s4, 0, s10
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v4
+; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
+; GFX6-NEXT:    s_ashr_i32 s4, s11, 31
+; GFX6-NEXT:    s_add_i32 s5, s11, s4
+; GFX6-NEXT:    s_xor_b32 s8, s5, s4
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s8
+; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
 ; GFX6-NEXT:    s_ashr_i32 s4, s6, 31
 ; GFX6-NEXT:    s_add_i32 s5, s6, s4
-; GFX6-NEXT:    s_ashr_i32 s6, s11, 31
-; GFX6-NEXT:    s_add_i32 s8, s11, s6
-; GFX6-NEXT:    s_xor_b32 s8, s8, s6
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v4
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
 ; GFX6-NEXT:    s_xor_b32 s5, s5, s4
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s5, v2
+; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    s_sub_i32 s6, 0, s8
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
 ; GFX6-NEXT:    v_xor_b32_e32 v1, s9, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s6, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
-; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s5, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
-; GFX6-NEXT:    s_sub_i32 s5, 0, s8
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, s5, v3
 ; GFX6-NEXT:    s_ashr_i32 s5, s7, 31
+; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GFX6-NEXT:    s_add_i32 s6, s7, s5
 ; GFX6-NEXT:    s_xor_b32 s6, s6, s5
-; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v2, s4, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s8
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s4, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v2, s4, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s4, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s8, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v3, s5, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s5, v3

 ; GFX6-NEXT:    s_mov_b32 s8, 0xffff
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_and_b32 s9, s2, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
 ; GFX6-NEXT:    s_lshr_b32 s9, s0, 16
 ; GFX6-NEXT:    s_and_b32 s0, s0, s8
-; GFX6-NEXT:    s_lshr_b32 s2, s2, 16
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
-; GFX6-NEXT:    s_and_b32 s2, s3, s8
+; GFX6-NEXT:    s_lshr_b32 s2, s2, 16
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s9
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v3
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
+; GFX6-NEXT:    s_and_b32 s2, s3, s8
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s2
+; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
 ; GFX6-NEXT:    s_lshr_b32 s0, s1, 16
-; GFX6-NEXT:    s_and_b32 s1, s1, s8
 ; GFX6-NEXT:    s_lshr_b32 s10, s3, 16
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX6-NEXT:    s_and_b32 s1, s1, s8
+; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v5
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s10
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v3
-; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v4, v6, v7
-; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v4
+; GFX6-NEXT:    v_mul_f32_e32 v6, v3, v6
+; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v8, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mad_f32 v4, -v4, v3, v6
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
+; GFX6-NEXT:    v_mad_f32 v3, -v6, v7, v3
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v7
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v8, vcc
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v3
 ; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v4i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX9-NEXT:    s_mov_b32 s8, 0xffff
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_and_b32 s1, s6, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s1
 ; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
 ; GFX9-NEXT:    s_and_b32 s4, s4, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s4
-; GFX9-NEXT:    s_lshr_b32 s4, s6, 16
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
+; GFX9-NEXT:    s_lshr_b32 s4, s6, 16
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s4
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
-; GFX9-NEXT:    s_and_b32 s0, s7, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v3
 ; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v4
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_mul_f32_e32 v1, v5, v6
-; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v5
+; GFX9-NEXT:    s_and_b32 s0, s7, s8
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
-; GFX9-NEXT:    s_and_b32 s0, s5, s8
+; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
 ; GFX9-NEXT:    s_lshr_b32 s6, s7, 16
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
+; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX9-NEXT:    s_and_b32 s0, s5, s8
+; GFX9-NEXT:    v_mad_f32 v3, -v1, v4, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s6
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
 ; GFX9-NEXT:    s_lshr_b32 s1, s5, 16
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v1, v6, v7
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v8
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mad_f32 v6, -v1, v5, v6
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
-; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
+; GFX9-NEXT:    v_mul_f32_e32 v7, v4, v7
+; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v9, v7
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
+; GFX9-NEXT:    v_mad_f32 v4, -v7, v8, v4
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v8
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0xffff
 ; GFX9-NEXT:    v_and_b32_e32 v0, v5, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v9, vcc
 ; GFX9-NEXT:    v_and_b32_e32 v1, v5, v1
 ; GFX9-NEXT:    v_lshl_or_b32 v1, v4, 16, v1
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v3, 16, v0
 ; GFX9-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv <4 x i16> %x, %y
   store <4 x i16> %r, <4 x i16> addrspace(1)* %out
   ret void

 ; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
 ; GFX6-NEXT:    s_mov_b32 s8, 0xffff
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_and_b32 s9, s2, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
 ; GFX6-NEXT:    s_and_b32 s10, s0, s8
-; GFX6-NEXT:    s_lshr_b32 s11, s2, 16
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT:    s_lshr_b32 s11, s2, 16
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s11
 ; GFX6-NEXT:    s_lshr_b32 s9, s0, 16
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s9
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX6-NEXT:    s_lshr_b32 s12, s3, 16
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GFX6-NEXT:    v_mad_f32 v1, -v1, v3, v4
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v3
+; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    s_and_b32 s2, s3, s8
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s2
+; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s2
 ; GFX6-NEXT:    s_and_b32 s2, s1, s8
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s11
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
-; GFX6-NEXT:    s_lshr_b32 s12, s3, 16
-; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s9, v1
-; GFX6-NEXT:    s_lshr_b32 s10, s1, 16
-; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s12
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s10
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
-; GFX6-NEXT:    v_mad_f32 v3, -v1, v2, v3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s12
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, v6, v7
+; GFX6-NEXT:    s_lshr_b32 s10, s1, 16
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s10
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v3
+; GFX6-NEXT:    v_mul_f32_e32 v2, v5, v6
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v2
+; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v5
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s12
-; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT:    v_mul_f32_e32 v4, v7, v8
+; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v4
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mad_f32 v4, -v4, v3, v7
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s11
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s12
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v3
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
 ; GFX6-NEXT:    v_and_b32_e32 v1, s8, v1
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v5
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
+; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: urem_v4i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c

 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s6
 ; GFX9-NEXT:    s_and_b32 s6, s5, s8
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s10
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s6
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_lshr_b32 s1, s5, 16
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v4
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s1
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mad_f32 v6, -v3, v5, v6
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_mul_f32_e32 v5, v7, v8
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v3
+; GFX9-NEXT:    v_mad_f32 v3, -v3, v5, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX9-NEXT:    v_mul_f32_e32 v5, v8, v9
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v7, vcc
+; GFX9-NEXT:    v_mad_f32 v5, -v5, v4, v8
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v3, s7
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s10
 ; GFX9-NEXT:    v_sub_u32_e32 v0, s4, v0
 ; GFX9-NEXT:    v_sub_u32_e32 v5, s0, v1
 ; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v3

 ;
 ; GFX6-LABEL: srem_v4i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xb
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_sext_i32_i16 s8, s2
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
-; GFX6-NEXT:    s_sext_i32_i16 s9, s0
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s9
-; GFX6-NEXT:    s_xor_b32 s8, s9, s8
+; GFX6-NEXT:    s_sext_i32_i16 s9, s2
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s9
+; GFX6-NEXT:    s_sext_i32_i16 s8, s0
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s8
+; GFX6-NEXT:    s_xor_b32 s9, s8, s9
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
+; GFX6-NEXT:    s_ashr_i32 s8, s9, 30
 ; GFX6-NEXT:    s_or_b32 s8, s8, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s8
+; GFX6-NEXT:    s_ashr_i32 s10, s2, 16
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
+; GFX6-NEXT:    v_mov_b32_e32 v3, s8
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s10
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
-; GFX6-NEXT:    s_ashr_i32 s2, s2, 16
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s2
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    s_ashr_i32 s0, s0, 16
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
+; GFX6-NEXT:    s_ashr_i32 s2, s0, 16
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v1
-; GFX6-NEXT:    s_xor_b32 s8, s0, s2
+; GFX6-NEXT:    s_xor_b32 s8, s2, s10
 ; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
 ; GFX6-NEXT:    s_or_b32 s8, s8, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
 ; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX6-NEXT:    v_mad_f32 v2, -v3, v1, v2
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s8
+; GFX6-NEXT:    s_sext_i32_i16 s8, s3
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v3, v3
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v4, vcc
+; GFX6-NEXT:    s_sext_i32_i16 s9, s1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s2
-; GFX6-NEXT:    s_sext_i32_i16 s2, s3
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v1
-; GFX6-NEXT:    s_sext_i32_i16 s0, s1
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s0
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s9
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
-; GFX6-NEXT:    s_xor_b32 s0, s0, s2
-; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
-; GFX6-NEXT:    s_or_b32 s0, s0, 1
-; GFX6-NEXT:    v_mul_f32_e32 v4, v1, v4
+; GFX6-NEXT:    s_xor_b32 s8, s9, s8
+; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
+; GFX6-NEXT:    s_or_b32 s8, s8, 1
+; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX6-NEXT:    v_mad_f32 v1, -v4, v2, v1
-; GFX6-NEXT:    v_mov_b32_e32 v5, s0
-; GFX6-NEXT:    s_ashr_i32 s0, s3, 16
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
+; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s0
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GFX6-NEXT:    s_ashr_i32 s2, s1, 16
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s2
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
-; GFX6-NEXT:    s_xor_b32 s3, s2, s0
-; GFX6-NEXT:    s_ashr_i32 s3, s3, 30
+; GFX6-NEXT:    v_mov_b32_e32 v5, s8
+; GFX6-NEXT:    s_ashr_i32 s8, s3, 16
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s8
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GFX6-NEXT:    s_ashr_i32 s3, s1, 16
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s3
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
+; GFX6-NEXT:    s_xor_b32 s9, s3, s8
+; GFX6-NEXT:    s_ashr_i32 s9, s9, 30
+; GFX6-NEXT:    s_or_b32 s9, s9, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v4
+; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
-; GFX6-NEXT:    s_or_b32 s3, s3, 1
-; GFX6-NEXT:    v_mov_b32_e32 v6, s3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v2|
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v6, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
+; GFX6-NEXT:    v_mov_b32_e32 v6, s9
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
+; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s10
+; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s8
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    s_mov_b32 s0, 0xffff
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_and_b32_e32 v1, s0, v1
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s2, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
+; GFX6-NEXT:    v_and_b32_e32 v1, s0, v1
 ; GFX6-NEXT:    v_or_b32_e32 v1, v1, v2
-; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v3
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v4
 ; GFX6-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_v4i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24

 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
 ; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_i3:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
-; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
+; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_bfe_u32 s0, s4, 0x30008
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s0
+; GFX9-NEXT:    s_bfe_u32 s3, s2, 0x30008
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s3
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX9-NEXT:    s_and_b32 s0, s4, 7
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v3, s0
-; GFX9-NEXT:    v_mul_f32_e32 v1, v3, v1
+; GFX9-NEXT:    s_and_b32 s2, s2, 7
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
+; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v1
-; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
+; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]
+; GFX9-NEXT:    global_store_byte v4, v0, s[0:1]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i3 %x, %y
   store i3 %r, i3 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @urem_i3(i3 addrspace(1)* %out, i3 %x, i3 %y) {
 ; CHECK-LABEL: @urem_i3(

 ; CHECK-NEXT:    [[TMP17:%.*]] = sub i32 [[TMP1]], [[TMP16]]
 ; CHECK-NEXT:    [[TMP18:%.*]] = and i32 [[TMP17]], 7
 ; CHECK-NEXT:    [[TMP19:%.*]] = trunc i32 [[TMP18]] to i3
 ; CHECK-NEXT:    store i3 [[TMP19]], i3 addrspace(1)* [[OUT:%.*]], align 1
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: urem_i3:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_bfe_u32 s1, s0, 0x30008
-; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s1
+; GFX6-NEXT:    s_bfe_u32 s2, s4, 0x30008
+; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v0, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX6-NEXT:    s_and_b32 s2, s0, 7
+; GFX6-NEXT:    s_and_b32 s2, s4, 7
 ; GFX6-NEXT:    v_cvt_f32_ubyte0_e32 v2, s2
-; GFX6-NEXT:    s_lshr_b32 s1, s0, 8
+; GFX6-NEXT:    s_lshr_b32 s2, s4, 8
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v1
 ; GFX6-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s1
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: urem_i3:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s2, s[0:1], 0x2c
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_bfe_u32 s3, s2, 0x30008
 ; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s3
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GFX9-NEXT:    s_and_b32 s4, s2, 7
-; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s4
+; GFX9-NEXT:    s_and_b32 s3, s2, 7
+; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v2, s3
 ; GFX9-NEXT:    s_lshr_b32 s3, s2, 8
 ; GFX9-NEXT:    v_mul_f32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v1
 ; GFX9-NEXT:    v_mad_f32 v1, -v1, v0, v2
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc

 ; CHECK-NEXT:    [[TMP21:%.*]] = shl i32 [[TMP20]], 29
 ; CHECK-NEXT:    [[TMP22:%.*]] = ashr i32 [[TMP21]], 29
 ; CHECK-NEXT:    [[TMP23:%.*]] = trunc i32 [[TMP22]] to i3
 ; CHECK-NEXT:    store i3 [[TMP23]], i3 addrspace(1)* [[OUT:%.*]], align 1
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: srem_i3:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_bfe_i32 s1, s0, 0x30008
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s1
-; GFX6-NEXT:    s_bfe_i32 s3, s0, 0x30000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s3
-; GFX6-NEXT:    s_xor_b32 s1, s3, s1
+; GFX6-NEXT:    s_bfe_i32 s2, s4, 0x30008
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GFX6-NEXT:    s_bfe_i32 s5, s4, 0x30000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s5
+; GFX6-NEXT:    s_xor_b32 s2, s5, s2
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GFX6-NEXT:    s_ashr_i32 s1, s1, 30
-; GFX6-NEXT:    s_or_b32 s1, s1, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s1
+; GFX6-NEXT:    s_ashr_i32 s2, s2, 30
+; GFX6-NEXT:    s_or_b32 s2, s2, 1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
-; GFX6-NEXT:    s_lshr_b32 s2, s0, 8
+; GFX6-NEXT:    s_lshr_b32 s3, s4, 8
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s2
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_and_b32_e32 v0, 7, v0
-; GFX6-NEXT:    buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i3:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
 ; GFX9-NEXT:    s_nop 0
 ; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)

 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s8, 0xffff
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_and_b32 s6, s0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GFX6-NEXT:    s_and_b32 s6, s2, s8
-; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GFX6-NEXT:    s_lshr_b32 s0, s0, 16
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s0
 ; GFX6-NEXT:    s_lshr_b32 s0, s2, 16
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, v4, v5
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    s_and_b32 s0, s1, s8
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GFX6-NEXT:    v_mad_f32 v2, -v1, v3, v4
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, s0
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
 ; GFX6-NEXT:    s_and_b32 s0, s3, s8
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v1
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v2, v4, v5
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_f32_e32 v2, v5, v6
 ; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v2
-; GFX6-NEXT:    v_mad_f32 v2, -v2, v4, v5
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NEXT:    v_mad_f32 v4, -v2, v3, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_f32_e32 v6, v5, v6
+; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mad_f32 v3, -v6, v1, v5
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v2
 ; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
-; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
-; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
+; GFX6-NEXT:    v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v3i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
 ; GFX9-NEXT:    s_mov_b32 s8, 0xffff
-; GFX9-NEXT:    v_mov_b32_e32 v1, 0
+; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX9-NEXT:    s_lshr_b32 s1, s4, 16
 ; GFX9-NEXT:    s_and_b32 s0, s6, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s0
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s0
 ; GFX9-NEXT:    s_and_b32 s0, s4, s8
-; GFX9-NEXT:    s_lshr_b32 s1, s6, 16
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s0
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v0
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
-; GFX9-NEXT:    s_lshr_b32 s0, s4, 16
+; GFX9-NEXT:    s_lshr_b32 s0, s6, 16
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v1
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT:    s_and_b32 s0, s7, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
 ; GFX9-NEXT:    v_mul_f32_e32 v3, v2, v3
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX9-NEXT:    v_mad_f32 v2, -v3, v0, v2
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
-; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
-; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX9-NEXT:    s_and_b32 s0, s7, s8
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_mad_f32 v3, -v2, v4, v5
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s0
+; GFX9-NEXT:    v_mad_f32 v2, -v3, v1, v2
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v1
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v3
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v2, s0
 ; GFX9-NEXT:    s_and_b32 s0, s5, s8
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v3, v4, v7
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v5
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
-; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
-; GFX9-NEXT:    v_mul_f32_e32 v3, v6, v7
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v2
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v3
-; GFX9-NEXT:    v_mad_f32 v3, -v3, v5, v6
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
-; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
-; GFX9-NEXT:    global_store_short v1, v3, s[2:3] offset:4
-; GFX9-NEXT:    global_store_dword v1, v0, s[2:3]
+; GFX9-NEXT:    v_mad_f32 v4, -v3, v5, v4
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX9-NEXT:    v_mul_f32_e32 v7, v6, v7
+; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v7
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
+; GFX9-NEXT:    v_mad_f32 v4, -v7, v2, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v2
+; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT:    global_store_short v0, v2, s[2:3] offset:4
+; GFX9-NEXT:    global_store_dword v0, v1, s[2:3]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv <3 x i16> %x, %y
   store <3 x i16> %r, <3 x i16> addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @urem_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %x, <3 x i16> %y) {
 ; CHECK-LABEL: @urem_v3i16(

 ; GFX6-LABEL: urem_v3i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s8, 0xffff
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mov_b32_e32 v1, s2
+; GFX6-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX6-NEXT:    s_and_b32 s6, s0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GFX6-NEXT:    s_and_b32 s6, s2, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s6
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GFX6-NEXT:    v_alignbit_b32 v4, s1, v4, 16
 ; GFX6-NEXT:    v_and_b32_e32 v5, s8, v4
-; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 16
-; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
-; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX6-NEXT:    v_mad_f32 v2, -v3, v0, v2
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v0
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v5
-; GFX6-NEXT:    v_and_b32_e32 v3, s8, v1
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, v5
+; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
+; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
+; GFX6-NEXT:    v_alignbit_b32 v3, s3, v3, 16
+; GFX6-NEXT:    v_and_b32_e32 v6, s8, v3
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
 ; GFX6-NEXT:    s_and_b32 s0, s1, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, v6
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX6-NEXT:    s_and_b32 s0, s3, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, s0
-; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v9, v2
+; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
+; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v1
+; GFX6-NEXT:    v_mad_f32 v1, -v1, v5, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v5
+; GFX6-NEXT:    v_mul_f32_e32 v5, v8, v9
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v6
-; GFX6-NEXT:    v_mad_f32 v3, -v5, v2, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, v4
+; GFX6-NEXT:    v_mad_f32 v4, -v5, v2, v8
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v2
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v3
-; GFX6-NEXT:    v_mad_f32 v3, -v3, v6, v7
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v6
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v2
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; GFX6-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: urem_v3i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24

 ; GFX9-NEXT:    s_lshr_b32 s4, s4, 16
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s4
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v2
 ; GFX9-NEXT:    v_mul_f32_e32 v3, v1, v3
 ; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v3
 ; GFX9-NEXT:    v_mad_f32 v1, -v3, v0, v1
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GFX9-NEXT:    v_mul_f32_e32 v1, v4, v5
+; GFX9-NEXT:    s_and_b32 s5, s5, s8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s1
-; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    s_and_b32 s1, s7, s8
-; GFX9-NEXT:    v_mad_f32 v3, -v1, v2, v4
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s1
-; GFX9-NEXT:    s_and_b32 s5, s5, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s5
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v6, v4
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v2
-; GFX9-NEXT:    v_sub_u32_e32 v0, s0, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s5
+; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
+; GFX9-NEXT:    v_trunc_f32_e32 v1, v5
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v1
+; GFX9-NEXT:    v_mad_f32 v1, -v1, v2, v4
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v2
+; GFX9-NEXT:    v_mul_f32_e32 v2, v6, v7
 ; GFX9-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v2
-; GFX9-NEXT:    v_mad_f32 v2, -v2, v4, v5
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
+; GFX9-NEXT:    v_mad_f32 v2, -v2, v3, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, s1
+; GFX9-NEXT:    v_sub_u32_e32 v0, s0, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    v_sub_u32_e32 v1, s4, v1
 ; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; GFX9-NEXT:    v_sub_u32_e32 v2, s5, v2
 ; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v0
 ; GFX9-NEXT:    global_store_short v3, v2, s[2:3] offset:4
 ; GFX9-NEXT:    global_store_dword v3, v0, s[2:3]
 ; GFX9-NEXT:    s_endpgm

 ;
 ; GFX6-LABEL: srem_v3i16:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_sext_i32_i16 s8, s2
-; GFX6-NEXT:    s_sext_i32_i16 s6, s0
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s6
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v1, s8
-; GFX6-NEXT:    s_xor_b32 s6, s8, s6
-; GFX6-NEXT:    s_ashr_i32 s6, s6, 30
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GFX6-NEXT:    s_sext_i32_i16 s6, s2
+; GFX6-NEXT:    s_sext_i32_i16 s8, s0
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v0, s8
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s6
+; GFX6-NEXT:    s_xor_b32 s8, s6, s8
+; GFX6-NEXT:    s_ashr_i32 s6, s8, 30
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v0
 ; GFX6-NEXT:    s_or_b32 s6, s6, 1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s6
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_mul_f32_e32 v2, v1, v2
-; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
-; GFX6-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
+; GFX6-NEXT:    v_mov_b32_e32 v4, s6
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s2
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v3, v2, v3
+; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX6-NEXT:    v_mad_f32 v2, -v3, v0, v2
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 16
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v3
 ; GFX6-NEXT:    v_bfe_i32 v3, v2, 0, 16
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v4, vcc
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, v3
 ; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 16
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v5
 ; GFX6-NEXT:    v_bfe_i32 v5, v1, 0, 16
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v6, v5
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v4
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
 ; GFX6-NEXT:    v_xor_b32_e32 v3, v5, v3
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s0
 ; GFX6-NEXT:    s_sext_i32_i16 s0, s1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    v_mad_f32 v6, -v5, v4, v6
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v7, v5
+; GFX6-NEXT:    v_mad_f32 v5, -v5, v4, v6
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v3, 30, v3
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v4|
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s0
 ; GFX6-NEXT:    v_or_b32_e32 v3, 1, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v3, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT:    s_sext_i32_i16 s2, s3
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX6-NEXT:    s_sext_i32_i16 s6, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s2
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s6
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v4
-; GFX6-NEXT:    s_xor_b32 s0, s2, s0
+; GFX6-NEXT:    s_xor_b32 s0, s6, s0
 ; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
 ; GFX6-NEXT:    s_or_b32 s0, s0, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v3, v5
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX6-NEXT:    v_mad_f32 v3, -v5, v4, v3
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
 ; GFX6-NEXT:    v_mov_b32_e32 v6, s0
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v4|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
 ; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, v1, v2
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
 ; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX6-NEXT:    buffer_store_short v2, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_v3i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34

 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
 ; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
 ; GFX6-NEXT:    s_and_b32 s9, s0, s3
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX6-NEXT:    s_and_b32 s8, s2, s3
-; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf000f
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
+; GFX6-NEXT:    v_mov_b32_e32 v2, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
-; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf000f
+; GFX6-NEXT:    s_bfe_u32 s0, s0, 0xf000f
 ; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s0
 ; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, v2
+; GFX6-NEXT:    s_bfe_u32 s2, s2, 0xf000f
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
-; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
 ; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v4, vcc
-; GFX6-NEXT:    v_mad_f32 v4, -v1, v5, v6
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v2
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v5
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_f32_e32 v1, v0, v6
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
+; GFX6-NEXT:    v_mul_f32_e32 v1, v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v1
-; GFX6-NEXT:    v_mad_f32 v0, -v1, v2, v0
+; GFX6-NEXT:    v_mad_f32 v6, -v1, v5, v6
+; GFX6-NEXT:    v_mul_f32_e32 v4, v0, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v4
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v1, vcc
+; GFX6-NEXT:    v_mad_f32 v0, -v4, v2, v0
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v2
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v7, vcc
 ; GFX6-NEXT:    v_and_b32_e32 v2, s3, v3
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_and_b32_e32 v3, s3, v4
+; GFX6-NEXT:    v_and_b32_e32 v3, s3, v5
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_waitcnt expcnt(0)
 ; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
 ; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v3i15:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34
 ; GFX9-NEXT:    s_movk_i32 s8, 0x7fff
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_and_b32 s0, s4, s8
 ; GFX9-NEXT:    s_and_b32 s1, s6, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s1
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s0
+; GFX9-NEXT:    v_mov_b32_e32 v3, s6
 ; GFX9-NEXT:    s_bfe_u32 s0, s6, 0xf000f
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s6
-; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_alignbit_b32 v3, s7, v3, 30
-; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s0
 ; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
+; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 30
-; GFX9-NEXT:    v_mul_f32_e32 v1, v7, v8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
 ; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mad_f32 v5, -v1, v6, v7
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, v0
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v3
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_f32_e32 v1, v0, v7
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v3
+; GFX9-NEXT:    v_mul_f32_e32 v1, v7, v8
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v1
-; GFX9-NEXT:    v_mad_f32 v0, -v1, v3, v0
+; GFX9-NEXT:    v_mad_f32 v7, -v1, v6, v7
+; GFX9-NEXT:    v_mul_f32_e32 v5, v0, v5
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v5
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
+; GFX9-NEXT:    v_mad_f32 v0, -v5, v3, v0
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v8, vcc
 ; GFX9-NEXT:    v_and_b32_e32 v3, s8, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, 0, v6, vcc
-; GFX9-NEXT:    v_and_b32_e32 v4, s8, v5
+; GFX9-NEXT:    v_and_b32_e32 v4, s8, v6
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v4, 15, v4
 ; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 30, v[0:1]
 ; GFX9-NEXT:    v_or_b32_e32 v3, v3, v4
 ; GFX9-NEXT:    v_or_b32_e32 v0, v3, v0
 ; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]
 ; GFX9-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
 ; GFX9-NEXT:    global_store_short v2, v0, s[2:3] offset:4
 ; GFX9-NEXT:    s_endpgm

 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
 ; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
 ; GFX6-NEXT:    s_and_b32 s10, s0, s3
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
-; GFX6-NEXT:    s_and_b32 s9, s2, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s9
-; GFX6-NEXT:    v_mov_b32_e32 v2, s0
+; GFX6-NEXT:    s_and_b32 s8, s2, s3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s8
+; GFX6-NEXT:    s_bfe_u32 s8, s0, 0xf000f
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v1
+; GFX6-NEXT:    v_mov_b32_e32 v2, s0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s8
 ; GFX6-NEXT:    v_alignbit_b32 v2, s1, v2, 30
-; GFX6-NEXT:    s_bfe_u32 s1, s0, 0xf000f
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mad_f32 v3, -v4, v1, v3
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v1
-; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
 ; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
-; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s2, v1
-; GFX6-NEXT:    v_mul_f32_e32 v1, v3, v4
+; GFX6-NEXT:    s_bfe_u32 s9, s2, 0xf000f
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v4, vcc
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v4, v2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v7, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mad_f32 v3, -v1, v5, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v4
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_lshr_b32 s0, s0, 15
-; GFX6-NEXT:    v_mul_f32_e32 v3, v7, v8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v6, s9
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v7, v5
+; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v9, v4
+; GFX6-NEXT:    v_mul_f32_e32 v3, v6, v7
 ; GFX6-NEXT:    v_trunc_f32_e32 v3, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v3
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mad_f32 v3, -v3, v4, v7
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v3
+; GFX6-NEXT:    v_mad_f32 v3, -v3, v5, v6
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, v5
+; GFX6-NEXT:    v_mul_f32_e32 v5, v8, v9
+; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v7, vcc
+; GFX6-NEXT:    v_mad_f32 v5, -v5, v4, v8
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, v4
+; GFX6-NEXT:    s_lshr_b32 s1, s0, 15
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v3, v2
-; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v4, v2
+; GFX6-NEXT:    s_lshr_b32 s0, s2, 15
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v3
 ; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s2, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
-; GFX6-NEXT:    v_and_b32_e32 v2, s3, v6
+; GFX6-NEXT:    v_and_b32_e32 v2, s3, v4
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_waitcnt expcnt(0)
 ; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
 ; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    s_endpgm

 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_alignbit_b32 v0, s5, v0, 30
 ; GFX9-NEXT:    s_and_b32 s5, s6, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5
 ; GFX9-NEXT:    s_and_b32 s0, s4, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s0
 ; GFX9-NEXT:    s_bfe_u32 s5, s6, 0xf000f
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v1
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s5
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s6
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s5
 ; GFX9-NEXT:    v_alignbit_b32 v3, s7, v3, 30
 ; GFX9-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX9-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mad_f32 v4, -v5, v1, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v1
-; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_and_b32_e32 v3, s8, v3
+; GFX9-NEXT:    s_bfe_u32 s1, s4, 0xf000f
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, v3
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s1
 ; GFX9-NEXT:    v_rcp_iflag_f32_e32 v8, v6
 ; GFX9-NEXT:    v_and_b32_e32 v0, s8, v0
-; GFX9-NEXT:    v_rcp_iflag_f32_e32 v9, v5
-; GFX9-NEXT:    s_lshr_b32 s0, s6, 15
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v9, v0
+; GFX9-NEXT:    v_rcp_iflag_f32_e32 v10, v5
 ; GFX9-NEXT:    v_mul_f32_e32 v4, v7, v8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX9-NEXT:    v_mad_f32 v7, -v4, v6, v7
-; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, v6
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX9-NEXT:    v_mul_f32_e32 v6, v8, v9
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v8, v4
+; GFX9-NEXT:    v_mad_f32 v4, -v4, v6, v7
+; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v6
+; GFX9-NEXT:    v_mul_f32_e32 v6, v9, v10
 ; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
-; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mad_f32 v6, -v6, v5, v9
 ; GFX9-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, v5
+; GFX9-NEXT:    s_lshr_b32 s0, s6, 15
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v4, s0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v5, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s6
 ; GFX9-NEXT:    s_lshr_b32 s0, s4, 15
 ; GFX9-NEXT:    v_sub_u32_e32 v4, s0, v4
 ; GFX9-NEXT:    v_and_b32_e32 v4, s8, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v5, s4, v1

 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v6, v4
 ; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GFX6-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, v5, v6
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mad_f32 v5, -v1, v4, v5
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v5|, |v4|
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v6, v1
+; GFX6-NEXT:    v_mad_f32 v1, -v1, v4, v5
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v4|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
 ; GFX6-NEXT:    s_movk_i32 s0, 0x7fff
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v6
 ; GFX6-NEXT:    v_and_b32_e32 v3, s0, v3
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
 ; GFX6-NEXT:    v_and_b32_e32 v2, s0, v2
 ; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_waitcnt expcnt(0)

 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX6-NEXT:    v_alignbit_b32 v0, s3, v0, 30
 ; GFX6-NEXT:    s_movk_i32 s3, 0x7fff
-; GFX6-NEXT:    s_and_b32 s11, s0, s3
-; GFX6-NEXT:    s_bfe_i32 s11, s11, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s11
-; GFX6-NEXT:    s_and_b32 s9, s2, s3
-; GFX6-NEXT:    s_bfe_i32 s9, s9, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s9
+; GFX6-NEXT:    s_and_b32 s10, s0, s3
+; GFX6-NEXT:    s_bfe_i32 s10, s10, 0xf0000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v2, s10
+; GFX6-NEXT:    s_and_b32 s8, s2, s3
+; GFX6-NEXT:    s_bfe_i32 s8, s8, 0xf0000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s8
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v2
-; GFX6-NEXT:    s_xor_b32 s9, s9, s11
-; GFX6-NEXT:    s_ashr_i32 s9, s9, 30
-; GFX6-NEXT:    s_or_b32 s9, s9, 1
+; GFX6-NEXT:    s_xor_b32 s8, s8, s10
+; GFX6-NEXT:    s_ashr_i32 s8, s8, 30
+; GFX6-NEXT:    s_or_b32 s8, s8, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GFX6-NEXT:    v_trunc_f32_e32 v4, v4
 ; GFX6-NEXT:    v_mad_f32 v3, -v4, v2, v3
+; GFX6-NEXT:    s_bfe_u32 s11, s0, 0xf000f
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v4, v4
-; GFX6-NEXT:    v_mov_b32_e32 v5, s9
+; GFX6-NEXT:    v_mov_b32_e32 v5, s8
+; GFX6-NEXT:    s_bfe_i32 s8, s11, 0xf0000
 ; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s8
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, 0, v5, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    s_bfe_u32 s12, s0, 0xf000f
+; GFX6-NEXT:    s_bfe_u32 s9, s2, 0xf000f
 ; GFX6-NEXT:    v_alignbit_b32 v1, s1, v1, 30
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
 ; GFX6-NEXT:    s_lshr_b32 s1, s0, 15
-; GFX6-NEXT:    s_bfe_i32 s0, s12, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v3, s0
-; GFX6-NEXT:    s_bfe_u32 s10, s2, 0xf000f
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
-; GFX6-NEXT:    s_lshr_b32 s8, s2, 15
-; GFX6-NEXT:    s_bfe_i32 s2, s10, 0xf0000
-; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s0
+; GFX6-NEXT:    s_bfe_i32 s0, s9, 0xf0000
+; GFX6-NEXT:    v_cvt_f32_i32_e32 v4, s0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v5, v3
-; GFX6-NEXT:    s_xor_b32 s0, s2, s0
+; GFX6-NEXT:    s_xor_b32 s0, s0, s8
 ; GFX6-NEXT:    s_ashr_i32 s0, s0, 30
 ; GFX6-NEXT:    s_or_b32 s0, s0, 1
 ; GFX6-NEXT:    v_mul_f32_e32 v5, v4, v5
 ; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
 ; GFX6-NEXT:    v_mad_f32 v4, -v5, v3, v4
 ; GFX6-NEXT:    v_cvt_i32_f32_e32 v5, v5
-; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
 ; GFX6-NEXT:    v_mov_b32_e32 v6, s0
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v3|
+; GFX6-NEXT:    v_and_b32_e32 v1, s3, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, 0, v6, vcc
 ; GFX6-NEXT:    v_bfe_i32 v4, v1, 0, 15
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v5, v4
 ; GFX6-NEXT:    v_and_b32_e32 v0, s3, v0
 ; GFX6-NEXT:    v_bfe_i32 v6, v0, 0, 15
 ; GFX6-NEXT:    v_cvt_f32_i32_e32 v7, v6
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v8, v5
 ; GFX6-NEXT:    v_xor_b32_e32 v4, v6, v4
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v4, 30, v4
 ; GFX6-NEXT:    v_or_b32_e32 v4, 1, v4
 ; GFX6-NEXT:    v_mul_f32_e32 v6, v7, v8
 ; GFX6-NEXT:    v_trunc_f32_e32 v6, v6
-; GFX6-NEXT:    v_mad_f32 v7, -v6, v5, v7
-; GFX6-NEXT:    v_cvt_i32_f32_e32 v6, v6
-; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v7|, |v5|
+; GFX6-NEXT:    v_cvt_i32_f32_e32 v8, v6
+; GFX6-NEXT:    v_mad_f32 v6, -v6, v5, v7
+; GFX6-NEXT:    v_cmp_ge_f32_e64 vcc, |v6|, |v5|
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, 0, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s1
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v4, v1
-; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v3
-; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
+; GFX6-NEXT:    s_lshr_b32 s0, s2, 15
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s0, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
+; GFX6-NEXT:    v_and_b32_e32 v3, s3, v3
 ; GFX6-NEXT:    v_lshl_b64 v[0:1], v[0:1], 30
+; GFX6-NEXT:    v_and_b32_e32 v2, s3, v2
+; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 15, v3
 ; GFX6-NEXT:    v_or_b32_e32 v2, v2, v3
 ; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
 ; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GFX6-NEXT:    s_waitcnt expcnt(0)
 ; GFX6-NEXT:    v_and_b32_e32 v0, 0x1fff, v1
 ; GFX6-NEXT:    buffer_store_short v0, off, s[4:7], 0 offset:4
 ; GFX6-NEXT:    s_endpgm
 ;

 define amdgpu_kernel void @udiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
 ; CHECK-LABEL: @udiv_i32_oddk_denom(
 ; CHECK-NEXT:    [[R:%.*]] = udiv i32 [[X:%.*]], 1235195
 ; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: udiv_i32_oddk_denom:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0xb2a50881
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s4, v0
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 1, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 20, v0
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_i32_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)

 ;
 ; GFX6-LABEL: udiv_v2i32_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
 ; GFX6-NEXT:    s_movk_i32 s4, 0x1000
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s8, s4, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
-; GFX6-NEXT:    s_lshl_b32 s9, s4, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT:    s_lshl_b32 s9, s4, s2
+; GFX6-NEXT:    s_lshl_b32 s8, s4, s3
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s8
+; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
+; GFX6-NEXT:    s_sub_i32 s3, 0, s8
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s0, 0x4f7ffffe
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v0, s0, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s0, v1
-; GFX6-NEXT:    s_sub_i32 s0, 0, s8
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v0
-; GFX6-NEXT:    s_sub_i32 s0, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
+; GFX6-NEXT:    s_sub_i32 s2, 0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s3, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s8
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s9
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s2, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s3, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s8
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 1, v1
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s0, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v2
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; GFX6-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s[0:1]
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v2i32_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX9-NEXT:    s_movk_i32 s4, 0x1000

 ; CHECK-NEXT:    [[TMP60:%.*]] = insertelement <2 x i32> [[TMP30]], i32 [[TMP59]], i64 1
 ; CHECK-NEXT:    store <2 x i32> [[TMP60]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: urem_v2i32_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
 ; GFX6-NEXT:    s_movk_i32 s4, 0x1000
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s8, s4, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
-; GFX6-NEXT:    s_lshl_b32 s3, s4, s3
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GFX6-NEXT:    s_mov_b32 s4, 0x4f7ffffe
+; GFX6-NEXT:    s_lshl_b32 s6, s4, s3
+; GFX6-NEXT:    s_lshl_b32 s7, s4, s2
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s7
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s6
+; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
+; GFX6-NEXT:    s_sub_i32 s3, 0, s6
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_f32_e32 v0, s4, v0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s4, v1
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; GFX6-NEXT:    s_sub_i32 s2, 0, s7
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s7
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s6
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s6, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
+; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: urem_v2i32_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX9-NEXT:    s_movk_i32 s4, 0x1000
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshl_b32 s5, s4, s3

 define amdgpu_kernel void @sdiv_i32_oddk_denom(i32 addrspace(1)* %out, i32 %x) {
 ; CHECK-LABEL: @sdiv_i32_oddk_denom(
 ; CHECK-NEXT:    [[R:%.*]] = sdiv i32 [[X:%.*]], 1235195
 ; CHECK-NEXT:    store i32 [[R]], i32 addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: sdiv_i32_oddk_denom:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0xb
+; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xb
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0xd9528441
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_hi_i32 v0, s0, v0
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_mul_hi_i32 v0, s4, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
 ; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 31, v0
 ; GFX6-NEXT:    v_ashrrev_i32_e32 v0, 20, v0
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_i32_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)

 ; CHECK-NEXT:    [[TMP81:%.*]] = sub i32 [[TMP80]], [[TMP46]]
 ; CHECK-NEXT:    [[TMP82:%.*]] = insertelement <2 x i32> [[TMP41]], i32 [[TMP81]], i64 1
 ; CHECK-NEXT:    store <2 x i32> [[TMP82]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: sdiv_v2i32_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GFX6-NEXT:    s_movk_i32 s10, 0x1000
-; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT:    s_movk_i32 s6, 0x1000
+; GFX6-NEXT:    s_mov_b32 s12, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0xb
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s2, s10, s2
-; GFX6-NEXT:    s_ashr_i32 s11, s2, 31
-; GFX6-NEXT:    s_add_i32 s2, s2, s11
-; GFX6-NEXT:    s_xor_b32 s12, s2, s11
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GFX6-NEXT:    s_lshl_b32 s0, s10, s3
-; GFX6-NEXT:    s_sub_i32 s3, 0, s12
+; GFX6-NEXT:    s_lshl_b32 s2, s6, s2
+; GFX6-NEXT:    s_ashr_i32 s10, s2, 31
+; GFX6-NEXT:    s_add_i32 s2, s2, s10
+; GFX6-NEXT:    s_xor_b32 s11, s2, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s11
+; GFX6-NEXT:    s_lshl_b32 s0, s6, s3
 ; GFX6-NEXT:    s_ashr_i32 s2, s0, 31
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    s_add_i32 s0, s0, s2
-; GFX6-NEXT:    s_xor_b32 s10, s0, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
-; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
+; GFX6-NEXT:    s_xor_b32 s13, s0, s2
+; GFX6-NEXT:    s_sub_i32 s0, 0, s11
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
+; GFX6-NEXT:    v_mul_f32_e32 v0, s12, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    s_ashr_i32 s1, s8, 31
-; GFX6-NEXT:    s_add_i32 s0, s8, s1
-; GFX6-NEXT:    s_xor_b32 s0, s0, s1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s3, v0
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; GFX6-NEXT:    s_xor_b32 s3, s1, s11
+; GFX6-NEXT:    s_sub_i32 s3, 0, s13
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v0
+; GFX6-NEXT:    s_ashr_i32 s0, s8, 31
+; GFX6-NEXT:    s_add_i32 s1, s8, s0
+; GFX6-NEXT:    s_xor_b32 s1, s1, s0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v1, s12, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s12
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s0, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s12, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
-; GFX6-NEXT:    s_sub_i32 s0, 0, s10
-; GFX6-NEXT:    v_mul_lo_u32 v3, s0, v1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s3, v1
+; GFX6-NEXT:    s_xor_b32 s3, s0, s10
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s11
+; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s1, v3
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
 ; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
 ; GFX6-NEXT:    s_add_i32 s1, s9, s0
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, s0
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, 1, v0
-; GFX6-NEXT:    s_xor_b32 s2, s0, s2
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s10
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s13
+; GFX6-NEXT:    s_xor_b32 s2, s0, s2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
+; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s10, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, 1, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
 ; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_v2i32_pow2_shl_denom:
 ; GFX9:       ; %bb.0:

 ; CHECK-NEXT:    [[TMP74:%.*]] = xor i32 [[TMP73]], [[TMP41]]
 ; CHECK-NEXT:    [[TMP75:%.*]] = sub i32 [[TMP74]], [[TMP41]]
 ; CHECK-NEXT:    [[TMP76:%.*]] = insertelement <2 x i32> [[TMP38]], i32 [[TMP75]], i64 1
 ; CHECK-NEXT:    store <2 x i32> [[TMP76]], <2 x i32> addrspace(1)* [[OUT:%.*]], align 8
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: srem_v2i32_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xb
+; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
 ; GFX6-NEXT:    s_movk_i32 s6, 0x1000
-; GFX6-NEXT:    s_mov_b32 s10, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s9, 0x4f7ffffe
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b32 s2, s6, s2
-; GFX6-NEXT:    s_ashr_i32 s4, s2, 31
-; GFX6-NEXT:    s_add_i32 s2, s2, s4
-; GFX6-NEXT:    s_xor_b32 s9, s2, s4
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s9
-; GFX6-NEXT:    s_lshl_b32 s2, s6, s3
-; GFX6-NEXT:    s_ashr_i32 s6, s2, 31
-; GFX6-NEXT:    s_add_i32 s2, s2, s6
+; GFX6-NEXT:    s_lshl_b32 s0, s6, s0
+; GFX6-NEXT:    s_ashr_i32 s8, s0, 31
+; GFX6-NEXT:    s_add_i32 s0, s0, s8
+; GFX6-NEXT:    s_xor_b32 s8, s0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT:    s_lshl_b32 s0, s6, s1
+; GFX6-NEXT:    s_ashr_i32 s1, s0, 31
+; GFX6-NEXT:    s_add_i32 s0, s0, s1
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX6-NEXT:    s_sub_i32 s8, 0, s9
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xb
-; GFX6-NEXT:    v_mul_f32_e32 v0, s10, v0
+; GFX6-NEXT:    s_xor_b32 s10, s0, s1
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s10
+; GFX6-NEXT:    s_sub_i32 s1, 0, s8
+; GFX6-NEXT:    v_mul_f32_e32 v0, s9, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s3, s0, 31
-; GFX6-NEXT:    s_add_i32 s0, s0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v0
-; GFX6-NEXT:    s_xor_b32 s8, s2, s6
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s8
-; GFX6-NEXT:    s_xor_b32 s0, s0, s3
-; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
+; GFX6-NEXT:    s_ashr_i32 s0, s2, 31
 ; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s10, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s1, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s9, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
-; GFX6-NEXT:    s_ashr_i32 s0, s1, 31
-; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v0
-; GFX6-NEXT:    s_add_i32 s1, s1, s0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
+; GFX6-NEXT:    s_add_i32 s1, s2, s0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    s_sub_i32 s2, 0, s10
+; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, s0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
+; GFX6-NEXT:    v_mul_hi_u32 v2, v1, v3
+; GFX6-NEXT:    s_ashr_i32 s2, s3, 31
+; GFX6-NEXT:    s_add_i32 s3, s3, s2
+; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GFX6-NEXT:    s_xor_b32 s3, s3, s2
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v0
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s8
-; GFX6-NEXT:    v_xor_b32_e32 v0, s3, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s3, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s1, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v1, s3, v1
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s1, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s10
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v0, s0, v0
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s3, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v1, s0, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s0, v1
+; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v1, vcc, s2, v1
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_v2i32_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dwordx2 s[6:7], s[0:1], 0x34

 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: udiv_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
-; GFX6-NEXT:    s_mov_b32 s3, 0x68958c89
+; GFX6-NEXT:    s_movk_i32 s4, 0xfee0
+; GFX6-NEXT:    s_mov_b32 s5, 0x68958c89
 ; GFX6-NEXT:    v_mov_b32_e32 v8, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mov_b32_e32 v7, 0
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX6-NEXT:    s_mov_b32 s11, 0xf000
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s5
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s5
+; GFX6-NEXT:    s_mov_b32 s10, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    s_movk_i32 s4, 0x11e
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s3
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s3
-; GFX6-NEXT:    s_mov_b32 s2, 0x976a7377
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s5
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, s5
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v9
 ; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GFX6-NEXT:    s_movk_i32 s3, 0x11f
-; GFX6-NEXT:    s_mov_b32 s9, s5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v5
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v9
+; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT:    s_movk_i32 s4, 0x11e
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v10
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT:    s_movk_i32 s3, 0x11f
+; GFX6-NEXT:    s_mov_b32 s2, 0x976a7377
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s2
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s2
 ; GFX6-NEXT:    v_mov_b32_e32 v5, s3
+; GFX6-NEXT:    s_mov_b32 s9, s5
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s2
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s7, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
 ; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
 ; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]

 ; GFX9-LABEL: udiv_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f176a73
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s4, 0xfee0
 ; GFX9-NEXT:    s_mov_b32 s5, 0x68958c89
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_movk_i32 s8, 0x11f
 ; GFX9-NEXT:    s_mov_b32 s9, 0x976a7376
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s5
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, s5
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v2, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s5
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v7, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    s_mov_b32 s2, 0x976a7377
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s2
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s8
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v4, s7, v2
 ; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[0:1], s6, v3
 ; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1]
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s2, v3
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    s_movk_i32 s6, 0x11e
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v5
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v4
-; GFX9-NEXT:    v_cndmask_b32_e32 v4, v7, v5, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, 2, v0
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[2:3]
-; GFX9-NEXT:    v_mov_b32_e32 v7, s7
-; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v7, v2, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v6, s[2:3]
+; GFX9-NEXT:    v_mov_b32_e32 v6, s7
+; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v6, v2, s[0:1]
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v2
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s9, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v2
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v5, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT:    global_store_dwordx2 v7, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv i64 %x, 1235195949943
   store i64 %r, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @udiv_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
 ; CHECK-LABEL: @udiv_i64_pow2k_denom(

 ; CHECK-NEXT:    store <2 x i64> [[TMP6]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: udiv_v2i64_mixed_pow2k_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s6, 0xf001
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_movk_i32 s4, 0xf001
+; GFX6-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX6-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GFX6-NEXT:    s_movk_i32 s0, 0xfff
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s6
-; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s6
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s6
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x9
+; GFX6-NEXT:    s_mov_b32 s11, 0xf000
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GFX6-NEXT:    s_mov_b32 s10, -1
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v3
+; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v3
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v1, v3
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v2, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s6
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s4
 ; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
-; GFX6-NEXT:    v_mul_lo_u32 v6, v3, s6
-; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v3, s4
+; GFX6-NEXT:    v_mul_lo_u32 v8, v0, s4
 ; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v5
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v8
 ; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v7, v10, vcc
+; GFX6-NEXT:    s_movk_i32 s0, 0xfff
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v6, v10, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v10, v3, v8
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v3, v8
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
-; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v9, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v2, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v10
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v2, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
 ; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v6, s11, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
+; GFX6-NEXT:    v_mul_lo_u32 v3, s6, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GFX6-NEXT:    s_lshr_b64 s[2:3], s[8:9], 12
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT:    s_lshr_b64 s[2:3], s[4:5], 12
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v6, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v7, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s0
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s0
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mov_b32_e32 v3, s11
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
+; GFX6-NEXT:    v_mov_b32_e32 v3, s7
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s6, v4
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s0, v4
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
 ; GFX6-NEXT:    s_movk_i32 s0, 0xffe
 ; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
 ; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, -1, v4, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, v1, v3, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v7, v5, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v0, v1, s[0:1]
 ; GFX6-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX6-NEXT:    v_mov_b32_e32 v1, s3
-; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udiv_v2i64_mixed_pow2k_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x457ff000
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s4, 0xf001
-; GFX9-NEXT:    v_mov_b32_e32 v7, 0
-; GFX9-NEXT:    v_mov_b32_e32 v5, 0
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_movk_i32 s8, 0xfff
 ; GFX9-NEXT:    v_mul_hi_u32 v2, v0, s4
-; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s4
+; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s4
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
-; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
-; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_lo_u32 v4, v0, v2
+; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
+; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v3
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
+; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v3
-; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v3, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, s4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v2, s4
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, s4
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, s4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s4
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v4
+; GFX9-NEXT:    v_sub_u32_e32 v5, v5, v0
+; GFX9-NEXT:    v_add_u32_e32 v5, v5, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v5
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v7, v10, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v6, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v5
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshr_b64 s[4:5], s[4:5], 12
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v9, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v6, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v7, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v11, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s8
-; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s6, v4
+; GFX9-NEXT:    v_sub_co_u32_e32 v5, vcc, s6, v5
 ; GFX9-NEXT:    s_movk_i32 s6, 0xffe
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s7
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
-; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v4
+; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v5
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v6
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 2, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 1, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v4
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v5
+; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v4, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v2, -1, v5, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v9, v7, s[0:1]
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v8, v6, s[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s4
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_store_dwordx4 v5, v[0:3], s[2:3]
+; GFX9-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX9-NEXT:    s_endpgm
   %r = udiv <2 x i64> %x, <i64 4096, i64 4095>
   store <2 x i64> %r, <2 x i64> addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @udiv_v2i64_pow2_shl_denom(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
 ; CHECK-LABEL: @udiv_v2i64_pow2_shl_denom(

 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: urem_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s2, 0xfee0
-; GFX6-NEXT:    s_mov_b32 s3, 0x689e0837
+; GFX6-NEXT:    s_movk_i32 s4, 0xfee0
+; GFX6-NEXT:    s_mov_b32 s5, 0x689e0837
 ; GFX6-NEXT:    v_mov_b32_e32 v8, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mov_b32_e32 v7, 0
-; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s3
-; GFX6-NEXT:    v_mul_lo_u32 v4, v1, s3
 ; GFX6-NEXT:    s_movk_i32 s12, 0x11f
+; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v5, v1, s5
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s5
 ; GFX6-NEXT:    s_mov_b32 s13, 0x9761f7c9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v3
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s9, s5
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GFX6-NEXT:    s_movk_i32 s5, 0x11e
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v3, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v6, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
+; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GFX6-NEXT:    s_mov_b32 s11, 0xf000
+; GFX6-NEXT:    s_mov_b32 s10, -1
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s3
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s3
-; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, s5
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, s5
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, s5
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_mul_lo_u32 v6, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v9
 ; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v5
 ; GFX6-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GFX6-NEXT:    s_mov_b32 s4, 0x9761f7c8
-; GFX6-NEXT:    s_mov_b32 s11, 0xf000
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v2, v5
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_mov_b32 s9, s5
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v10, v2, v9
+; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    s_mov_b32 s10, -1
-; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
+; GFX6-NEXT:    s_movk_i32 s5, 0x11e
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v10
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s6, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v5, s7, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GFX6-NEXT:    s_mov_b32 s8, s4
+; GFX6-NEXT:    s_mov_b32 s4, 0x9761f7c8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v0, s12
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v0, s13
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s13

 ; GFX9-LABEL: urem_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f1761f8
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX9-NEXT:    v_madmk_f32 v0, v1, 0x438f8000, v0
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s4, 0xfee0
 ; GFX9-NEXT:    s_mov_b32 s5, 0x689e0837
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_movk_i32 s8, 0x11f
 ; GFX9-NEXT:    s_mov_b32 s9, 0x9761f7c9
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s4
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v1, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s5
 ; GFX9-NEXT:    s_mov_b32 s10, 0x9761f7c8
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s4
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, s5
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v2, s5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v0, s5
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v2, v4
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v8, v7
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v2, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v9
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v7, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, s9
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s9
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_sub_co_u32_e64 v0, s[0:1], s6, v0
 ; GFX9-NEXT:    v_sub_u32_e32 v2, s7, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s8
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1]
 ; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[2:3], s9, v0
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, vcc, 0, v2, s[2:3]
 ; GFX9-NEXT:    s_movk_i32 s6, 0x11e
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v5
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v5
-; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s9, v4
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
-; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v7
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s7
 ; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v5, v1, s[0:1]
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s6, v1
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u32_e32 vcc, s10, v0
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s8, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v7, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    global_store_dwordx2 v6, v[0:1], s[4:5]
+; GFX9-NEXT:    global_store_dwordx2 v7, v[0:1], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %r = urem i64 %x, 1235195393993
   store i64 %r, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @urem_i64_pow2k_denom(i64 addrspace(1)* %out, i64 %x) {
 ; CHECK-LABEL: @urem_i64_pow2k_denom(

 ; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: sdiv_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s2, 0xffed2705
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_mov_b32 s8, 0xffed2705
+; GFX6-NEXT:    v_mov_b32_e32 v6, 0
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s4, s8
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s8
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s8
+; GFX6-NEXT:    v_mul_hi_u32 v7, s8, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
-; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, v8, v12, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s2
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s0, s6, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_addc_u32 s1, s7, s2
 ; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s1, s11, s2
 ; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v5, s1, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s3, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s3
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
 ; GFX6-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s3, v4
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
 ; GFX6-NEXT:    s_mov_b32 s0, 0x12d8fa
 ; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v3

 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_mov_b32 s8, 0xffed2705
-; GFX9-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
-; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
+; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
 ; GFX9-NEXT:    s_add_u32 s0, s6, s2
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_mov_b32 s3, s2
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s2
 ; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
+; GFX9-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s3
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0
 ; GFX9-NEXT:    v_sub_co_u32_e32 v4, vcc, s0, v4
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v3, v2, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s3, v4

 ; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: sdiv_i64_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s3, 0
 ; GFX6-NEXT:    s_movk_i32 s2, 0x1000
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
-; GFX6-NEXT:    s_ashr_i32 s12, s3, 31
-; GFX6-NEXT:    s_add_u32 s2, s2, s12
-; GFX6-NEXT:    s_mov_b32 s13, s12
-; GFX6-NEXT:    s_addc_u32 s3, s3, s12
-; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GFX6-NEXT:    s_sub_u32 s4, 0, s2
-; GFX6-NEXT:    s_subb_u32 s5, 0, s3
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
+; GFX6-NEXT:    s_ashr_i32 s8, s3, 31
+; GFX6-NEXT:    s_add_u32 s2, s2, s8
+; GFX6-NEXT:    s_mov_b32 s9, s8
+; GFX6-NEXT:    s_addc_u32 s3, s3, s8
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s11
+; GFX6-NEXT:    s_sub_u32 s12, 0, s10
+; GFX6-NEXT:    s_subb_u32 s4, 0, s11
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s15, s14
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v6, s12, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v6, s12, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, s12, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, s12, v0
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s0, s6, s2
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; GFX6-NEXT:    s_addc_u32 s1, s7, s2
+; GFX6-NEXT:    s_mov_b32 s3, s2
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[0:1], s[2:3]
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mov_b32_e32 v6, 0
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s4, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
-; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
+; GFX6-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GFX6-NEXT:    s_mov_b32 s4, s8
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, s3, v0
-; GFX6-NEXT:    v_mov_b32_e32 v5, s3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s11, v0
+; GFX6-NEXT:    v_mov_b32_e32 v5, s11
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s10, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s13, v2
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s12, v3
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
 ; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
 ; GFX6-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
 ; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v6, s11
+; GFX6-NEXT:    v_mov_b32_e32 v6, s13
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
+; GFX6-NEXT:    s_xor_b64 s[0:1], s[2:3], s[8:9]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v0, s0, v0
 ; GFX6-NEXT:    v_xor_b32_e32 v1, s1, v1
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
 ; GFX9-NEXT:    s_mov_b32 s3, 0
 ; GFX9-NEXT:    s_movk_i32 s2, 0x1000
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s8, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s8
 ; GFX9-NEXT:    s_mov_b32 s9, s8
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s8
 ; GFX9-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s10
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s11
 ; GFX9-NEXT:    s_sub_u32 s12, 0, s10
 ; GFX9-NEXT:    s_subb_u32 s4, 0, s11
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s12, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1
-; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v5, s12, v0
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s12, v1
+; GFX9-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX9-NEXT:    v_mul_lo_u32 v6, s12, v0
+; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
+; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
-; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
-; GFX9-NEXT:    v_mul_lo_u32 v5, s12, v3
+; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v3, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v1, v5, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v6, s12, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s12, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s12, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
-; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v5
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v5
+; GFX9-NEXT:    v_add_u32_e32 v6, v7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, s12, v0
+; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s12, s7, 31
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX9-NEXT:    s_add_u32 s0, s6, s12
-; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
 ; GFX9-NEXT:    s_mov_b32 s13, s12
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s12
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[12:13]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v5, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v3, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s11, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v6, s11
 ; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v0
 ; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
 ; GFX9-NEXT:    v_sub_u32_e32 v5, s7, v3

 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x457ff000
 ; GFX6-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_movk_i32 s6, 0xf001
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_movk_i32 s10, 0xf001
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xd
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s0, s9, 31
-; GFX6-NEXT:    s_lshr_b32 s0, s0, 20
-; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v3, v1, s6
-; GFX6-NEXT:    s_add_u32 s2, s8, s0
-; GFX6-NEXT:    s_addc_u32 s3, s9, 0
-; GFX6-NEXT:    s_ashr_i32 s8, s11, 31
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, s6
+; GFX6-NEXT:    s_ashr_i32 s2, s5, 31
+; GFX6-NEXT:    s_lshr_b32 s8, s2, 20
+; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s10
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s10
+; GFX6-NEXT:    s_add_u32 s4, s4, s8
+; GFX6-NEXT:    s_addc_u32 s5, s5, 0
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v4
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    s_ashr_i64 s[2:3], s[2:3], 12
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
-; GFX6-NEXT:    s_mov_b32 s9, s8
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mov_b32_e32 v6, 0
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v5, v2, s6
-; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v5, v2, s10
+; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v0
+; GFX6-NEXT:    s_ashr_i64 s[8:9], s[4:5], 12
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s10
 ; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s8
-; GFX6-NEXT:    s_addc_u32 s1, s11, s8
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s4, s6, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[8:9]
+; GFX6-NEXT:    s_addc_u32 s5, s7, s2
+; GFX6-NEXT:    s_mov_b32 s3, s2
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[4:5], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s1, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
-; GFX6-NEXT:    s_movk_i32 s9, 0xfff
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_movk_i32 s0, 0xfff
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s9
-; GFX6-NEXT:    v_mul_hi_u32 v3, s9, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s9
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s0
+; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s0
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s0, v4
-; GFX6-NEXT:    v_mov_b32_e32 v3, s1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s11
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s9, v4
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s0, v4
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
 ; GFX6-NEXT:    s_movk_i32 s0, 0xffe
 ; GFX6-NEXT:    v_cmp_lt_u32_e32 vcc, s0, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
 ; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
 ; GFX6-NEXT:    v_cmp_lt_u32_e64 s[0:1], s0, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
 ; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, -1, v4, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v7, v5, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s8, v0
-; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s8
+; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s2, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s2, v1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s2
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v1, v3, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v0, s2
-; GFX6-NEXT:    v_mov_b32_e32 v1, s3
+; GFX6-NEXT:    v_mov_b32_e32 v0, s8
+; GFX6-NEXT:    v_mov_b32_e32 v1, s9
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: ssdiv_v2i64_mixed_pow2k_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x457ff000
 ; GFX9-NEXT:    v_mov_b32_e32 v1, 0x4f800000
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_movk_i32 s8, 0xf001
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
 ; GFX9-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s5, 31
-; GFX9-NEXT:    s_lshr_b32 s2, s2, 20
-; GFX9-NEXT:    v_mul_hi_u32 v2, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s8
+; GFX9-NEXT:    s_lshr_b32 s9, s2, 20
+; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s8
-; GFX9-NEXT:    s_add_u32 s4, s4, s2
+; GFX9-NEXT:    s_add_u32 s4, s4, s9
 ; GFX9-NEXT:    s_addc_u32 s5, s5, 0
-; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v3, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v5
+; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v6, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v8, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v2, s8
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
+; GFX9-NEXT:    s_ashr_i64 s[4:5], s[4:5], 12
 ; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX9-NEXT:    v_sub_u32_e32 v5, v5, v0
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v5
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v4, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
 ; GFX9-NEXT:    s_add_u32 s6, s6, s2
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_mov_b32 s3, s2
 ; GFX9-NEXT:    s_addc_u32 s7, s7, s2
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[2:3]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s6, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
 ; GFX9-NEXT:    s_movk_i32 s3, 0xfff
+; GFX9-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x24
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v5, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s3
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v0

 ; CHECK-NEXT:    store <2 x i64> [[TMP8]], <2 x i64> addrspace(1)* [[OUT:%.*]], align 16
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
 ; GFX6-NEXT:    s_mov_b32 s3, 0
 ; GFX6-NEXT:    s_movk_i32 s2, 0x1000
-; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
-; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
+; GFX6-NEXT:    s_mov_b32 s20, 0x4f800000
+; GFX6-NEXT:    s_mov_b32 s21, 0x5f7ffffc
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b64 s[12:13], s[2:3], s6
+; GFX6-NEXT:    s_lshl_b64 s[10:11], s[2:3], s6
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX6-NEXT:    s_ashr_i32 s16, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s16
 ; GFX6-NEXT:    s_mov_b32 s17, s16
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s16
-; GFX6-NEXT:    s_xor_b64 s[14:15], s[2:3], s[16:17]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s14
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s15
-; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
-; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
-; GFX6-NEXT:    s_sub_u32 s6, 0, s14
-; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
+; GFX6-NEXT:    s_xor_b64 s[8:9], s[2:3], s[16:17]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT:    s_mov_b32 s22, 0x2f800000
+; GFX6-NEXT:    s_mov_b32 s23, 0xcf800000
+; GFX6-NEXT:    s_sub_u32 s4, 0, s8
+; GFX6-NEXT:    v_mac_f32_e32 v0, s20, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_subb_u32 s7, 0, s15
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
+; GFX6-NEXT:    s_subb_u32 s5, 0, s9
+; GFX6-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mul_f32_e32 v0, s21, v0
+; GFX6-NEXT:    v_mul_f32_e32 v1, s22, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
+; GFX6-NEXT:    v_mac_f32_e32 v0, s23, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v0
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v0
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s5, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s2, s9, 31
-; GFX6-NEXT:    s_add_u32 s0, s8, s2
+; GFX6-NEXT:    s_ashr_i32 s2, s13, 31
+; GFX6-NEXT:    s_add_u32 s4, s12, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_addc_u32 s5, s13, s2
 ; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s1, s9, s2
-; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[4:5], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s13, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s9, v0
-; GFX6-NEXT:    s_xor_b64 s[2:3], s[2:3], s[16:17]
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT:    s_ashr_i32 s18, s11, 31
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s14, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s14, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s15, v0
-; GFX6-NEXT:    v_mov_b32_e32 v7, s15
+; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
+; GFX6-NEXT:    v_mov_b32_e32 v7, s9
+; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[16:17]
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_lo_u32 v3, s14, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v0
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s9, v2
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s8, v3
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s13, v2
+; GFX6-NEXT:    s_mov_b32 s19, s18
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s12, v3
 ; GFX6-NEXT:    v_subb_u32_e64 v5, s[0:1], v5, v7, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s14, v3
+; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s8, v3
 ; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s15, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s14, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s15, v5
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, v8, v7, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v0
 ; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v0
 ; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v1, s[0:1]
-; GFX6-NEXT:    s_ashr_i32 s8, s13, 31
+; GFX6-NEXT:    s_add_u32 s0, s10, s18
+; GFX6-NEXT:    s_addc_u32 s1, s11, s18
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[18:19]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v11, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v12, s11
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v5
-; GFX6-NEXT:    s_add_u32 s12, s12, s8
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, v10, v8, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v8, s9
-; GFX6-NEXT:    s_mov_b32 s9, s8
-; GFX6-NEXT:    s_addc_u32 s13, s13, s8
-; GFX6-NEXT:    s_xor_b64 s[12:13], s[12:13], s[8:9]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s12
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v11, s13
+; GFX6-NEXT:    v_mov_b32_e32 v8, s13
+; GFX6-NEXT:    v_mac_f32_e32 v11, s20, v12
 ; GFX6-NEXT:    v_subb_u32_e32 v2, vcc, v8, v2, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s15, v2
-; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s14, v3
+; GFX6-NEXT:    v_rcp_f32_e32 v8, v11
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX6-NEXT:    v_mul_f32_e32 v8, s21, v8
+; GFX6-NEXT:    v_mul_f32_e32 v11, s22, v8
+; GFX6-NEXT:    v_trunc_f32_e32 v11, v11
+; GFX6-NEXT:    v_mac_f32_e32 v8, s23, v11
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v8, v8
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v11, v11
+; GFX6-NEXT:    s_sub_u32 s8, 0, s10
+; GFX6-NEXT:    s_subb_u32 s12, 0, s11
+; GFX6-NEXT:    v_mul_hi_u32 v12, s8, v8
+; GFX6-NEXT:    v_mul_lo_u32 v13, s8, v11
 ; GFX6-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v2
-; GFX6-NEXT:    v_mac_f32_e32 v10, s18, v11
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GFX6-NEXT:    v_rcp_f32_e32 v3, v10
-; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
-; GFX6-NEXT:    s_sub_u32 s14, 0, s12
-; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v3
-; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v3
-; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v5
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
+; GFX6-NEXT:    v_mul_lo_u32 v14, s12, v8
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v10, v3, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v10, s8, v8
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v12, v13
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v14
+; GFX6-NEXT:    v_mul_lo_u32 v13, v8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v14, v8, v10
+; GFX6-NEXT:    v_mul_hi_u32 v12, v8, v3
+; GFX6-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v9, v7, s[0:1]
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v2, s14, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, s14, v5
-; GFX6-NEXT:    s_subb_u32 s15, 0, s13
-; GFX6-NEXT:    v_mul_lo_u32 v8, s15, v3
-; GFX6-NEXT:    v_xor_b32_e32 v0, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, s14, v3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; GFX6-NEXT:    v_mul_lo_u32 v8, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GFX6-NEXT:    v_mul_hi_u32 v11, v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v5, v2
-; GFX6-NEXT:    v_xor_b32_e32 v1, s3, v1
+; GFX6-NEXT:    v_mul_lo_u32 v9, v11, v10
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[2:3]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v14, v13
+; GFX6-NEXT:    v_mul_hi_u32 v10, v11, v10
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v12, v11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, v11, v3
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v10, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v12, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GFX6-NEXT:    v_add_i32_e64 v3, s[0:1], v8, v3
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v7, vcc, v11, v5, s[0:1]
+; GFX6-NEXT:    v_mul_lo_u32 v8, s8, v7
+; GFX6-NEXT:    v_mul_hi_u32 v9, s8, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v3
+; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
 ; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v5, v7
-; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v11, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, s8, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; GFX6-NEXT:    v_mul_lo_u32 v10, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v13, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v12, v3, v9
+; GFX6-NEXT:    v_mul_hi_u32 v14, v7, v9
+; GFX6-NEXT:    v_mul_lo_u32 v9, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v12, v10
+; GFX6-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v12, v14, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_add_i32_e64 v2, s[0:1], v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v8, s14, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, s14, v2
-; GFX6-NEXT:    v_mul_lo_u32 v10, s15, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_mul_lo_u32 v9, s14, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v13, v2, v9
-; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v9
-; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GFX6-NEXT:    v_addc_u32_e32 v13, vcc, 0, v14, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v13, v11, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v10, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
-; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    s_mov_b32 s15, s14
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
+; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[0:1]
+; GFX6-NEXT:    s_add_u32 s0, s14, s2
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    s_mov_b32 s3, s2
+; GFX6-NEXT:    s_addc_u32 s1, s15, s2
+; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v10, s11, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, s8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v7, s8, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, s8, v3
+; GFX6-NEXT:    v_mul_hi_u32 v10, s9, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v3
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v9, s11, v2
-; GFX6-NEXT:    v_mul_hi_u32 v2, s11, v2
-; GFX6-NEXT:    v_mov_b32_e32 v8, s3
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v8, s9, v2
+; GFX6-NEXT:    v_mul_hi_u32 v2, s9, v2
+; GFX6-NEXT:    v_xor_b32_e32 v0, s16, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s17, v1
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v3
-; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v2
-; GFX6-NEXT:    v_mul_lo_u32 v6, s13, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s2, v0
-; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v3
+; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v2
+; GFX6-NEXT:    v_mul_lo_u32 v6, s11, v2
+; GFX6-NEXT:    v_mov_b32_e32 v9, s17
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s16, v0
+; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, s12, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v2
 ; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s11, v4
-; GFX6-NEXT:    v_mov_b32_e32 v7, s13
-; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s10, v5
+; GFX6-NEXT:    v_sub_i32_e32 v6, vcc, s9, v4
+; GFX6-NEXT:    v_mov_b32_e32 v7, s11
+; GFX6-NEXT:    v_sub_i32_e32 v5, vcc, s8, v5
 ; GFX6-NEXT:    v_subb_u32_e64 v6, s[0:1], v6, v7, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s12, v5
+; GFX6-NEXT:    v_subrev_i32_e64 v7, s[0:1], s10, v5
 ; GFX6-NEXT:    v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v6
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[0:1]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v6
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v8, v7, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v7, s[0:1], 2, v2
 ; GFX6-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e64 v9, s[0:1], 1, v2
 ; GFX6-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v10, v8, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v8, s11
+; GFX6-NEXT:    v_mov_b32_e32 v8, s9
 ; GFX6-NEXT:    v_subb_u32_e32 v4, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v4
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v5
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v4
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
 ; GFX6-NEXT:    v_cndmask_b32_e32 v4, v8, v5, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v9, v7, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT:    s_xor_b64 s[0:1], s[14:15], s[8:9]
+; GFX6-NEXT:    s_xor_b64 s[0:1], s[2:3], s[18:19]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
 ; GFX6-NEXT:    v_xor_b32_e32 v2, s0, v2
 ; GFX6-NEXT:    v_xor_b32_e32 v3, s1, v3
 ; GFX6-NEXT:    v_mov_b32_e32 v4, s1
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s0, v2
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
 ; GFX9-NEXT:    s_mov_b32 s3, 0
 ; GFX9-NEXT:    s_movk_i32 s2, 0x1000
 ; GFX9-NEXT:    s_mov_b32 s18, 0x4f800000
 ; GFX9-NEXT:    s_mov_b32 s19, 0x5f7ffffc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_lshl_b64 s[8:9], s[2:3], s6
+; GFX9-NEXT:    s_lshl_b64 s[10:11], s[2:3], s6
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s12, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s12
 ; GFX9-NEXT:    s_mov_b32 s13, s12
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s12
-; GFX9-NEXT:    s_xor_b64 s[10:11], s[2:3], s[12:13]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s10
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s11
+; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[12:13]
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GFX9-NEXT:    s_mov_b32 s20, 0x2f800000
 ; GFX9-NEXT:    s_mov_b32 s21, 0xcf800000
-; GFX9-NEXT:    s_sub_u32 s14, 0, s10
+; GFX9-NEXT:    s_sub_u32 s14, 0, s8
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s18, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX9-NEXT:    s_subb_u32 s4, 0, s11
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    s_subb_u32 s4, 0, s9
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, s19, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, s20, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s21, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s14, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s14, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s14, v0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s14, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, s14, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s14, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s14, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x34
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, s14, v0
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v8, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s14, s5, 31
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_add_u32 s2, s4, s14
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_addc_u32 s3, s5, s14
 ; GFX9-NEXT:    s_mov_b32 s15, s14
 ; GFX9-NEXT:    s_xor_b64 s[16:17], s[2:3], s[14:15]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s16, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s16, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s16, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s17, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s17, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s17, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s17, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s17, v0
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX9-NEXT:    s_xor_b64 s[12:13], s[14:15], s[12:13]
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v1
-; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GFX9-NEXT:    v_mul_lo_u32 v4, s11, v0
-; GFX9-NEXT:    v_mov_b32_e32 v7, s11
-; GFX9-NEXT:    s_ashr_i32 s14, s9, 31
+; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v1
+; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
+; GFX9-NEXT:    v_mov_b32_e32 v6, s9
+; GFX9-NEXT:    s_ashr_i32 s14, s11, 31
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v0
+; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v4
 ; GFX9-NEXT:    v_sub_u32_e32 v4, s17, v2
 ; GFX9-NEXT:    s_mov_b32 s15, s14
 ; GFX9-NEXT:    v_sub_co_u32_e64 v3, s[0:1], s16, v3
-; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v7, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v7, vcc, s10, v3
+; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v6, s[0:1]
+; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s8, v3
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v7
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
-; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v7, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 2, v0
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v6
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v4
+; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v6, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, 2, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, 1, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v4, v10, v8, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v8, s17
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v8, v2, s[0:1]
-; GFX9-NEXT:    s_add_u32 s0, s8, s14
-; GFX9-NEXT:    s_addc_u32 s1, s9, s14
-; GFX9-NEXT:    s_xor_b64 s[8:9], s[0:1], s[14:15]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v11, s9
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
+; GFX9-NEXT:    s_add_u32 s0, s10, s14
+; GFX9-NEXT:    s_addc_u32 s1, s11, s14
+; GFX9-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s10
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s11
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v2
+; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, vcc
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v3
+; GFX9-NEXT:    v_mac_f32_e32 v8, s18, v10
+; GFX9-NEXT:    v_rcp_f32_e32 v3, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
-; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
-; GFX9-NEXT:    v_mac_f32_e32 v10, s18, v11
-; GFX9-NEXT:    v_cndmask_b32_e32 v2, v8, v3, vcc
-; GFX9-NEXT:    v_rcp_f32_e32 v3, v10
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX9-NEXT:    v_cndmask_b32_e64 v2, v9, v7, s[2:3]
-; GFX9-NEXT:    v_mul_f32_e32 v3, s19, v3
-; GFX9-NEXT:    v_mul_f32_e32 v4, s20, v3
-; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX9-NEXT:    v_mac_f32_e32 v3, s21, v4
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v2
+; GFX9-NEXT:    s_sub_u32 s8, 0, s10
+; GFX9-NEXT:    v_mul_f32_e32 v2, s19, v3
+; GFX9-NEXT:    v_mul_f32_e32 v3, s20, v2
+; GFX9-NEXT:    v_trunc_f32_e32 v3, v3
+; GFX9-NEXT:    v_mac_f32_e32 v2, s21, v3
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX9-NEXT:    s_sub_u32 s2, 0, s8
-; GFX9-NEXT:    s_subb_u32 s3, 0, s9
-; GFX9-NEXT:    v_mul_hi_u32 v7, s2, v3
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v4
-; GFX9-NEXT:    v_mul_lo_u32 v9, s3, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v3
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v2
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v7
-; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v2
-; GFX9-NEXT:    v_mul_hi_u32 v2, v4, v2
-; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
-; GFX9-NEXT:    s_mov_b32 s11, s10
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
-; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v9, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v10, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v11, s2, v2
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
-; GFX9-NEXT:    v_add_u32_e32 v8, v9, v8
-; GFX9-NEXT:    v_add_u32_e32 v8, v8, v10
-; GFX9-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v11
-; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v11
-; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v10, v3
+; GFX9-NEXT:    s_subb_u32 s9, 0, s11
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v11, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, s8, v2
+; GFX9-NEXT:    v_mul_lo_u32 v12, s8, v3
+; GFX9-NEXT:    v_mul_lo_u32 v13, s9, v2
+; GFX9-NEXT:    v_mul_lo_u32 v11, s8, v2
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
+; GFX9-NEXT:    v_add_u32_e32 v10, v10, v12
+; GFX9-NEXT:    v_add_u32_e32 v10, v10, v13
+; GFX9-NEXT:    v_mul_lo_u32 v13, v2, v10
+; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v11
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v10
+; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v9, v6, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v11
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v14, v13
+; GFX9-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v12, v3, v10
+; GFX9-NEXT:    v_mul_lo_u32 v10, v3, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v8, v11, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v12, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v10
+; GFX9-NEXT:    v_add_co_u32_e64 v2, s[2:3], v2, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
-; GFX9-NEXT:    s_add_u32 s0, s6, s10
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
-; GFX9-NEXT:    s_addc_u32 s1, s7, s10
-; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v3, v8, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v9, s8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v10, s8, v2
+; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v4, s[0:1]
+; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v2
+; GFX9-NEXT:    v_add_u32_e32 v3, v3, v8
+; GFX9-NEXT:    v_add_u32_e32 v9, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v10, s8, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, v9, v4
+; GFX9-NEXT:    v_mul_lo_u32 v11, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v4
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v10
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v10
+; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v10
+; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v6, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v11, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v12, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v9, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v5, v9, vcc
+; GFX9-NEXT:    s_ashr_i32 s8, s7, 31
+; GFX9-NEXT:    s_add_u32 s0, s6, s8
+; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v3, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4
+; GFX9-NEXT:    s_mov_b32 s9, s8
+; GFX9-NEXT:    s_addc_u32 s1, s7, s8
+; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, s6, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, s6, v3
+; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GFX9-NEXT:    v_mul_hi_u32 v8, s6, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v10, s7, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s7, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v9, s7, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v2, s7, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s12, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s13, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v4, s8, v3
-; GFX9-NEXT:    v_mul_hi_u32 v5, s8, v2
-; GFX9-NEXT:    v_mul_lo_u32 v7, s9, v2
-; GFX9-NEXT:    v_mov_b32_e32 v8, s13
+; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v3
+; GFX9-NEXT:    v_mul_hi_u32 v5, s10, v2
+; GFX9-NEXT:    v_mul_lo_u32 v6, s11, v2
+; GFX9-NEXT:    v_mov_b32_e32 v9, s13
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s12, v0
 ; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
-; GFX9-NEXT:    v_mul_lo_u32 v5, s8, v2
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
-; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
-; GFX9-NEXT:    v_sub_u32_e32 v7, s7, v4
-; GFX9-NEXT:    v_mov_b32_e32 v8, s9
+; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v6
+; GFX9-NEXT:    v_sub_u32_e32 v6, s7, v4
+; GFX9-NEXT:    v_mov_b32_e32 v8, s11
 ; GFX9-NEXT:    v_sub_co_u32_e64 v5, s[0:1], s6, v5
-; GFX9-NEXT:    v_subb_co_u32_e64 v7, vcc, v7, v8, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v8, vcc, s8, v5
-; GFX9-NEXT:    v_subbrev_co_u32_e32 v7, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v7
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v9, vcc
+; GFX9-NEXT:    v_subb_co_u32_e64 v6, vcc, v6, v8, s[0:1]
+; GFX9-NEXT:    v_subrev_co_u32_e32 v8, vcc, s10, v5
+; GFX9-NEXT:    v_subbrev_co_u32_e32 v6, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v8
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v7
-; GFX9-NEXT:    v_cndmask_b32_e32 v7, v9, v8, vcc
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v6
+; GFX9-NEXT:    v_cndmask_b32_e32 v6, v9, v8, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, 2, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v3, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, 1, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v3, vcc
-; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v7
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[2:3]
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v6
+; GFX9-NEXT:    v_cndmask_b32_e64 v6, v11, v9, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v9, s7
 ; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v9, v4, s[0:1]
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v4
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s11, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v5
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s10, v5
 ; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v4
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v4
 ; GFX9-NEXT:    v_cndmask_b32_e32 v4, v9, v5, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v4, v10, v8, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX9-NEXT:    s_xor_b64 s[0:1], s[10:11], s[14:15]
-; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
+; GFX9-NEXT:    s_xor_b64 s[0:1], s[8:9], s[14:15]
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v2, s0, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v3, s1, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v4, s1
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s0, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_store_dwordx4 v6, v[0:3], s[4:5]
+; GFX9-NEXT:    global_store_dwordx4 v7, v[0:3], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
   %r = sdiv <2 x i64> %x, %shl.y
   store <2 x i64> %r, <2 x i64> addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @srem_i64_oddk_denom(i64 addrspace(1)* %out, i64 %x) {
 ; CHECK-LABEL: @srem_i64_oddk_denom(
 ; CHECK-NEXT:    [[R:%.*]] = srem i64 [[X:%.*]], 1235195
 ; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: srem_i64_oddk_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX6-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s2, 0xffed2705
-; GFX6-NEXT:    v_mov_b32_e32 v8, 0
-; GFX6-NEXT:    v_mov_b32_e32 v7, 0
+; GFX6-NEXT:    s_mov_b32 s8, 0xffed2705
+; GFX6-NEXT:    v_mov_b32_e32 v6, 0
+; GFX6-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s2
-; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_mov_b32 s4, s8
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, v1, s8
+; GFX6-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, v0, v2
+; GFX6-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v7, v9, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s2
-; GFX6-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, s2
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, s8
+; GFX6-NEXT:    v_mul_hi_u32 v7, s8, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v5
-; GFX6-NEXT:    v_mul_lo_u32 v5, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, v8, v12, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v11, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v6, v7, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    s_ashr_i32 s2, s11, 31
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s2
+; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[2:3]
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s2, s7, 31
+; GFX6-NEXT:    s_add_u32 s0, s6, s2
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_addc_u32 s1, s7, s2
 ; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s1, s11, s2
 ; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX6-NEXT:    v_mul_hi_u32 v5, s1, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX6-NEXT:    s_mov_b32 s3, 0x12d8fb
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s3, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s3
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GFX6-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v0
 ; GFX6-NEXT:    v_subbrev_u32_e32 v3, vcc, 0, v1, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s3, v2
 ; GFX6-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v3, vcc

 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i64_oddk_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GFX9-NEXT:    v_madak_f32 v0, 0, v0, 0x4996c7d8
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    s_mov_b32 s8, 0xffed2705
-; GFX9-NEXT:    v_mov_b32_e32 v7, 0
+; GFX9-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, s8
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v0, s8
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v2, v2, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v6, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v7, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v9, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v2, s8
-; GFX9-NEXT:    v_mul_hi_u32 v6, s8, v0
-; GFX9-NEXT:    v_mul_lo_u32 v8, v0, s8
+; GFX9-NEXT:    v_mul_hi_u32 v7, s8, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, s8
 ; GFX9-NEXT:    v_sub_u32_e32 v4, v4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v8
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v9, v2, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v2, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v6, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v7, v12, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v2, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v6, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v9, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v5, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s2, s7, 31
 ; GFX9-NEXT:    s_add_u32 s0, s6, s2
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_mov_b32 s3, s2
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s2
 ; GFX9-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s0, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s0, v1
-; GFX9-NEXT:    v_mul_hi_u32 v6, s1, v1
+; GFX9-NEXT:    v_mul_hi_u32 v7, s1, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v6, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s1, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s1, v0
 ; GFX9-NEXT:    s_mov_b32 s3, 0x12d8fb
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v5, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v5, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v2, vcc
 ; GFX9-NEXT:    v_mul_hi_u32 v2, s3, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, s3
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, s3
 ; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s0, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s3, v0

 ; CHECK-NEXT:    store i64 [[R]], i64 addrspace(1)* [[OUT:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
 ; GFX6-LABEL: srem_i64_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dword s4, s[0:1], 0xd
 ; GFX6-NEXT:    s_mov_b32 s3, 0
 ; GFX6-NEXT:    s_movk_i32 s2, 0x1000
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s4
 ; GFX6-NEXT:    s_mov_b32 s5, s4
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s4
-; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[4:5]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GFX6-NEXT:    s_sub_u32 s2, 0, s12
-; GFX6-NEXT:    s_subb_u32 s3, 0, s13
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
+; GFX6-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
+; GFX6-NEXT:    s_sub_u32 s10, 0, s8
+; GFX6-NEXT:    s_subb_u32 s4, 0, s9
 ; GFX6-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_mov_b32 s15, s14
-; GFX6-NEXT:    s_mov_b32 s6, -1
-; GFX6-NEXT:    s_mov_b32 s4, s8
+; GFX6-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
-; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
-; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
+; GFX6-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GFX6-NEXT:    v_trunc_f32_e32 v2, v2
+; GFX6-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    s_mov_b32 s5, s9
-; GFX6-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s3, v0
-; GFX6-NEXT:    v_mul_lo_u32 v4, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s10, v2
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v6, s10, v0
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GFX6-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GFX6-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v6, s10, v4
+; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GFX6-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX6-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX6-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    s_ashr_i32 s10, s7, 31
+; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
-; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
-; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    s_add_u32 s0, s6, s10
+; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; GFX6-NEXT:    s_addc_u32 s1, s7, s10
+; GFX6-NEXT:    s_mov_b32 s11, s10
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[0:1], s[10:11]
+; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GFX6-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v4, vcc
-; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mov_b32_e32 v6, 0
-; GFX6-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s2, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s2, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v0
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
-; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
+; GFX6-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s10, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s11, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s11, v1
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, s12, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, s12, v0
-; GFX6-NEXT:    v_mul_lo_u32 v3, s13, v0
-; GFX6-NEXT:    v_mul_lo_u32 v0, s12, v0
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v1, s8, v1
+; GFX6-NEXT:    v_mul_hi_u32 v2, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s9, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s13
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s9
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
+; GFX6-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
 ; GFX6-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
-; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
+; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
 ; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v5, s11
+; GFX6-NEXT:    v_mov_b32_e32 v5, s13
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GFX6-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
 ; GFX6-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v0, s14, v0
-; GFX6-NEXT:    v_xor_b32_e32 v1, s14, v1
-; GFX6-NEXT:    v_mov_b32_e32 v2, s14
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s14, v0
+; GFX6-NEXT:    v_xor_b32_e32 v0, s10, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s10, v1
+; GFX6-NEXT:    v_mov_b32_e32 v2, s10
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s10, v0
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x34
 ; GFX9-NEXT:    s_mov_b32 s3, 0
 ; GFX9-NEXT:    s_movk_i32 s2, 0x1000
 ; GFX9-NEXT:    v_mov_b32_e32 v2, 0
+; GFX9-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s4
 ; GFX9-NEXT:    s_mov_b32 s5, s4
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s4
 ; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[4:5]
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GFX9-NEXT:    s_sub_u32 s10, 0, s8
 ; GFX9-NEXT:    s_subb_u32 s4, 0, s9
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v1
-; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v0
-; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
-; GFX9-NEXT:    v_add_u32_e32 v3, v3, v6
-; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v5
-; GFX9-NEXT:    v_mul_lo_u32 v5, v1, v5
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
-; GFX9-NEXT:    v_mul_hi_u32 v9, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GFX9-NEXT:    v_mul_hi_u32 v5, s10, v0
+; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v1
+; GFX9-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v0
+; GFX9-NEXT:    v_add_u32_e32 v4, v5, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v5, v7
+; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v6, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
-; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v1, v4, s[2:3]
-; GFX9-NEXT:    v_mul_lo_u32 v5, s10, v3
+; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v3, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v1, v5, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v6, s10, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s10, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s4, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s10, v0
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
-; GFX9-NEXT:    v_add_u32_e32 v5, v7, v5
-; GFX9-NEXT:    v_add_u32_e32 v5, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX9-NEXT:    v_mul_hi_u32 v8, v3, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v5
+; GFX9-NEXT:    v_add_u32_e32 v1, v1, v5
+; GFX9-NEXT:    v_add_u32_e32 v6, v7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GFX9-NEXT:    v_add_u32_e32 v6, v6, v8
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v8, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s10, s7, 31
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v6, v5, vcc
-; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v3, v7, vcc
 ; GFX9-NEXT:    s_add_u32 s0, s6, s10
-; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v5, s[2:3]
-; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3
+; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v4
 ; GFX9-NEXT:    s_mov_b32 s11, s10
 ; GFX9-NEXT:    s_addc_u32 s1, s7, s10
 ; GFX9-NEXT:    s_xor_b64 s[6:7], s[0:1], s[10:11]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, s6, v1
-; GFX9-NEXT:    v_mul_hi_u32 v4, s6, v0
-; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GFX9-NEXT:    v_mul_lo_u32 v4, s6, v1
+; GFX9-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s6, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v6, s7, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v5, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v4, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v7, v2, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v5, v0, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v2, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v6, v3, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v3, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s8, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v3, v1
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v4
 ; GFX9-NEXT:    v_sub_co_u32_e64 v0, s[0:1], s6, v0
 ; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v1

 ; GFX6-LABEL: srem_v2i64_pow2_shl_denom:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x11
 ; GFX6-NEXT:    s_mov_b32 s3, 0
 ; GFX6-NEXT:    s_movk_i32 s2, 0x1000
 ; GFX6-NEXT:    s_mov_b32 s18, 0x4f800000
 ; GFX6-NEXT:    s_mov_b32 s19, 0x5f7ffffc
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_lshl_b64 s[14:15], s[2:3], s6
+; GFX6-NEXT:    s_lshl_b64 s[16:17], s[2:3], s6
 ; GFX6-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX6-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX6-NEXT:    s_add_u32 s2, s2, s4
 ; GFX6-NEXT:    s_mov_b32 s5, s4
 ; GFX6-NEXT:    s_addc_u32 s3, s3, s4
-; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[4:5]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s16
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s17
+; GFX6-NEXT:    s_xor_b64 s[10:11], s[2:3], s[4:5]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s10
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s11
 ; GFX6-NEXT:    s_mov_b32 s20, 0x2f800000
 ; GFX6-NEXT:    s_mov_b32 s21, 0xcf800000
-; GFX6-NEXT:    s_sub_u32 s6, 0, s16
+; GFX6-NEXT:    s_sub_u32 s4, 0, s10
 ; GFX6-NEXT:    v_mac_f32_e32 v0, s18, v1
 ; GFX6-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX6-NEXT:    s_subb_u32 s7, 0, s17
-; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GFX6-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
+; GFX6-NEXT:    s_subb_u32 s5, 0, s11
+; GFX6-NEXT:    s_load_dwordx4 s[12:15], s[0:1], 0xd
+; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    v_mul_f32_e32 v0, s19, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, s20, v0
 ; GFX6-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mac_f32_e32 v0, s21, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX6-NEXT:    s_ashr_i32 s12, s9, 31
-; GFX6-NEXT:    s_add_u32 s0, s8, s12
-; GFX6-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s6, v1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s7, v0
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v0
-; GFX6-NEXT:    s_mov_b32 s13, s12
+; GFX6-NEXT:    s_ashr_i32 s8, s13, 31
+; GFX6-NEXT:    s_mov_b32 s9, s8
+; GFX6-NEXT:    v_mul_hi_u32 v3, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s4, v1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s5, v0
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v0
+; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GFX6-NEXT:    v_mul_lo_u32 v3, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v4, v0, v5
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v4
+; GFX6-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GFX6-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v6, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v6, v1, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v1, v2
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, 0, v6, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v6, v1, v5
-; GFX6-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GFX6-NEXT:    s_addc_u32 s1, s9, s12
-; GFX6-NEXT:    s_xor_b64 s[8:9], s[0:1], s[12:13]
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v4, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v7, vcc
 ; GFX6-NEXT:    v_mov_b32_e32 v4, 0
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v7, v4, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX6-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v5, vcc
 ; GFX6-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[2:3]
-; GFX6-NEXT:    v_mul_lo_u32 v5, s6, v2
-; GFX6-NEXT:    v_mul_hi_u32 v7, s6, v0
-; GFX6-NEXT:    v_mul_lo_u32 v8, s7, v0
-; GFX6-NEXT:    s_mov_b32 s7, 0xf000
+; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v2
+; GFX6-NEXT:    v_mul_hi_u32 v7, s4, v0
+; GFX6-NEXT:    v_mul_lo_u32 v8, s5, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_mul_lo_u32 v7, s6, v0
+; GFX6-NEXT:    v_mul_lo_u32 v7, s4, v0
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GFX6-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v12, v0, v5
-; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GFX6-NEXT:    v_mul_hi_u32 v9, v2, v7
+; GFX6-NEXT:    v_mul_lo_u32 v9, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v11, v0, v5
+; GFX6-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GFX6-NEXT:    v_mul_hi_u32 v12, v2, v7
 ; GFX6-NEXT:    v_mul_lo_u32 v7, v2, v7
 ; GFX6-NEXT:    v_mul_hi_u32 v8, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GFX6-NEXT:    v_addc_u32_e32 v11, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GFX6-NEXT:    v_addc_u32_e32 v10, vcc, 0, v11, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, v5
-; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v8, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v7
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v10, v12, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v8, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GFX6-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GFX6-NEXT:    s_add_u32 s2, s12, s8
+; GFX6-NEXT:    s_addc_u32 s3, s13, s8
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[2:3], s[8:9]
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v3, s8, v0
-; GFX6-NEXT:    v_mul_hi_u32 v5, s8, v1
-; GFX6-NEXT:    v_mul_hi_u32 v7, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v1, s9, v1
+; GFX6-NEXT:    v_mul_lo_u32 v2, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v3, s12, v0
+; GFX6-NEXT:    v_mul_hi_u32 v5, s12, v1
+; GFX6-NEXT:    v_mul_hi_u32 v7, s13, v1
+; GFX6-NEXT:    v_mul_lo_u32 v1, s13, v1
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s9, v0
-; GFX6-NEXT:    s_mov_b32 s6, -1
+; GFX6-NEXT:    v_mul_lo_u32 v5, s13, v0
+; GFX6-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v1, s16, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, s16, v0
-; GFX6-NEXT:    v_mul_lo_u32 v3, s17, v0
-; GFX6-NEXT:    v_mul_lo_u32 v0, s16, v0
+; GFX6-NEXT:    v_mul_lo_u32 v1, s10, v1
+; GFX6-NEXT:    v_mul_hi_u32 v2, s10, v0
+; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v0
+; GFX6-NEXT:    v_mul_lo_u32 v0, s10, v0
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s9, v1
-; GFX6-NEXT:    v_mov_b32_e32 v3, s17
-; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
+; GFX6-NEXT:    v_mov_b32_e32 v3, s11
+; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v0
+; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v0
 ; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v2, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v7
 ; GFX6-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
+; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s10, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s11, v7
+; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v5
-; GFX6-NEXT:    v_subrev_i32_e64 v3, s[0:1], s16, v5
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s10, v5
 ; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v7
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s11, v7
+; GFX6-NEXT:    s_ashr_i32 s0, s17, 31
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
-; GFX6-NEXT:    s_ashr_i32 s2, s15, 31
-; GFX6-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GFX6-NEXT:    s_add_u32 s2, s16, s0
+; GFX6-NEXT:    s_mov_b32 s1, s0
+; GFX6-NEXT:    s_addc_u32 s3, s17, s0
+; GFX6-NEXT:    s_xor_b64 s[16:17], s[2:3], s[0:1]
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s16
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v10, s17
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
-; GFX6-NEXT:    s_add_u32 s8, s14, s2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v7, v2, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v7, s9
-; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s9, s15, s2
-; GFX6-NEXT:    s_xor_b64 s[8:9], s[8:9], s[2:3]
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v8, s8
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v9, s9
+; GFX6-NEXT:    v_mov_b32_e32 v7, s13
+; GFX6-NEXT:    v_mac_f32_e32 v9, s18, v10
 ; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v7, v1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v1
-; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX6-NEXT:    v_mac_f32_e32 v8, s18, v9
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v0
-; GFX6-NEXT:    v_rcp_f32_e32 v8, v8
-; GFX6-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc
-; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT:    v_rcp_f32_e32 v7, v9
+; GFX6-NEXT:    s_sub_u32 s9, 0, s16
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v1
+; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
+; GFX6-NEXT:    v_mul_f32_e32 v7, s19, v7
+; GFX6-NEXT:    v_mul_f32_e32 v10, s20, v7
+; GFX6-NEXT:    v_trunc_f32_e32 v10, v10
+; GFX6-NEXT:    v_mac_f32_e32 v7, s21, v10
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v7, v7
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v0
+; GFX6-NEXT:    s_subb_u32 s10, 0, s17
+; GFX6-NEXT:    v_mul_hi_u32 v11, s9, v7
+; GFX6-NEXT:    v_mul_lo_u32 v12, s9, v10
+; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v1
+; GFX6-NEXT:    v_mul_lo_u32 v13, s10, v7
+; GFX6-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v11, v12
+; GFX6-NEXT:    v_mul_lo_u32 v11, s9, v7
+; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v9, v13
+; GFX6-NEXT:    v_mul_lo_u32 v13, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v12, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v14, v7, v11
+; GFX6-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v8
+; GFX6-NEXT:    v_mul_lo_u32 v8, v10, v11
+; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[2:3]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v2, v5, v3, s[0:1]
-; GFX6-NEXT:    v_mul_f32_e32 v3, s19, v8
-; GFX6-NEXT:    v_mul_f32_e32 v5, s20, v3
-; GFX6-NEXT:    v_trunc_f32_e32 v5, v5
-; GFX6-NEXT:    v_mac_f32_e32 v3, s21, v5
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GFX6-NEXT:    s_sub_u32 s2, 0, s8
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v2, s2, v3
-; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v5
-; GFX6-NEXT:    s_subb_u32 s3, 0, s9
-; GFX6-NEXT:    v_mul_lo_u32 v8, s3, v3
-; GFX6-NEXT:    s_ashr_i32 s14, s11, 31
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v7
-; GFX6-NEXT:    v_mul_lo_u32 v7, s2, v3
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
-; GFX6-NEXT:    v_mul_lo_u32 v8, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GFX6-NEXT:    v_mul_hi_u32 v11, v5, v2
-; GFX6-NEXT:    v_mul_lo_u32 v2, v5, v2
-; GFX6-NEXT:    s_mov_b32 s15, s14
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v14, v13
+; GFX6-NEXT:    v_mul_hi_u32 v11, v10, v11
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, 0, v12, vcc
+; GFX6-NEXT:    v_mul_hi_u32 v12, v10, v9
+; GFX6-NEXT:    v_mul_lo_u32 v9, v10, v9
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v8, v3
+; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v11, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v12, v4, vcc
+; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v9
+; GFX6-NEXT:    v_add_i32_e64 v3, s[0:1], v7, v3
+; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v6, v5, vcc
+; GFX6-NEXT:    v_addc_u32_e64 v7, vcc, v10, v5, s[0:1]
+; GFX6-NEXT:    v_mul_lo_u32 v8, s9, v7
+; GFX6-NEXT:    v_mul_hi_u32 v9, s9, v3
+; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[2:3]
+; GFX6-NEXT:    v_mul_lo_u32 v2, s10, v3
+; GFX6-NEXT:    s_ashr_i32 s10, s15, 31
 ; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, 0, v10, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v10, v5, v7
-; GFX6-NEXT:    v_mul_hi_u32 v7, v5, v7
-; GFX6-NEXT:    v_xor_b32_e32 v0, s12, v0
-; GFX6-NEXT:    v_xor_b32_e32 v1, s12, v1
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v9, v7, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v11, v4, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v9, s9, v3
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v8
+; GFX6-NEXT:    v_mul_lo_u32 v11, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v13, v3, v2
+; GFX6-NEXT:    v_mul_hi_u32 v12, v3, v9
+; GFX6-NEXT:    v_mul_hi_u32 v14, v7, v9
+; GFX6-NEXT:    v_mul_lo_u32 v9, v7, v9
+; GFX6-NEXT:    v_mul_hi_u32 v8, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
+; GFX6-NEXT:    v_addc_u32_e32 v12, vcc, 0, v13, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v2, v7, v2
+; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v11, v9
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v12, v14, vcc
+; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v8, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v7, v2
-; GFX6-NEXT:    v_add_i32_e64 v2, s[0:1], v3, v2
 ; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_addc_u32_e64 v3, vcc, v5, v7, s[0:1]
-; GFX6-NEXT:    v_mul_lo_u32 v8, s2, v3
-; GFX6-NEXT:    v_mul_hi_u32 v9, s2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v10, s3, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GFX6-NEXT:    v_mul_lo_u32 v9, s2, v2
-; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GFX6-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX6-NEXT:    v_mul_hi_u32 v13, v2, v9
-; GFX6-NEXT:    v_mul_hi_u32 v11, v3, v9
-; GFX6-NEXT:    v_mul_lo_u32 v9, v3, v9
-; GFX6-NEXT:    v_mul_hi_u32 v10, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GFX6-NEXT:    v_addc_u32_e32 v13, vcc, 0, v14, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, v3, v8
-; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
-; GFX6-NEXT:    v_addc_u32_e32 v9, vcc, v13, v11, vcc
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v10, v4, vcc
-; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GFX6-NEXT:    v_addc_u32_e32 v8, vcc, v6, v8, vcc
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v8, s[0:1]
-; GFX6-NEXT:    s_add_u32 s0, s10, s14
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
-; GFX6-NEXT:    s_addc_u32 s1, s11, s14
-; GFX6-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; GFX6-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[0:1]
+; GFX6-NEXT:    s_add_u32 s0, s14, s10
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
+; GFX6-NEXT:    s_mov_b32 s11, s10
+; GFX6-NEXT:    s_addc_u32 s1, s15, s10
+; GFX6-NEXT:    s_xor_b64 s[12:13], s[0:1], s[10:11]
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v5, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v7, s10, v2
-; GFX6-NEXT:    v_mul_hi_u32 v9, s10, v3
-; GFX6-NEXT:    v_mul_hi_u32 v10, s11, v3
-; GFX6-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GFX6-NEXT:    v_mul_lo_u32 v5, s12, v3
+; GFX6-NEXT:    v_mul_hi_u32 v7, s12, v2
+; GFX6-NEXT:    v_mul_hi_u32 v8, s12, v3
+; GFX6-NEXT:    v_mul_hi_u32 v10, s13, v3
+; GFX6-NEXT:    v_mul_lo_u32 v3, s13, v3
 ; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v9, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v9, s11, v2
-; GFX6-NEXT:    v_mul_hi_u32 v2, s11, v2
-; GFX6-NEXT:    v_mov_b32_e32 v8, s12
-; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
+; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, 0, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v8, s13, v2
+; GFX6-NEXT:    v_mul_hi_u32 v2, s13, v2
+; GFX6-NEXT:    v_xor_b32_e32 v0, s8, v0
+; GFX6-NEXT:    v_xor_b32_e32 v1, s8, v1
+; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
 ; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GFX6-NEXT:    v_addc_u32_e32 v4, vcc, v10, v4, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3
 ; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v6, v4, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s8, v3
-; GFX6-NEXT:    v_mul_hi_u32 v4, s8, v2
-; GFX6-NEXT:    v_mul_lo_u32 v5, s9, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s12, v0
-; GFX6-NEXT:    v_mul_lo_u32 v2, s8, v2
-; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc
+; GFX6-NEXT:    v_mul_lo_u32 v3, s16, v3
+; GFX6-NEXT:    v_mul_hi_u32 v4, s16, v2
+; GFX6-NEXT:    v_mul_lo_u32 v5, s17, v2
+; GFX6-NEXT:    v_mov_b32_e32 v9, s8
+; GFX6-NEXT:    v_subrev_i32_e32 v0, vcc, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v2, s16, v2
+; GFX6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v9, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s11, v3
-; GFX6-NEXT:    v_mov_b32_e32 v5, s9
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s10, v2
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, s13, v3
+; GFX6-NEXT:    v_mov_b32_e32 v5, s17
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s12, v2
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s8, v2
+; GFX6-NEXT:    v_subrev_i32_e64 v6, s[0:1], s16, v2
 ; GFX6-NEXT:    v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v7
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s17, v7
 ; GFX6-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v6
-; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s8, v6
+; GFX6-NEXT:    v_cmp_le_u32_e64 s[2:3], s16, v6
+; GFX6-NEXT:    v_subrev_i32_e64 v5, s[0:1], s16, v6
 ; GFX6-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[2:3]
-; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v7
+; GFX6-NEXT:    v_cmp_eq_u32_e64 s[2:3], s17, v7
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[2:3]
 ; GFX6-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
 ; GFX6-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v7, v4, s[0:1]
-; GFX6-NEXT:    v_mov_b32_e32 v7, s11
+; GFX6-NEXT:    v_mov_b32_e32 v7, s13
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s17, v3
 ; GFX6-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s16, v2
 ; GFX6-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
+; GFX6-NEXT:    v_cmp_eq_u32_e32 vcc, s17, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
 ; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GFX6-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v2, s14, v2
-; GFX6-NEXT:    v_xor_b32_e32 v3, s14, v3
-; GFX6-NEXT:    v_mov_b32_e32 v4, s14
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s14, v2
+; GFX6-NEXT:    v_xor_b32_e32 v2, s10, v2
+; GFX6-NEXT:    v_xor_b32_e32 v3, s10, v3
+; GFX6-NEXT:    v_mov_b32_e32 v4, s10
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s10, v2
 ; GFX6-NEXT:    v_subb_u32_e32 v3, vcc, v3, v4, vcc
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: srem_v2i64_pow2_shl_denom:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x44
 ; GFX9-NEXT:    s_mov_b32 s3, 0
 ; GFX9-NEXT:    s_movk_i32 s2, 0x1000
 ; GFX9-NEXT:    s_mov_b32 s16, 0x4f800000
 ; GFX9-NEXT:    s_mov_b32 s17, 0x5f7ffffc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    s_lshl_b64 s[12:13], s[2:3], s6
+; GFX9-NEXT:    s_lshl_b64 s[14:15], s[2:3], s6
 ; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], s4
 ; GFX9-NEXT:    s_ashr_i32 s4, s3, 31
 ; GFX9-NEXT:    s_add_u32 s2, s2, s4
 ; GFX9-NEXT:    s_mov_b32 s5, s4
 ; GFX9-NEXT:    s_addc_u32 s3, s3, s4
-; GFX9-NEXT:    s_xor_b64 s[14:15], s[2:3], s[4:5]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s14
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s15
+; GFX9-NEXT:    s_xor_b64 s[12:13], s[2:3], s[4:5]
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s12
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s13
 ; GFX9-NEXT:    s_mov_b32 s18, 0x2f800000
 ; GFX9-NEXT:    s_mov_b32 s19, 0xcf800000
-; GFX9-NEXT:    s_sub_u32 s4, 0, s14
+; GFX9-NEXT:    s_sub_u32 s4, 0, s12
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s16, v1
 ; GFX9-NEXT:    v_rcp_f32_e32 v0, v0
-; GFX9-NEXT:    s_subb_u32 s5, 0, s15
-; GFX9-NEXT:    v_mov_b32_e32 v6, 0
+; GFX9-NEXT:    s_subb_u32 s5, 0, s13
+; GFX9-NEXT:    v_mov_b32_e32 v7, 0
 ; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x34
 ; GFX9-NEXT:    v_mul_f32_e32 v0, s17, v0
 ; GFX9-NEXT:    v_mul_f32_e32 v1, s18, v0
 ; GFX9-NEXT:    v_trunc_f32_e32 v1, v1
 ; GFX9-NEXT:    v_mac_f32_e32 v0, s19, v1
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_ashr_i32 s6, s9, 31
 ; GFX9-NEXT:    s_mov_b32 s7, s6
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s4, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s4, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s5, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v0
 ; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v3, v0, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v1, v2
-; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v7, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v4
+; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v3
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v5
+; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v6, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v2
+; GFX9-NEXT:    v_mul_lo_u32 v2, v1, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_mov_b32_e32 v5, 0
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, s[2:3], v0, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v2, vcc, v1, v3, s[2:3]
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s4, v2
-; GFX9-NEXT:    v_mul_hi_u32 v7, s4, v0
+; GFX9-NEXT:    v_mul_hi_u32 v6, s4, v0
 ; GFX9-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GFX9-NEXT:    v_mul_lo_u32 v9, s4, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
-; GFX9-NEXT:    v_add_u32_e32 v4, v7, v4
+; GFX9-NEXT:    v_add_u32_e32 v4, v6, v4
+; GFX9-NEXT:    v_mul_lo_u32 v6, s4, v0
 ; GFX9-NEXT:    v_add_u32_e32 v4, v4, v8
-; GFX9-NEXT:    v_mul_lo_u32 v10, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v9
-; GFX9-NEXT:    v_mul_hi_u32 v12, v0, v4
-; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v2, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v7, v2, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, 0, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_mul_lo_u32 v9, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v11, v0, v4
+; GFX9-NEXT:    v_mul_hi_u32 v10, v0, v6
+; GFX9-NEXT:    v_mul_hi_u32 v12, v2, v6
+; GFX9-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GFX9-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v7, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v8, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, 0, v11, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v2, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v8, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, vcc, v1, v4, s[2:3]
 ; GFX9-NEXT:    s_add_u32 s2, s8, s6
 ; GFX9-NEXT:    s_addc_u32 s3, s9, s6
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2
 ; GFX9-NEXT:    s_xor_b64 s[8:9], s[2:3], s[6:7]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v1
 ; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v1
-; GFX9-NEXT:    v_mul_hi_u32 v7, s9, v1
+; GFX9-NEXT:    v_mul_hi_u32 v6, s9, v1
 ; GFX9-NEXT:    v_mul_lo_u32 v1, s9, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v0
 ; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0
 ; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v4, v2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v0, vcc, v3, v0, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v5, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v1, s14, v1
-; GFX9-NEXT:    v_mul_hi_u32 v2, s14, v0
-; GFX9-NEXT:    v_mul_lo_u32 v3, s15, v0
-; GFX9-NEXT:    v_mul_lo_u32 v0, s14, v0
+; GFX9-NEXT:    v_mul_lo_u32 v1, s12, v1
+; GFX9-NEXT:    v_mul_hi_u32 v2, s12, v0
+; GFX9-NEXT:    v_mul_lo_u32 v3, s13, v0
+; GFX9-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1
 ; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3
 ; GFX9-NEXT:    v_sub_co_u32_e64 v0, s[0:1], s8, v0
 ; GFX9-NEXT:    v_sub_u32_e32 v2, s9, v1
-; GFX9-NEXT:    v_mov_b32_e32 v3, s15
+; GFX9-NEXT:    v_mov_b32_e32 v3, s13
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[2:3], s14, v0
-; GFX9-NEXT:    v_subbrev_co_u32_e64 v7, vcc, 0, v2, s[2:3]
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v7
+; GFX9-NEXT:    v_subrev_co_u32_e64 v4, s[2:3], s12, v0
+; GFX9-NEXT:    v_subbrev_co_u32_e64 v6, vcc, 0, v2, s[2:3]
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s13, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v4
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s12, v4
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v7
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v6
 ; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v2, vcc, v2, v3, s[2:3]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s14, v4
+; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s12, v4
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v8
-; GFX9-NEXT:    v_cndmask_b32_e64 v2, v7, v2, s[2:3]
-; GFX9-NEXT:    v_mov_b32_e32 v7, s9
-; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v7, v1, s[0:1]
-; GFX9-NEXT:    s_ashr_i32 s0, s13, 31
-; GFX9-NEXT:    s_add_u32 s8, s12, s0
+; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, v2, s[2:3]
+; GFX9-NEXT:    v_mov_b32_e32 v6, s9
+; GFX9-NEXT:    v_subb_co_u32_e64 v1, vcc, v6, v1, s[0:1]
+; GFX9-NEXT:    s_ashr_i32 s0, s15, 31
+; GFX9-NEXT:    s_add_u32 s8, s14, s0
 ; GFX9-NEXT:    s_mov_b32 s1, s0
-; GFX9-NEXT:    s_addc_u32 s9, s13, s0
+; GFX9-NEXT:    s_addc_u32 s9, s15, s0
 ; GFX9-NEXT:    s_xor_b64 s[8:9], s[8:9], s[0:1]
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v9, s8
-; GFX9-NEXT:    v_cvt_f32_u32_e32 v10, s9
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s15, v1
-; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s14, v0
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, s8
+; GFX9-NEXT:    v_cvt_f32_u32_e32 v8, s9
+; GFX9-NEXT:    s_sub_u32 s7, 0, s8
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
+; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
+; GFX9-NEXT:    v_mac_f32_e32 v6, s16, v8
+; GFX9-NEXT:    v_rcp_f32_e32 v6, v6
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
+; GFX9-NEXT:    s_subb_u32 s12, 0, s9
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s15, v1
-; GFX9-NEXT:    v_mac_f32_e32 v9, s16, v10
-; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc
-; GFX9-NEXT:    v_rcp_f32_e32 v8, v9
-; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v7
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT:    v_mul_f32_e32 v6, s17, v6
+; GFX9-NEXT:    v_mul_f32_e32 v10, s18, v6
+; GFX9-NEXT:    v_trunc_f32_e32 v10, v10
+; GFX9-NEXT:    v_mac_f32_e32 v6, s19, v10
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
+; GFX9-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
+; GFX9-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v11, s7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v12, s7, v10
+; GFX9-NEXT:    v_mul_lo_u32 v13, s12, v6
+; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v8
+; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
+; GFX9-NEXT:    v_add_u32_e32 v9, v11, v12
+; GFX9-NEXT:    v_mul_lo_u32 v11, s7, v6
+; GFX9-NEXT:    v_add_u32_e32 v9, v9, v13
+; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v11
+; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v11
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[2:3]
-; GFX9-NEXT:    v_mul_f32_e32 v3, s17, v8
-; GFX9-NEXT:    v_mul_f32_e32 v4, s18, v3
-; GFX9-NEXT:    v_trunc_f32_e32 v4, v4
-; GFX9-NEXT:    v_mac_f32_e32 v3, s19, v4
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GFX9-NEXT:    s_sub_u32 s2, 0, s8
-; GFX9-NEXT:    s_subb_u32 s3, 0, s9
-; GFX9-NEXT:    v_mul_hi_u32 v7, s2, v3
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v4
-; GFX9-NEXT:    v_mul_lo_u32 v9, s3, v3
-; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v3
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v8
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v9
-; GFX9-NEXT:    v_mul_lo_u32 v8, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v2
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v7
-; GFX9-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v2
-; GFX9-NEXT:    v_mul_hi_u32 v2, v4, v2
+; GFX9-NEXT:    v_mul_hi_u32 v11, v10, v11
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v14, v13
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v12, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v8, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v11, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v12, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v9
+; GFX9-NEXT:    v_add_co_u32_e64 v3, s[2:3], v6, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v5, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v10, v4, s[2:3]
+; GFX9-NEXT:    v_mul_lo_u32 v8, s7, v6
+; GFX9-NEXT:    v_mul_hi_u32 v9, s7, v3
+; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
+; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v3
 ; GFX9-NEXT:    s_ashr_i32 s12, s11, 31
-; GFX9-NEXT:    s_mov_b32 s13, s12
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v9, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v7
-; GFX9-NEXT:    v_add_co_u32_e64 v2, s[0:1], v3, v2
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v3, vcc, v4, v7, s[0:1]
-; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v3
-; GFX9-NEXT:    v_mul_hi_u32 v9, s2, v2
-; GFX9-NEXT:    v_mul_lo_u32 v10, s3, v2
-; GFX9-NEXT:    v_mul_lo_u32 v11, s2, v2
-; GFX9-NEXT:    v_add_u32_e32 v4, v4, v7
 ; GFX9-NEXT:    v_add_u32_e32 v8, v9, v8
-; GFX9-NEXT:    v_add_u32_e32 v8, v8, v10
-; GFX9-NEXT:    v_mul_lo_u32 v12, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v13, v2, v11
-; GFX9-NEXT:    v_mul_hi_u32 v14, v2, v8
-; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v11
-; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v9, v3, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, 0, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v3, v3, v8
+; GFX9-NEXT:    v_mul_lo_u32 v9, s7, v3
+; GFX9-NEXT:    v_add_u32_e32 v2, v8, v2
+; GFX9-NEXT:    v_mul_lo_u32 v11, v3, v2
+; GFX9-NEXT:    v_mul_hi_u32 v13, v3, v2
+; GFX9-NEXT:    v_mul_hi_u32 v12, v3, v9
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
+; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v10, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v6, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v10, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v5, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v8, s[0:1]
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, 0, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v2, v6, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v11, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v12, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v7, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v6, v2
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v5, v8, vcc
+; GFX9-NEXT:    v_add_u32_e32 v4, v10, v4
 ; GFX9-NEXT:    s_add_u32 s0, s10, s12
-; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
+; GFX9-NEXT:    v_addc_co_u32_e64 v4, vcc, v4, v6, s[2:3]
+; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v3, v2
+; GFX9-NEXT:    s_mov_b32 s13, s12
 ; GFX9-NEXT:    s_addc_u32 s1, s11, s12
 ; GFX9-NEXT:    s_xor_b64 s[10:11], s[0:1], s[12:13]
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GFX9-NEXT:    v_mul_hi_u32 v7, s10, v2
-; GFX9-NEXT:    v_mul_hi_u32 v9, s10, v3
+; GFX9-NEXT:    v_mul_hi_u32 v6, s10, v2
+; GFX9-NEXT:    v_mul_hi_u32 v8, s10, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v10, s11, v3
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s11, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v7, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v9, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v9, s11, v2
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v6, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, s11, v2
 ; GFX9-NEXT:    v_mul_hi_u32 v2, s11, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v0
 ; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v1
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v4
-; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v7, v2, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v6, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v8, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v6, v2, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v7, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v5, s9, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s8, v2
-; GFX9-NEXT:    v_mov_b32_e32 v8, s6
+; GFX9-NEXT:    v_mov_b32_e32 v9, s6
 ; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3
 ; GFX9-NEXT:    v_add_u32_e32 v3, v3, v5
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s6, v0
 ; GFX9-NEXT:    v_sub_co_u32_e64 v2, s[0:1], s10, v2
 ; GFX9-NEXT:    v_sub_u32_e32 v4, s11, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s9
-; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v8, vcc
+; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v9, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[0:1]
-; GFX9-NEXT:    v_subrev_co_u32_e64 v7, s[2:3], s8, v2
+; GFX9-NEXT:    v_subrev_co_u32_e64 v6, s[2:3], s8, v2
 ; GFX9-NEXT:    v_subbrev_co_u32_e64 v8, vcc, 0, v4, s[2:3]
 ; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v7
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v6
 ; GFX9-NEXT:    v_cndmask_b32_e64 v10, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v8
 ; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v10, vcc
 ; GFX9-NEXT:    v_subb_co_u32_e64 v4, vcc, v4, v5, s[2:3]
-; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s8, v7
+; GFX9-NEXT:    v_subrev_co_u32_e32 v5, vcc, s8, v6
 ; GFX9-NEXT:    v_subbrev_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e64 s[2:3], 0, v9
 ; GFX9-NEXT:    v_cndmask_b32_e64 v4, v8, v4, s[2:3]
 ; GFX9-NEXT:    v_mov_b32_e32 v8, s11
 ; GFX9-NEXT:    v_subb_co_u32_e64 v3, vcc, v8, v3, s[0:1]
 ; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s9, v3
 ; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2
 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
 ; GFX9-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v3
 ; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v9, vcc
 ; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v8
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
-; GFX9-NEXT:    v_cndmask_b32_e64 v4, v7, v5, s[2:3]
+; GFX9-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[2:3]
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v2, s12, v2
 ; GFX9-NEXT:    v_xor_b32_e32 v3, s12, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v4, s12
 ; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s12, v2
 ; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v4, vcc
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX9-NEXT:    global_store_dwordx4 v6, v[0:3], s[4:5]
+; GFX9-NEXT:    global_store_dwordx4 v7, v[0:3], s[4:5]
 ; GFX9-NEXT:    s_endpgm
   %shl.y = shl <2 x i64> <i64 4096, i64 4096>, %y
   %r = srem <2 x i64> %x, %shl.y
   store <2 x i64> %r, <2 x i64> addrspace(1)* %out
   ret void
 }

llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll

 ; GFX8-NEXT:    s_mov_b64 s[8:9], exec
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, s9, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1_vgpr2
 ; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX8-NEXT:    s_cbranch_execz BB4_2
 ; GFX8-NEXT:  ; %bb.1:
+; GFX8-NEXT:    s_bcnt1_i32_b64 s12, s[8:9]
+; GFX8-NEXT:    v_mov_b32_e32 v1, s12
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s12, s6
-; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[8:9]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s0, v1
-; GFX8-NEXT:    s_mov_b32 s13, s7
-; GFX8-NEXT:    s_mul_i32 s7, s1, s6
-; GFX8-NEXT:    s_mul_i32 s6, s0, s6
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
-; GFX8-NEXT:    s_mov_b32 s15, 0xf000
-; GFX8-NEXT:    s_mov_b32 s14, -1
+; GFX8-NEXT:    s_mov_b32 s8, s6
+; GFX8-NEXT:    s_mul_i32 s6, s1, s12
+; GFX8-NEXT:    s_mov_b32 s11, 0xf000
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v1
+; GFX8-NEXT:    s_mul_i32 s6, s0, s12
+; GFX8-NEXT:    s_mov_b32 s10, -1
+; GFX8-NEXT:    s_mov_b32 s9, s7
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    buffer_atomic_add_x2 v[1:2], off, s[12:15], 0 glc
+; GFX8-NEXT:    buffer_atomic_add_x2 v[1:2], off, s[8:11], 0 glc
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    buffer_wbinvl1_vol
 ; GFX8-NEXT:  BB4_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_lo_u32 v1, s1, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s0, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s0, v0
-; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_mov_b32_e32 v2, s1
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s2, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
+; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s1, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX8-NEXT:    s_mov_b32 s6, -1
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: add_i64_uniform:
 ; GFX9:       ; %bb.0: ; %entry

 ; GFX8-NEXT:    s_mov_b64 s[8:9], exec
 ; GFX8-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
 ; GFX8-NEXT:    v_mbcnt_hi_u32_b32 v0, s9, v0
 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1_vgpr2
 ; GFX8-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX8-NEXT:    s_cbranch_execz BB10_2
 ; GFX8-NEXT:  ; %bb.1:
+; GFX8-NEXT:    s_bcnt1_i32_b64 s12, s[8:9]
+; GFX8-NEXT:    v_mov_b32_e32 v1, s12
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s12, s6
-; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[8:9]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s0, v1
-; GFX8-NEXT:    s_mov_b32 s13, s7
-; GFX8-NEXT:    s_mul_i32 s7, s1, s6
-; GFX8-NEXT:    s_mul_i32 s6, s0, s6
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
-; GFX8-NEXT:    s_mov_b32 s15, 0xf000
-; GFX8-NEXT:    s_mov_b32 s14, -1
+; GFX8-NEXT:    s_mov_b32 s8, s6
+; GFX8-NEXT:    s_mul_i32 s6, s1, s12
+; GFX8-NEXT:    s_mov_b32 s11, 0xf000
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v1
+; GFX8-NEXT:    s_mul_i32 s6, s0, s12
+; GFX8-NEXT:    s_mov_b32 s10, -1
+; GFX8-NEXT:    s_mov_b32 s9, s7
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    buffer_atomic_sub_x2 v[1:2], off, s[12:15], 0 glc
+; GFX8-NEXT:    buffer_atomic_sub_x2 v[1:2], off, s[8:11], 0 glc
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    buffer_wbinvl1_vol
 ; GFX8-NEXT:  BB10_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[2:3]
-; GFX8-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_lo_u32 v1, s1, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s0, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s0, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s0, v0
-; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_mov_b32_e32 v2, s1
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
-; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s2, v0
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v2
+; GFX8-NEXT:    v_readfirstlane_b32 s1, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
+; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s1, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX8-NEXT:    s_mov_b32 s6, -1
 ; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sub_i64_uniform:
 ; GFX9:       ; %bb.0: ; %entry

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1_vgpr2
 ; GFX8-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX8-NEXT:    s_cbranch_execz BB5_2
 ; GFX8-NEXT:  ; %bb.1:
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_hi_u32 v1, s2, v1
+; GFX8-NEXT:    v_mul_hi_u32 v2, s2, v1
 ; GFX8-NEXT:    s_mul_i32 s7, s3, s6
 ; GFX8-NEXT:    s_mul_i32 s6, s2, s6
-; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v2
+; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX8-NEXT:    s_mov_b32 m0, -1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    ds_add_rtn_u64 v[1:2], v3, v[1:2]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:  BB5_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s4, s0
-; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s3, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s2, v0
+; GFX8-NEXT:    s_mov_b32 s4, s0
 ; GFX8-NEXT:    s_mov_b32 s5, s1
 ; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX8-NEXT:    s_mov_b32 s6, -1
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX8-NEXT:    s_endpgm
 ;

 ; GFX8-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX8-NEXT:    ; implicit-def: $vgpr1_vgpr2
 ; GFX8-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX8-NEXT:    s_cbranch_execz BB12_2
 ; GFX8-NEXT:  ; %bb.1:
 ; GFX8-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    v_mul_hi_u32 v1, s2, v1
+; GFX8-NEXT:    v_mul_hi_u32 v2, s2, v1
 ; GFX8-NEXT:    s_mul_i32 s7, s3, s6
 ; GFX8-NEXT:    s_mul_i32 s6, s2, s6
-; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
-; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v1
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s6
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s7, v2
+; GFX8-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX8-NEXT:    s_mov_b32 m0, -1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    ds_sub_rtn_u64 v[1:2], v3, v[1:2]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:  BB12_2:
 ; GFX8-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX8-NEXT:    s_mov_b32 s4, s0
-; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
-; GFX8-NEXT:    v_mul_lo_u32 v1, s3, v0
-; GFX8-NEXT:    v_mul_hi_u32 v3, s2, v0
+; GFX8-NEXT:    v_mul_lo_u32 v3, s3, v0
+; GFX8-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX8-NEXT:    v_mul_lo_u32 v0, s2, v0
+; GFX8-NEXT:    s_mov_b32 s4, s0
 ; GFX8-NEXT:    s_mov_b32 s5, s1
 ; GFX8-NEXT:    v_readfirstlane_b32 s1, v2
-; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
+; GFX8-NEXT:    v_readfirstlane_b32 s0, v1
+; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v3
 ; GFX8-NEXT:    v_mov_b32_e32 v2, s1
 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s0, v0
 ; GFX8-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX8-NEXT:    s_mov_b32 s6, -1
 ; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
 ; GFX8-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX8-NEXT:    s_endpgm
 ;

llvm/test/CodeGen/AMDGPU/bypass-div.ll

 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v2, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v3, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v4, v4, v3
 ; GFX9-NEXT:    v_xor_b32_e32 v5, v5, v3
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v4
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, 0, v4
 ; GFX9-NEXT:    v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v16, 0
+; GFX9-NEXT:    v_mov_b32_e32 v14, 0
 ; GFX9-NEXT:    v_mac_f32_e32 v6, 0x4f800000, v7
 ; GFX9-NEXT:    v_rcp_f32_e32 v6, v6
-; GFX9-NEXT:    v_mov_b32_e32 v15, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v6, 0x5f7ffffc, v6
 ; GFX9-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v6
 ; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
 ; GFX9-NEXT:    v_mac_f32_e32 v6, 0xcf800000, v7
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v6
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v7
+; GFX9-NEXT:    v_mul_lo_u32 v11, v9, v6
+; GFX9-NEXT:    v_mul_lo_u32 v10, v8, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v8, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v6
-; GFX9-NEXT:    v_add3_u32 v10, v11, v12, v10
+; GFX9-NEXT:    v_add3_u32 v10, v12, v10, v11
+; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v13
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v6, v10
-; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v13
-; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v10
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v14, v12
-; GFX9-NEXT:    v_mul_lo_u32 v14, v7, v13
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v15, v6, v10
+; GFX9-NEXT:    v_mul_lo_u32 v16, v7, v13
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v7, v13
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v14
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v14, v15, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v16
+; GFX9-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, v15, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v13, v10
 ; GFX9-NEXT:    v_add_co_u32_e64 v6, s[4:5], v6, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v10
-; GFX9-NEXT:    v_mul_hi_u32 v13, v8, v6
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v12, s[4:5]
+; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v10
+; GFX9-NEXT:    v_mul_hi_u32 v15, v8, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v9, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v6
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v11
-; GFX9-NEXT:    v_add3_u32 v9, v13, v12, v9
-; GFX9-NEXT:    v_mul_lo_u32 v12, v6, v9
-; GFX9-NEXT:    v_mul_hi_u32 v13, v6, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v12, v8
-; GFX9-NEXT:    v_mul_hi_u32 v8, v10, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v12, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v9
+; GFX9-NEXT:    v_add_u32_e32 v7, v7, v12
+; GFX9-NEXT:    v_add3_u32 v9, v15, v13, v9
+; GFX9-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GFX9-NEXT:    v_mul_lo_u32 v16, v10, v8
+; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v8
+; GFX9-NEXT:    v_mul_lo_u32 v17, v6, v9
+; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v10, v10, v9
+; GFX9-NEXT:    v_mul_hi_u32 v9, v6, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v17
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v16
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v15, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v9, s[4:5]
+; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v0, v8
 ; GFX9-NEXT:    v_xor_b32_e32 v9, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v6
-; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v6
+; GFX9-NEXT:    v_mul_hi_u32 v13, v9, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v6
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v12, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v13, v1, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v1, v6
-; GFX9-NEXT:    v_mul_hi_u32 v13, v1, v7
+; GFX9-NEXT:    v_mul_hi_u32 v15, v1, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v12
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v6, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v13
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v12, v6, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v14, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v4, v6
 ; GFX9-NEXT:    v_add3_u32 v10, v12, v11, v10
 ; GFX9-NEXT:    v_sub_u32_e32 v11, v1, v10
 ; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v9, v13
 ; GFX9-NEXT:    v_subb_co_u32_e64 v11, s[4:5], v11, v5, vcc

 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v11
+; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
 ; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT:    v_mul_lo_u32 v11, v8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v6, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4

 ; GFX9-NEXT:    v_xor_b32_e32 v3, v4, v3
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v3
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v6, v5
 ; GFX9-NEXT:    v_sub_co_u32_e32 v7, vcc, 0, v3
 ; GFX9-NEXT:    v_subb_co_u32_e32 v8, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v15, 0
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v6
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v14, 0
+; GFX9-NEXT:    v_mov_b32_e32 v13, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v6, v6
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v6
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v6
-; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v4
-; GFX9-NEXT:    v_mul_hi_u32 v10, v7, v4
-; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v6
+; GFX9-NEXT:    v_mul_lo_u32 v10, v8, v4
+; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v6
+; GFX9-NEXT:    v_mul_hi_u32 v11, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v7, v4
-; GFX9-NEXT:    v_add3_u32 v9, v10, v11, v9
+; GFX9-NEXT:    v_add3_u32 v9, v11, v9, v10
+; GFX9-NEXT:    v_mul_hi_u32 v10, v4, v12
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v9
-; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v12
-; GFX9-NEXT:    v_mul_hi_u32 v10, v4, v9
-; GFX9-NEXT:    v_mul_hi_u32 v16, v6, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v13, v11
-; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v12
+; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v9
+; GFX9-NEXT:    v_mul_lo_u32 v16, v6, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v12
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v10, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v13
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v14, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v14, v6, v9
+; GFX9-NEXT:    v_mul_lo_u32 v9, v6, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v16
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v11, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v14, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v9, vcc, v6, v10, s[4:5]
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v7, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_add_u32_e32 v6, v6, v10
 ; GFX9-NEXT:    v_add3_u32 v8, v12, v11, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v4, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v16, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v13, v9, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v12, v11
-; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
-; GFX9-NEXT:    v_mul_lo_u32 v7, v9, v7
+; GFX9-NEXT:    v_mul_lo_u32 v12, v9, v7
+; GFX9-NEXT:    v_mul_hi_u32 v7, v9, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, v15, v16, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v11, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v14, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v11, v12
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v15, v9, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v6, vcc, v6, v8, s[4:5]
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v7, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v0, v7
 ; GFX9-NEXT:    v_xor_b32_e32 v8, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v8, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v8, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v7, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v10, v9
 ; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v1, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v1, v6
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
 ; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v10, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v12, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v12, v13, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v9, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v5, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v3, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v3, v6
 ; GFX9-NEXT:    v_mul_lo_u32 v4, v3, v4
 ; GFX9-NEXT:    v_add3_u32 v6, v10, v6, v9
 ; GFX9-NEXT:    v_sub_u32_e32 v9, v1, v6

 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v11
+; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
 ; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT:    v_mul_lo_u32 v11, v8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v6, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4

 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v2, v3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v7, v3, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v6, v4, v3
 ; GFX9-NEXT:    v_xor_b32_e32 v5, v5, v3
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, v6
 ; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, v5
 ; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, 0, v6
 ; GFX9-NEXT:    v_subb_co_u32_e32 v9, vcc, 0, v5, vcc
-; GFX9-NEXT:    v_mov_b32_e32 v16, 0
+; GFX9-NEXT:    v_mov_b32_e32 v14, 0
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0x4f800000, v7
 ; GFX9-NEXT:    v_rcp_f32_e32 v4, v4
-; GFX9-NEXT:    v_mov_b32_e32 v15, 0
 ; GFX9-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GFX9-NEXT:    v_mul_f32_e32 v7, 0x2f800000, v4
 ; GFX9-NEXT:    v_trunc_f32_e32 v7, v7
 ; GFX9-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v7
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v4
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v4
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v7
+; GFX9-NEXT:    v_mul_lo_u32 v11, v9, v4
+; GFX9-NEXT:    v_mul_lo_u32 v10, v8, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v8, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v4
-; GFX9-NEXT:    v_add3_u32 v10, v11, v12, v10
+; GFX9-NEXT:    v_add3_u32 v10, v12, v10, v11
+; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v13
 ; GFX9-NEXT:    v_mul_lo_u32 v12, v4, v10
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v13
-; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v10
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v14, v12
-; GFX9-NEXT:    v_mul_lo_u32 v14, v7, v13
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v11, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v10
+; GFX9-NEXT:    v_mul_lo_u32 v16, v7, v13
 ; GFX9-NEXT:    v_mul_hi_u32 v13, v7, v13
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v12, v14
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v12
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v7, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v14, v15, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v7, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v11, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
+; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v11, v16
+; GFX9-NEXT:    v_mov_b32_e32 v11, 0
+; GFX9-NEXT:    v_addc_co_u32_e32 v13, vcc, v15, v13, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v12, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v13, v10
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v11, s[4:5]
-; GFX9-NEXT:    v_mul_lo_u32 v12, v8, v10
-; GFX9-NEXT:    v_mul_hi_u32 v13, v8, v4
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v12, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v10, vcc, v7, v12, s[4:5]
+; GFX9-NEXT:    v_mul_lo_u32 v13, v8, v10
+; GFX9-NEXT:    v_mul_hi_u32 v15, v8, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v9, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v8, v4
-; GFX9-NEXT:    v_add_u32_e32 v7, v7, v11
-; GFX9-NEXT:    v_add3_u32 v9, v13, v12, v9
-; GFX9-NEXT:    v_mul_lo_u32 v12, v4, v9
-; GFX9-NEXT:    v_mul_hi_u32 v13, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v9
-; GFX9-NEXT:    v_add_co_u32_e32 v12, vcc, v13, v12
-; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v10, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, v16, v14, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v12, v8
-; GFX9-NEXT:    v_mul_hi_u32 v8, v10, v9
-; GFX9-NEXT:    v_mul_lo_u32 v9, v10, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v8, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v12, v9
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v16, v8, vcc
-; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v8, s[4:5]
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
+; GFX9-NEXT:    v_add_u32_e32 v7, v7, v12
+; GFX9-NEXT:    v_add3_u32 v9, v15, v13, v9
+; GFX9-NEXT:    v_mul_hi_u32 v15, v10, v8
+; GFX9-NEXT:    v_mul_lo_u32 v16, v10, v8
+; GFX9-NEXT:    v_mul_hi_u32 v8, v4, v8
+; GFX9-NEXT:    v_mul_lo_u32 v17, v4, v9
+; GFX9-NEXT:    v_mul_hi_u32 v13, v10, v9
+; GFX9-NEXT:    v_mul_lo_u32 v10, v10, v9
+; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v9
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v17
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v16
+; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v9, v15, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v8, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v14, v9, vcc
+; GFX9-NEXT:    v_addc_co_u32_e64 v7, vcc, v7, v9, s[4:5]
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v7, vcc
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v8, 31, v1
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v0, v8
 ; GFX9-NEXT:    v_xor_b32_e32 v9, v9, v8
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v9, v7
-; GFX9-NEXT:    v_mul_hi_u32 v11, v9, v4
-; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v7
+; GFX9-NEXT:    v_mul_hi_u32 v12, v9, v4
+; GFX9-NEXT:    v_mul_hi_u32 v13, v9, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v8, vcc
 ; GFX9-NEXT:    v_xor_b32_e32 v1, v1, v8
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v16, v12, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v12, v1, v4
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v12, v10
+; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, v14, v13, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v13, v1, v4
 ; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX9-NEXT:    v_mul_hi_u32 v13, v1, v7
+; GFX9-NEXT:    v_mul_hi_u32 v15, v1, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v7
-; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v12
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v11, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v10, v13
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v12, v4, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v11, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v16, v10, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v14, v10, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v5, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v12, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v13, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v10, v12, v11, v10
 ; GFX9-NEXT:    v_sub_u32_e32 v11, v1, v10
 ; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v9, v13
 ; GFX9-NEXT:    v_subb_co_u32_e64 v11, s[4:5], v11, v5, vcc

 ; GFX9-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v9, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v8, v6, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GFX9-NEXT:    v_add3_u32 v8, v10, v8, v9
 ; GFX9-NEXT:    v_mul_hi_u32 v9, v4, v11
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v14, v4, v8
-; GFX9-NEXT:    v_mul_hi_u32 v15, v5, v8
-; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v8
+; GFX9-NEXT:    v_mul_hi_u32 v14, v5, v11
+; GFX9-NEXT:    v_mul_lo_u32 v11, v5, v11
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v10
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v13, v14, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v14, v5, v11
-; GFX9-NEXT:    v_mul_hi_u32 v11, v5, v11
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v14
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v10, v11, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v15, v12, vcc
+; GFX9-NEXT:    v_mul_hi_u32 v10, v5, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v8, v5, v8
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v15, v14, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v10, vcc, v10, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v9, v8
 ; GFX9-NEXT:    v_add_co_u32_e64 v4, s[4:5], v4, v8
 ; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, v13, v10, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v8, vcc, v5, v9, s[4:5]
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v6, v8
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v6, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GFX9-NEXT:    v_add_u32_e32 v5, v5, v9
 ; GFX9-NEXT:    v_add3_u32 v7, v11, v10, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v10, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v11, v4, v6
 ; GFX9-NEXT:    v_mul_hi_u32 v15, v4, v7
 ; GFX9-NEXT:    v_mul_hi_u32 v14, v8, v7
 ; GFX9-NEXT:    v_mul_lo_u32 v7, v8, v7
 ; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v10
-; GFX9-NEXT:    v_mul_hi_u32 v11, v8, v6
-; GFX9-NEXT:    v_mul_lo_u32 v6, v8, v6
+; GFX9-NEXT:    v_mul_lo_u32 v11, v8, v6
+; GFX9-NEXT:    v_mul_hi_u32 v6, v8, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v15, vcc, v13, v15, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v10, v6
-; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v11, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v10, v11
+; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v15, v6, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v14, v12, vcc
 ; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v7
 ; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v13, v8, vcc
 ; GFX9-NEXT:    v_addc_co_u32_e64 v5, vcc, v5, v7, s[4:5]
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v6
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v7, v0, v4

llvm/test/CodeGen/AMDGPU/ds_write2.ll

 ; CI-NEXT:    v_lshlrev_b32_e32 v0, 4, v0
 ; CI-NEXT:    s_mov_b32 m0, -1
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
 ; CI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
 ; CI-NEXT:    s_waitcnt lgkmcnt(0)
 ; CI-NEXT:    v_mov_b32_e32 v1, s0
 ; CI-NEXT:    v_mov_b32_e32 v2, s1
-; CI-NEXT:    ds_write2_b32 v0, v1, v2 offset1:1
 ; CI-NEXT:    v_mov_b32_e32 v3, s2
-; CI-NEXT:    v_mov_b32_e32 v1, s3
-; CI-NEXT:    ds_write2_b32 v0, v3, v1 offset0:2 offset1:3
+; CI-NEXT:    v_mov_b32_e32 v4, s3
+; CI-NEXT:    ds_write2_b32 v0, v1, v2 offset1:1
+; CI-NEXT:    ds_write2_b32 v0, v3, v4 offset0:2 offset1:3
 ; CI-NEXT:    s_endpgm
 ;
 ; GFX9-ALIGNED-LABEL: simple_write2_v4f32_superreg_align4:
 ; GFX9-ALIGNED:       ; %bb.0:
 ; GFX9-ALIGNED-NEXT:    s_load_dword s4, s[0:1], 0x24
 ; GFX9-ALIGNED-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c
 ; GFX9-ALIGNED-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-ALIGNED-NEXT:    v_lshl_add_u32 v0, v0, 4, s4

llvm/test/CodeGen/AMDGPU/idot2.ll

 ; GFX7-NEXT:    s_mov_b32 s11, s3
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-NEXT:    s_mov_b64 s[8:9], s[4:5]
 ; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX7-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX7-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
 ; GFX7-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX7-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT:    s_load_dword s5, s[0:1], 0x0
 ; GFX7-NEXT:    s_mov_b32 s4, 0xffff
 ; GFX7-NEXT:    s_mov_b32 s2, -1
 ; GFX7-NEXT:    s_waitcnt vmcnt(1)
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
 ; GFX7-NEXT:    v_and_b32_e32 v2, s4, v2
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x0
 ; GFX7-NEXT:    v_mul_u32_u24_e32 v0, v0, v2
 ; GFX7-NEXT:    v_mad_u32_u24 v0, v3, v1, v0
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s5, v0
+; GFX7-NEXT:    v_add_i32_e32 v0, vcc, s4, v0
 ; GFX7-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: udot2_MulMul:
 ; GFX8:       ; %bb.0: ; %entry
 ; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0

 ; GFX7-NEXT:    s_mov_b32 s11, s3
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX7-NEXT:    s_mov_b64 s[8:9], s[4:5]
 ; GFX7-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX7-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX7-NEXT:    buffer_load_dword v2, v[0:1], s[8:11], 0 addr64
 ; GFX7-NEXT:    s_mov_b64 s[8:9], s[6:7]
 ; GFX7-NEXT:    buffer_load_dword v0, v[0:1], s[8:11], 0 addr64
-; GFX7-NEXT:    s_load_dword s5, s[0:1], 0x0
 ; GFX7-NEXT:    s_mov_b32 s4, 0xffff
 ; GFX7-NEXT:    s_mov_b32 s2, -1
 ; GFX7-NEXT:    s_waitcnt vmcnt(1)
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v1, 16, v2
 ; GFX7-NEXT:    v_and_b32_e32 v2, s4, v2
 ; GFX7-NEXT:    s_waitcnt vmcnt(0)
 ; GFX7-NEXT:    v_lshrrev_b32_e32 v3, 16, v0
 ; GFX7-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX7-NEXT:    s_load_dword s4, s[0:1], 0x0
 ; GFX7-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX7-NEXT:    v_mad_u32_u24 v1, v3, v1, s5
+; GFX7-NEXT:    v_mad_u32_u24 v1, v3, v1, s4
 ; GFX7-NEXT:    v_mad_u32_u24 v0, v0, v2, v1
 ; GFX7-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GFX7-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: udot2_MultipleUses_add1:
 ; GFX8:       ; %bb.0: ; %entry
 ; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

llvm/test/CodeGen/AMDGPU/idot8s.ll

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    v_mov_b32_e32 v5, 12
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ushort v4, v[0:1]
+; GFX8-NEXT:    flat_load_ushort v3, v[0:1]
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v3
-; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 4, v2
+; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v4
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v17, 12, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v4
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 8, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v15, 12, v15
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v5, 12, v16
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v16, 12, v17
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v14, 12, v14
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v15, 12, v15
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v4, v5, v16, v4
+; GFX8-NEXT:    v_mad_u16 v3, v5, v16, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v14, 12, v14
-; GFX8-NEXT:    v_mad_u16 v4, v10, v15, v4
+; GFX8-NEXT:    v_mad_u16 v3, v10, v15, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v13, 12, v13
-; GFX8-NEXT:    v_mad_u16 v4, v9, v14, v4
+; GFX8-NEXT:    v_mad_u16 v3, v9, v14, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v18
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v18, 12, v19
-; GFX8-NEXT:    v_mad_u16 v4, v8, v13, v4
+; GFX8-NEXT:    v_mad_u16 v3, v8, v13, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v12, 12, v12
-; GFX8-NEXT:    v_mad_u16 v4, v17, v18, v4
+; GFX8-NEXT:    v_mad_u16 v3, v17, v18, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v11, 12, v11
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
-; GFX8-NEXT:    v_mad_u16 v4, v7, v12, v4
+; GFX8-NEXT:    v_mad_u16 v3, v7, v12, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v11
-; GFX8-NEXT:    v_mad_u16 v2, v3, v2, v4
+; GFX8-NEXT:    v_mad_u16 v2, v4, v2, v3
 ; GFX8-NEXT:    v_mad_u16 v2, v6, v11, v2
 ; GFX8-NEXT:    flat_store_short v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: idot8_acc16:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    v_mov_b32_e32 v5, 12
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ubyte v4, v[0:1]
+; GFX8-NEXT:    flat_load_ubyte v3, v[0:1]
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v3
-; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 4, v2
+; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v4
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v17, 12, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 28, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v4
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 8, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v15, 12, v15
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v5, 12, v16
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v16, 12, v17
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v14, 12, v14
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v10, 12, v10
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v15, 12, v15
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v4, v5, v16, v4
+; GFX8-NEXT:    v_mad_u16 v3, v5, v16, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v14, 12, v14
-; GFX8-NEXT:    v_mad_u16 v4, v10, v15, v4
+; GFX8-NEXT:    v_mad_u16 v3, v10, v15, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v13, 12, v13
-; GFX8-NEXT:    v_mad_u16 v4, v9, v14, v4
+; GFX8-NEXT:    v_mad_u16 v3, v9, v14, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v18
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v18, 12, v19
-; GFX8-NEXT:    v_mad_u16 v4, v8, v13, v4
+; GFX8-NEXT:    v_mad_u16 v3, v8, v13, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v12, 12, v12
-; GFX8-NEXT:    v_mad_u16 v4, v17, v18, v4
+; GFX8-NEXT:    v_mad_u16 v3, v17, v18, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v11, 12, v11
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
-; GFX8-NEXT:    v_mad_u16 v4, v7, v12, v4
+; GFX8-NEXT:    v_mad_u16 v3, v7, v12, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v11
-; GFX8-NEXT:    v_mad_u16 v2, v3, v2, v4
+; GFX8-NEXT:    v_mad_u16 v2, v4, v2, v3
 ; GFX8-NEXT:    v_mad_u16 v2, v6, v11, v2
 ; GFX8-NEXT:    flat_store_byte v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: idot8_acc8:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    v_mov_b32_e32 v5, 12
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ushort v4, v[0:1]
+; GFX8-NEXT:    flat_load_ushort v3, v[0:1]
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 4, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 8, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 20, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 28, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 4, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 8, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 28, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 4, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 8, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 28, v2
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v16, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v16, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v18, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_sdwa v5, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 12, v3
+; GFX8-NEXT:    v_lshlrev_b16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v2, 12, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v11, 12, v11
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v11
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v2, v3, v2, v4
+; GFX8-NEXT:    v_mad_u16 v2, v4, v2, v3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_mad_u16 v2, v6, v11, v2
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v8, 12, v8
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_mad_u16 v2, v7, v12, v2

 ; GFX7-NEXT:    buffer_store_byte v0, off, s[0:3], 0
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: idot8_acc8_vecMul:
 ; GFX8:       ; %bb.0: ; %entry
 ; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
-; GFX8-NEXT:    v_mov_b32_e32 v5, 12
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
+; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v3, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v2, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
+; GFX8-NEXT:    flat_load_dword v4, v[0:1]
+; GFX8-NEXT:    flat_load_dword v2, v[2:3]
 ; GFX8-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s1
-; GFX8-NEXT:    flat_load_ubyte v4, v[0:1]
-; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
+; GFX8-NEXT:    flat_load_ubyte v5, v[0:1]
+; GFX8-NEXT:    v_mov_b32_e32 v3, 12
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 28, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 20, v3
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 20, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 28, v4
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 28, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v13, 12, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v14, 8, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v3
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 20, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v15, 4, v2
-; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 4, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 20, v2
+; GFX8-NEXT:    v_lshlrev_b16_e32 v16, 12, v4
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v17, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v18, 12, v2
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v5, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_lshlrev_b16_e32 v5, 12, v10
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v19, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v8, 12, v4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v4
+; GFX8-NEXT:    v_lshlrev_b16_sdwa v4, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 12, v10
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v7, 12, v7
+; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v12, 12, v12
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v10, 12, v16
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v16, 12, v17
-; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v3
-; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 12, v6
-; GFX8-NEXT:    v_lshlrev_b16_e32 v6, 12, v15
-; GFX8-NEXT:    v_ashrrev_i16_e32 v15, 12, v18
+; GFX8-NEXT:    v_ashrrev_i16_e32 v17, 12, v18
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v18, 12, v19
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v19, 12, v2
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v2, 12, v11
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v8, 12, v8
-; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
 ; GFX8-NEXT:    v_lshlrev_b16_e32 v14, 12, v14
+; GFX8-NEXT:    v_lshlrev_b16_e32 v13, 12, v13
+; GFX8-NEXT:    v_lshlrev_b16_e32 v15, 12, v15
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v7, 12, v7
-; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
+; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v2, 12, v2
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v12, 12, v12
-; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v14
-; GFX8-NEXT:    v_mul_lo_u16_e32 v10, v10, v15
-; GFX8-NEXT:    v_mul_lo_u16_sdwa v2, v3, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_mul_lo_u16_e32 v10, v10, v17
+; GFX8-NEXT:    v_mul_lo_u16_sdwa v2, v6, v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_ashrrev_i16_e32 v4, 12, v4
+; GFX8-NEXT:    v_ashrrev_i16_e32 v11, 12, v15
+; GFX8-NEXT:    v_ashrrev_i16_e32 v3, 12, v3
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v9, 12, v9
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v8, 12, v8
+; GFX8-NEXT:    v_ashrrev_i16_e32 v14, 12, v14
 ; GFX8-NEXT:    v_ashrrev_i16_e32 v13, 12, v13
-; GFX8-NEXT:    v_mul_lo_u16_sdwa v3, v7, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT:    v_mul_lo_u16_e32 v15, v16, v18
+; GFX8-NEXT:    v_mul_lo_u16_sdwa v6, v7, v12 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_mul_lo_u16_e32 v17, v16, v18
 ; GFX8-NEXT:    v_mul_lo_u16_sdwa v7, v8, v13 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX8-NEXT:    v_mul_lo_u16_e32 v8, v9, v11
-; GFX8-NEXT:    v_or_b32_sdwa v3, v15, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_ashrrev_i16_e32 v5, 12, v5
-; GFX8-NEXT:    v_ashrrev_i16_e32 v6, 12, v6
-; GFX8-NEXT:    v_mul_lo_u16_e32 v14, v17, v19
-; GFX8-NEXT:    v_mul_lo_u16_sdwa v5, v5, v6 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_mul_lo_u16_e32 v8, v9, v14
+; GFX8-NEXT:    v_mul_lo_u16_e32 v15, v4, v19
+; GFX8-NEXT:    v_mul_lo_u16_sdwa v9, v3, v11 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_or_b32_sdwa v7, v8, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_sdwa v6, v14, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_lshlrev_b32_e32 v9, 16, v3
-; GFX8-NEXT:    v_or_b32_sdwa v8, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_sdwa v3, v15, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_sdwa v8, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
+; GFX8-NEXT:    v_or_b32_sdwa v3, v3, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 16, v7
+; GFX8-NEXT:    v_or_b32_e32 v9, v9, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v10, 8, v3
-; GFX8-NEXT:    v_or_b32_sdwa v3, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_e32 v5, v5, v2
-; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 8, v3
 ; GFX8-NEXT:    v_lshrrev_b64 v[2:3], 24, v[2:3]
-; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 8, v5
+; GFX8-NEXT:    v_lshrrev_b32_e32 v9, 8, v9
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_add_u16_e32 v3, v8, v4
-; GFX8-NEXT:    v_add_u16_e32 v3, v3, v5
+; GFX8-NEXT:    v_add_u16_e32 v3, v8, v5
+; GFX8-NEXT:    v_add_u16_e32 v3, v3, v9
 ; GFX8-NEXT:    v_add_u16_e32 v3, v3, v7
 ; GFX8-NEXT:    v_add_u16_e32 v2, v3, v2
-; GFX8-NEXT:    v_mad_u16 v2, v17, v19, v2
-; GFX8-NEXT:    v_add_u16_e32 v2, v2, v6
-; GFX8-NEXT:    v_mad_u16 v2, v16, v18, v2
+; GFX8-NEXT:    v_mad_u16 v2, v4, v19, v2
 ; GFX8-NEXT:    v_add_u16_e32 v2, v2, v10
+; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 8, v6
+; GFX8-NEXT:    v_mad_u16 v2, v16, v18, v2
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v6
 ; GFX8-NEXT:    flat_store_byte v[0:1], v2
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: idot8_acc8_vecMul:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s10, -1

llvm/test/CodeGen/AMDGPU/idot8u.ll

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ushort v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ushort v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
-; GFX8-NEXT:    flat_store_short v[2:3], v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
+; GFX8-NEXT:    flat_store_short v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc16:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s10, -1
 ; GFX9-NEXT:    s_mov_b32 s11, 0xe00000

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ubyte v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ubyte v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc8:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s10, -1
 ; GFX9-NEXT:    s_mov_b32 s11, 0xe00000

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ubyte v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ubyte v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 24, v4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v0
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v1
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc4:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s10, -1
 ; GFX9-NEXT:    s_mov_b32 s11, 0xe00000

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ubyte v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ubyte v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v4
-; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 24, v4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 4, 4
-; GFX8-NEXT:    v_and_b32_e32 v4, 15, v4
-; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v0
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 4, 4
+; GFX8-NEXT:    v_lshrrev_b32_e32 v2, 28, v0
+; GFX8-NEXT:    v_lshrrev_b32_e32 v3, 24, v0
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 4, 4
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
+; GFX8-NEXT:    s_waitcnt vmcnt(1)
+; GFX8-NEXT:    v_lshrrev_b32_e32 v11, 28, v1
+; GFX8-NEXT:    v_lshrrev_b32_e32 v12, 24, v1
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v18
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v18
 ; GFX8-NEXT:    v_mad_u16 v0, v10, v17, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v9, v16, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v8, v15, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v7, v14, v0
 ; GFX8-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX8-NEXT:    v_mad_u16 v0, v5, v12, v0
-; GFX8-NEXT:    v_mad_u16 v0, v1, v11, v0
+; GFX8-NEXT:    v_mad_u16 v0, v3, v12, v0
+; GFX8-NEXT:    v_mad_u16 v0, v2, v11, v0
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_CommutationInsideMAD:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s10, -1
 ; GFX9-NEXT:    s_mov_b32 s11, 0xe00000

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
-; GFX8-NEXT:    flat_load_ushort v18, v[2:3]
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
+; GFX8-NEXT:    flat_load_ushort v18, v[4:5]
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(2)
-; GFX8-NEXT:    v_and_b32_e32 v1, 15, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 4, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 16, 4
+; GFX8-NEXT:    v_and_b32_e32 v2, 15, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_and_b32_e32 v11, 15, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 4, 4
+; GFX8-NEXT:    v_and_b32_e32 v11, 15, v1
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 4, 4
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 4, 4
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_mad_u16 v1, v1, v11, v18
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 8, 4
-; GFX8-NEXT:    v_mad_u16 v1, v5, v12, v1
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 12, 4
-; GFX8-NEXT:    v_mad_u16 v1, v6, v13, v1
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 16, 4
-; GFX8-NEXT:    v_mad_u16 v1, v7, v14, v1
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 20, 4
-; GFX8-NEXT:    v_mad_u16 v1, v8, v15, v1
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 24, 4
-; GFX8-NEXT:    v_mad_u16 v1, v9, v16, v1
-; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 28, v4
+; GFX8-NEXT:    v_mad_u16 v2, v2, v11, v18
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 8, 4
+; GFX8-NEXT:    v_mad_u16 v2, v3, v12, v2
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 12, 4
+; GFX8-NEXT:    v_mad_u16 v2, v6, v13, v2
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 16, 4
+; GFX8-NEXT:    v_mad_u16 v2, v7, v14, v2
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 20, 4
+; GFX8-NEXT:    v_mad_u16 v2, v8, v15, v2
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 24, 4
+; GFX8-NEXT:    v_mad_u16 v2, v9, v16, v2
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 28, v0
-; GFX8-NEXT:    v_mad_u16 v1, v10, v17, v1
-; GFX8-NEXT:    v_mad_u16 v0, v4, v0, v1
-; GFX8-NEXT:    flat_store_short v[2:3], v0
+; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v1
+; GFX8-NEXT:    v_mad_u16 v2, v10, v17, v2
+; GFX8-NEXT:    v_mad_u16 v0, v0, v1, v2
+; GFX8-NEXT:    flat_store_short v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc16_vecMul:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s10, -1
 ; GFX9-NEXT:    s_mov_b32 s11, 0xe00000

 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX8-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX8-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX8-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v1, s5
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s4, v2
 ; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GFX8-NEXT:    flat_load_dword v4, v[0:1]
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s6, v2
-; GFX8-NEXT:    v_mov_b32_e32 v1, s7
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX8-NEXT:    v_mov_b32_e32 v3, s7
+; GFX8-NEXT:    v_add_u32_e32 v2, vcc, s6, v2
+; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX8-NEXT:    flat_load_dword v0, v[0:1]
-; GFX8-NEXT:    v_mov_b32_e32 v3, s1
-; GFX8-NEXT:    v_mov_b32_e32 v2, s0
+; GFX8-NEXT:    flat_load_dword v1, v[2:3]
+; GFX8-NEXT:    v_mov_b32_e32 v5, s1
+; GFX8-NEXT:    v_mov_b32_e32 v4, s0
 ; GFX8-NEXT:    s_mov_b32 s10, -1
 ; GFX8-NEXT:    s_mov_b32 s11, 0xe80000
 ; GFX8-NEXT:    s_add_u32 s8, s8, s3
 ; GFX8-NEXT:    s_addc_u32 s9, s9, 0
 ; GFX8-NEXT:    s_waitcnt vmcnt(1)
-; GFX8-NEXT:    v_and_b32_e32 v1, 15, v4
-; GFX8-NEXT:    v_bfe_u32 v5, v4, 4, 4
-; GFX8-NEXT:    v_bfe_u32 v6, v4, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v7, v4, 12, 4
+; GFX8-NEXT:    v_and_b32_e32 v2, 15, v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_and_b32_e32 v11, 15, v0
-; GFX8-NEXT:    v_bfe_u32 v12, v0, 4, 4
-; GFX8-NEXT:    v_bfe_u32 v13, v0, 8, 4
-; GFX8-NEXT:    v_bfe_u32 v14, v0, 12, 4
-; GFX8-NEXT:    v_bfe_u32 v8, v4, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v15, v0, 16, 4
-; GFX8-NEXT:    v_bfe_u32 v9, v4, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v10, v4, 24, 4
-; GFX8-NEXT:    v_bfe_u32 v16, v0, 20, 4
-; GFX8-NEXT:    v_bfe_u32 v17, v0, 24, 4
-; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 28, v4
+; GFX8-NEXT:    v_and_b32_e32 v11, 15, v1
+; GFX8-NEXT:    v_bfe_u32 v3, v0, 4, 4
+; GFX8-NEXT:    v_bfe_u32 v12, v1, 4, 4
+; GFX8-NEXT:    v_bfe_u32 v6, v0, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v13, v1, 8, 4
+; GFX8-NEXT:    v_bfe_u32 v7, v0, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v14, v1, 12, 4
+; GFX8-NEXT:    v_bfe_u32 v8, v0, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v15, v1, 16, 4
+; GFX8-NEXT:    v_bfe_u32 v9, v0, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v10, v0, 24, 4
+; GFX8-NEXT:    v_bfe_u32 v16, v1, 20, 4
+; GFX8-NEXT:    v_bfe_u32 v17, v1, 24, 4
 ; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 28, v0
-; GFX8-NEXT:    v_mul_u32_u24_e32 v0, v4, v0
-; GFX8-NEXT:    v_mul_u32_u24_e32 v4, v10, v17
-; GFX8-NEXT:    flat_load_ubyte v10, v[2:3]
-; GFX8-NEXT:    v_mul_u32_u24_e32 v1, v1, v11
-; GFX8-NEXT:    v_mul_u32_u24_e32 v5, v5, v12
+; GFX8-NEXT:    v_lshrrev_b32_e32 v1, 28, v1
+; GFX8-NEXT:    v_mul_u32_u24_e32 v0, v0, v1
+; GFX8-NEXT:    v_mul_u32_u24_e32 v1, v10, v17
+; GFX8-NEXT:    flat_load_ubyte v10, v[4:5]
+; GFX8-NEXT:    v_mul_u32_u24_e32 v2, v2, v11
+; GFX8-NEXT:    v_mul_u32_u24_e32 v3, v3, v12
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v6, v6, v13
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v7, v7, v14
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v8, v8, v15
 ; GFX8-NEXT:    v_mul_u32_u24_e32 v9, v9, v16
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v10
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v5
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v6
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v7
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v8
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v9
-; GFX8-NEXT:    v_add_u16_e32 v1, v1, v4
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v10
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v3
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v6
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v7
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v8
+; GFX8-NEXT:    v_add_u16_e32 v2, v2, v9
+; GFX8-NEXT:    v_add_u16_e32 v1, v2, v1
 ; GFX8-NEXT:    v_add_u16_e32 v0, v1, v0
 ; GFX8-NEXT:    v_and_b32_e32 v0, 15, v0
-; GFX8-NEXT:    flat_store_byte v[2:3], v0
+; GFX8-NEXT:    flat_store_byte v[4:5], v0
 ; GFX8-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: udot8_acc4_vecMul:
 ; GFX9:       ; %bb.0: ; %entry
 ; GFX9-NEXT:    s_mov_b32 s8, SCRATCH_RSRC_DWORD0
 ; GFX9-NEXT:    s_mov_b32 s9, SCRATCH_RSRC_DWORD1
 ; GFX9-NEXT:    s_mov_b32 s10, -1
 ; GFX9-NEXT:    s_mov_b32 s11, 0xe00000

llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

 ; SI-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: umulo_i64_v_v:
 ; GFX9:       ; %bb.0: ; %bb
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v2
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v3
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v6, v5
 ; GFX9-NEXT:    v_mul_hi_u32 v10, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v1, v1, v3
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v7
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v10, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v4, v1
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v8, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v9, v8
+; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v4, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v10, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v3, v1
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v2
 ; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, 0, v[3:4]
-; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v7
+; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v8
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 bb:
   %umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %x, i64 %y)
   ret { i64, i1 } %umulo
 }
 
 define { i64, i1 } @smulo_i64_s_s(i64 %x, i64 %y) {

 ; SI-NEXT:    v_mov_b32_e32 v1, v5
 ; SI-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: smulo_i64_s_s:
 ; GFX9:       ; %bb.0: ; %bb
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX9-NEXT:    v_mul_hi_u32 v6, v0, v2
-; GFX9-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GFX9-NEXT:    v_mul_lo_u32 v7, v1, v2
-; GFX9-NEXT:    v_mul_hi_u32 v4, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v4, v0, v3
+; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v2
+; GFX9-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v6, v5
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, 0, v8, vcc
-; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v7
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, v9, v8
 ; GFX9-NEXT:    v_mul_hi_i32 v10, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v8, v4, vcc
-; GFX9-NEXT:    v_mul_lo_u32 v8, v1, v3
-; GFX9-NEXT:    v_addc_co_u32_e32 v9, vcc, 0, v10, vcc
+; GFX9-NEXT:    v_mul_lo_u32 v9, v1, v3
+; GFX9-NEXT:    v_addc_co_u32_e32 v4, vcc, v4, v7, vcc
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, 0, v10, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v10, 0
-; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v8
-; GFX9-NEXT:    v_addc_co_u32_e32 v8, vcc, v10, v9, vcc
+; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v9
+; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v10, v7, vcc
 ; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v4, v2
-; GFX9-NEXT:    v_subb_co_u32_e32 v11, vcc, v8, v10, vcc
+; GFX9-NEXT:    v_subb_co_u32_e32 v11, vcc, v7, v10, vcc
 ; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v1, v8, v11, vcc
-; GFX9-NEXT:    v_cndmask_b32_e32 v8, v4, v9, vcc
-; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v8, v0
+; GFX9-NEXT:    v_cndmask_b32_e32 v1, v7, v11, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v7, v4, v9, vcc
+; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, v7, v0
 ; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v1, v10, vcc
 ; GFX9-NEXT:    v_cmp_gt_i32_e32 vcc, 0, v3
 ; GFX9-NEXT:    v_cndmask_b32_e32 v4, v1, v4, vcc
-; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v7
+; GFX9-NEXT:    v_add3_u32 v1, v6, v5, v8
 ; GFX9-NEXT:    v_ashrrev_i32_e32 v5, 31, v1
-; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v9, vcc
+; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v9, vcc
 ; GFX9-NEXT:    v_mov_b32_e32 v6, v5
 ; GFX9-NEXT:    v_mul_lo_u32 v0, v0, v2
 ; GFX9-NEXT:    v_cmp_ne_u64_e32 vcc, v[3:4], v[5:6]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 bb:
   %smulo = tail call { i64, i1 } @llvm.smul.with.overflow.i64(i64 %x, i64 %y)
   ret { i64, i1 } %smulo

llvm/test/CodeGen/AMDGPU/llvm.powi.ll

 }
 
 define float @v_powi_neg1_f32(float %l) {
 ; GFX7-LABEL: v_powi_neg1_f32:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
 ; GFX7-NEXT:    v_rcp_f32_e32 v2, v1
-; GFX7-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
-; GFX7-NEXT:    v_fma_f32 v2, v3, v2, v2
 ; GFX7-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX7-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT:    v_fma_f32 v2, v4, v2, v2
 ; GFX7-NEXT:    v_mul_f32_e32 v4, v3, v2
 ; GFX7-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX7-NEXT:    v_fma_f32 v4, v5, v2, v4
 ; GFX7-NEXT:    v_fma_f32 v1, -v1, v4, v3
 ; GFX7-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
 ; GFX7-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;

 
 define float @v_powi_neg2_f32(float %l) {
 ; GFX7-LABEL: v_powi_neg2_f32:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
 ; GFX7-NEXT:    v_rcp_f32_e32 v2, v1
-; GFX7-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
-; GFX7-NEXT:    v_fma_f32 v2, v3, v2, v2
 ; GFX7-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX7-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT:    v_fma_f32 v2, v4, v2, v2
 ; GFX7-NEXT:    v_mul_f32_e32 v4, v3, v2
 ; GFX7-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX7-NEXT:    v_fma_f32 v4, v5, v2, v4
 ; GFX7-NEXT:    v_fma_f32 v1, -v1, v4, v3
 ; GFX7-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
 ; GFX7-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;

 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_mul_f32_e32 v0, v0, v0
 ; GFX7-NEXT:    v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
 ; GFX7-NEXT:    v_rcp_f32_e32 v2, v1
-; GFX7-NEXT:    v_fma_f32 v3, -v1, v2, 1.0
-; GFX7-NEXT:    v_fma_f32 v2, v3, v2, v2
 ; GFX7-NEXT:    v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX7-NEXT:    v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT:    v_fma_f32 v2, v4, v2, v2
 ; GFX7-NEXT:    v_mul_f32_e32 v4, v3, v2
 ; GFX7-NEXT:    v_fma_f32 v5, -v1, v4, v3
 ; GFX7-NEXT:    v_fma_f32 v4, v5, v2, v4
 ; GFX7-NEXT:    v_fma_f32 v1, -v1, v4, v3
 ; GFX7-NEXT:    v_div_fmas_f32 v1, v1, v2, v4
 ; GFX7-NEXT:    v_div_fixup_f32 v0, v1, v0, 1.0
 ; GFX7-NEXT:    s_setpc_b64 s[30:31]
 ;

llvm/test/CodeGen/AMDGPU/mul.ll

 ; SI-DAG: s_mul_i32
 ; SI-DAG: v_mul_hi_u32
 
 ; VI: v_mul_hi_u32
 ; VI: s_mul_i32
 ; VI: s_mul_i32
 ; VI: v_mul_hi_u32
 ; VI: v_mul_hi_u32
-; VI: s_mul_i32
 ; VI: v_mad_u64_u32
 ; VI: s_mul_i32
+; VI: s_mul_i32
 ; VI: v_mad_u64_u32
 ; VI: s_mul_i32
 ; VI: s_mul_i32
 ; VI: v_mad_u64_u32
 ; VI: s_mul_i32
 
 
 ; GCN: buffer_store_dwordx4

llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll

 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ; GFX8:    flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
 ;
-; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
-; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
+; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-4096
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
+; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX9:    global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
 ;
 ; GFX10:   global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX10:   global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
 ; GFX10:   global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX10:   global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}
 ; GFX10:   global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off offset:-2048
 ; GFX10:   global_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], off{{$}}

llvm/test/CodeGen/AMDGPU/salu-to-valu.ll

entry:
   %tmp5 = or <8 x i32> %tmp4, %c
   store <8 x i32> %tmp5, <8 x i32> addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
 
 ; SI: s_mov_b32 {{s[0-9]+}}, 0x13480
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64
-; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64
+; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}}
 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}}
 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}}
 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}}

llvm/test/CodeGen/AMDGPU/sdiv.ll

 }
 
 define amdgpu_kernel void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
 ; GCN-LABEL: sdiv_i32_4:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    s_mov_b32 s10, s2
-; GCN-NEXT:    s_mov_b32 s11, s3
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s8, s6
-; GCN-NEXT:    s_mov_b32 s9, s7
-; GCN-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; GCN-NEXT:    s_mov_b32 s0, s4
 ; GCN-NEXT:    s_mov_b32 s1, s5
+; GCN-NEXT:    s_mov_b32 s4, s6
+; GCN-NEXT:    s_mov_b32 s5, s7
+; GCN-NEXT:    s_mov_b32 s6, s2
+; GCN-NEXT:    s_mov_b32 s7, s3
+; GCN-NEXT:    buffer_load_dword v0, off, s[4:7], 0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    v_lshrrev_b32_e32 v1, 30, v1
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
 ; GCN-NEXT:    v_ashrrev_i32_e32 v0, 2, v0
 ; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; TONGA-LABEL: sdiv_i32_4:
 ; TONGA:       ; %bb.0:
 ; TONGA-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s3, 0xf000
 ; TONGA-NEXT:    s_mov_b32 s2, -1
-; TONGA-NEXT:    s_mov_b32 s10, s2
-; TONGA-NEXT:    s_mov_b32 s11, s3
 ; TONGA-NEXT:    s_waitcnt lgkmcnt(0)
-; TONGA-NEXT:    s_mov_b32 s8, s6
-; TONGA-NEXT:    s_mov_b32 s9, s7
-; TONGA-NEXT:    buffer_load_dword v0, off, s[8:11], 0
 ; TONGA-NEXT:    s_mov_b32 s0, s4
 ; TONGA-NEXT:    s_mov_b32 s1, s5
+; TONGA-NEXT:    s_mov_b32 s4, s6
+; TONGA-NEXT:    s_mov_b32 s5, s7
+; TONGA-NEXT:    s_mov_b32 s6, s2
+; TONGA-NEXT:    s_mov_b32 s7, s3
+; TONGA-NEXT:    buffer_load_dword v0, off, s[4:7], 0
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; TONGA-NEXT:    v_lshrrev_b32_e32 v1, 30, v1
 ; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v0, v1
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v0, 2, v0
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; TONGA-NEXT:    s_endpgm
 ;

 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s8, s2
 ; GCN-NEXT:    s_mov_b32 s9, s3
 ; GCN-NEXT:    buffer_load_dwordx4 v[0:3], off, s[8:11], 0
 ; GCN-NEXT:    s_mov_b32 s2, 0x4f7ffffe
 ; GCN-NEXT:    s_mov_b32 s4, s0
 ; GCN-NEXT:    s_mov_b32 s5, s1
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_ashrrev_i32_e32 v5, 31, v2
-; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v3
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v7, v3
-; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v0
-; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1
-; GCN-NEXT:    v_xor_b32_e32 v2, v2, v5
-; GCN-NEXT:    v_xor_b32_e32 v3, v3, v7
-; GCN-NEXT:    v_xor_b32_e32 v8, v4, v5
-; GCN-NEXT:    v_cvt_f32_u32_e32 v5, v2
-; GCN-NEXT:    v_xor_b32_e32 v9, v6, v7
+; GCN-NEXT:    v_ashrrev_i32_e32 v4, 31, v2
+; GCN-NEXT:    v_ashrrev_i32_e32 v5, 31, v3
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_xor_b32_e32 v2, v2, v4
+; GCN-NEXT:    v_xor_b32_e32 v3, v3, v5
+; GCN-NEXT:    v_cvt_f32_u32_e32 v6, v2
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v7, v3
 ; GCN-NEXT:    v_sub_i32_e32 v10, vcc, 0, v2
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v5, v5
 ; GCN-NEXT:    v_sub_i32_e32 v11, vcc, 0, v3
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v6
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v7, v7
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v4, v0
-; GCN-NEXT:    v_mul_f32_e32 v5, s2, v5
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
+; GCN-NEXT:    v_ashrrev_i32_e32 v8, 31, v0
+; GCN-NEXT:    v_ashrrev_i32_e32 v9, 31, v1
+; GCN-NEXT:    v_mul_f32_e32 v6, s2, v6
 ; GCN-NEXT:    v_mul_f32_e32 v7, s2, v7
+; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v7, v7
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
-; GCN-NEXT:    v_mul_lo_u32 v10, v10, v5
-; GCN-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v9, v1
+; GCN-NEXT:    v_mul_lo_u32 v10, v10, v6
 ; GCN-NEXT:    v_mul_lo_u32 v11, v11, v7
-; GCN-NEXT:    v_xor_b32_e32 v1, v1, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v5, v10
-; GCN-NEXT:    v_mul_hi_u32 v6, v7, v11
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v7
-; GCN-NEXT:    v_mul_hi_u32 v5, v1, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v4, v2
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v4
-; GCN-NEXT:    v_mul_lo_u32 v10, v5, v3
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, 1, v5
-; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v6, v0
+; GCN-NEXT:    v_xor_b32_e32 v0, v0, v8
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v9
+; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
+; GCN-NEXT:    v_mul_hi_u32 v11, v7, v11
+; GCN-NEXT:    v_xor_b32_e32 v4, v8, v4
+; GCN-NEXT:    v_xor_b32_e32 v5, v9, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
+; GCN-NEXT:    v_mul_hi_u32 v6, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v7
+; GCN-NEXT:    v_mul_lo_u32 v8, v6, v2
+; GCN-NEXT:    v_mul_lo_u32 v9, v7, v3
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, 1, v6
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, 1, v7
+; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, v8, v0
+; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, v9, v1
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v2
-; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, v10, v1
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[2:3], v1, v3
-; GCN-NEXT:    v_subrev_i32_e32 v6, vcc, v2, v0
-; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v7, s[0:1]
-; GCN-NEXT:    v_subrev_i32_e32 v7, vcc, v3, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v5, v5, v11, s[2:3]
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s[0:1]
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v7, s[2:3]
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, 1, v4
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v5
+; GCN-NEXT:    v_subrev_i32_e32 v8, vcc, v2, v0
+; GCN-NEXT:    v_subrev_i32_e32 v9, vcc, v3, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s[2:3]
+; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v8, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v9, s[2:3]
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v6
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v7
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v8, vcc
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v3
-; GCN-NEXT:    v_cndmask_b32_e32 v1, v5, v7, vcc
-; GCN-NEXT:    v_xor_b32_e32 v0, v0, v8
-; GCN-NEXT:    v_xor_b32_e32 v1, v1, v9
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v8
-; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v9
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v7, v9, vcc
+; GCN-NEXT:    v_xor_b32_e32 v0, v0, v4
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v5
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v5
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; TONGA-LABEL: sdiv_v2i32:
 ; TONGA:       ; %bb.0:
 ; TONGA-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s7, 0xf000
 ; TONGA-NEXT:    s_mov_b32 s6, -1

 ; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v4, v2
 ; TONGA-NEXT:    v_xor_b32_e32 v2, v2, v4
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v5, v2
 ; TONGA-NEXT:    v_sub_u32_e32 v6, vcc, 0, v2
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v7, 31, v0
 ; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v7, v0
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v5, v5
 ; TONGA-NEXT:    v_xor_b32_e32 v0, v0, v7
-; TONGA-NEXT:    v_xor_b32_e32 v4, v7, v4
+; TONGA-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; TONGA-NEXT:    v_mul_f32_e32 v5, s2, v5
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; TONGA-NEXT:    v_mul_lo_u32 v6, v6, v5
 ; TONGA-NEXT:    v_mul_hi_u32 v6, v5, v6
 ; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v6, v5
 ; TONGA-NEXT:    v_mul_hi_u32 v5, v0, v5
-; TONGA-NEXT:    v_ashrrev_i32_e32 v6, 31, v3
-; TONGA-NEXT:    v_mul_lo_u32 v8, v5, v2
+; TONGA-NEXT:    v_mul_lo_u32 v6, v5, v2
 ; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v5
-; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v8, v0
+; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v6, v0
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v2
-; TONGA-NEXT:    v_subrev_u32_e32 v8, vcc, v2, v0
+; TONGA-NEXT:    v_subrev_u32_e32 v6, vcc, v2, v0
 ; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s[0:1]
-; TONGA-NEXT:    v_cndmask_b32_e64 v0, v0, v8, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v5
+; TONGA-NEXT:    v_cndmask_b32_e64 v0, v0, v6, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v5
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v2
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v6, v3
-; TONGA-NEXT:    v_xor_b32_e32 v2, v0, v6
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v8, v3
+; TONGA-NEXT:    v_xor_b32_e32 v2, v0, v8
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v0, v2
-; TONGA-NEXT:    v_sub_u32_e32 v9, vcc, 0, v2
-; TONGA-NEXT:    v_ashrrev_i32_e32 v3, 31, v1
-; TONGA-NEXT:    v_add_u32_e32 v1, vcc, v3, v1
+; TONGA-NEXT:    v_sub_u32_e32 v3, vcc, 0, v2
+; TONGA-NEXT:    v_ashrrev_i32_e32 v9, 31, v1
+; TONGA-NEXT:    v_add_u32_e32 v1, vcc, v9, v1
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v3
-; TONGA-NEXT:    v_xor_b32_e32 v6, v3, v6
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v9
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[0:1]
 ; TONGA-NEXT:    v_mul_f32_e32 v0, s2, v0
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; TONGA-NEXT:    v_mul_lo_u32 v9, v9, v0
-; TONGA-NEXT:    v_mul_hi_u32 v7, v0, v9
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v7, v0
+; TONGA-NEXT:    v_mul_lo_u32 v3, v3, v0
+; TONGA-NEXT:    v_mul_hi_u32 v3, v0, v3
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
 ; TONGA-NEXT:    v_mul_hi_u32 v3, v1, v0
-; TONGA-NEXT:    v_xor_b32_e32 v0, v5, v4
-; TONGA-NEXT:    v_sub_u32_e32 v0, vcc, v0, v4
-; TONGA-NEXT:    v_mul_lo_u32 v4, v3, v2
+; TONGA-NEXT:    v_xor_b32_e32 v0, v7, v4
+; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v0
+; TONGA-NEXT:    v_sub_u32_e32 v0, vcc, v5, v0
+; TONGA-NEXT:    v_mul_lo_u32 v6, v3, v2
 ; TONGA-NEXT:    v_add_u32_e32 v5, vcc, 1, v3
-; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v4, v1
+; TONGA-NEXT:    v_xor_b32_e32 v4, v9, v8
+; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v6, v1
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v1, v2
-; TONGA-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v1
 ; TONGA-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; TONGA-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v3
+; TONGA-NEXT:    v_subrev_u32_e32 v5, vcc, v2, v1
+; TONGA-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v5, vcc, 1, v3
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
-; TONGA-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
-; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v6
-; TONGA-NEXT:    v_sub_u32_e32 v1, vcc, v1, v6
+; TONGA-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc
+; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v4
+; TONGA-NEXT:    v_sub_u32_e32 v1, vcc, v1, v4
 ; TONGA-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; TONGA-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_v2i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s6, -1

 ; GCN-NEXT:    buffer_load_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-NEXT:    buffer_load_dwordx4 v[4:7], off, s[4:7], 0 offset:16
 ; GCN-NEXT:    s_mov_b32 s2, 0x4f7ffffe
 ; GCN-NEXT:    s_mov_b32 s8, s0
 ; GCN-NEXT:    s_mov_b32 s9, s1
 ; GCN-NEXT:    s_waitcnt vmcnt(1)
 ; GCN-NEXT:    v_ashrrev_i32_e32 v8, 31, v0
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
-; GCN-NEXT:    v_ashrrev_i32_e32 v11, 31, v5
 ; GCN-NEXT:    v_ashrrev_i32_e32 v9, 31, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
-; GCN-NEXT:    v_xor_b32_e32 v5, v5, v11
-; GCN-NEXT:    v_xor_b32_e32 v15, v8, v9
-; GCN-NEXT:    v_xor_b32_e32 v4, v4, v9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v9, v5
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v8, v0
+; GCN-NEXT:    v_xor_b32_e32 v4, v4, v9
+; GCN-NEXT:    v_xor_b32_e32 v16, v8, v9
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v8
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v8, v4
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v9, v9
+; GCN-NEXT:    v_ashrrev_i32_e32 v11, 31, v5
 ; GCN-NEXT:    v_ashrrev_i32_e32 v13, 31, v6
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
+; GCN-NEXT:    v_ashrrev_i32_e32 v15, 31, v7
 ; GCN-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v8, v8
-; GCN-NEXT:    v_mul_f32_e32 v9, s2, v9
-; GCN-NEXT:    v_xor_b32_e32 v6, v6, v13
-; GCN-NEXT:    v_xor_b32_e32 v16, v10, v11
-; GCN-NEXT:    v_cvt_f32_u32_e32 v11, v6
-; GCN-NEXT:    v_cvt_u32_f32_e32 v9, v9
 ; GCN-NEXT:    v_ashrrev_i32_e32 v12, 31, v2
+; GCN-NEXT:    v_ashrrev_i32_e32 v14, 31, v3
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v13, v6
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v15, v7
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v12, v2
-; GCN-NEXT:    v_mul_f32_e32 v8, s2, v8
-; GCN-NEXT:    v_xor_b32_e32 v17, v12, v13
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v14, v3
+; GCN-NEXT:    v_xor_b32_e32 v5, v5, v11
+; GCN-NEXT:    v_xor_b32_e32 v6, v6, v13
+; GCN-NEXT:    v_xor_b32_e32 v7, v7, v15
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v8, v8
+; GCN-NEXT:    v_xor_b32_e32 v17, v10, v11
+; GCN-NEXT:    v_xor_b32_e32 v18, v12, v13
+; GCN-NEXT:    v_xor_b32_e32 v19, v14, v15
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v10
+; GCN-NEXT:    v_cvt_f32_u32_e32 v10, v5
 ; GCN-NEXT:    v_xor_b32_e32 v2, v2, v12
-; GCN-NEXT:    v_sub_i32_e32 v12, vcc, 0, v5
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v11, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v12, v9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v12, v6
+; GCN-NEXT:    v_xor_b32_e32 v3, v3, v14
+; GCN-NEXT:    v_cvt_f32_u32_e32 v14, v7
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v10, v10
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v12, v12
+; GCN-NEXT:    v_mul_f32_e32 v8, s2, v8
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v14, v14
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v8, v8
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v10, v1
-; GCN-NEXT:    v_xor_b32_e32 v1, v1, v10
-; GCN-NEXT:    v_sub_i32_e32 v10, vcc, 0, v4
-; GCN-NEXT:    v_mul_lo_u32 v10, v10, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v9, v12
-; GCN-NEXT:    v_mul_f32_e32 v11, s2, v11
-; GCN-NEXT:    v_cvt_u32_f32_e32 v11, v11
-; GCN-NEXT:    v_mul_hi_u32 v10, v8, v10
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v12, v9
-; GCN-NEXT:    v_sub_i32_e32 v12, vcc, 0, v6
-; GCN-NEXT:    v_mul_lo_u32 v12, v12, v11
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_sub_i32_e32 v9, vcc, 0, v4
+; GCN-NEXT:    v_mul_f32_e32 v10, s2, v10
+; GCN-NEXT:    v_mul_f32_e32 v12, s2, v12
+; GCN-NEXT:    v_mul_f32_e32 v14, s2, v14
+; GCN-NEXT:    v_mul_lo_u32 v9, v9, v8
+; GCN-NEXT:    v_cvt_u32_f32_e32 v10, v10
+; GCN-NEXT:    v_cvt_u32_f32_e32 v12, v12
+; GCN-NEXT:    v_cvt_u32_f32_e32 v14, v14
+; GCN-NEXT:    v_sub_i32_e32 v11, vcc, 0, v5
+; GCN-NEXT:    v_sub_i32_e32 v13, vcc, 0, v6
+; GCN-NEXT:    v_sub_i32_e32 v15, vcc, 0, v7
+; GCN-NEXT:    v_mul_lo_u32 v11, v11, v10
+; GCN-NEXT:    v_mul_lo_u32 v13, v13, v12
+; GCN-NEXT:    v_mul_lo_u32 v15, v15, v14
+; GCN-NEXT:    v_mul_hi_u32 v9, v8, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v10, v11
+; GCN-NEXT:    v_mul_hi_u32 v13, v12, v13
+; GCN-NEXT:    v_mul_hi_u32 v15, v14, v15
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_mul_hi_u32 v8, v0, v8
-; GCN-NEXT:    v_ashrrev_i32_e32 v14, 31, v7
-; GCN-NEXT:    v_mul_hi_u32 v12, v11, v12
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v14, v7
-; GCN-NEXT:    v_xor_b32_e32 v7, v7, v14
-; GCN-NEXT:    v_cvt_f32_u32_e32 v10, v7
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v8, v4
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v10
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v15, v14
 ; GCN-NEXT:    v_mul_hi_u32 v9, v1, v9
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v10, v10
-; GCN-NEXT:    v_mul_hi_u32 v11, v2, v11
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v10
+; GCN-NEXT:    v_mul_lo_u32 v12, v8, v4
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v11
+; GCN-NEXT:    v_mul_lo_u32 v14, v9, v5
+; GCN-NEXT:    v_mul_lo_u32 v15, v10, v6
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v12
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; GCN-NEXT:    v_sub_i32_e32 v12, vcc, v0, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v12, s[0:1]
+; GCN-NEXT:    v_mul_lo_u32 v12, v11, v7
+; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v14
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v15
+; GCN-NEXT:    v_add_i32_e32 v13, vcc, 1, v8
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v12
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v0, v9, v5
-; GCN-NEXT:    v_mul_f32_e32 v10, s2, v10
-; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v10
-; GCN-NEXT:    v_mul_lo_u32 v10, v11, v6
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v1, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, 1, v9
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[2:3], v0, v5
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v10
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v1, s[2:3]
-; GCN-NEXT:    v_sub_i32_e32 v9, vcc, v0, v5
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, 1, v11
+; GCN-NEXT:    v_add_i32_e32 v14, vcc, 1, v9
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[2:3], v1, v5
+; GCN-NEXT:    v_add_i32_e32 v15, vcc, 1, v10
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v2, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v8
-; GCN-NEXT:    v_cndmask_b32_e64 v10, v11, v10, s[4:5]
-; GCN-NEXT:    v_sub_i32_e32 v11, vcc, v2, v6
-; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v9, s[2:3]
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, 1, v1
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v5
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v1, v9, vcc
-; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v12, s[0:1]
-; GCN-NEXT:    v_xor_b32_e32 v1, v8, v15
-; GCN-NEXT:    v_xor_b32_e32 v5, v0, v16
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v1, v15
-; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v5, v16
-; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v7
-; GCN-NEXT:    v_mul_lo_u32 v5, v5, v4
-; GCN-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v9, v3
-; GCN-NEXT:    v_xor_b32_e32 v3, v3, v9
-; GCN-NEXT:    v_mul_hi_u32 v5, v4, v5
-; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v11, s[4:5]
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, 1, v10
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v11
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[6:7], v3, v7
+; GCN-NEXT:    v_cndmask_b32_e64 v8, v8, v13, s[0:1]
+; GCN-NEXT:    v_sub_i32_e32 v13, vcc, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v9, v9, v14, s[2:3]
+; GCN-NEXT:    v_sub_i32_e32 v14, vcc, v1, v5
+; GCN-NEXT:    v_cndmask_b32_e64 v10, v10, v15, s[4:5]
+; GCN-NEXT:    v_sub_i32_e32 v15, vcc, v2, v6
+; GCN-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[6:7]
+; GCN-NEXT:    v_sub_i32_e32 v12, vcc, v3, v7
+; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v13, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v14, s[2:3]
+; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v15, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v12, s[6:7]
+; GCN-NEXT:    v_add_i32_e32 v13, vcc, 1, v8
+; GCN-NEXT:    v_add_i32_e32 v14, vcc, 1, v9
+; GCN-NEXT:    v_add_i32_e32 v15, vcc, 1, v10
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, 1, v11
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v0, v4
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v8, v13, vcc
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v5
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v9, v14, vcc
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v2, v6
-; GCN-NEXT:    v_cndmask_b32_e32 v2, v10, v8, vcc
-; GCN-NEXT:    v_xor_b32_e32 v2, v2, v17
-; GCN-NEXT:    v_mul_lo_u32 v5, v4, v7
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v17
-; GCN-NEXT:    v_xor_b32_e32 v6, v9, v14
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v3, v7
-; GCN-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; GCN-NEXT:    v_sub_i32_e32 v5, vcc, v3, v7
-; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, 1, v4
+; GCN-NEXT:    v_cndmask_b32_e32 v2, v10, v15, vcc
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v7
-; GCN-NEXT:    v_cndmask_b32_e32 v3, v4, v5, vcc
-; GCN-NEXT:    v_xor_b32_e32 v3, v3, v6
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v6
+; GCN-NEXT:    v_cndmask_b32_e32 v3, v11, v12, vcc
+; GCN-NEXT:    v_xor_b32_e32 v0, v0, v16
+; GCN-NEXT:    v_xor_b32_e32 v1, v1, v17
+; GCN-NEXT:    v_xor_b32_e32 v2, v2, v18
+; GCN-NEXT:    v_xor_b32_e32 v3, v3, v19
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v16
+; GCN-NEXT:    v_sub_i32_e32 v1, vcc, v1, v17
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, v2, v18
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, v3, v19
 ; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; TONGA-LABEL: sdiv_v4i32:
 ; TONGA:       ; %bb.0:
 ; TONGA-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s7, 0xf000
 ; TONGA-NEXT:    s_mov_b32 s6, -1
 ; TONGA-NEXT:    s_mov_b32 s2, s6
 ; TONGA-NEXT:    s_mov_b32 s3, s7
 ; TONGA-NEXT:    s_waitcnt lgkmcnt(0)
 ; TONGA-NEXT:    s_mov_b32 s0, s10
 ; TONGA-NEXT:    s_mov_b32 s1, s11
 ; TONGA-NEXT:    buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; TONGA-NEXT:    s_mov_b32 s10, 0x4f7ffffe
-; TONGA-NEXT:    s_mov_b32 s4, s8
+; TONGA-NEXT:    s_mov_b32 s4, 0x4f7ffffe
 ; TONGA-NEXT:    s_mov_b32 s5, s9
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v8, 31, v0
 ; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v8, v0
 ; TONGA-NEXT:    v_xor_b32_e32 v0, v0, v8
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v4, v0
+; TONGA-NEXT:    v_ashrrev_i32_e32 v12, 31, v1
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v14, 31, v2
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v4, v4
-; TONGA-NEXT:    v_mul_f32_e32 v4, s10, v4
+; TONGA-NEXT:    v_mul_f32_e32 v4, s4, v4
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v9, v4
 ; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, 0, v0
 ; TONGA-NEXT:    v_mul_lo_u32 v10, v4, v9
 ; TONGA-NEXT:    buffer_load_dwordx4 v[4:7], off, s[0:3], 0
 ; TONGA-NEXT:    v_mul_hi_u32 v10, v9, v10
 ; TONGA-NEXT:    v_add_u32_e32 v9, vcc, v10, v9
-; TONGA-NEXT:    v_ashrrev_i32_e32 v10, 31, v1
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v11, 31, v4
 ; TONGA-NEXT:    v_add_u32_e32 v4, vcc, v11, v4
 ; TONGA-NEXT:    v_xor_b32_e32 v4, v4, v11
 ; TONGA-NEXT:    v_mul_hi_u32 v9, v4, v9
-; TONGA-NEXT:    v_xor_b32_e32 v8, v11, v8
-; TONGA-NEXT:    v_mul_lo_u32 v12, v9, v0
+; TONGA-NEXT:    v_mul_lo_u32 v10, v9, v0
 ; TONGA-NEXT:    v_add_u32_e32 v13, vcc, 1, v9
-; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v4, v12
+; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v4, v10
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v0
-; TONGA-NEXT:    v_sub_u32_e32 v12, vcc, v4, v0
+; TONGA-NEXT:    v_sub_u32_e32 v10, vcc, v4, v0
 ; TONGA-NEXT:    v_cndmask_b32_e64 v9, v9, v13, s[0:1]
-; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v12, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v12, vcc, 1, v9
+; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v10, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v10, vcc, 1, v9
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v10, v1
-; TONGA-NEXT:    v_xor_b32_e32 v1, v0, v10
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v12, v1
+; TONGA-NEXT:    v_xor_b32_e32 v1, v0, v12
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v0, v1
-; TONGA-NEXT:    v_sub_u32_e32 v13, vcc, 0, v1
-; TONGA-NEXT:    v_ashrrev_i32_e32 v4, 31, v5
-; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v4, v5
+; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, 0, v1
+; TONGA-NEXT:    v_ashrrev_i32_e32 v13, 31, v5
+; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v13, v5
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v4
-; TONGA-NEXT:    v_cndmask_b32_e64 v9, v9, v12, s[0:1]
-; TONGA-NEXT:    v_xor_b32_e32 v4, v4, v10
-; TONGA-NEXT:    v_mul_f32_e32 v0, s10, v0
+; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v13
+; TONGA-NEXT:    v_mul_f32_e32 v0, s4, v0
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v0, v0
+; TONGA-NEXT:    v_mul_lo_u32 v4, v4, v0
+; TONGA-NEXT:    v_mul_hi_u32 v4, v0, v4
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
+; TONGA-NEXT:    v_mul_hi_u32 v4, v5, v0
+; TONGA-NEXT:    v_xor_b32_e32 v0, v11, v8
+; TONGA-NEXT:    v_cndmask_b32_e64 v8, v9, v10, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v8, v8, v0
+; TONGA-NEXT:    v_mul_lo_u32 v9, v4, v1
+; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v0, v8
+; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v4
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v10, 31, v6
-; TONGA-NEXT:    v_mul_lo_u32 v13, v13, v0
-; TONGA-NEXT:    v_mul_hi_u32 v11, v0, v13
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v11, v0
-; TONGA-NEXT:    v_mul_hi_u32 v11, v5, v0
-; TONGA-NEXT:    v_xor_b32_e32 v0, v9, v8
-; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v8, v0
-; TONGA-NEXT:    v_mul_lo_u32 v8, v11, v1
-; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v11
-; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, v5, v8
+; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, v5, v9
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v5, v1
-; TONGA-NEXT:    v_cndmask_b32_e64 v8, v11, v9, s[0:1]
-; TONGA-NEXT:    v_sub_u32_e32 v9, vcc, v5, v1
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v8
+; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v8, s[0:1]
+; TONGA-NEXT:    v_sub_u32_e32 v8, vcc, v5, v1
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v4
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
 ; TONGA-NEXT:    v_add_u32_e32 v1, vcc, v14, v2
 ; TONGA-NEXT:    v_xor_b32_e32 v2, v1, v14
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v1, v2
 ; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, 0, v2
-; TONGA-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[0:1]
-; TONGA-NEXT:    v_ashrrev_i32_e32 v9, 31, v3
+; TONGA-NEXT:    v_xor_b32_e32 v9, v13, v12
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; TONGA-NEXT:    v_mul_f32_e32 v1, s10, v1
+; TONGA-NEXT:    v_mul_f32_e32 v1, s4, v1
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v1, v1
 ; TONGA-NEXT:    v_mul_lo_u32 v5, v5, v1
 ; TONGA-NEXT:    v_mul_hi_u32 v5, v1, v5
 ; TONGA-NEXT:    v_add_u32_e32 v1, vcc, v5, v1
 ; TONGA-NEXT:    v_add_u32_e32 v5, vcc, v10, v6
 ; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v10
 ; TONGA-NEXT:    v_mul_hi_u32 v6, v5, v1
-; TONGA-NEXT:    v_xor_b32_e32 v1, v8, v4
-; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v4, v1
-; TONGA-NEXT:    v_xor_b32_e32 v10, v10, v14
+; TONGA-NEXT:    v_cndmask_b32_e64 v1, v4, v8, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v9
+; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v9, v1
 ; TONGA-NEXT:    v_mul_lo_u32 v4, v6, v2
-; TONGA-NEXT:    v_add_u32_e32 v8, vcc, 1, v6
+; TONGA-NEXT:    v_add_u32_e32 v9, vcc, 1, v6
+; TONGA-NEXT:    v_ashrrev_i32_e32 v8, 31, v3
 ; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v5, v4
 ; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v2
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v8, s[0:1]
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v9, s[0:1]
 ; TONGA-NEXT:    v_sub_u32_e32 v6, vcc, v4, v2
 ; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[0:1]
 ; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v5
 ; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
 ; TONGA-NEXT:    s_mov_b64 s[0:1], vcc
-; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v9, v3
-; TONGA-NEXT:    v_xor_b32_e32 v3, v2, v9
+; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v8, v3
+; TONGA-NEXT:    v_xor_b32_e32 v3, v2, v8
 ; TONGA-NEXT:    v_cvt_f32_u32_e32 v2, v3
-; TONGA-NEXT:    v_sub_u32_e32 v8, vcc, 0, v3
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[0:1]
-; TONGA-NEXT:    v_ashrrev_i32_e32 v4, 31, v7
+; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, 0, v3
+; TONGA-NEXT:    v_ashrrev_i32_e32 v9, 31, v7
+; TONGA-NEXT:    v_add_u32_e32 v7, vcc, v9, v7
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; TONGA-NEXT:    v_add_u32_e32 v7, vcc, v4, v7
-; TONGA-NEXT:    v_xor_b32_e32 v9, v4, v9
-; TONGA-NEXT:    v_xor_b32_e32 v4, v7, v4
-; TONGA-NEXT:    v_mul_f32_e32 v2, s10, v2
+; TONGA-NEXT:    v_xor_b32_e32 v7, v7, v9
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v5, v6, s[0:1]
+; TONGA-NEXT:    v_xor_b32_e32 v8, v9, v8
+; TONGA-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; TONGA-NEXT:    v_mul_lo_u32 v8, v8, v2
-; TONGA-NEXT:    v_mul_hi_u32 v6, v2, v8
-; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v6, v2
-; TONGA-NEXT:    v_mul_hi_u32 v6, v4, v2
-; TONGA-NEXT:    v_xor_b32_e32 v2, v5, v10
-; TONGA-NEXT:    v_subrev_u32_e32 v2, vcc, v10, v2
-; TONGA-NEXT:    v_mul_lo_u32 v5, v6, v3
-; TONGA-NEXT:    v_add_u32_e32 v7, vcc, 1, v6
-; TONGA-NEXT:    v_sub_u32_e32 v4, vcc, v4, v5
-; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v3
-; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v7, s[0:1]
-; TONGA-NEXT:    v_sub_u32_e32 v6, vcc, v4, v3
-; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v6, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v5
-; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v3
-; TONGA-NEXT:    v_cndmask_b32_e32 v3, v5, v6, vcc
-; TONGA-NEXT:    v_xor_b32_e32 v3, v3, v9
-; TONGA-NEXT:    v_subrev_u32_e32 v3, vcc, v9, v3
+; TONGA-NEXT:    s_mov_b32 s4, s8
+; TONGA-NEXT:    v_mul_lo_u32 v4, v4, v2
+; TONGA-NEXT:    v_mul_hi_u32 v4, v2, v4
+; TONGA-NEXT:    v_add_u32_e32 v2, vcc, v4, v2
+; TONGA-NEXT:    v_mul_hi_u32 v4, v7, v2
+; TONGA-NEXT:    v_xor_b32_e32 v2, v10, v14
+; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v2
+; TONGA-NEXT:    v_subrev_u32_e32 v2, vcc, v2, v5
+; TONGA-NEXT:    v_mul_lo_u32 v6, v4, v3
+; TONGA-NEXT:    v_add_u32_e32 v5, vcc, 1, v4
+; TONGA-NEXT:    v_sub_u32_e32 v6, vcc, v7, v6
+; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v6, v3
+; TONGA-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]
+; TONGA-NEXT:    v_sub_u32_e32 v5, vcc, v6, v3
+; TONGA-NEXT:    v_cndmask_b32_e64 v5, v6, v5, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v6, vcc, 1, v4
+; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v3
+; TONGA-NEXT:    v_cndmask_b32_e32 v3, v4, v6, vcc
+; TONGA-NEXT:    v_xor_b32_e32 v3, v3, v8
+; TONGA-NEXT:    v_subrev_u32_e32 v3, vcc, v8, v3
 ; TONGA-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; TONGA-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: sdiv_v4i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_mov_b32 s11, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s10, -1

 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v2, v1
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
 ; GCN-NEXT:    v_mul_f32_e32 v1, v3, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
-; GCN-NEXT:    v_mad_f32 v3, -v1, v2, v3
-; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v1
+; GCN-NEXT:    v_mad_f32 v1, -v1, v2, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 8
 ; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; TONGA-LABEL: v_sdiv_i8:
 ; TONGA:       ; %bb.0:
 ; TONGA-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s3, 0xf000

 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_cvt_f32_i32_e32 v2, v1
 ; TONGA-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; TONGA-NEXT:    v_or_b32_e32 v0, 1, v0
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v4, v2
 ; TONGA-NEXT:    v_mul_f32_e32 v1, v3, v4
 ; TONGA-NEXT:    v_trunc_f32_e32 v1, v1
-; TONGA-NEXT:    v_mad_f32 v3, -v1, v2, v3
-; TONGA-NEXT:    v_cvt_i32_f32_e32 v1, v1
-; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v2|
+; TONGA-NEXT:    v_cvt_i32_f32_e32 v4, v1
+; TONGA-NEXT:    v_mad_f32 v1, -v1, v2, v3
+; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v2|
 ; TONGA-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v1, v0
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 8
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; TONGA-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: v_sdiv_i8:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000

 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
 ; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v3, v1
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 23
 ; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; TONGA-LABEL: v_sdiv_i23:
 ; TONGA:       ; %bb.0:
 ; TONGA-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s3, 0xf000

 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 23
 ; TONGA-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; TONGA-NEXT:    v_xor_b32_e32 v0, v0, v2
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v4, v3
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; TONGA-NEXT:    v_or_b32_e32 v0, 1, v0
 ; TONGA-NEXT:    v_mul_f32_e32 v2, v1, v4
 ; TONGA-NEXT:    v_trunc_f32_e32 v2, v2
+; TONGA-NEXT:    v_cvt_i32_f32_e32 v4, v2
 ; TONGA-NEXT:    v_mad_f32 v1, -v2, v3, v1
-; TONGA-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; TONGA-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v2, v0
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 23
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; TONGA-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: v_sdiv_i23:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000

 }
 
 define amdgpu_kernel void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
 ; GCN-LABEL: v_sdiv_i24:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    s_mov_b32 s10, s2
-; GCN-NEXT:    s_mov_b32 s11, s3
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s8, s6
-; GCN-NEXT:    s_mov_b32 s9, s7
-; GCN-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NEXT:    buffer_load_sbyte v1, off, s[8:11], 0 offset:2
-; GCN-NEXT:    buffer_load_ushort v2, off, s[8:11], 0 offset:4
-; GCN-NEXT:    buffer_load_sbyte v3, off, s[8:11], 0 offset:6
 ; GCN-NEXT:    s_mov_b32 s0, s4
 ; GCN-NEXT:    s_mov_b32 s1, s5
+; GCN-NEXT:    s_mov_b32 s4, s6
+; GCN-NEXT:    s_mov_b32 s5, s7
+; GCN-NEXT:    s_mov_b32 s6, s2
+; GCN-NEXT:    s_mov_b32 s7, s3
+; GCN-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
+; GCN-NEXT:    buffer_load_sbyte v1, off, s[4:7], 0 offset:2
+; GCN-NEXT:    buffer_load_ushort v2, off, s[4:7], 0 offset:4
+; GCN-NEXT:    buffer_load_sbyte v3, off, s[4:7], 0 offset:6
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    v_lshlrev_b32_e32 v4, 16, v3
 ; GCN-NEXT:    v_or_b32_e32 v2, v2, v4
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v2, v2
 ; GCN-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
 ; GCN-NEXT:    v_or_b32_e32 v0, v0, v4
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v0, v0
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v2
 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v3
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 30, v1
 ; GCN-NEXT:    v_or_b32_e32 v1, 1, v1
 ; GCN-NEXT:    v_mul_f32_e32 v3, v0, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v3
 ; GCN-NEXT:    v_mad_f32 v0, -v3, v2, v0
-; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, |v2|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; TONGA-LABEL: v_sdiv_i24:
 ; TONGA:       ; %bb.0:
 ; TONGA-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; TONGA-NEXT:    s_mov_b32 s3, 0xf000
 ; TONGA-NEXT:    s_mov_b32 s2, -1
-; TONGA-NEXT:    s_mov_b32 s10, s2
-; TONGA-NEXT:    s_mov_b32 s11, s3
 ; TONGA-NEXT:    s_waitcnt lgkmcnt(0)
-; TONGA-NEXT:    s_mov_b32 s8, s6
-; TONGA-NEXT:    s_mov_b32 s9, s7
-; TONGA-NEXT:    buffer_load_ushort v0, off, s[8:11], 0
-; TONGA-NEXT:    buffer_load_sbyte v1, off, s[8:11], 0 offset:2
-; TONGA-NEXT:    buffer_load_ushort v2, off, s[8:11], 0 offset:4
-; TONGA-NEXT:    buffer_load_sbyte v3, off, s[8:11], 0 offset:6
 ; TONGA-NEXT:    s_mov_b32 s0, s4
 ; TONGA-NEXT:    s_mov_b32 s1, s5
+; TONGA-NEXT:    s_mov_b32 s4, s6
+; TONGA-NEXT:    s_mov_b32 s5, s7
+; TONGA-NEXT:    s_mov_b32 s6, s2
+; TONGA-NEXT:    s_mov_b32 s7, s3
+; TONGA-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
+; TONGA-NEXT:    buffer_load_sbyte v1, off, s[4:7], 0 offset:2
+; TONGA-NEXT:    buffer_load_ushort v2, off, s[4:7], 0 offset:4
+; TONGA-NEXT:    buffer_load_sbyte v3, off, s[4:7], 0 offset:6
 ; TONGA-NEXT:    s_waitcnt vmcnt(0)
 ; TONGA-NEXT:    v_lshlrev_b32_e32 v4, 16, v3
 ; TONGA-NEXT:    v_or_b32_e32 v2, v2, v4
 ; TONGA-NEXT:    v_cvt_f32_i32_e32 v2, v2
 ; TONGA-NEXT:    v_lshlrev_b32_e32 v4, 16, v1
 ; TONGA-NEXT:    v_or_b32_e32 v0, v0, v4
 ; TONGA-NEXT:    v_cvt_f32_i32_e32 v0, v0
 ; TONGA-NEXT:    v_rcp_iflag_f32_e32 v4, v2
 ; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v3
 ; TONGA-NEXT:    v_ashrrev_i32_e32 v1, 30, v1
 ; TONGA-NEXT:    v_or_b32_e32 v1, 1, v1
 ; TONGA-NEXT:    v_mul_f32_e32 v3, v0, v4
 ; TONGA-NEXT:    v_trunc_f32_e32 v3, v3
+; TONGA-NEXT:    v_cvt_i32_f32_e32 v4, v3
 ; TONGA-NEXT:    v_mad_f32 v0, -v3, v2, v0
-; TONGA-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; TONGA-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, |v2|
 ; TONGA-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
+; TONGA-NEXT:    v_add_u32_e32 v0, vcc, v4, v0
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; TONGA-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: v_sdiv_i24:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000

 ; GCN-NEXT:    v_xor_b32_e32 v5, v5, v0
 ; GCN-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v3, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v1, v3, v2
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v3
-; GCN-NEXT:    v_subrev_i32_e32 v1, vcc, v1, v5
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v1, v2
-; GCN-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v3
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
-; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, 1, v3
+; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[0:1]
+; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v2, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, 1, v1
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v2
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v1, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 25
 ; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; TONGA-LABEL: v_sdiv_i25:
 ; TONGA:       ; %bb.0:

 ; TONGA-NEXT:    v_xor_b32_e32 v5, v5, v0
 ; TONGA-NEXT:    v_xor_b32_e32 v0, v0, v1
 ; TONGA-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
 ; TONGA-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; TONGA-NEXT:    v_mul_lo_u32 v4, v4, v3
 ; TONGA-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; TONGA-NEXT:    v_add_u32_e32 v3, vcc, v4, v3
 ; TONGA-NEXT:    v_mul_hi_u32 v3, v5, v3
-; TONGA-NEXT:    v_mul_lo_u32 v1, v3, v2
-; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v3
-; TONGA-NEXT:    v_subrev_u32_e32 v1, vcc, v1, v5
-; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v1, v2
-; TONGA-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; TONGA-NEXT:    v_subrev_u32_e32 v4, vcc, v2, v1
-; TONGA-NEXT:    v_cndmask_b32_e64 v1, v1, v4, s[0:1]
-; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v3
-; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
-; TONGA-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
+; TONGA-NEXT:    v_mul_lo_u32 v4, v3, v2
+; TONGA-NEXT:    v_add_u32_e32 v1, vcc, 1, v3
+; TONGA-NEXT:    v_subrev_u32_e32 v4, vcc, v4, v5
+; TONGA-NEXT:    v_cmp_ge_u32_e64 s[0:1], v4, v2
+; TONGA-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s[0:1]
+; TONGA-NEXT:    v_subrev_u32_e32 v3, vcc, v2, v4
+; TONGA-NEXT:    v_cndmask_b32_e64 v3, v4, v3, s[0:1]
+; TONGA-NEXT:    v_add_u32_e32 v4, vcc, 1, v1
+; TONGA-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v2
+; TONGA-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; TONGA-NEXT:    v_xor_b32_e32 v1, v1, v0
 ; TONGA-NEXT:    v_subrev_u32_e32 v0, vcc, v0, v1
 ; TONGA-NEXT:    v_bfe_i32 v0, v0, 0, 25
 ; TONGA-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; TONGA-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: v_sdiv_i25:
 ; GFX9:       ; %bb.0:

llvm/test/CodeGen/AMDGPU/sdiv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
 
 define amdgpu_kernel void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_sdiv:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i32 s12, s3, 31
-; GCN-NEXT:    s_add_u32 s2, s2, s12
-; GCN-NEXT:    s_mov_b32 s13, s12
-; GCN-NEXT:    s_addc_u32 s3, s3, s12
-; GCN-NEXT:    s_xor_b64 s[2:3], s[2:3], s[12:13]
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT:    s_sub_u32 s4, 0, s2
-; GCN-NEXT:    s_subb_u32 s5, 0, s3
-; GCN-NEXT:    s_ashr_i32 s14, s11, 31
+; GCN-NEXT:    s_ashr_i32 s8, s3, 31
+; GCN-NEXT:    s_add_u32 s2, s2, s8
+; GCN-NEXT:    s_mov_b32 s9, s8
+; GCN-NEXT:    s_addc_u32 s3, s3, s8
+; GCN-NEXT:    s_xor_b64 s[10:11], s[2:3], s[8:9]
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s10
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s11
+; GCN-NEXT:    s_sub_u32 s12, 0, s10
+; GCN-NEXT:    s_subb_u32 s4, 0, s11
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s15, s14
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s9
+; GCN-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s12, v0
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s12, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s12, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, s12, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
 ; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
-; GCN-NEXT:    s_add_u32 s0, s10, s14
-; GCN-NEXT:    s_addc_u32 s1, s11, s14
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    s_xor_b64 s[10:11], s[0:1], s[14:15]
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_ashr_i32 s2, s7, 31
+; GCN-NEXT:    s_add_u32 s0, s6, s2
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
+; GCN-NEXT:    s_addc_u32 s1, s7, s2
+; GCN-NEXT:    s_mov_b32 s3, s2
+; GCN-NEXT:    s_xor_b64 s[12:13], s[0:1], s[2:3]
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s11, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s11, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT:    s_mov_b32 s4, s8
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
-; GCN-NEXT:    v_mov_b32_e32 v5, s3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
+; GCN-NEXT:    v_mov_b32_e32 v5, s11
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v3, s10, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s13, v2
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s12, v3
 ; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s10, v3
 ; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
 ; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
 ; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v6, s11
+; GCN-NEXT:    v_mov_b32_e32 v6, s13
 ; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s11, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s11, v2
 ; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    s_xor_b64 s[0:1], s[14:15], s[12:13]
+; GCN-NEXT:    s_xor_b64 s[0:1], s[2:3], s[8:9]
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_xor_b32_e32 v1, s1, v1
 ; GCN-NEXT:    v_mov_b32_e32 v2, s1
 ; GCN-NEXT:    v_subrev_i32_e32 v0, vcc, s0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm

 ; GCN-NEXT:    v_mul_f32_e32 v6, 0x2f800000, v5
 ; GCN-NEXT:    v_trunc_f32_e32 v6, v6
 ; GCN-NEXT:    v_mac_f32_e32 v5, 0xcf800000, v6
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v6, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v6
 ; GCN-NEXT:    v_mul_lo_u32 v11, v8, v5
+; GCN-NEXT:    v_mul_lo_u32 v12, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GCN-NEXT:    v_mul_lo_u32 v10, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v11, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v13, v5, v10
+; GCN-NEXT:    v_mul_lo_u32 v10, v5, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v5, v12
+; GCN-NEXT:    v_mul_hi_u32 v13, v5, v9
 ; GCN-NEXT:    v_mul_hi_u32 v16, v6, v9
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v9
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
-; GCN-NEXT:    v_mul_lo_u32 v13, v6, v10
-; GCN-NEXT:    v_mul_hi_u32 v10, v6, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v11, vcc
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v12, v13
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v10, vcc
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v15, v13, vcc
+; GCN-NEXT:    v_mul_lo_u32 v13, v6, v12
+; GCN-NEXT:    v_mul_hi_u32 v12, v6, v12
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v13
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v11, v12, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v16, v14, vcc
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_add_i32_e64 v5, s[4:5], v5, v9
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v11, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v9, vcc, v6, v10, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v11, v7, v9
 ; GCN-NEXT:    v_mul_hi_u32 v12, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v8, v8, v5
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v5
 ; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v11, v8
-; GCN-NEXT:    v_mul_lo_u32 v13, v5, v8
-; GCN-NEXT:    v_mul_hi_u32 v16, v5, v7
-; GCN-NEXT:    v_mul_hi_u32 v17, v5, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v9, v7
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v8
+; GCN-NEXT:    v_mul_hi_u32 v13, v5, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v5, v8
+; GCN-NEXT:    v_mul_hi_u32 v17, v9, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v9, v7
-; GCN-NEXT:    v_add_i32_e32 v13, vcc, v16, v13
+; GCN-NEXT:    v_add_i32_e32 v12, vcc, v13, v12
 ; GCN-NEXT:    v_mul_hi_u32 v11, v9, v8
-; GCN-NEXT:    v_addc_u32_e32 v16, vcc, v15, v17, vcc
+; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v15, v16, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v9, v8
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v13, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v16, v12, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v12, v7
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v13, v17, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v14, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v15, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v10
 ; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v6, v8, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v6, vcc
 ; GCN-NEXT:    v_ashrrev_i32_e32 v7, 31, v1

 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v14, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v2, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v5
+; GCN-NEXT:    v_mul_lo_u32 v11, v2, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
-; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_sub_i32_e32 v10, vcc, v1, v8
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
-; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v10, v3, vcc
+; GCN-NEXT:    v_sub_i32_e32 v9, vcc, v1, v8
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v11
+; GCN-NEXT:    v_subb_u32_e64 v9, s[4:5], v9, v3, vcc
 ; GCN-NEXT:    v_sub_i32_e64 v10, s[4:5], v0, v2
 ; GCN-NEXT:    v_subbrev_u32_e64 v9, s[4:5], 0, v9, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v9, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v10, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v9, v3
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v8, vcc

 ; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v2, v0
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
 ; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v3, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v3, -v2, v1, v3
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
 ; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_sdiv24_48:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
; GCN-IR-NEXT:    s_endpgm
   store i48 %result, i48 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_sdiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_sdiv_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_ashr_i32 s2, s7, 31
 ; GCN-NEXT:    s_add_u32 s0, s6, s2
 ; GCN-NEXT:    s_addc_u32 s1, s7, s2
 ; GCN-NEXT:    s_mov_b32 s3, s2
 ; GCN-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GCN-NEXT:    s_sub_u32 s3, 0, s8
-; GCN-NEXT:    s_subb_u32 s10, 0, s9
+; GCN-NEXT:    s_subb_u32 s6, 0, s9
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s3, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s3, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s6, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s3, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s3, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s10, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s3, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s3, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s6, v0
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, 24, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT:    v_mul_hi_u32 v5, 24, v2
+; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, s8, v1
 ; GCN-NEXT:    v_mul_hi_u32 v3, s8, v0
 ; GCN-NEXT:    v_mul_lo_u32 v4, s9, v0
 ; GCN-NEXT:    v_mov_b32_e32 v5, s9
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2

 ; GCN-NEXT:    v_rcp_f32_e32 v3, v3
 ; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
+; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v3
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v9
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v13, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v9, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
 ; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
-; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
-; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v13, v14, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v11, v15, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v4, 24
 ; GCN-NEXT:    v_mul_hi_u32 v3, 24, v3
 ; GCN-NEXT:    v_mul_hi_u32 v6, 24, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v13, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, 0, v3
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
-; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 24, v6
-; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
-; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
-; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
+; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v5
+; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 24, v8
+; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
+; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v7, v0
+; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v9, v8, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
 ; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v11, v9, s[4:5]
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_sdiv_k_num_i64:

 ; GCN-NEXT:    v_rcp_f32_e32 v3, v3
 ; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v3
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v3
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
 ; GCN-NEXT:    v_mac_f32_e32 v3, 0xcf800000, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, v5, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v3
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_mul_hi_u32 v8, v5, v3
+; GCN-NEXT:    v_mul_lo_u32 v7, v5, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v3
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v9
 ; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v7
 ; GCN-NEXT:    v_mul_hi_u32 v14, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v13, v9, vcc
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v10, v11
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v9, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v13, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v9, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
 ; GCN-NEXT:    v_add_i32_e64 v3, s[4:5], v3, v7
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v9, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v7, vcc, v4, v8, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v9, v5, v7
 ; GCN-NEXT:    v_mul_hi_u32 v10, v5, v3
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v3
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v3
 ; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v6
-; GCN-NEXT:    v_mul_lo_u32 v11, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v14, v3, v5
-; GCN-NEXT:    v_mul_hi_u32 v15, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v7, v5
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v7, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v7, v5
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v14, v11
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_mul_hi_u32 v9, v7, v6
-; GCN-NEXT:    v_addc_u32_e32 v14, vcc, v13, v15, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v13, v14, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v11, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v10, vcc
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v10, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v11, v15, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v8
 ; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v4, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v3, s4, v3
 ; GCN-NEXT:    v_mul_hi_u32 v5, s4, v4
 ; GCN-NEXT:    v_lshlrev_b32_e32 v6, 15, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v13, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, 0, v3
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v4, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_lo_u32 v7, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_sub_i32_e32 v7, vcc, 0, v5
-; GCN-NEXT:    v_sub_i32_e32 v6, vcc, s4, v6
-; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v1, vcc
-; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v6, v0
-; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v1
+; GCN-NEXT:    v_sub_i32_e32 v6, vcc, 0, v5
+; GCN-NEXT:    v_sub_i32_e32 v7, vcc, s4, v8
+; GCN-NEXT:    v_subb_u32_e64 v6, s[4:5], v6, v1, vcc
+; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v7, v0
+; GCN-NEXT:    v_subbrev_u32_e64 v6, s[4:5], 0, v6, s[4:5]
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v9, v8, s[4:5]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v6, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v9, v8, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 2, v3
 ; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v4, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v10, s[4:5], 1, v3
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v11, s[4:5], 0, v4, s[4:5]
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v6
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v7, v11, v9, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v6, v11, v9, s[4:5]
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v6, v0
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v7, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v9, v0, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v10, v8, s[4:5]
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v7, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v4, v6, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v3, v0, v2
 ; GCN-NEXT:    v_xor_b32_e32 v0, v1, v2
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v3, v2, vcc
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_sdiv_pow2_k_num_i64:

 ; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_sdiv24_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %x.shr = ashr i64 %x, 40
   %result = sdiv i64 24, %x.shr
   ret i64 %result
 }
 
 define i64 @v_test_sdiv24_pow2_k_num_i64(i64 %x) {
 ; GCN-LABEL: v_test_sdiv24_pow2_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-NEXT:    s_mov_b32 s4, 0x47000000
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_sdiv24_pow2_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v3, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %x.shr = ashr i64 %x, 40
   %result = sdiv i64 32768, %x.shr
   ret i64 %result
 }
 

 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v0, 30, v0
 ; GCN-IR-NEXT:    v_or_b32_e32 v0, 1, v0
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38000000, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, s4, v1
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v0, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %x.shr = ashr i64 %x, 40
   %result = sdiv i64 %x.shr, 32768
   ret i64 %result
 }

llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll

 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}shl_base_atomicrmw_global_atomic_csub_ptr:
 ; GCN-DAG: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5]
 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 43
 ; GCN: v_add_co_u32_e64 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4
-; GCN: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo
-; GCN: global_atomic_csub v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]], off offset:512 glc
+; GCN-DAG: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo
+; GCN-DAG: global_atomic_csub v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]], off offset:512 glc
 ; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[EXTRA_LO]]:[[EXTRA_HI]]{{\]}}
 define i32 @shl_base_atomicrmw_global_atomic_csub_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
   %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
   %cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64
   %shl = shl i64 %cast, 2
   %castback = inttoptr i64 %shl to i32 addrspace(1)*
   %val = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %castback, i32 43)
   store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4
   ret i32 %val
 }
 
 declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0
 
 attributes #0 = { argmemonly nounwind }

llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

 ; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0
 ; SI-NEXT:    buffer_store_dword v0, v[1:2], s[0:3], 0 addr64
 ; SI-NEXT:    s_endpgm
 ;
 ; VI-LABEL: v_test_i16_x_sub_64_zext_to_i32:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; VI-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
-; VI-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
+; VI-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; VI-NEXT:    s_waitcnt lgkmcnt(0)
-; VI-NEXT:    v_mov_b32_e32 v2, s3
-; VI-NEXT:    v_add_u32_e32 v1, vcc, s2, v1
-; VI-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; VI-NEXT:    v_add_u32_e32 v3, vcc, s0, v0
-; VI-NEXT:    flat_load_ushort v0, v[1:2]
-; VI-NEXT:    v_mov_b32_e32 v4, s1
-; VI-NEXT:    v_addc_u32_e32 v4, vcc, 0, v4, vcc
+; VI-NEXT:    v_mov_b32_e32 v3, s3
+; VI-NEXT:    v_add_u32_e32 v0, vcc, s2, v1
+; VI-NEXT:    v_addc_u32_e32 v1, vcc, 0, v3, vcc
+; VI-NEXT:    flat_load_ushort v0, v[0:1]
+; VI-NEXT:    v_mov_b32_e32 v3, s1
+; VI-NEXT:    v_add_u32_e32 v2, vcc, s0, v2
+; VI-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    v_subrev_u16_e32 v0, 64, v0
-; VI-NEXT:    flat_store_dword v[3:4], v0
+; VI-NEXT:    flat_store_dword v[2:3], v0
 ; VI-NEXT:    s_endpgm
 ;
 ; GFX9-LABEL: v_test_i16_x_sub_64_zext_to_i32:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
 ; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/srem64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
 
 define amdgpu_kernel void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_srem:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT:    s_sub_u32 s2, 0, s12
-; GCN-NEXT:    s_subb_u32 s3, 0, s13
-; GCN-NEXT:    s_mov_b32 s4, s8
+; GCN-NEXT:    s_sub_u32 s8, 0, s12
+; GCN-NEXT:    s_subb_u32 s4, 0, s13
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s5, s9
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s8, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s8, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s7, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s13
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
 ; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
 ; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
 ; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
 ; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
 ; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v5, s11
+; GCN-NEXT:    v_mov_b32_e32 v5, s7
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
 ; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-IR-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[6:7], 0

 ; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v5, v5
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
+; GCN-NEXT:    v_mul_lo_u32 v11, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v8
+; GCN-NEXT:    v_mul_hi_u32 v10, v4, v11
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v11
+; GCN-NEXT:    v_mul_hi_u32 v11, v5, v11
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v11, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
-; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v8, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
+; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v14, v15, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v16, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
 ; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_ashrrev_i32_e32 v6, 31, v1

 ; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-NEXT:    v_xor_b32_e32 v5, v0, v2
 ; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v3
 ; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
 ; GCN-NEXT:    v_mul_f32_e32 v4, v1, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
+; GCN-NEXT:    v_cvt_i32_f32_e32 v6, v4
 ; GCN-NEXT:    v_mad_f32 v1, -v4, v3, v1
-; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
 ; GCN-NEXT:    v_mul_lo_u32 v1, v1, v2
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_srem24_64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ashr_i64 v[2:3], v[2:3], 40
 ; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v3, v2
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-IR-NEXT:    v_xor_b32_e32 v5, v0, v2
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v4, v3
 ; GCN-IR-NEXT:    v_or_b32_e32 v5, 1, v5
 ; GCN-IR-NEXT:    v_mul_f32_e32 v4, v1, v4
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v4, v4
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v6, v4
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v4, v3, v1
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v3|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v6, v1
 ; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %1 = ashr i64 %x, 40
   %2 = ashr i64 %y, 40
   %result = srem i64 %1, %2
; GCN-IR-NEXT:    s_endpgm
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 ; 32 known sign bits
 define amdgpu_kernel void @s_test_srem32_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_srem32_64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s4, s[0:1], 0xe
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s7
-; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s0
-; GCN-NEXT:    s_xor_b32 s1, s7, s0
-; GCN-NEXT:    s_ashr_i32 s1, s1, 30
-; GCN-NEXT:    s_or_b32 s1, s1, 1
+; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
+; GCN-NEXT:    v_cvt_f32_i32_e32 v1, s3
+; GCN-NEXT:    s_xor_b32 s2, s3, s4
+; GCN-NEXT:    s_ashr_i32 s2, s2, 30
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT:    v_mov_b32_e32 v3, s1
-; GCN-NEXT:    s_mov_b32 s1, s5
+; GCN-NEXT:    s_or_b32 s2, s2, 1
+; GCN-NEXT:    v_mov_b32_e32 v3, s2
+; GCN-NEXT:    s_mov_b32 s5, s1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT:    s_mov_b32 s4, s0
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem32_64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s4, s[0:1], 0xe
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s7
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s0
-; GCN-IR-NEXT:    s_xor_b32 s1, s7, s0
-; GCN-IR-NEXT:    s_ashr_i32 s1, s1, 30
-; GCN-IR-NEXT:    s_or_b32 s1, s1, 1
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, s3
+; GCN-IR-NEXT:    s_xor_b32 s2, s3, s4
+; GCN-IR-NEXT:    s_ashr_i32 s2, s2, 30
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, s1
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
+; GCN-IR-NEXT:    s_or_b32 s2, s2, 1
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, s2
+; GCN-IR-NEXT:    s_mov_b32 s5, s1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, |v0|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s7, v0
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT:    s_mov_b32 s4, s0
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s3, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = ashr i64 %x, 32
   %2 = ashr i64 %y, 32
   %result = srem i64 %1, %2
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 ; 33 known sign bits
 define amdgpu_kernel void @s_test_srem33_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_srem33_64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i64 s[2:3], s[10:11], 31
-; GCN-NEXT:    s_ashr_i64 s[4:5], s[0:1], 31
+; GCN-NEXT:    s_ashr_i64 s[2:3], s[6:7], 31
+; GCN-NEXT:    s_ashr_i64 s[8:9], s[0:1], 31
 ; GCN-NEXT:    s_ashr_i32 s0, s1, 31
-; GCN-NEXT:    s_add_u32 s4, s4, s0
+; GCN-NEXT:    s_add_u32 s8, s8, s0
 ; GCN-NEXT:    s_mov_b32 s1, s0
-; GCN-NEXT:    s_addc_u32 s5, s5, s0
-; GCN-NEXT:    s_xor_b64 s[12:13], s[4:5], s[0:1]
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT:    s_sub_u32 s4, 0, s12
-; GCN-NEXT:    s_subb_u32 s5, 0, s13
-; GCN-NEXT:    s_ashr_i32 s10, s11, 31
+; GCN-NEXT:    s_addc_u32 s9, s9, s0
+; GCN-NEXT:    s_xor_b64 s[8:9], s[8:9], s[0:1]
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
+; GCN-NEXT:    s_sub_u32 s6, 0, s8
+; GCN-NEXT:    s_subb_u32 s10, 0, s9
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s11, s10
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GCN-NEXT:    v_mul_lo_u32 v6, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
-; GCN-NEXT:    v_mul_hi_u32 v9, v2, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v8, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s9
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s10, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v5
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_lo_u32 v6, s6, v4
+; GCN-NEXT:    v_mul_hi_u32 v7, s6, v0
+; GCN-NEXT:    v_mul_lo_u32 v8, s10, v0
+; GCN-NEXT:    s_ashr_i32 s10, s7, 31
+; GCN-NEXT:    s_mov_b32 s11, s10
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_mul_lo_u32 v7, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
 ; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v7, v12, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v10, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[0:1]
 ; GCN-NEXT:    s_add_u32 s0, s2, s10
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    s_addc_u32 s1, s3, s10
-; GCN-NEXT:    s_xor_b64 s[14:15], s[0:1], s[10:11]
+; GCN-NEXT:    s_xor_b64 s[12:13], s[0:1], s[10:11]
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, s14, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s14, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, s14, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, s15, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, s15, v2
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v5, s15, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s15, v0
-; GCN-NEXT:    s_mov_b32 s4, s8
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v4, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s12, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s12, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s13, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s13, v2
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s13, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s13, v0
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
-; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
-; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
-; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
+; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
+; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s15, v1
-; GCN-NEXT:    v_mov_b32_e32 v3, s13
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s14, v0
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s13, v1
+; GCN-NEXT:    v_mov_b32_e32 v3, s9
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s12, v0
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
+; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s8, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
+; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s9, v5
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
-; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
+; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s8, v4
+; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s8, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s9, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
 ; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v5, s15
+; GCN-NEXT:    v_mov_b32_e32 v5, s13
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s9, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GCN-NEXT:    v_xor_b32_e32 v0, s10, v0
 ; GCN-NEXT:    v_xor_b32_e32 v1, s10, v1
 ; GCN-NEXT:    v_mov_b32_e32 v2, s10
; GCN-IR-NEXT:    s_endpgm
   %result = srem i64 %1, %2
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_srem24_48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
 ; GCN-LABEL: s_test_srem24_48:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GCN-NEXT:    s_load_dword s2, s[0:1], 0xb
 ; GCN-NEXT:    s_load_dword s3, s[0:1], 0xc
-; GCN-NEXT:    s_load_dword s6, s[0:1], 0xd
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_load_dword s4, s[0:1], 0xd
+; GCN-NEXT:    s_load_dword s5, s[0:1], 0xe
+; GCN-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_mov_b32_e32 v2, s2
-; GCN-NEXT:    s_sext_i32_i16 s1, s3
-; GCN-NEXT:    v_mov_b32_e32 v0, s6
-; GCN-NEXT:    s_sext_i32_i16 s0, s0
-; GCN-NEXT:    v_alignbit_b32 v0, s0, v0, 24
+; GCN-NEXT:    s_sext_i32_i16 s3, s3
+; GCN-NEXT:    v_mov_b32_e32 v0, s4
+; GCN-NEXT:    s_sext_i32_i16 s5, s5
+; GCN-NEXT:    v_alignbit_b32 v0, s5, v0, 24
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
-; GCN-NEXT:    v_alignbit_b32 v2, s1, v2, 24
+; GCN-NEXT:    v_alignbit_b32 v2, s3, v2, 24
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v3, v2
 ; GCN-NEXT:    v_xor_b32_e32 v5, v2, v0
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v4, v1
 ; GCN-NEXT:    v_ashrrev_i32_e32 v5, 30, v5
 ; GCN-NEXT:    v_or_b32_e32 v5, 1, v5
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v4, v3, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v4, v4
+; GCN-NEXT:    v_cvt_i32_f32_e32 v6, v4
 ; GCN-NEXT:    v_mad_f32 v3, -v4, v1, v3
-; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v3|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v6
 ; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v2, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT:    buffer_store_dword v0, off, s[4:7], 0
-; GCN-NEXT:    buffer_store_short v1, off, s[4:7], 0 offset:4
+; GCN-NEXT:    buffer_store_dword v0, off, s[0:3], 0
+; GCN-NEXT:    buffer_store_short v1, off, s[0:3], 0 offset:4
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem24_48:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
 ; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xb
 ; GCN-IR-NEXT:    s_load_dword s3, s[0:1], 0xc
 ; GCN-IR-NEXT:    s_load_dword s6, s[0:1], 0xd
; GCN-IR-NEXT:    s_endpgm
   store i48 %result, i48 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_srem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_srem_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_ashr_i32 s0, s7, 31
 ; GCN-NEXT:    s_add_u32 s2, s6, s0
 ; GCN-NEXT:    s_addc_u32 s3, s7, s0
 ; GCN-NEXT:    s_mov_b32 s1, s0
 ; GCN-NEXT:    s_xor_b64 s[8:9], s[2:3], s[0:1]
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s9
 ; GCN-NEXT:    s_sub_u32 s2, 0, s8
 ; GCN-NEXT:    s_subb_u32 s3, 0, s9
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, s2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
+; GCN-NEXT:    v_mul_lo_u32 v9, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, 24, v0
-; GCN-NEXT:    v_mul_hi_u32 v5, 24, v3
-; GCN-NEXT:    v_mul_hi_u32 v3, 0, v3
+; GCN-NEXT:    v_mul_hi_u32 v5, 24, v2
+; GCN-NEXT:    v_mul_hi_u32 v2, 0, v2
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v2, v5, vcc
+; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, 0, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s8, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s8, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s9, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s9

 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
 ; GCN-NEXT:    v_mov_b32_e32 v11, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
 ; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v10, v14, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, 24

 ; GCN-IR-NEXT:    v_or_b32_e32 v5, v5, v3
 ; GCN-IR-NEXT:    v_or_b32_e32 v2, v4, v2
 ; GCN-IR-NEXT:  BB11_6: ; %Flow4
 ; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
 ; GCN-IR-NEXT:    v_mul_lo_u32 v3, v0, v5
 ; GCN-IR-NEXT:    v_mul_hi_u32 v4, v0, v2
 ; GCN-IR-NEXT:    v_mul_lo_u32 v1, v1, v2
 ; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, v2
-; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, v4, v3
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %result = srem i64 24, %x
   ret i64 %result
 }
 
 define i64 @v_test_srem_pow2_k_num_i64(i64 %x) {

 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
 ; GCN-NEXT:    v_mov_b32_e32 v11, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v6, v4, v2
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v2
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
 ; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v7
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v7
-; GCN-NEXT:    v_mul_hi_u32 v7, v3, v7
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v12, v8, vcc
-; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v8, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v10, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v10, v14, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %result = srem i64 %x, 32768
   ret i64 %result
 }
 
 define amdgpu_kernel void @s_test_srem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_srem24_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s6, 0x41c00000
+; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
-; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s4
-; GCN-NEXT:    s_ashr_i32 s5, s4, 30
-; GCN-NEXT:    s_or_b32 s5, s5, 1
-; GCN-NEXT:    v_mov_b32_e32 v3, s5
+; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-NEXT:    s_ashr_i32 s4, s2, 30
+; GCN-NEXT:    s_or_b32 s4, s4, 1
+; GCN-NEXT:    v_mov_b32_e32 v3, s4
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    v_mul_f32_e32 v1, s6, v1
+; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
-; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s6
+; GCN-NEXT:    v_mad_f32 v2, -v1, v0, s5
 ; GCN-NEXT:    v_cvt_i32_f32_e32 v1, v1
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem24_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s6, 0x41c00000
+; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_ashr_i64 s[4:5], s[2:3], 40
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s4
-; GCN-IR-NEXT:    s_ashr_i32 s5, s4, 30
-; GCN-IR-NEXT:    s_or_b32 s5, s5, 1
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, s5
+; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-IR-NEXT:    s_ashr_i32 s4, s2, 30
+; GCN-IR-NEXT:    s_or_b32 s4, s4, 1
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, s4
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
-; GCN-IR-NEXT:    v_mul_f32_e32 v1, s6, v1
+; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
-; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s6
+; GCN-IR-NEXT:    v_mad_f32 v2, -v1, v0, s5
 ; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v1, v1
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v0|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v3, vcc
 ; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-IR-NEXT:    s_endpgm
   %x.shr = ashr i64 %x, 40
   %result = srem i64 24, %x.shr
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_srem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_srem24_k_den_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s1, 0x46b6fe00
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
+; GCN-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
-; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s6
-; GCN-NEXT:    s_ashr_i32 s0, s6, 30
-; GCN-NEXT:    s_or_b32 s0, s0, 1
-; GCN-NEXT:    v_mov_b32_e32 v1, s0
+; GCN-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-NEXT:    s_ashr_i32 s3, s2, 30
+; GCN-NEXT:    s_or_b32 s3, s3, 1
+; GCN-NEXT:    v_mov_b32_e32 v1, s3
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v0, -v2, s1, v0
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
+; GCN-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-NEXT:    v_mad_f32 v0, -v2, s4, v0
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-NEXT:    s_movk_i32 s0, 0x5b7f
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-NEXT:    s_mov_b32 s4, s0
+; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_srem24_k_den_i64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s1, 0x46b6fe00
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
+; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_ashr_i64 s[6:7], s[6:7], 40
-; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s6
-; GCN-IR-NEXT:    s_ashr_i32 s0, s6, 30
-; GCN-IR-NEXT:    s_or_b32 s0, s0, 1
-; GCN-IR-NEXT:    v_mov_b32_e32 v1, s0
+; GCN-IR-NEXT:    s_ashr_i64 s[2:3], s[2:3], 40
+; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v0, s2
+; GCN-IR-NEXT:    s_ashr_i32 s3, s2, 30
+; GCN-IR-NEXT:    s_or_b32 s3, s3, 1
+; GCN-IR-NEXT:    v_mov_b32_e32 v1, s3
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, 0x38331158, v0
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s1, v0
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s1
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v2
+; GCN-IR-NEXT:    v_mad_f32 v0, -v2, s4, v0
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v0, 0, v1, vcc
-; GCN-IR-NEXT:    s_movk_i32 s0, 0x5b7f
-; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
+; GCN-IR-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
+; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-IR-NEXT:    s_mov_b32 s4, s0
+; GCN-IR-NEXT:    s_mov_b32 s5, s1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %x.shr = ashr i64 %x, 40
   %result = srem i64 %x.shr, 23423
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define i64 @v_test_srem24_k_num_i64(i64 %x) {
 ; GCN-LABEL: v_test_srem24_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
 ; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_srem24_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
 ; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %x.shr = ashr i64 %x, 40
   %result = srem i64 24, %x.shr
   ret i64 %result
 }
 
 define i64 @v_test_srem24_pow2_k_num_i64(i64 %x) {
 ; GCN-LABEL: v_test_srem24_pow2_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-NEXT:    s_mov_b32 s4, 0x47000000
 ; GCN-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
 ; GCN-NEXT:    v_or_b32_e32 v3, 1, v3
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
 ; GCN-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_srem24_pow2_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v3, 30, v0
 ; GCN-IR-NEXT:    v_or_b32_e32 v3, 1, v3
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, s4, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v1, s4
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, |v1|
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v1, s4
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, |v1|
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v3, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-IR-NEXT:    v_mul_lo_u32 v0, v1, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 0x8000, v0
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %x.shr = ashr i64 %x, 40
   %result = srem i64 32768, %x.shr
   ret i64 %result

 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ashr_i64 v[0:1], v[0:1], 40
 ; GCN-IR-NEXT:    s_mov_b32 s4, 0x47000000
 ; GCN-IR-NEXT:    v_cvt_f32_i32_e32 v1, v0
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v2, 30, v0
 ; GCN-IR-NEXT:    v_or_b32_e32 v2, 1, v2
 ; GCN-IR-NEXT:    v_mul_f32_e32 v3, 0x38000000, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v3, v3
+; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v4, v3
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v3, s4, v1
-; GCN-IR-NEXT:    v_cvt_i32_f32_e32 v3, v3
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, s4
 ; GCN-IR-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
-; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
+; GCN-IR-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
 ; GCN-IR-NEXT:    v_lshlrev_b32_e32 v1, 15, v1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
 ; GCN-IR-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GCN-IR-NEXT:    v_ashrrev_i32_e32 v1, 31, v0
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %x.shr = ashr i64 %x, 40
   %result = srem i64 %x.shr, 32768
   ret i64 %result
 }

llvm/test/CodeGen/AMDGPU/udiv64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
 
 define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT:    s_sub_u32 s4, 0, s2
-; GCN-NEXT:    s_subb_u32 s5, 0, s3
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
+; GCN-NEXT:    s_sub_u32 s8, 0, s12
+; GCN-NEXT:    s_subb_u32 s4, 0, s13
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s4, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s5, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v0
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s4, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s4, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s5, v0
-; GCN-NEXT:    s_mov_b32 s5, s9
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s8, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s8, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT:    s_mov_b32 s4, s8
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s2, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s3, v0
-; GCN-NEXT:    v_mov_b32_e32 v5, s3
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, s12, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s12, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s13, v0
+; GCN-NEXT:    v_mov_b32_e32 v5, s13
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v3, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s11, v2
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s10, v3
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s7, v2
+; GCN-NEXT:    v_sub_i32_e32 v3, vcc, s6, v3
 ; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s2, v3
+; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s12, v3
 ; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v5
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v4
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
 ; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
 ; GCN-NEXT:    v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v6, s11
+; GCN-NEXT:    v_mov_b32_e32 v6, s7
 ; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v6, v2, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
-; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s3, v2
+; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v2
 ; GCN-NEXT:    v_cndmask_b32_e32 v2, v6, v3, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv_i64:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
 ; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-IR-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[6:7], 0

 ; GCN-NEXT:    v_rcp_f32_e32 v4, v4
 ; GCN-NEXT:    v_mov_b32_e32 v13, 0
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v5, v5
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
+; GCN-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v4
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v10
 ; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v14, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v10
+; GCN-NEXT:    v_mul_hi_u32 v10, v5, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
-; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v8, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
+; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v14, v15, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v16, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
 ; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v8, v0, v5
 ; GCN-NEXT:    v_mul_hi_u32 v9, v1, v5
 ; GCN-NEXT:    v_mul_lo_u32 v5, v1, v5
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v8, v1, v4
 ; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v4, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v14, v6, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v2, v5
 ; GCN-NEXT:    v_mul_hi_u32 v7, v2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, v3, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; GCN-NEXT:    v_sub_i32_e32 v8, vcc, v1, v6
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v7
-; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
+; GCN-NEXT:    v_sub_i32_e32 v7, vcc, v1, v6
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, v0, v9
+; GCN-NEXT:    v_subb_u32_e64 v7, s[4:5], v7, v3, vcc
 ; GCN-NEXT:    v_sub_i32_e64 v8, s[4:5], v0, v2
 ; GCN-NEXT:    v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v7, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v8, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v7, v3
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v1, v6, vcc

 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %result = udiv i64 %x, %y
   ret i64 %result
 }
 
 define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv24_64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    s_lshr_b32 s0, s0, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    s_lshr_b32 s0, s7, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s2, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv24_64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s2, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %result = udiv i64 %1, %2
   ret i64 %result
 }
 
 define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv32_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-NEXT:    s_mov_b32 s4, s0
-; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv32_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
 ; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s3
-; GCN-IR-NEXT:    s_mov_b32 s4, s0
-; GCN-IR-NEXT:    s_mov_b32 s5, s1
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = lshr i64 %x, 32
   %2 = lshr i64 %y, 32
   %result = udiv i64 %1, %2
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv31_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    s_lshr_b32 s0, s0, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    s_lshr_b32 s0, s7, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s2, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_lshr_b32 s2, s3, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv31_i64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s2, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffffff, v0
 ; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = lshr i64 %x, 33
   %2 = lshr i64 %y, 33
   %result = udiv i64 %1, %2
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_udiv23_i64:
 ; GCN:       ; %bb.0:
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s1, s5
-; GCN-NEXT:    s_lshr_b32 s0, s0, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    s_lshr_b32 s0, s7, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-NEXT:    s_mov_b32 s0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s2, 9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_lshr_b32 s2, s3, 9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv23_i64:
 ; GCN-IR:       ; %bb.0:
-; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dword s0, s[0:1], 0xe
-; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    s_load_dword s2, s[0:1], 0xe
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s1, s5
-; GCN-IR-NEXT:    s_lshr_b32 s0, s0, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    s_lshr_b32 s0, s7, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
-; GCN-IR-NEXT:    s_mov_b32 s0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s2, 9
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
+; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 9
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v3, v2
 ; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v3, vcc
 ; GCN-IR-NEXT:    v_and_b32_e32 v0, 0x7fffff, v0

 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_and_b32 s7, s7, s4
 ; GCN-NEXT:    s_and_b32 s6, s6, s5
 ; GCN-NEXT:    s_sub_u32 s8, 0, s2
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v1
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v1
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
 ; GCN-NEXT:    v_mac_f32_e32 v1, 0xcf800000, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT:    s_subb_u32 s9, 0, s3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    s_subb_u32 s4, 0, s3
 ; GCN-NEXT:    v_mov_b32_e32 v8, 0
-; GCN-NEXT:    v_mul_lo_u32 v3, s8, v2
-; GCN-NEXT:    v_mul_hi_u32 v4, s8, v1
-; GCN-NEXT:    v_mul_lo_u32 v5, s9, v1
-; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v4, s8, v1
+; GCN-NEXT:    v_mul_hi_u32 v3, s8, v1
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v5, s4, v1
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v1
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v1, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, v1, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v3
+; GCN-NEXT:    v_mul_hi_u32 v5, v1, v6
+; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3
 ; GCN-NEXT:    v_mul_hi_u32 v10, v2, v3
 ; GCN-NEXT:    v_mul_lo_u32 v3, v2, v3
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v2, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v5, v4, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v5, v6, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-NEXT:    v_add_i32_e64 v1, s[2:3], v1, v3
 ; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v2, v4, s[2:3]
 ; GCN-NEXT:    v_mul_lo_u32 v5, s8, v3
 ; GCN-NEXT:    v_mul_hi_u32 v6, s8, v1
-; GCN-NEXT:    v_mul_lo_u32 v7, s9, v1
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v1
+; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_mul_lo_u32 v6, s8, v1
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
-; GCN-NEXT:    v_mul_lo_u32 v11, v1, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v1, v5
-; GCN-NEXT:    v_mul_hi_u32 v12, v1, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v6
+; GCN-NEXT:    v_mul_lo_u32 v10, v1, v5
+; GCN-NEXT:    v_mul_hi_u32 v12, v1, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v1, v6
+; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
 ; GCN-NEXT:    v_mul_hi_u32 v7, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v9, v13, vcc
+; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v9, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v10, vcc
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v6, v3
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v5, vcc
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v10, v6
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v11, v13, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v7, v8, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v5, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
 ; GCN-NEXT:    v_mov_b32_e32 v3, s6
 ; GCN-NEXT:    v_alignbit_b32 v3, s7, v3, 24
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v5, v3, v1
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v2
; GCN-IR-NEXT:    s_endpgm
   store i48 %result, i48 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_udiv_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_mov_b32 s11, 0xf000
 ; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
 ; GCN-NEXT:    s_sub_u32 s2, 0, s6
 ; GCN-NEXT:    s_subb_u32 s3, 0, s7
 ; GCN-NEXT:    s_mov_b32 s8, s4
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, s2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s2, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v2, v1, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
 ; GCN-NEXT:    v_mov_b32_e32 v5, s7
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
-; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
-; GCN-NEXT:    v_mul_lo_u32 v3, s6, v0
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
-; GCN-NEXT:    v_sub_i32_e32 v3, vcc, 24, v3
-; GCN-NEXT:    v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
-; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s6, v3
-; GCN-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
-; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v4
+; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v0
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 24, v4
+; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v5, vcc
+; GCN-NEXT:    v_subrev_i32_e64 v5, s[0:1], s6, v4
+; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v2
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]
 ; GCN-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v4, v6, v5, s[0:1]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v2
+; GCN-NEXT:    v_cndmask_b32_e64 v2, v6, v5, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v5, s[0:1], 2, v0
-; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1]
-; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_addc_u32_e64 v6, s[0:1], 0, v3, s[0:1]
 ; GCN-NEXT:    v_add_i32_e64 v7, s[0:1], 1, v0
-; GCN-NEXT:    v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1]
+; GCN-NEXT:    v_subb_u32_e32 v1, vcc, 0, v1, vcc
+; GCN-NEXT:    v_addc_u32_e64 v3, s[0:1], 0, v3, s[0:1]
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4
-; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
-; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3
+; GCN-NEXT:    v_cndmask_b32_e64 v2, v3, v6, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
+; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s6, v4
+; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s7, v1
-; GCN-NEXT:    v_cndmask_b32_e32 v1, v4, v3, vcc
-; GCN-NEXT:    v_cndmask_b32_e64 v2, v2, v6, s[0:1]
+; GCN-NEXT:    v_cndmask_b32_e32 v1, v3, v4, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v7, v5, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv_k_num_i64:

 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
+; GCN-NEXT:    v_mov_b32_e32 v10, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v13, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v11, vcc
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
 ; GCN-NEXT:    v_mul_hi_u32 v4, v0, v2
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
 ; GCN-NEXT:    s_mov_b32 s4, 0x8000
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, v2
-; GCN-NEXT:    v_sub_i32_e32 v5, vcc, 0, v3
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s4, v4
-; GCN-NEXT:    v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
-; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v4, v0
-; GCN-NEXT:    v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
-; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v5, v1
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
+; GCN-NEXT:    v_sub_i32_e32 v5, vcc, s4, v5
+; GCN-NEXT:    v_subb_u32_e64 v4, s[4:5], v4, v1, vcc
+; GCN-NEXT:    v_sub_i32_e64 v6, s[4:5], v5, v0
+; GCN-NEXT:    v_subbrev_u32_e64 v4, s[4:5], 0, v4, s[4:5]
+; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v4, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[4:5]
 ; GCN-NEXT:    v_cmp_ge_u32_e64 s[4:5], v6, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v5, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v5, v7, v6, s[4:5]
+; GCN-NEXT:    v_cmp_eq_u32_e64 s[4:5], v4, v1
+; GCN-NEXT:    v_cndmask_b32_e64 v4, v7, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v6, s[4:5], 2, v2
 ; GCN-NEXT:    v_addc_u32_e64 v7, s[4:5], 0, v12, s[4:5]
 ; GCN-NEXT:    v_add_i32_e64 v8, s[4:5], 1, v2
 ; GCN-NEXT:    v_subb_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v9, s[4:5], 0, v12, s[4:5]
-; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v5
+; GCN-NEXT:    v_cmp_ne_u32_e64 s[4:5], 0, v4
 ; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v3, v1
-; GCN-NEXT:    v_cndmask_b32_e64 v5, v8, v6, s[4:5]
+; GCN-NEXT:    v_cndmask_b32_e64 v4, v8, v6, s[4:5]
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
-; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v0
+; GCN-NEXT:    v_cmp_ge_u32_e32 vcc, v5, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v9, v7, s[4:5]
-; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v5, vcc
+; GCN-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, 0, v1, vcc
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
 ; GCN-IR-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-IR-NEXT:    v_ffbh_u32_e32 v2, v0
 ; GCN-IR-NEXT:    v_add_i32_e32 v2, vcc, 32, v2

 }
 
 define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_udiv_k_den_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    s_movk_i32 s2, 0xffe8
-; GCN-NEXT:    v_mov_b32_e32 v8, 0
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
+; GCN-NEXT:    s_movk_i32 s4, 0xffe8
+; GCN-NEXT:    v_mov_b32_e32 v6, 0
+; GCN-NEXT:    v_mov_b32_e32 v2, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
-; GCN-NEXT:    s_mov_b32 s6, -1
-; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
-; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s4, s8
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
-; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
-; GCN-NEXT:    s_mov_b32 s5, s9
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v5, v1, s4
+; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, s4
+; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
+; GCN-NEXT:    v_mul_lo_u32 v7, v3, s4
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v8
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v6, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
+; GCN-NEXT:    s_mov_b32 s9, s5
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s10, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v4, s10, v1
-; GCN-NEXT:    v_mul_hi_u32 v5, s11, v1
-; GCN-NEXT:    v_mul_lo_u32 v1, s11, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GCN-NEXT:    v_mul_lo_u32 v3, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v4, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v1
+; GCN-NEXT:    v_mul_lo_u32 v1, s7, v1
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_lo_u32 v5, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v3, v0, 24
 ; GCN-NEXT:    v_mul_lo_u32 v4, v0, 24
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s10, v4
-; GCN-NEXT:    v_mov_b32_e32 v3, s11
+; GCN-NEXT:    v_sub_i32_e32 v4, vcc, s6, v4
+; GCN-NEXT:    v_mov_b32_e32 v3, s7
 ; GCN-NEXT:    v_subb_u32_e32 v2, vcc, v3, v2, vcc
 ; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, 24, v4
 ; GCN-NEXT:    v_subbrev_u32_e32 v5, vcc, 0, v2, vcc
 ; GCN-NEXT:    v_cmp_lt_u32_e32 vcc, 23, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v3, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v5
 ; GCN-NEXT:    v_cndmask_b32_e32 v3, -1, v3, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, 2, v0
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, 1, v0
 ; GCN-NEXT:    v_cmp_lt_u32_e64 s[0:1], 23, v4
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]
 ; GCN-NEXT:    v_cmp_eq_u32_e64 s[0:1], 0, v2
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v3
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, -1, v4, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2
 ; GCN-NEXT:    v_cndmask_b32_e32 v3, v8, v6, vcc
 ; GCN-NEXT:    v_cndmask_b32_e32 v2, v7, v5, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v1, v1, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_udiv_k_den_i64:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
 ; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-IR-NEXT:    s_flbit_i32_b32 s2, s6
 ; GCN-IR-NEXT:    s_flbit_i32_b32 s3, s7

 ; GCN-NEXT:    v_mov_b32_e32 v9, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v4, v2, s6
-; GCN-NEXT:    v_mul_lo_u32 v5, v3, s6
-; GCN-NEXT:    v_mul_lo_u32 v6, v2, s6
+; GCN-NEXT:    v_mul_lo_u32 v6, v3, s6
+; GCN-NEXT:    v_mul_lo_u32 v5, v2, s6
 ; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_mul_lo_u32 v7, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v5, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v5
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v4
 ; GCN-NEXT:    v_mul_hi_u32 v11, v3, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v5, vcc
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v10, v8, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v3, v5
+; GCN-NEXT:    v_mul_hi_u32 v5, v3, v5
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v5, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v9, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v10, v6, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v6, v2, s6
 ; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v7, v4, s6
 ; GCN-NEXT:    v_mul_lo_u32 v8, v2, s6
 ; GCN-NEXT:    v_subrev_i32_e32 v6, vcc, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_mul_lo_u32 v7, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v11, v2, v8
 ; GCN-NEXT:    v_mul_hi_u32 v12, v2, v6
 ; GCN-NEXT:    v_mul_hi_u32 v13, v4, v6
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v11, v7
 ; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v10, v12, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v8, v4, v8
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v12
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v8, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v13, v9, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v6, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v12
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v11, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v13, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v7, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v2
 ; GCN-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v1, v3

llvm/test/CodeGen/AMDGPU/udivrem.ll

 ; R600-NEXT:     LSHR * T3.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX6-LABEL: test_udivrem:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dword s3, s[0:1], 0x26
 ; GFX6-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
 ; GFX6-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x13
-; GFX6-NEXT:    s_load_dword s0, s[0:1], 0x1d
 ; GFX6-NEXT:    s_mov_b32 s7, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s6, -1
 ; GFX6-NEXT:    s_mov_b32 s10, s6
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s3
 ; GFX6-NEXT:    s_sub_i32 s2, 0, s3
 ; GFX6-NEXT:    s_mov_b32 s11, s7
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, s2, v0
+; GFX6-NEXT:    s_load_dword s2, s[0:1], 0x1d
 ; GFX6-NEXT:    v_mul_hi_u32 v1, v0, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v1, v0
-; GFX6-NEXT:    v_mul_hi_u32 v0, s0, v0
+; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
+; GFX6-NEXT:    v_mul_hi_u32 v0, s2, v0
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v0, s3
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s0, v1
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s2, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, v2, s[0:1]
 ; GFX6-NEXT:    v_add_i32_e32 v2, vcc, 1, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v1
 ; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, v2, s[0:1]
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s3, v1

 ; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX6-LABEL: test_udivrem_v2:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0xb
 ; GFX6-NEXT:    s_mov_b32 s2, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
-; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s7
+; GFX6-NEXT:    s_sub_i32 s3, 0, s7
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
 ; GFX6-NEXT:    v_mul_f32_e32 v0, s2, v0
 ; GFX6-NEXT:    v_mul_f32_e32 v1, s2, v1
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GFX6-NEXT:    s_sub_i32 s2, 0, s6
+; GFX6-NEXT:    v_mul_lo_u32 v3, s3, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_sub_i32 s2, 0, s7
-; GFX6-NEXT:    v_mul_lo_u32 v3, s2, v1
+; GFX6-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX6-NEXT:    s_mov_b32 s2, -1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
 ; GFX6-NEXT:    v_mul_hi_u32 v3, v1, v3
+; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
-; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v3, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s6
 ; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s7
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
 ; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
+; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s7, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s6, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s7, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s6, v0
 ; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v2, vcc, s7, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s7, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
 ; GFX6-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: test_udivrem_v2:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x2c
 ; GFX8-NEXT:    s_mov_b32 s3, 0x4f7ffffe
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

 ; R600-NEXT:     SUB_INT * T1.W, PV.Y, KC0[4].Y,
 ; R600-NEXT:     CNDE_INT T3.X, PV.W, T0.Y, PS,
 ; R600-NEXT:     LSHR * T0.X, KC0[2].Y, literal.x,
 ; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
 ;
 ; GFX6-LABEL: test_udivrem_v4:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0xd
-; GFX6-NEXT:    s_mov_b32 s13, 0x4f7ffffe
+; GFX6-NEXT:    s_mov_b32 s14, 0x4f7ffffe
 ; GFX6-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x9
 ; GFX6-NEXT:    s_mov_b32 s3, 0xf000
+; GFX6-NEXT:    s_mov_b32 s2, -1
 ; GFX6-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX6-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX6-NEXT:    s_sub_i32 s2, 0, s8
-; GFX6-NEXT:    s_sub_i32 s12, 0, s9
+; GFX6-NEXT:    s_sub_i32 s12, 0, s8
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v2, s10
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v0, v0
 ; GFX6-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v3, s10
-; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
-; GFX6-NEXT:    v_mul_f32_e32 v0, s13, v0
+; GFX6-NEXT:    s_sub_i32 s13, 0, s9
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_f32_e32 v0, s14, v0
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX6-NEXT:    v_mul_f32_e32 v1, s13, v1
+; GFX6-NEXT:    v_mul_f32_e32 v1, s14, v1
 ; GFX6-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v3
-; GFX6-NEXT:    v_mul_lo_u32 v2, s2, v0
-; GFX6-NEXT:    s_mov_b32 s2, -1
-; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v1
-; GFX6-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX6-NEXT:    v_mul_f32_e32 v2, s14, v2
+; GFX6-NEXT:    v_mul_lo_u32 v3, s12, v0
+; GFX6-NEXT:    v_cvt_f32_u32_e32 v5, s11
+; GFX6-NEXT:    v_mul_lo_u32 v4, s13, v1
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX6-NEXT:    v_mul_hi_u32 v3, v0, v3
+; GFX6-NEXT:    s_sub_i32 s12, 0, s10
 ; GFX6-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v2, v0
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v3, v0
 ; GFX6-NEXT:    v_mul_hi_u32 v0, s4, v0
+; GFX6-NEXT:    v_rcp_iflag_f32_e32 v3, v5
 ; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v4, v1
-; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
-; GFX6-NEXT:    v_mul_f32_e32 v2, s13, v3
+; GFX6-NEXT:    v_mul_lo_u32 v4, s12, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
+; GFX6-NEXT:    v_mul_hi_u32 v1, s5, v1
+; GFX6-NEXT:    v_mul_f32_e32 v3, s14, v3
+; GFX6-NEXT:    v_mul_hi_u32 v4, v2, v4
 ; GFX6-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_subrev_i32_e32 v3, vcc, s8, v0
+; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s8, v0
+; GFX6-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
-; GFX6-NEXT:    s_sub_i32 s4, 0, s10
-; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
-; GFX6-NEXT:    v_mul_lo_u32 v3, s4, v2
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
-; GFX6-NEXT:    v_mul_hi_u32 v3, v2, v3
-; GFX6-NEXT:    v_rcp_iflag_f32_e32 v4, v5
 ; GFX6-NEXT:    s_sub_i32 s4, 0, s11
-; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GFX6-NEXT:    v_mul_f32_e32 v3, s13, v4
-; GFX6-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s9, v1
+; GFX6-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
+; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
+; GFX6-NEXT:    v_mul_lo_u32 v4, s4, v3
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, s5, v1
 ; GFX6-NEXT:    v_mul_hi_u32 v2, s6, v2
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
+; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v4
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s9, v1
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
-; GFX6-NEXT:    v_mul_lo_u32 v5, s4, v3
-; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
 ; GFX6-NEXT:    v_mul_lo_u32 v2, v2, s10
-; GFX6-NEXT:    v_mul_hi_u32 v4, v3, v5
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
-; GFX6-NEXT:    v_subrev_i32_e32 v5, vcc, s10, v2
+; GFX6-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
 ; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GFX6-NEXT:    v_mul_hi_u32 v3, s7, v3
-; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
-; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, s6, v2
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
+; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_mul_lo_u32 v3, v3, s11
+; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
+; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s10, v2
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2
 ; GFX6-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc
 ; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, s7, v3
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GFX6-NEXT:    v_subrev_i32_e32 v4, vcc, s11, v3
 ; GFX6-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3
 ; GFX6-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
 ; GFX6-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
 ; GFX6-NEXT:    s_endpgm
 ;
 ; GFX8-LABEL: test_udivrem_v4:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x34
-; GFX8-NEXT:    s_mov_b32 s12, 0x4f7ffffe
+; GFX8-NEXT:    s_mov_b32 s3, 0x4f7ffffe
 ; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GFX8-NEXT:    s_sub_i32 s2, 0, s8
 ; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s9
-; GFX8-NEXT:    v_cvt_f32_u32_e32 v4, s11
+; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, s10
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0
-; GFX8-NEXT:    s_sub_i32 s3, 0, s9
 ; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1
-; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s10
-; GFX8-NEXT:    v_mul_f32_e32 v0, s12, v0
+; GFX8-NEXT:    v_mul_f32_e32 v0, s3, v0
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GFX8-NEXT:    v_mul_f32_e32 v1, s12, v1
+; GFX8-NEXT:    v_mul_f32_e32 v1, s3, v1
 ; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2
-; GFX8-NEXT:    v_mul_lo_u32 v3, s2, v0
+; GFX8-NEXT:    v_mul_lo_u32 v2, s2, v0
+; GFX8-NEXT:    s_sub_i32 s2, 0, s9
+; GFX8-NEXT:    v_mul_lo_u32 v4, s2, v1
 ; GFX8-NEXT:    s_sub_i32 s2, 0, s10
-; GFX8-NEXT:    v_mul_f32_e32 v2, s12, v2
-; GFX8-NEXT:    v_mul_hi_u32 v3, v0, v3
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v2, v2
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v0
+; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v2
+; GFX8-NEXT:    v_mul_hi_u32 v4, v1, v4
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v2, v0
 ; GFX8-NEXT:    v_mul_hi_u32 v0, s4, v0
-; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v4
-; GFX8-NEXT:    v_mul_lo_u32 v4, s3, v1
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v3
+; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, s11
 ; GFX8-NEXT:    v_mul_lo_u32 v0, v0, s8
-; GFX8-NEXT:    v_mul_f32_e32 v3, s12, v3
-; GFX8-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GFX8-NEXT:    v_mul_f32_e32 v2, s3, v2
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3
 ; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s4, v0
 ; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s8, v0
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s8, v0
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v0
 ; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v4, v1
 ; GFX8-NEXT:    v_mul_hi_u32 v1, s5, v1
 ; GFX8-NEXT:    v_mul_lo_u32 v4, s2, v2
-; GFX8-NEXT:    s_sub_i32 s2, 0, s11
+; GFX8-NEXT:    v_mul_f32_e32 v3, s3, v3
+; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX8-NEXT:    v_mul_lo_u32 v1, v1, s9
 ; GFX8-NEXT:    v_mul_hi_u32 v4, v2, v4
+; GFX8-NEXT:    s_sub_i32 s2, 0, s11
 ; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s5, v1
 ; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s9, v1
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
 ; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s9, v1
 ; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s9, v1
 ; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
 ; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v4, v2

llvm/test/CodeGen/AMDGPU/urem64.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
 
 define amdgpu_kernel void @s_test_urem_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
 ; GCN-LABEL: s_test_urem_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0xd
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
+; GCN-NEXT:    s_mov_b32 s11, 0xf000
+; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s12
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s13
-; GCN-NEXT:    s_sub_u32 s2, 0, s12
-; GCN-NEXT:    s_subb_u32 s3, 0, s13
-; GCN-NEXT:    s_mov_b32 s4, s8
+; GCN-NEXT:    s_sub_u32 s8, 0, s12
+; GCN-NEXT:    s_subb_u32 s4, 0, s13
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    s_mov_b32 s5, s9
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
-; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v4, s8, v2
+; GCN-NEXT:    v_mul_lo_u32 v7, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v6, s8, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_lo_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v4
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v9, v1, vcc
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v4
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[2:3]
+; GCN-NEXT:    v_mul_hi_u32 v6, s8, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s8, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, s4, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s8, v0
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v2, v6, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v6, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v3, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v2, v6, s[2:3]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, 0, v3, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v5, s10, v0
-; GCN-NEXT:    v_mul_hi_u32 v6, s10, v3
-; GCN-NEXT:    v_mul_hi_u32 v7, s11, v3
-; GCN-NEXT:    v_mul_lo_u32 v3, s11, v3
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v2, vcc
+; GCN-NEXT:    s_waitcnt lgkmcnt(0)
+; GCN-NEXT:    v_mul_lo_u32 v4, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v6, s6, v2
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v2
+; GCN-NEXT:    v_mul_lo_u32 v2, s7, v2
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_mul_lo_u32 v6, s11, v0
-; GCN-NEXT:    v_mul_hi_u32 v0, s11, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_mul_lo_u32 v6, s7, v0
+; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
+; GCN-NEXT:    s_mov_b32 s8, s4
+; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v5, v0, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s12, v1
 ; GCN-NEXT:    v_mul_hi_u32 v2, s12, v0
 ; GCN-NEXT:    v_mul_lo_u32 v3, s13, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s12, v0
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s11, v1
+; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s7, v1
 ; GCN-NEXT:    v_mov_b32_e32 v3, s13
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s10, v0
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc
 ; GCN-NEXT:    v_subrev_i32_e64 v4, s[0:1], s12, v0
 ; GCN-NEXT:    v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s13, v5
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[2:3]
 ; GCN-NEXT:    v_cmp_le_u32_e64 s[2:3], s12, v4
 ; GCN-NEXT:    v_subrev_i32_e64 v3, s[0:1], s12, v4
 ; GCN-NEXT:    v_cndmask_b32_e64 v7, 0, -1, s[2:3]
 ; GCN-NEXT:    v_cmp_eq_u32_e64 s[2:3], s13, v5
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, v6, v7, s[2:3]
 ; GCN-NEXT:    v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1]
 ; GCN-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v6
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v5, v2, s[0:1]
-; GCN-NEXT:    v_mov_b32_e32 v5, s11
+; GCN-NEXT:    v_mov_b32_e32 v5, s7
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v5, v1, vcc
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s13, v1
 ; GCN-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_le_u32_e32 vcc, s12, v0
 ; GCN-NEXT:    v_cndmask_b32_e64 v6, 0, -1, vcc
 ; GCN-NEXT:    v_cmp_eq_u32_e32 vcc, s13, v1
 ; GCN-NEXT:    v_cndmask_b32_e32 v5, v5, v6, vcc
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5
 ; GCN-NEXT:    v_cndmask_b32_e32 v1, v1, v2, vcc
 ; GCN-NEXT:    v_cndmask_b32_e64 v2, v4, v3, s[0:1]
 ; GCN-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[8:11], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem_i64:
 ; GCN-IR:       ; %bb.0: ; %_udiv-special-cases
 ; GCN-IR-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-IR-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-IR-NEXT:    v_cmp_eq_u64_e64 s[8:9], s[6:7], 0

 ; GCN-NEXT:    v_rcp_f32_e32 v4, v4
 ; GCN-NEXT:    v_mov_b32_e32 v13, 0
 ; GCN-NEXT:    v_mul_f32_e32 v4, 0x5f7ffffc, v4
 ; GCN-NEXT:    v_mul_f32_e32 v5, 0x2f800000, v4
 ; GCN-NEXT:    v_trunc_f32_e32 v5, v5
 ; GCN-NEXT:    v_mac_f32_e32 v4, 0xcf800000, v5
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v4
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v5
-; GCN-NEXT:    v_mul_hi_u32 v8, v6, v4
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v7, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v9
-; GCN-NEXT:    v_mul_lo_u32 v9, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
+; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v8, v6, v5
+; GCN-NEXT:    v_mul_lo_u32 v11, v7, v4
+; GCN-NEXT:    v_mul_lo_u32 v10, v6, v4
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v11
+; GCN-NEXT:    v_mul_hi_u32 v9, v4, v10
 ; GCN-NEXT:    v_mul_lo_u32 v11, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v10, v4, v8
-; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v8
 ; GCN-NEXT:    v_mul_hi_u32 v15, v5, v8
 ; GCN-NEXT:    v_mul_lo_u32 v8, v5, v8
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
-; GCN-NEXT:    v_mul_lo_u32 v12, v5, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v5, v9
-; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v14, v10, vcc
-; GCN-NEXT:    v_add_i32_e32 v11, vcc, v11, v12
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v10, v9, vcc
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v11
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v14, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v12, v5, v10
+; GCN-NEXT:    v_mul_hi_u32 v10, v5, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v9, v12
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v15, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e64 v4, s[4:5], v4, v8
 ; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v14, v10, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v8, vcc, v5, v9, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v10, v6, v8
 ; GCN-NEXT:    v_mul_hi_u32 v11, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v7, v7, v4
 ; GCN-NEXT:    v_mul_lo_u32 v6, v6, v4
 ; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
 ; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_mul_lo_u32 v12, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v15, v4, v6
-; GCN-NEXT:    v_mul_hi_u32 v16, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v11, v8, v6
+; GCN-NEXT:    v_mul_lo_u32 v11, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v6
+; GCN-NEXT:    v_mul_hi_u32 v15, v4, v7
+; GCN-NEXT:    v_mul_hi_u32 v16, v8, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v8, v6
-; GCN-NEXT:    v_add_i32_e32 v12, vcc, v15, v12
+; GCN-NEXT:    v_add_i32_e32 v11, vcc, v12, v11
 ; GCN-NEXT:    v_mul_hi_u32 v10, v8, v7
-; GCN-NEXT:    v_addc_u32_e32 v15, vcc, v14, v16, vcc
+; GCN-NEXT:    v_addc_u32_e32 v12, vcc, v14, v15, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v7, v8, v7
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v12, v6
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v15, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v11, v6
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v12, v16, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v10, v13, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v14, v8, vcc
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v9
 ; GCN-NEXT:    v_addc_u32_e64 v5, vcc, v5, v7, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v6
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, 0, v5, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v6, v0, v5

 ; GCN-IR-NEXT:    v_or_b32_e32 v7, v9, v5
 ; GCN-IR-NEXT:    v_or_b32_e32 v4, v8, v4
 ; GCN-IR-NEXT:  BB1_6: ; %Flow4
 ; GCN-IR-NEXT:    s_or_b64 exec, exec, s[6:7]
 ; GCN-IR-NEXT:    v_mul_lo_u32 v5, v2, v7
 ; GCN-IR-NEXT:    v_mul_hi_u32 v6, v2, v4
 ; GCN-IR-NEXT:    v_mul_lo_u32 v3, v3, v4
 ; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GCN-IR-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-IR-NEXT:    v_add_i32_e32 v4, vcc, v6, v5
+; GCN-IR-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
 ; GCN-IR-NEXT:    v_subb_u32_e32 v1, vcc, v1, v3, vcc
 ; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %result = urem i64 %x, %y
   ret i64 %result
 }
 
 define amdgpu_kernel void @s_test_urem31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
; GCN-IR-NEXT:    s_endpgm
   %result = urem i64 %1, %2
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_urem31_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
 ; GCN-LABEL: s_test_urem31_v2i64:
 ; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-NEXT:    s_lshr_b32 s3, s3, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-NEXT:    s_lshr_b32 s2, s11, 1
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT:    s_lshr_b32 s1, s11, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-NEXT:    s_lshr_b32 s1, s3, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-NEXT:    s_brev_b32 s0, -2
-; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem31_v2i64:
 ; GCN-IR:       ; %bb.0:
+; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-IR-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 1
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-IR-NEXT:    s_lshr_b32 s1, s3, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-IR-NEXT:    s_brev_b32 s0, -2
-; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = lshr <2 x i64> %x, <i64 33, i64 33>
   %2 = lshr <2 x i64> %y, <i64 33, i64 33>
   %result = urem <2 x i64> %1, %2
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
 }
; GCN-IR-NEXT:    s_endpgm
   %result = urem i64 %1, %2
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_urem23_64_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %x, <2 x i64> %y) {
 ; GCN-LABEL: s_test_urem23_64_v2i64:
 ; GCN:       ; %bb.0:
+; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-NEXT:    s_mov_b32 s6, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-NEXT:    s_lshr_b32 s3, s3, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-NEXT:    s_lshr_b32 s2, s11, 9
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-NEXT:    s_lshr_b32 s1, s11, 9
-; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-NEXT:    s_lshr_b32 s1, s3, 9
+; GCN-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-NEXT:    s_brev_b32 s0, -2
-; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem23_64_v2i64:
 ; GCN-IR:       ; %bb.0:
+; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0x11
 ; GCN-IR-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x9
-; GCN-IR-NEXT:    s_load_dwordx4 s[8:11], s[0:1], 0xd
-; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x11
+; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0xd
 ; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
 ; GCN-IR-NEXT:    s_mov_b32 s6, -1
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_lshr_b32 s2, s9, 1
+; GCN-IR-NEXT:    s_lshr_b32 s8, s9, 1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s8
 ; GCN-IR-NEXT:    s_lshr_b32 s0, s1, 1
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s0
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s2
-; GCN-IR-NEXT:    s_lshr_b32 s3, s3, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v4, s3
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v1, s0
+; GCN-IR-NEXT:    s_lshr_b32 s2, s11, 9
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v0
-; GCN-IR-NEXT:    s_lshr_b32 s1, s11, 9
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s1
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v3, s2
+; GCN-IR-NEXT:    s_lshr_b32 s1, s3, 9
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v5, s1
 ; GCN-IR-NEXT:    v_mul_f32_e32 v2, v1, v2
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_mad_f32 v1, -v2, v0, v1
-; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v2, v4
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
-; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s0
-; GCN-IR-NEXT:    v_mul_f32_e32 v2, v3, v2
-; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
-; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v5, v2
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
-; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v4, v3
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v4
-; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v5, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s3
+; GCN-IR-NEXT:    v_mad_f32 v4, -v2, v0, v1
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v6, v3
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v4|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
+; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-IR-NEXT:    v_mul_f32_e32 v2, v5, v6
+; GCN-IR-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v4, v2
+; GCN-IR-NEXT:    v_mad_f32 v2, -v2, v3, v5
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v2|, v3
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s8
+; GCN-IR-NEXT:    v_addc_u32_e32 v2, vcc, 0, v4, vcc
+; GCN-IR-NEXT:    v_mul_lo_u32 v2, v2, s2
+; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s0, v0
 ; GCN-IR-NEXT:    s_brev_b32 s0, -2
-; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_sub_i32_e32 v2, vcc, s1, v2
+; GCN-IR-NEXT:    v_and_b32_e32 v0, s0, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v2, s0, v2
-; GCN-IR-NEXT:    v_mov_b32_e32 v3, v1
 ; GCN-IR-NEXT:    buffer_store_dwordx4 v[0:3], off, s[4:7], 0
 ; GCN-IR-NEXT:    s_endpgm
   %1 = lshr <2 x i64> %x, <i64 33, i64 41>
   %2 = lshr <2 x i64> %y, <i64 33, i64 41>
   %result = urem <2 x i64> %1, %2
   store <2 x i64> %result, <2 x i64> addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_urem_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_urem_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
-; GCN-NEXT:    v_mov_b32_e32 v2, 0
+; GCN-NEXT:    v_mov_b32_e32 v3, 0
 ; GCN-NEXT:    s_mov_b32 s11, 0xf000
 ; GCN-NEXT:    s_mov_b32 s10, -1
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s6
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v1, s7
 ; GCN-NEXT:    s_sub_u32 s2, 0, s6
 ; GCN-NEXT:    s_subb_u32 s3, 0, s7
 ; GCN-NEXT:    s_mov_b32 s8, s4
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0x4f800000, v1
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    s_mov_b32 s9, s5
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
-; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v0
-; GCN-NEXT:    v_trunc_f32_e32 v3, v3
-; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v3
+; GCN-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v0
+; GCN-NEXT:    v_trunc_f32_e32 v2, v2
+; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
-; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
+; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_mul_hi_u32 v5, s2, v0
-; GCN-NEXT:    v_mul_lo_u32 v4, s2, v3
+; GCN-NEXT:    v_mul_lo_u32 v4, s2, v2
 ; GCN-NEXT:    v_mul_lo_u32 v7, s3, v0
 ; GCN-NEXT:    v_mul_lo_u32 v6, s2, v0
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
 ; GCN-NEXT:    v_mul_hi_u32 v5, v0, v6
 ; GCN-NEXT:    v_mul_lo_u32 v7, v0, v4
 ; GCN-NEXT:    v_mul_hi_u32 v9, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v8, v3, v6
-; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
+; GCN-NEXT:    v_mul_hi_u32 v8, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v6, v2, v6
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
-; GCN-NEXT:    v_mul_hi_u32 v10, v3, v4
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v2, v9, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, v3, v4
+; GCN-NEXT:    v_mul_hi_u32 v10, v2, v4
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v3, v9, vcc
+; GCN-NEXT:    v_mul_lo_u32 v4, v2, v4
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v7, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v1, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v5, v4
 ; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v4
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v2, v6, vcc
-; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v3, v5, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v6, s2, v4
-; GCN-NEXT:    v_mul_hi_u32 v7, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v3, v6, vcc
+; GCN-NEXT:    v_addc_u32_e64 v4, vcc, v2, v5, s[0:1]
+; GCN-NEXT:    v_mul_hi_u32 v6, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v7, s2, v4
 ; GCN-NEXT:    v_mul_lo_u32 v8, s3, v0
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_mul_lo_u32 v7, s2, v0
+; GCN-NEXT:    v_mul_lo_u32 v9, s2, v0
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v7
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v6
-; GCN-NEXT:    v_mul_lo_u32 v10, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v12, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v11, v0, v7
-; GCN-NEXT:    v_mul_hi_u32 v9, v4, v7
-; GCN-NEXT:    v_mul_lo_u32 v7, v4, v7
-; GCN-NEXT:    v_mul_hi_u32 v8, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v11, v10
-; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v2, v12, vcc
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v9
+; GCN-NEXT:    v_mul_hi_u32 v11, v0, v6
+; GCN-NEXT:    v_mul_hi_u32 v12, v4, v9
+; GCN-NEXT:    v_mul_lo_u32 v9, v4, v9
+; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
+; GCN-NEXT:    v_mul_hi_u32 v7, v4, v6
+; GCN-NEXT:    v_addc_u32_e32 v10, vcc, v3, v11, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v6
-; GCN-NEXT:    v_add_i32_e32 v7, vcc, v10, v7
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v7, v4
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc
-; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v3, v1, s[0:1]
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v8, v9
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v10, v12, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v6, v4
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v3, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v5
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v2, v1, s[0:1]
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v4
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, 24
+; GCN-NEXT:    v_mul_lo_u32 v2, v1, 24
 ; GCN-NEXT:    v_mul_hi_u32 v0, v0, 24
 ; GCN-NEXT:    v_mul_hi_u32 v1, v1, 24
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v2, v1, vcc
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v1, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v1, s7, v0
 ; GCN-NEXT:    v_mul_hi_u32 v2, s6, v0
 ; GCN-NEXT:    v_mul_lo_u32 v0, s6, v0
 ; GCN-NEXT:    v_mov_b32_e32 v3, s7
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-NEXT:    v_subb_u32_e64 v2, s[0:1], v2, v3, vcc

 }
 
 define amdgpu_kernel void @s_test_urem_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_urem_k_den_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0x4f800000
 ; GCN-NEXT:    v_madak_f32 v0, 0, v0, 0x41c00000
 ; GCN-NEXT:    v_rcp_f32_e32 v0, v0
-; GCN-NEXT:    s_movk_i32 s2, 0xffe8
-; GCN-NEXT:    v_mov_b32_e32 v8, 0
-; GCN-NEXT:    v_mov_b32_e32 v7, 0
+; GCN-NEXT:    s_movk_i32 s4, 0xffe8
+; GCN-NEXT:    v_mov_b32_e32 v6, 0
+; GCN-NEXT:    v_mov_b32_e32 v2, 0
 ; GCN-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_mac_f32_e32 v0, 0xcf800000, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v0, v0
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v1, v1
-; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
 ; GCN-NEXT:    s_mov_b32 s11, 0xf000
-; GCN-NEXT:    v_mul_hi_u32 v2, v0, s2
-; GCN-NEXT:    v_mul_lo_u32 v3, v1, s2
-; GCN-NEXT:    v_mul_lo_u32 v4, v0, s2
 ; GCN-NEXT:    s_mov_b32 s10, -1
-; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, v0, v2
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v6, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v3, v0, v2
-; GCN-NEXT:    v_mul_hi_u32 v9, v1, v2
-; GCN-NEXT:    v_mul_lo_u32 v2, v1, v2
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_mul_lo_u32 v6, v1, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, v1, v4
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v3, vcc
+; GCN-NEXT:    v_mul_hi_u32 v3, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v5, v1, s4
+; GCN-NEXT:    v_mul_lo_u32 v4, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v3, vcc, v0, v3
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_mul_hi_u32 v7, v0, v4
+; GCN-NEXT:    v_mul_lo_u32 v5, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v8, v0, v3
+; GCN-NEXT:    v_mul_hi_u32 v9, v1, v4
+; GCN-NEXT:    v_mul_lo_u32 v4, v1, v4
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v5
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v6, v8, vcc
+; GCN-NEXT:    v_mul_hi_u32 v8, v1, v3
+; GCN-NEXT:    v_mul_lo_u32 v3, v1, v3
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v7, v9, vcc
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v8, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_add_i32_e64 v0, s[2:3], v0, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_hi_u32 v5, v0, s4
+; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v1, v4, s[2:3]
+; GCN-NEXT:    v_mul_lo_u32 v7, v3, s4
+; GCN-NEXT:    v_mul_lo_u32 v8, v0, s4
+; GCN-NEXT:    v_subrev_i32_e32 v5, vcc, v0, v5
+; GCN-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v7
+; GCN-NEXT:    v_mul_lo_u32 v7, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v9, v0, v8
+; GCN-NEXT:    v_mul_hi_u32 v10, v0, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v5
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s8, s4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v3, v4, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v9, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_add_i32_e64 v0, s[0:1], v0, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_hi_u32 v4, v0, s2
-; GCN-NEXT:    v_addc_u32_e64 v2, vcc, v1, v3, s[0:1]
-; GCN-NEXT:    v_mul_lo_u32 v5, v2, s2
-; GCN-NEXT:    v_mul_lo_u32 v6, v0, s2
-; GCN-NEXT:    v_subrev_i32_e32 v4, vcc, v0, v4
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v9, v7
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v6, v10, vcc
+; GCN-NEXT:    v_mul_lo_u32 v10, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_mul_lo_u32 v3, v3, v5
 ; GCN-NEXT:    s_mov_b32 s9, s5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
-; GCN-NEXT:    v_mul_lo_u32 v5, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v9, v0, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v0, v4
-; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v9, v5
-; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v8, v10, vcc
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v6, v2, v6
-; GCN-NEXT:    v_mul_lo_u32 v2, v2, v4
-; GCN-NEXT:    v_add_i32_e32 v5, vcc, v5, v10
-; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v6, vcc
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v5, v2
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v3
-; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v4, s[0:1]
-; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GCN-NEXT:    v_add_i32_e32 v5, vcc, v7, v10
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v11, v2, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v6, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v1, vcc, v1, v4
+; GCN-NEXT:    v_addc_u32_e64 v1, vcc, v1, v5, s[2:3]
+; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v3
 ; GCN-NEXT:    v_addc_u32_e32 v1, vcc, 0, v1, vcc
-; GCN-NEXT:    v_mul_lo_u32 v2, s6, v1
-; GCN-NEXT:    v_mul_hi_u32 v3, s6, v0
-; GCN-NEXT:    v_mul_hi_u32 v4, s6, v1
-; GCN-NEXT:    v_mul_hi_u32 v5, s7, v1
+; GCN-NEXT:    v_mul_lo_u32 v3, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v4, s6, v0
+; GCN-NEXT:    v_mul_hi_u32 v5, s6, v1
+; GCN-NEXT:    v_mul_hi_u32 v7, s7, v1
 ; GCN-NEXT:    v_mul_lo_u32 v1, s7, v1
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v3, v2
-; GCN-NEXT:    v_addc_u32_e32 v3, vcc, v8, v4, vcc
-; GCN-NEXT:    v_mul_lo_u32 v4, s7, v0
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v4, v3
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v6, v5, vcc
+; GCN-NEXT:    v_mul_lo_u32 v5, s7, v0
 ; GCN-NEXT:    v_mul_hi_u32 v0, s7, v0
-; GCN-NEXT:    v_add_i32_e32 v2, vcc, v4, v2
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v3, v0, vcc
-; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v5, v7, vcc
+; GCN-NEXT:    v_add_i32_e32 v3, vcc, v5, v3
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, v4, v0, vcc
+; GCN-NEXT:    v_addc_u32_e32 v2, vcc, v7, v2, vcc
 ; GCN-NEXT:    v_add_i32_e32 v0, vcc, v0, v1
-; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v8, v2, vcc
+; GCN-NEXT:    v_addc_u32_e32 v1, vcc, v6, v2, vcc
 ; GCN-NEXT:    v_mul_hi_u32 v2, v0, 24
 ; GCN-NEXT:    v_mul_lo_u32 v1, v1, 24
 ; GCN-NEXT:    v_mul_lo_u32 v0, v0, 24
 ; GCN-NEXT:    v_add_i32_e32 v1, vcc, v2, v1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s6, v0
 ; GCN-NEXT:    v_mov_b32_e32 v2, s7
 ; GCN-NEXT:    v_subb_u32_e32 v1, vcc, v2, v1, vcc
 ; GCN-NEXT:    v_subrev_i32_e32 v2, vcc, 24, v0

 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v2, v0
 ; GCN-NEXT:    v_cvt_f32_u32_e32 v3, v1
 ; GCN-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
 ; GCN-NEXT:    v_subb_u32_e32 v5, vcc, 0, v1, vcc
 ; GCN-NEXT:    v_mov_b32_e32 v12, 0
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0x4f800000, v3
 ; GCN-NEXT:    v_rcp_f32_e32 v2, v2
-; GCN-NEXT:    v_mov_b32_e32 v11, 0
+; GCN-NEXT:    v_mov_b32_e32 v10, 0
 ; GCN-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v2
 ; GCN-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v2
 ; GCN-NEXT:    v_trunc_f32_e32 v3, v3
 ; GCN-NEXT:    v_mac_f32_e32 v2, 0xcf800000, v3
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GCN-NEXT:    v_mul_hi_u32 v7, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v6, v4, v3
-; GCN-NEXT:    v_mul_lo_u32 v8, v5, v2
-; GCN-NEXT:    v_mul_lo_u32 v9, v4, v2
+; GCN-NEXT:    v_mul_lo_u32 v9, v5, v2
+; GCN-NEXT:    v_mul_lo_u32 v8, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
-; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v8
-; GCN-NEXT:    v_mul_lo_u32 v8, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v10, v2, v9
-; GCN-NEXT:    v_mul_hi_u32 v7, v2, v6
-; GCN-NEXT:    v_mul_hi_u32 v13, v3, v6
+; GCN-NEXT:    v_add_i32_e32 v6, vcc, v6, v9
+; GCN-NEXT:    v_mul_hi_u32 v7, v2, v8
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v6
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v6
+; GCN-NEXT:    v_mul_lo_u32 v13, v3, v8
+; GCN-NEXT:    v_mul_hi_u32 v8, v3, v8
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v9
+; GCN-NEXT:    v_addc_u32_e32 v9, vcc, v12, v11, vcc
+; GCN-NEXT:    v_mul_hi_u32 v11, v3, v6
 ; GCN-NEXT:    v_mul_lo_u32 v6, v3, v6
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v10, v8
-; GCN-NEXT:    v_mul_lo_u32 v10, v3, v9
-; GCN-NEXT:    v_mul_hi_u32 v9, v3, v9
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v7, vcc
-; GCN-NEXT:    v_add_i32_e32 v8, vcc, v8, v10
-; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v7, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v13, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v7, vcc, v7, v13
+; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v9, v8, vcc
+; GCN-NEXT:    v_addc_u32_e32 v8, vcc, v11, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v6, vcc, v7, v6
 ; GCN-NEXT:    v_add_i32_e64 v2, s[4:5], v2, v6
 ; GCN-NEXT:    v_addc_u32_e32 v7, vcc, v12, v8, vcc
 ; GCN-NEXT:    v_addc_u32_e64 v6, vcc, v3, v7, s[4:5]
 ; GCN-NEXT:    v_mul_lo_u32 v8, v4, v6
 ; GCN-NEXT:    v_mul_hi_u32 v9, v4, v2
 ; GCN-NEXT:    v_mul_lo_u32 v5, v5, v2
 ; GCN-NEXT:    v_mul_lo_u32 v4, v4, v2
 ; GCN-NEXT:    v_add_i32_e32 v8, vcc, v9, v8
 ; GCN-NEXT:    v_add_i32_e32 v5, vcc, v8, v5
-; GCN-NEXT:    v_mul_lo_u32 v10, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v13, v2, v4
-; GCN-NEXT:    v_mul_hi_u32 v14, v2, v5
-; GCN-NEXT:    v_mul_hi_u32 v9, v6, v4
+; GCN-NEXT:    v_mul_lo_u32 v9, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v11, v2, v4
+; GCN-NEXT:    v_mul_hi_u32 v13, v2, v5
+; GCN-NEXT:    v_mul_hi_u32 v14, v6, v4
 ; GCN-NEXT:    v_mul_lo_u32 v4, v6, v4
-; GCN-NEXT:    v_add_i32_e32 v10, vcc, v13, v10
+; GCN-NEXT:    v_add_i32_e32 v9, vcc, v11, v9
 ; GCN-NEXT:    v_mul_hi_u32 v8, v6, v5
-; GCN-NEXT:    v_addc_u32_e32 v13, vcc, v12, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v11, vcc, v12, v13, vcc
 ; GCN-NEXT:    v_mul_lo_u32 v5, v6, v5
-; GCN-NEXT:    v_add_i32_e32 v4, vcc, v10, v4
-; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v13, v9, vcc
-; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v11, vcc
+; GCN-NEXT:    v_add_i32_e32 v4, vcc, v9, v4
+; GCN-NEXT:    v_addc_u32_e32 v4, vcc, v11, v14, vcc
+; GCN-NEXT:    v_addc_u32_e32 v6, vcc, v8, v10, vcc
 ; GCN-NEXT:    v_add_i32_e32 v4, vcc, v4, v5
 ; GCN-NEXT:    v_addc_u32_e32 v5, vcc, v12, v6, vcc
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v7
 ; GCN-NEXT:    v_addc_u32_e64 v3, vcc, v3, v5, s[4:5]
 ; GCN-NEXT:    v_add_i32_e32 v2, vcc, v2, v4
 ; GCN-NEXT:    v_addc_u32_e32 v2, vcc, 0, v3, vcc
 ; GCN-NEXT:    v_lshrrev_b32_e32 v2, 17, v2
 ; GCN-NEXT:    v_mul_lo_u32 v3, v1, v2
; GCN-IR-NEXT:    s_setpc_b64 s[30:31]
   %result = urem i64 %x, 32768
   ret i64 %result
 }
 
 define amdgpu_kernel void @s_test_urem24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_urem24_k_num_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s5, 0x41c00000
+; GCN-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_mov_b32 s2, -1
-; GCN-NEXT:    s_lshr_b32 s4, s3, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GCN-NEXT:    v_mul_f32_e32 v1, s5, v1
+; GCN-NEXT:    v_mul_f32_e32 v1, s4, v1
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s5
+; GCN-NEXT:    v_mad_f32 v1, -v1, v0, s4
 ; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-NEXT:    s_mov_b32 s2, -1
 ; GCN-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
 ; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem24_k_num_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s5, 0x41c00000
+; GCN-IR-NEXT:    s_mov_b32 s4, 0x41c00000
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_mov_b32 s2, -1
-; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
 ; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-IR-NEXT:    v_rcp_iflag_f32_e32 v1, v0
-; GCN-IR-NEXT:    v_mul_f32_e32 v1, s5, v1
+; GCN-IR-NEXT:    v_mul_f32_e32 v1, s4, v1
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s5
+; GCN-IR-NEXT:    v_mad_f32 v1, -v1, v0, s4
 ; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v1|, v0
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
 ; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s4
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
 ; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, 24, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
 ; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-IR-NEXT:    s_endpgm
   %x.shr = lshr i64 %x, 40
   %result = urem i64 24, %x.shr
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define amdgpu_kernel void @s_test_urem24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
 ; GCN-LABEL: s_test_urem24_k_den_i64:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-NEXT:    s_mov_b32 s4, 0x46b6fe00
-; GCN-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-NEXT:    s_mov_b32 s6, -1
+; GCN-NEXT:    s_mov_b32 s5, 0x46b6fe00
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-NEXT:    s_lshr_b32 s2, s3, 8
-; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-NEXT:    s_movk_i32 s3, 0x5b7f
-; GCN-NEXT:    s_mov_b32 s5, s1
+; GCN-NEXT:    s_movk_i32 s2, 0x5b7f
+; GCN-NEXT:    s_lshr_b32 s4, s3, 8
+; GCN-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
 ; GCN-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-NEXT:    v_mad_f32 v0, -v1, s4, v0
-; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
-; GCN-NEXT:    s_mov_b32 s4, s0
-; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-NEXT:    v_mad_f32 v0, -v1, s5, v0
+; GCN-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s5
 ; GCN-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-NEXT:    s_mov_b32 s2, -1
+; GCN-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GCN-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
-; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-NEXT:    s_endpgm
 ;
 ; GCN-IR-LABEL: s_test_urem24_k_den_i64:
 ; GCN-IR:       ; %bb.0:
 ; GCN-IR-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x9
-; GCN-IR-NEXT:    s_mov_b32 s4, 0x46b6fe00
-; GCN-IR-NEXT:    s_mov_b32 s7, 0xf000
-; GCN-IR-NEXT:    s_mov_b32 s6, -1
+; GCN-IR-NEXT:    s_mov_b32 s5, 0x46b6fe00
 ; GCN-IR-NEXT:    s_waitcnt lgkmcnt(0)
-; GCN-IR-NEXT:    s_lshr_b32 s2, s3, 8
-; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s2
-; GCN-IR-NEXT:    s_movk_i32 s3, 0x5b7f
-; GCN-IR-NEXT:    s_mov_b32 s5, s1
+; GCN-IR-NEXT:    s_movk_i32 s2, 0x5b7f
+; GCN-IR-NEXT:    s_lshr_b32 s4, s3, 8
+; GCN-IR-NEXT:    v_cvt_f32_u32_e32 v0, s4
+; GCN-IR-NEXT:    s_mov_b32 s3, 0xf000
 ; GCN-IR-NEXT:    v_mul_f32_e32 v1, 0x38331158, v0
 ; GCN-IR-NEXT:    v_trunc_f32_e32 v1, v1
 ; GCN-IR-NEXT:    v_cvt_u32_f32_e32 v2, v1
-; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s4, v0
-; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s4
-; GCN-IR-NEXT:    s_mov_b32 s4, s0
-; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
-; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s3
+; GCN-IR-NEXT:    v_mad_f32 v0, -v1, s5, v0
+; GCN-IR-NEXT:    v_cmp_ge_f32_e64 vcc, |v0|, s5
 ; GCN-IR-NEXT:    v_mov_b32_e32 v1, 0
-; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s2, v0
+; GCN-IR-NEXT:    v_addc_u32_e32 v0, vcc, 0, v2, vcc
+; GCN-IR-NEXT:    v_mul_lo_u32 v0, v0, s2
+; GCN-IR-NEXT:    s_mov_b32 s2, -1
+; GCN-IR-NEXT:    v_sub_i32_e32 v0, vcc, s4, v0
 ; GCN-IR-NEXT:    v_and_b32_e32 v0, 0xffffff, v0
-; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-IR-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GCN-IR-NEXT:    s_endpgm
   %x.shr = lshr i64 %x, 40
   %result = urem i64 %x.shr, 23423
   store i64 %result, i64 addrspace(1)* %out
   ret void
 }
 
 define i64 @v_test_urem24_k_num_i64(i64 %x) {