[PowerPC][NFC] Rename instruction formats in PPCInstrPrefix.td

[amyk]

Summary

This patch renames some of the instruction formats within PPCInstrPrefix.td to adopt a more uniform naming convention.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

46

Note that I've changed this format to have SI34_FRS5. I was originally going to change just D34 to SI34 but then the instruction format name would be MLS_DForm_R_SI34_RTA5. This would not be possible, as there already exists an instruction format with this name (below the current instruction format).

[lei]

Just 1 minor name change. Otherwise LGTM.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

46

Based on the other names, I think this should be MLS_DForm_R_SI34_FRSA5 since D_RA is 34 bits immediate + 5 bit register field RA.

[stefanp]

Talked this over with the team and we have decided on a way to rename that class. See the comment.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

46

Hi Amy,
After a discussion with the team we think it would be better just to add a _MEM to this name (So, MLS_DForm_R_SI34_RTA5_MEM).

The two names are the same because the formats are effectively the same. This is just a special case where the immediate and the register have been combined to form a memory address. If we add the MEM at the end we can indicate that this is a memory op and make that the difference from the other class.

[amyk]

Addressed review comment of adding _MEM to the instruction format.

[amyk]

@lei @stefanp I've changed the instruction format to accommodate _MEM in the naming. Please let me know if you have any other concerns.

[lei]

Thanks for the update!

[stefanp]

Thank you for fixing this Amy.
LGTM.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
   // and one for 32-bit arguments, this bit breaks the degeneracy between
   // the two forms and allows TableGen to generate mapping tables.
   bit Interpretation64Bit = 0;
 
   // Fields used for relation models.
   string BaseName = "";
 }
 
-class MLS_DForm_R_D34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+class MLS_DForm_R_SI34_FRS5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                             InstrItinClass itin, list<dag> pattern>
   : PI<1, opcode, OOL, IOL, asmstr, itin> {
   bits<5> FRS;
   bits<39> D_RA;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-7} = 2;
class MLS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
   let Inst{14-31} = SI{33-16};
 
   // The instruction.
   let Inst{38-42} = RT;
   let Inst{43-47} = RA;
   let Inst{48-63} = SI{15-0};
 }
 
-class MLS_DForm2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+class MLS_DForm_SI34_RT5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                          InstrItinClass itin, list<dag> pattern>
   : PI<1, opcode, OOL, IOL, asmstr, itin> {
   bits<5> RT;
   bits<34> SI;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-7} = 2;
multiclass MLS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
                                    dag PCRel_IOL, string asmstr,
                                    InstrItinClass itin> {
   def NAME : MLS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
                                    !strconcat(asmstr, ", 0"), itin, []>;
   def pc : MLS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
                                  !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
 }
 
-class 8LS_DForm_R_D34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
+class 8LS_DForm_R_SI34_RTA5<bits<6> opcode, dag OOL, dag IOL, string asmstr,
                             InstrItinClass itin, list<dag> pattern>
   : PI<1, opcode, OOL, IOL, asmstr, itin> {
   bits<5> RT;
   bits<39> D_RA;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-10} = 0;
   let Inst{11} = PCRel;
   let Inst{12-13} = 0;
   let Inst{14-31} = D_RA{33-16}; // d0
 
   // The instruction.
   let Inst{38-42} = RT{4-0};
   let Inst{43-47} = D_RA{38-34}; // RA
   let Inst{48-63} = D_RA{15-0}; // d1
 }
 
 // 8LS:D-Form: [ 1 0 0 // R // d0
 //               PO TX T RA d1 ]
-class 8LS_DForm_R_D34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
+class 8LS_DForm_R_SI34_XT6_RA5<bits<5> opcode, dag OOL, dag IOL, string asmstr,
                                InstrItinClass itin, list<dag> pattern>
   : PI<1, { opcode, ? }, OOL, IOL, asmstr, itin> {
   bits<6> XT;
   bits<39> D_RA;
 
   let Pattern = pattern;
 
   // The prefix.
   let Inst{6-7} = 0;
   let Inst{8} = 0;
   let Inst{9-10} = 0; // reserved
   let Inst{11} = PCRel;
   let Inst{12-13} = 0; // reserved
   let Inst{14-31} = D_RA{33-16}; // d0
 
   // The instruction.
   let Inst{37} = XT{5};
   let Inst{38-42} = XT{4-0};
   let Inst{43-47} = D_RA{38-34}; // RA
   let Inst{48-63} = D_RA{15-0}; // d1
 }
 
-multiclass MLS_DForm_R_D34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
+multiclass MLS_DForm_R_SI34_FRS5_p<bits<6> opcode, dag OOL, dag IOL,
                                    dag PCRel_IOL, string asmstr,
                                    InstrItinClass itin> {
-  def NAME : MLS_DForm_R_D34_RTA5<opcode, OOL, IOL,
+  def NAME : MLS_DForm_R_SI34_FRS5<opcode, OOL, IOL,
                                    !strconcat(asmstr, ", 0"), itin, []>;
-  def pc : MLS_DForm_R_D34_RTA5<opcode, OOL, PCRel_IOL,
+  def pc : MLS_DForm_R_SI34_FRS5<opcode, OOL, PCRel_IOL,
                                  !strconcat(asmstr, ", 1"), itin, []>,
                                  isPCRel;
 }
 
-multiclass 8LS_DForm_R_D34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
+multiclass 8LS_DForm_R_SI34_RTA5_p<bits<6> opcode, dag OOL, dag IOL,
                                    dag PCRel_IOL, string asmstr,
                                    InstrItinClass itin> {
-  def NAME : 8LS_DForm_R_D34_RTA5<opcode, OOL, IOL,
+  def NAME : 8LS_DForm_R_SI34_RTA5<opcode, OOL, IOL,
                                    !strconcat(asmstr, ", 0"), itin, []>;
-  def pc : 8LS_DForm_R_D34_RTA5<opcode, OOL, PCRel_IOL,
+  def pc : 8LS_DForm_R_SI34_RTA5<opcode, OOL, PCRel_IOL,
                                  !strconcat(asmstr, ", 1"), itin, []>, isPCRel;
 }
 
-multiclass 8LS_DForm_R_D34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
+multiclass 8LS_DForm_R_SI34_XT6_RA5_p<bits<5> opcode, dag OOL, dag IOL,
                                       dag PCRel_IOL, string asmstr,
                                       InstrItinClass itin> {
-  def NAME : 8LS_DForm_R_D34_XT6_RA5<opcode, OOL, IOL,
+  def NAME : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, IOL,
                                       !strconcat(asmstr, ", 0"), itin, []>;
-  def pc : 8LS_DForm_R_D34_XT6_RA5<opcode, OOL, PCRel_IOL,
+  def pc : 8LS_DForm_R_SI34_XT6_RA5<opcode, OOL, PCRel_IOL,
                                     !strconcat(asmstr, ", 1"), itin, []>,
                                     isPCRel;
 }
 
 def PrefixInstrs : Predicate<"PPCSubTarget->hasPrefixInstrs()">;
 
 let Predicates = [PrefixInstrs] in {
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
     defm PADDI8 :
       MLS_DForm_R_SI34_RTA5_p<14, (outs g8rc:$RT), (ins g8rc:$RA, s34imm:$SI),
                               (ins immZero:$RA, s34imm:$SI),
                               "paddi $RT, $RA, $SI", IIC_LdStLFD>;
     let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
-      def PLI8 : MLS_DForm2_r0<14, (outs g8rc:$RT),
+      def PLI8 : MLS_DForm_SI34_RT5<14, (outs g8rc:$RT),
                                     (ins s34imm:$SI),
                                     "pli $RT, $SI", IIC_IntSimple, []>;
     }
   }
   defm PADDI :
     MLS_DForm_R_SI34_RTA5_p<14, (outs gprc:$RT), (ins gprc:$RA, s34imm:$SI),
                             (ins immZero:$RA, s34imm:$SI),
                             "paddi $RT, $RA, $SI", IIC_LdStLFD>;
   let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
-    def PLI : MLS_DForm2_r0<14, (outs gprc:$RT),
+    def PLI : MLS_DForm_SI34_RT5<14, (outs gprc:$RT),
                                  (ins s34imm:$SI),
                                  "pli $RT, $SI", IIC_IntSimple, []>;
   }
 
   let mayLoad = 1, mayStore = 0 in {
     defm PLXV :
-      8LS_DForm_R_D34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
+      8LS_DForm_R_SI34_XT6_RA5_p<25, (outs vsrc:$XT), (ins memri34:$D_RA),
                                  (ins memri34_pcrel:$D_RA), "plxv $XT, $D_RA",
                                  IIC_LdStLFD>;
     defm PLFS :
-      MLS_DForm_R_D34_RTA5_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<48, (outs f4rc:$FRT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plfs $FRT, $D_RA",
                               IIC_LdStLFD>;
     defm PLFD :
-      MLS_DForm_R_D34_RTA5_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<50, (outs f8rc:$FRT), (ins memri34:$D_RA),
                               (ins  memri34_pcrel:$D_RA), "plfd $FRT, $D_RA",
                               IIC_LdStLFD>;
     defm PLXSSP :
-      8LS_DForm_R_D34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
+      8LS_DForm_R_SI34_RTA5_p<43, (outs vfrc:$VRT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plxssp $VRT, $D_RA",
                               IIC_LdStLFD>;
     defm PLXSD :
-      8LS_DForm_R_D34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
+      8LS_DForm_R_SI34_RTA5_p<42, (outs vfrc:$VRT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plxsd $VRT, $D_RA",
                               IIC_LdStLFD>;
     let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
       defm PLBZ8 :
-        MLS_DForm_R_D34_RTA5_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
+        MLS_DForm_R_SI34_FRS5_p<34, (outs g8rc:$RT), (ins memri34:$D_RA),
                                 (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
                                 IIC_LdStLFD>;
       defm PLHZ8 :
-        MLS_DForm_R_D34_RTA5_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
+        MLS_DForm_R_SI34_FRS5_p<40, (outs g8rc:$RT), (ins memri34:$D_RA),
                                 (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
                                 IIC_LdStLFD>;
       defm PLHA8 :
-        MLS_DForm_R_D34_RTA5_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
+        MLS_DForm_R_SI34_FRS5_p<42, (outs g8rc:$RT), (ins memri34:$D_RA),
                                 (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
                                 IIC_LdStLFD>;
       defm PLWA8 :
-        8LS_DForm_R_D34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
+        8LS_DForm_R_SI34_RTA5_p<41, (outs g8rc:$RT), (ins memri34:$D_RA),
                                 (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
                                 IIC_LdStLFD>;
       defm PLWZ8 :
-        MLS_DForm_R_D34_RTA5_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
+        MLS_DForm_R_SI34_FRS5_p<32, (outs g8rc:$RT), (ins memri34:$D_RA),
                                 (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
                                 IIC_LdStLFD>;
     }
     defm PLBZ :
-      MLS_DForm_R_D34_RTA5_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<34, (outs gprc:$RT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plbz $RT, $D_RA",
                               IIC_LdStLFD>;
     defm PLHZ :
-      MLS_DForm_R_D34_RTA5_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<40, (outs gprc:$RT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plhz $RT, $D_RA",
                               IIC_LdStLFD>;
     defm PLHA :
-      MLS_DForm_R_D34_RTA5_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<42, (outs gprc:$RT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plha $RT, $D_RA",
                               IIC_LdStLFD>;
     defm PLWZ :
-      MLS_DForm_R_D34_RTA5_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<32, (outs gprc:$RT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plwz $RT, $D_RA",
                               IIC_LdStLFD>;
     defm PLWA :
-      8LS_DForm_R_D34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
+      8LS_DForm_R_SI34_RTA5_p<41, (outs gprc:$RT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "plwa $RT, $D_RA",
                               IIC_LdStLFD>;
     defm PLD :
-      8LS_DForm_R_D34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
+      8LS_DForm_R_SI34_RTA5_p<57, (outs g8rc:$RT), (ins memri34:$D_RA),
                               (ins memri34_pcrel:$D_RA), "pld $RT, $D_RA",
                               IIC_LdStLFD>;
   }
 
   let mayStore = 1, mayLoad = 0 in {
     defm PSTXV :
-      8LS_DForm_R_D34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
+      8LS_DForm_R_SI34_XT6_RA5_p<27, (outs), (ins vsrc:$XS, memri34:$D_RA),
                                 (ins vsrc:$XS, memri34_pcrel:$D_RA),
                                 "pstxv $XS, $D_RA", IIC_LdStLFD>;
     defm PSTFS :
-      MLS_DForm_R_D34_RTA5_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<52, (outs), (ins f4rc:$FRS, memri34:$D_RA),
                               (ins f4rc:$FRS, memri34_pcrel:$D_RA),
                               "pstfs $FRS, $D_RA", IIC_LdStLFD>;
     defm PSTFD :
-      MLS_DForm_R_D34_RTA5_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<54, (outs), (ins f8rc:$FRS, memri34:$D_RA),
                               (ins f8rc:$FRS, memri34_pcrel:$D_RA),
                               "pstfd $FRS, $D_RA", IIC_LdStLFD>;
     defm PSTXSSP :
-      8LS_DForm_R_D34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
+      8LS_DForm_R_SI34_RTA5_p<47, (outs), (ins vfrc:$VRS, memri34:$D_RA),
                               (ins vfrc:$VRS, memri34_pcrel:$D_RA),
                               "pstxssp $VRS, $D_RA", IIC_LdStLFD>;
     defm PSTXSD :
-      8LS_DForm_R_D34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
+      8LS_DForm_R_SI34_RTA5_p<46, (outs), (ins vfrc:$VRS, memri34:$D_RA),
                               (ins vfrc:$VRS, memri34_pcrel:$D_RA),
                               "pstxsd $VRS, $D_RA", IIC_LdStLFD>;
     let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
       defm PSTB8 :
-        MLS_DForm_R_D34_RTA5_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
+        MLS_DForm_R_SI34_FRS5_p<38, (outs), (ins g8rc:$RS, memri34:$D_RA),
                                 (ins g8rc:$RS, memri34_pcrel:$D_RA),
                                 "pstb $RS, $D_RA", IIC_LdStLFD>;
       defm PSTH8 :
-        MLS_DForm_R_D34_RTA5_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
+        MLS_DForm_R_SI34_FRS5_p<44, (outs), (ins g8rc:$RS, memri34:$D_RA),
                                 (ins g8rc:$RS, memri34_pcrel:$D_RA),
                                 "psth $RS, $D_RA", IIC_LdStLFD>;
       defm PSTW8 :
-        MLS_DForm_R_D34_RTA5_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
+        MLS_DForm_R_SI34_FRS5_p<36, (outs), (ins g8rc:$RS, memri34:$D_RA),
                                 (ins g8rc:$RS, memri34_pcrel:$D_RA),
                                 "pstw $RS, $D_RA", IIC_LdStLFD>;
     }
     defm PSTB :
-      MLS_DForm_R_D34_RTA5_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<38, (outs), (ins gprc:$RS, memri34:$D_RA),
                               (ins gprc:$RS, memri34_pcrel:$D_RA),
                               "pstb $RS, $D_RA", IIC_LdStLFD>;
     defm PSTH :
-      MLS_DForm_R_D34_RTA5_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<44, (outs), (ins gprc:$RS, memri34:$D_RA),
                               (ins gprc:$RS, memri34_pcrel:$D_RA),
                               "psth $RS, $D_RA", IIC_LdStLFD>;
     defm PSTW :
-      MLS_DForm_R_D34_RTA5_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
+      MLS_DForm_R_SI34_FRS5_p<36, (outs), (ins gprc:$RS, memri34:$D_RA),
                               (ins gprc:$RS, memri34_pcrel:$D_RA),
                               "pstw $RS, $D_RA", IIC_LdStLFD>;
     defm PSTD :
-      8LS_DForm_R_D34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
+      8LS_DForm_R_SI34_RTA5_p<61, (outs), (ins g8rc:$RS, memri34:$D_RA),
                               (ins g8rc:$RS, memri34_pcrel:$D_RA),
                               "pstd $RS, $D_RA", IIC_LdStLFD>;
   }
 }