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[ARM] Constant long shift combines
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Authored by dmgreen on Mar 3 2020, 11:34 AM.

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Summary

This changes the way that asrl and lsrl intrinsics are lowered, going via a the ISEL ASRL and LSLL nodes instead of straight to machine nodes. On top of that, it adds some constant folds for long shifts, in case it turns out that the shift amount was either constant or 0.

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Event Timeline

dmgreen created this revision.Mar 3 2020, 11:34 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 3 2020, 11:34 AM
samparker added inline comments.Mar 4 2020, 2:01 AM
llvm/lib/Target/ARM/ARMISelLowering.cpp
14090

Well this answers my question in the other review...

14102

And why don't we have to worry about arithmetic shifts?

dmgreen updated this revision to Diff 248247.Mar 4 2020, 10:48 AM
dmgreen marked an inline comment as done.

Tighten up bounds and rebase onto tests.

llvm/lib/Target/ARM/ARMISelLowering.cpp
14102

I think my argument was that any "shift right" becomes a "logical shift left", as the signedness doesn't end up mattering.

samparker accepted this revision.Mar 12 2020, 1:56 AM

Sorry, I forgot about this. LGTM

This revision is now accepted and ready to land.Mar 12 2020, 1:56 AM
This revision was automatically updated to reflect the committed changes.