[MCA][WIP] Modelling CPU front-ent: Fetch stage/Instruction Byte Buffer unit/Decoder stage (PR42202)

[lebedev.ri]

Summary

Not sure how further i will take this, but was bored and thought i'd take a stab..

References:

• https://www.realworldtech.com/bulldozer/5/
• https://www.agner.org/optimize/microarchitecture.pdf 19.3 (bdver2), 18.4 (K10), 20.3 (ryzen)

https://bugs.llvm.org/show_bug.cgi?id=42202

[andreadb]

Hi Roman,

I think that we should further discuss this design in an RFC or on the bugzilla.

For now, I consider this patch an interesting prototype (which presumably works for bdver2). However, a proper design will have to be more generic, and it would require more details. How many more details are required really depends on how accurate the simulation should be.

In my opinion, processor models should be able to describe how decoders work via tablegen.
For example, target should be able to declare:

• the number of available decoders
• the features of each decoder
  • The "maximum number of bytes" that a decoder can peek from a byte window during a cycle).
  • How many uOp can be generated in a cycle; etc.

Depending on how accurate we want to be, we may also need to model some properties of (what AMD calls) the "Instruction Byte Buffer" (IBB).
An accurate simulation requires that the decoder stage keeps track of which instruction byte window is active during a cycle, and which byte offset should be used by decoders (that is the offset from the last successful decoded instruction). Without that knowledge we lose some accuracy (i.e. we don't accurately model the throughput from the decoders).

If we decide that we don't want to go to that level of details, we still need to keep into account that processors may implement loop caches.
MCA should allow users to specify whether they want to simulate fetches from the instruction cache or from a hardware loop buffer (if available at decoding stage). The latter would provide a different throughput, and it would also be subject to different limitations than the decoders. I understand that this may not be useful for bdver2 (or btver2 FWIW). However, it would be useful for pretty much all modern Intel processors, and Zen.

The assumption that microcoded instructions always decode to more than 2 uOPs is a good default assumption. However, it would be nicer if processor models were able to override that quantity.

P.s.: if you want to accurately model frontend stalls caused by backpressure, then you need to use your pass in conjunction with the "MicroOpQueueStage" stage.

As a side note (not related to this patch). In terms of overall simulation: if we start adding more stages then we should consider at some point whether to increase the number of default iterations.

[lebedev.ri]

Thanks for taking a look.
Indeed, this is nowhere near review/integration ready,
i was hoping the patch's laid-back description
and the sheer amount of TODO/FIXME comments in the code made that obvious :)

[lebedev.ri]

In D75214#1895126, @andreadb wrote:

we still need to keep into account that processors may implement loop caches.

I agree this may be useful, but i currently don't believe that to be a blocker here.
We currently don't model that, and since we don't model loops at all,
it would be a whole new user-activatable mode.
I'm not sure it should be implemented in this very patch.

[andreadb]

In D75214#1911336, @lebedev.ri wrote:

In D75214#1895126, @andreadb wrote:

we still need to keep into account that processors may implement loop caches.

I agree this may be useful, but i currently don't believe that to be a blocker here.

It may not be a blocker for your prototype. However, a proper design should allow the definition of a loop buffer.

We currently don't model that, and since we don't model loops at all,
it would be a whole new user-activatable mode.

The idea is to let users decide whether they want to simulate fetches from the loop cache or not. A new pipeline option (example --simulate-loop-buffer; or something similar) could be implemented to enable that simulation. We could have that by default, the absence of that option implies that the normal legacy decoders path is enabled during the entire simulation.
So, I am not sure I understand what you mean by "we don't model loops at all".

I'm not sure it should be implemented in this very patch.

No problem.
Personally, I still consider this patch a "something not for review". I still want to see a proper RFC for this where to discuss requirements, etc.

-Andrea

llvm/include/llvm/MCA/CodeEmitter.h

class CodeEmitter {
   EncodingInfo getOrCreateEncodingInfo(unsigned MCID);
 
 public:
   CodeEmitter(const MCSubtargetInfo &ST, const MCAsmBackend &AB,
               const MCCodeEmitter &CE, ArrayRef<MCInst> S)
       : STI(ST), MAB(AB), MCE(CE), VecOS(Code), Sequence(S),
         Encodings(S.size()) {}
 
+  const MCInst &getInst(unsigned MCID) const { return Sequence[MCID]; }
+
   StringRef getEncoding(unsigned MCID) {
     EncodingInfo EI = getOrCreateEncodingInfo(MCID);
     return StringRef(&Code[EI.first], EI.second);
   }
 };
 
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_MCA_CODEEMITTER_H

llvm/include/llvm/MCA/HardwareUnits/InstructionBuffer.h

+//===---------------------- InstructionBuffer.h -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file simulates the hardware responsible for queueing instruction bytes
+/// between fetch unit and decode unit.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MCA_INSTRUCTION_BUFFER_H
+#define LLVM_MCA_INSTRUCTION_BUFFER_H
+
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/MCA/HardwareUnits/HardwareUnit.h"
+#include <vector>
+
+namespace llvm {
+namespace mca {
+
+class InstructionBuffer final : public HardwareUnit {
+public:
+  struct Buffer {
+    int NumBytesRemaining;
+    bool FetchCompleted;
+
+    Buffer();
+
+    // Can we read from this buffer yet?
+    bool isReady() const;
+    // Is this buffer actually alive, or we just didn't GC it yet?
+    bool isDepleted() const;
+  };
+
+private:
+  std::vector<Buffer> Buffers;
+  unsigned NumKnownDepletedBuffers;
+
+  // Per cycle
+  MutableArrayRef<Buffer> BuffersAvaliableToDecoderThisCycle;
+  unsigned BytesRemaining;
+  unsigned FetchesPerformed;
+
+  static constexpr unsigned MaxBuffersTotal = 16U;
+  static constexpr unsigned BytesPerBuffer = 16U;
+  static constexpr unsigned BytesFetchedPerCycle = 32U;
+  static constexpr unsigned BuffersFilledPerCycle =
+      BytesFetchedPerCycle / BytesPerBuffer;
+  static_assert(BuffersFilledPerCycle * BytesPerBuffer == BytesFetchedPerCycle,
+                "Fetch amount should be a multiple of buffer size");
+
+  static constexpr unsigned NumBuffersDecoderCanAccessPerCycle = 2U;
+  static constexpr unsigned NumBytesDecoderCanAccessPerCycle =
+      NumBuffersDecoderCanAccessPerCycle * BytesPerBuffer;
+  static constexpr unsigned MaxFetchesPerCycle = 4U;
+
+  bool canAccomodateInstructionFetch() const;
+  void enqueueInstructionFetch();
+  unsigned getNumDepletedBuffers() const;
+  void recalculateNumDepletedBuffers();
+
+  unsigned getNumOccupiedBuffers() const;
+  unsigned getNumVacantBuffers() const;
+
+public:
+  InstructionBuffer();
+
+  void cycleStart();
+
+  unsigned getNumBytesRemaining() const;
+  void consumeNumBytes(unsigned NumBytesToConsume);
+
+  void cycleEnd();
+};
+
+} // namespace mca
+} // namespace llvm
+
+#endif // LLVM_MCA_INSTRUCTION_BUFFER_H

llvm/include/llvm/MCA/InstrBuilder.h

 
 #ifndef LLVM_MCA_INSTRBUILDER_H
 #define LLVM_MCA_INSTRBUILDER_H
 
 #include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MCA/CodeEmitter.h"
 #include "llvm/MCA/Instruction.h"
 #include "llvm/MCA/Support.h"
 #include "llvm/Support/Error.h"
 
 namespace llvm {
 namespace mca {
 
 /// A builder class that knows how to construct Instruction objects.
class InstrBuilder {
   SmallVector<uint64_t, 8> ProcResourceMasks;
 
   DenseMap<unsigned short, std::unique_ptr<const InstrDesc>> Descriptors;
   DenseMap<const MCInst *, std::unique_ptr<const InstrDesc>> VariantDescriptors;
 
   bool FirstCallInst;
   bool FirstReturnInst;
 
-  Expected<const InstrDesc &> createInstrDescImpl(const MCInst &MCI);
-  Expected<const InstrDesc &> getOrCreateInstrDesc(const MCInst &MCI);
+  Expected<const InstrDesc &>
+  createInstrDescImpl(CodeEmitter &CE, unsigned MCID, const MCInst &MCI);
+  Expected<const InstrDesc &>
+  getOrCreateInstrDesc(CodeEmitter &CE, unsigned MCID, const MCInst &MCI);
 
   InstrBuilder(const InstrBuilder &) = delete;
   InstrBuilder &operator=(const InstrBuilder &) = delete;
 
   void populateWrites(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
   void populateReads(InstrDesc &ID, const MCInst &MCI, unsigned SchedClassID);
   Error verifyInstrDesc(const InstrDesc &ID, const MCInst &MCI) const;
 
 public:
   InstrBuilder(const MCSubtargetInfo &STI, const MCInstrInfo &MCII,
                const MCRegisterInfo &RI, const MCInstrAnalysis *IA);
 
   void clear() {
     VariantDescriptors.shrink_and_clear();
     FirstCallInst = true;
     FirstReturnInst = true;
   }
 
-  Expected<std::unique_ptr<Instruction>> createInstruction(const MCInst &MCI);
+  Expected<std::unique_ptr<Instruction>> createInstruction(CodeEmitter &CE,
+                                                           unsigned MCID);
 };
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_MCA_INSTRBUILDER_H

llvm/include/llvm/MCA/Instruction.h

struct InstrDesc {
   uint64_t UsedBuffers;
 
   // A bitmask of used processor resource units.
   uint64_t UsedProcResUnits;
 
   // A bitmask of used processor resource groups.
   uint64_t UsedProcResGroups;
 
+  // How many bytes does the endcoding of this instruction occupy.
+  unsigned EncodingByteLength;
+  // What latency does this instruction incur.
   unsigned MaxLatency;
   // Number of MicroOps for this instruction.
   unsigned NumMicroOps;
   // SchedClassID used to construct this InstrDesc.
   // This information is currently used by views to do fast queries on the
   // subtarget when computing the reciprocal throughput.
   unsigned SchedClassID;
 
public:
   InstructionBase(const InstrDesc &D) : Desc(D), IsOptimizableMove(false) {}
 
   SmallVectorImpl<WriteState> &getDefs() { return Defs; }
   const ArrayRef<WriteState> getDefs() const { return Defs; }
   SmallVectorImpl<ReadState> &getUses() { return Uses; }
   const ArrayRef<ReadState> getUses() const { return Uses; }
   const InstrDesc &getDesc() const { return Desc; }
 
+  unsigned getEncodingByteLength() const { return Desc.EncodingByteLength; }
   unsigned getLatency() const { return Desc.MaxLatency; }
   unsigned getNumMicroOps() const { return Desc.NumMicroOps; }
 
   bool hasDependentUsers() const {
     return any_of(Defs,
                   [](const WriteState &Def) { return Def.getNumUsers() > 0; });
   }
 

llvm/include/llvm/MCA/Stages/DecodeStage.h

+//===---------------------- DecodeStage.h -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines a stage that implements instruction decoding
+/// into micro-ops.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MCA_DECODE_STAGE_H
+#define LLVM_MCA_DECODE_STAGE_H
+
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/MCA/Instruction.h"
+#include "llvm/MCA/Stages/Stage.h"
+#include "llvm/Support/Error.h"
+#include <memory>
+
+namespace llvm {
+namespace mca {
+
+class InstructionBuffer;
+class SourceMgr;
+
+/// A stage that simulates an instruction decoder.
+class DecodeStage : public Stage {
+  InstructionBuffer &Buffer;
+  SourceMgr &SM;
+
+  SmallVector<std::unique_ptr<Instruction>, 16> Instructions;
+  unsigned NumRetired;
+
+  InstRef CurrentInstruction;
+
+  // Updates the program counter, and sets 'CurrentInstruction'.
+  void getNextInstructionFromSourceManager();
+
+  struct MicroOpEngine {
+    InstRef IR;
+    int MicroOpsLeftToGenerate;
+  } MicroOpEngine;
+  SmallVector<InstRef, 8> Decoders;
+
+  DecodeStage(const DecodeStage &Other) = delete;
+  DecodeStage &operator=(const DecodeStage &Other) = delete;
+
+  bool microOpDecodersHaveWorkToComplete() const;
+
+  // Is this instruction microcoded?
+  static bool IsMicroCoded(const InstRef &IR);
+
+  InstRef peekNextInstructionFromBuffer() const;
+  InstRef getNextInstructionFromBuffer();
+
+  // Would we be able to place this decoded (from it's byte encoding)
+  // instruction onto micro-op decoders?
+  bool canEnqueueForMicroOpDecoding(const InstRef &IR) const;
+
+  Error performMicroOpDecoding();
+
+public:
+  DecodeStage(InstructionBuffer &Buffer, SourceMgr &SM);
+
+  Error cycleStart() override;
+
+  // Are there any instructions currently being decoded?
+  bool hasWorkToComplete() const override;
+
+  // Would decoder be able to start decoding next instruction?
+  bool isAvailable(const InstRef & /*unused*/) const override;
+
+  // Start decoding the next instruction.
+  Error execute(InstRef & /*unused*/) override;
+
+  // Actually generate microcodes, if any.
+  Error cycleEnd() override;
+};
+
+} // namespace mca
+} // namespace llvm
+
+#endif // LLVM_MCA_DECODE_STAGE_H

llvm/include/llvm/MCA/Stages/EntryStage.h

class EntryStage final : public Stage {
   void getNextInstruction();
 
   EntryStage(const EntryStage &Other) = delete;
   EntryStage &operator=(const EntryStage &Other) = delete;
 
 public:
   EntryStage(SourceMgr &SM) : CurrentInstruction(), SM(SM), NumRetired(0) { }
 
-  bool isAvailable(const InstRef &IR) const override;
+  bool isAvailable(const InstRef & /*unused*/) const override;
   bool hasWorkToComplete() const override;
-  Error execute(InstRef &IR) override;
+  Error execute(InstRef & /*unused*/) override;
   Error cycleStart() override;
   Error cycleEnd() override;
 };
 
 } // namespace mca
 } // namespace llvm
 
 #endif // LLVM_MCA_FETCH_STAGE_H

llvm/include/llvm/MCA/Stages/FetchStage.h

+//===----------------- FetchStage.h ------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// FIXME
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MCA_FETCH_STAGE_H
+#define LLVM_MCA_FETCH_STAGE_H
+
+#include "llvm/MCA/Stages/Stage.h"
+#include "llvm/Support/Error.h"
+
+namespace llvm {
+namespace mca {
+
+class InstRef;
+class InstructionBuffer;
+
+class FetchStage final : public Stage {
+  InstructionBuffer &Buffer;
+
+  FetchStage(const FetchStage &Other) = delete;
+  FetchStage &operator=(const FetchStage &Other) = delete;
+
+public:
+  FetchStage(InstructionBuffer &Buffer);
+
+  Error cycleStart() override;
+
+  bool hasWorkToComplete() const override;
+
+  bool isAvailable(const InstRef & /*unused*/) const override;
+
+  Error execute(InstRef & /*unused*/) override;
+
+  Error cycleEnd() override;
+};
+
+} // namespace mca
+} // namespace llvm
+
+#endif // LLVM_MCA_FETCH_STAGE_H

llvm/lib/MCA/CMakeLists.txt

 add_llvm_component_library(LLVMMCA
   CodeEmitter.cpp
   Context.cpp
   HWEventListener.cpp
   HardwareUnits/HardwareUnit.cpp
+  HardwareUnits/InstructionBuffer.cpp
   HardwareUnits/LSUnit.cpp
   HardwareUnits/RegisterFile.cpp
   HardwareUnits/ResourceManager.cpp
   HardwareUnits/RetireControlUnit.cpp
   HardwareUnits/Scheduler.cpp
   InstrBuilder.cpp
   Instruction.cpp
   Pipeline.cpp
+  Stages/DecodeStage.cpp
   Stages/DispatchStage.cpp
   Stages/EntryStage.cpp
   Stages/ExecuteStage.cpp
+  Stages/FetchStage.cpp
   Stages/InstructionTables.cpp
   Stages/MicroOpQueueStage.cpp
   Stages/RetireStage.cpp
   Stages/Stage.cpp
   Support.cpp
 
   ADDITIONAL_HEADER_DIRS
   ${LLVM_MAIN_INCLUDE_DIR}/llvm/MCA
   )

llvm/lib/MCA/Context.cpp

 /// This file defines a class for holding ownership of various simulated
 /// hardware units.  A Context also provides a utility routine for constructing
 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
 /// stages.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MCA/Context.h"
+#include "llvm/MCA/HardwareUnits/InstructionBuffer.h"
 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
 #include "llvm/MCA/HardwareUnits/Scheduler.h"
+#include "llvm/MCA/Stages/DecodeStage.h"
 #include "llvm/MCA/Stages/DispatchStage.h"
 #include "llvm/MCA/Stages/EntryStage.h"
 #include "llvm/MCA/Stages/ExecuteStage.h"
+#include "llvm/MCA/Stages/FetchStage.h"
 #include "llvm/MCA/Stages/MicroOpQueueStage.h"
 #include "llvm/MCA/Stages/RetireStage.h"
 
 namespace llvm {
 namespace mca {
 
 std::unique_ptr<Pipeline>
 Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
   const MCSchedModel &SM = STI.getSchedModel();
 
   // Create the hardware units defining the backend.
+  auto IB = std::make_unique<InstructionBuffer>();
   auto RCU = std::make_unique<RetireControlUnit>(SM);
   auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
   auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
                                        Opts.StoreQueueSize, Opts.AssumeNoAlias);
   auto HWS = std::make_unique<Scheduler>(SM, *LSU);
 
   // Create the pipeline stages.
-  auto Fetch = std::make_unique<EntryStage>(SrcMgr);
+  auto Fetch = std::make_unique<FetchStage>(*IB);
+  auto Decode = std::make_unique<DecodeStage>(*IB, SrcMgr);
+  auto Entry = std::make_unique<EntryStage>(SrcMgr);
   auto Dispatch = std::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
                                                    *RCU, *PRF);
   auto Execute =
       std::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
   auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
 
   // Pass the ownership of all the hardware units to this Context.
+  // FIXME: parametrize and enable globally.
+  if (STI.getTargetTriple().getArch() == Triple::ArchType::x86_64 &&
+      STI.getCPU() == "bdver2")
+    addHardwareUnit(std::move(IB));
   addHardwareUnit(std::move(RCU));
   addHardwareUnit(std::move(PRF));
   addHardwareUnit(std::move(LSU));
   addHardwareUnit(std::move(HWS));
 
   // Build the pipeline.
   auto StagePipeline = std::make_unique<Pipeline>();
+  // FIXME: parametrize and enable globally.
+  if (STI.getTargetTriple().getArch() == Triple::ArchType::x86_64 &&
+      STI.getCPU() == "bdver2") {
     StagePipeline->appendStage(std::move(Fetch));
+    StagePipeline->appendStage(std::move(Decode));
+  } else
+    StagePipeline->appendStage(std::move(Entry));
   if (Opts.MicroOpQueueSize)
     StagePipeline->appendStage(std::make_unique<MicroOpQueueStage>(
         Opts.MicroOpQueueSize, Opts.DecodersThroughput));
   StagePipeline->appendStage(std::move(Dispatch));
   StagePipeline->appendStage(std::move(Execute));
   StagePipeline->appendStage(std::move(Retire));
   return StagePipeline;
 }
 
 } // namespace mca
 } // namespace llvm

llvm/lib/MCA/HardwareUnits/InstructionBuffer.cpp

+//===------------------ InstructionBuffer.cpp -------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the anchor for the base class that describes
+/// simulated hardware units.
+///
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MCA/HardwareUnits/InstructionBuffer.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/iterator_range.h"
+#include <algorithm>
+#include <cassert>
+#include <iterator>
+#include <numeric>
+
+namespace llvm {
+namespace mca {
+
+#define DEBUG_TYPE "llvm-mca"
+
+const unsigned InstructionBuffer::MaxBuffersTotal;
+const unsigned InstructionBuffer::BytesPerBuffer;
+const unsigned InstructionBuffer::BytesFetchedPerCycle;
+const unsigned InstructionBuffer::BuffersFilledPerCycle;
+const unsigned InstructionBuffer::NumBuffersDecoderCanAccessPerCycle;
+const unsigned InstructionBuffer::NumBytesDecoderCanAccessPerCycle;
+
+InstructionBuffer::InstructionBuffer() : NumKnownDepletedBuffers(0) {
+  // Really overallocate to avoid allocations at all.
+  Buffers.reserve(4 * MaxBuffersTotal);
+};
+
+InstructionBuffer::Buffer::Buffer()
+    : NumBytesRemaining(-1), FetchCompleted(false) {}
+
+bool InstructionBuffer::Buffer::isReady() const { return FetchCompleted; };
+
+bool InstructionBuffer::Buffer::isDepleted() const {
+  if (!isReady()) // Can't deplete a buffer that hasn't fetched yet.
+    return false;
+  assert(NumBytesRemaining >= 0 &&
+         "Shouldn't ever over-consume bytes in the buffer.");
+  return NumBytesRemaining == 0;
+};
+
+unsigned InstructionBuffer::getNumDepletedBuffers() const {
+#ifndef NDEBUG
+  llvm::for_each(ArrayRef<Buffer>(Buffers).take_front(NumKnownDepletedBuffers),
+                 [](const Buffer &Buf) {
+                   assert(Buf.isDepleted() &&
+                          "All buffers that we counted as depleted should "
+                          "actually be depleted.");
+                 });
+#endif
+
+  // Ignore known-depleted buffers.
+  auto Range =
+      make_range(Buffers.begin() + NumKnownDepletedBuffers, Buffers.end());
+  // And find first non-depleted one.
+  auto It = find_if(Range, [](const Buffer &Buf) { return !Buf.isDepleted(); });
+  // So how many depleted buffers there are total?
+  return std::distance(Buffers.begin(), It);
+}
+
+void InstructionBuffer::recalculateNumDepletedBuffers() {
+  NumKnownDepletedBuffers = getNumDepletedBuffers();
+}
+
+unsigned InstructionBuffer::getNumOccupiedBuffers() const {
+  unsigned NumOccupiedBuffers = Buffers.size() - getNumDepletedBuffers();
+  assert(NumOccupiedBuffers <= MaxBuffersTotal &&
+         "There is a hard limit on the buffer count.");
+  return NumOccupiedBuffers;
+}
+
+unsigned InstructionBuffer::getNumVacantBuffers() const {
+  int NumVacantBuffers = (int)MaxBuffersTotal - getNumOccupiedBuffers();
+  assert(NumVacantBuffers >= 0 && "Can't have negative count of empty buffers");
+  return NumVacantBuffers;
+}
+
+bool InstructionBuffer::canAccomodateInstructionFetch() const {
+  return getNumVacantBuffers() >= BuffersFilledPerCycle;
+}
+
+void InstructionBuffer::enqueueInstructionFetch() {
+  assert(canAccomodateInstructionFetch() &&
+         "Should not be performing fetch if can't accomodate for it.");
+
+  for (int NumBuffersFilled = 0; NumBuffersFilled != BuffersFilledPerCycle;
+       ++NumBuffersFilled)
+    Buffers.emplace_back();
+}
+
+void InstructionBuffer::cycleStart() {
+  // The fetches from previous cycle (if any) have completed by now.
+  for (Buffer &Buf : llvm::reverse(Buffers)) {
+    if (Buf.FetchCompleted)
+      break; // All the earlier buffers already completed fetching.
+    Buf.NumBytesRemaining = BytesPerBuffer;
+    Buf.FetchCompleted = true;
+  }
+
+  // And if can accomodate it, enqueue next fetch.
+  if (canAccomodateInstructionFetch())
+    enqueueInstructionFetch();
+
+  // Finally, which buffers can decoder actually look into this cycle?
+  BuffersAvaliableToDecoderThisCycle = Buffers;
+  assert(NumKnownDepletedBuffers == getNumDepletedBuffers() &&
+         "NumKnownDepletedBuffers should not be outdated yet.");
+  BuffersAvaliableToDecoderThisCycle =
+      BuffersAvaliableToDecoderThisCycle.drop_front(NumKnownDepletedBuffers)
+          .take_front(NumBuffersDecoderCanAccessPerCycle)
+          .take_while([](const Buffer &Buf) { return Buf.isReady(); });
+
+#ifndef NDEBUG
+  assert(BuffersAvaliableToDecoderThisCycle.size() <=
+             NumBuffersDecoderCanAccessPerCycle &&
+         "Predicate error?");
+  llvm::for_each(BuffersAvaliableToDecoderThisCycle, [](const Buffer &Buf) {
+    assert(Buf.isReady() && !Buf.isDepleted() &&
+           "Should have only selected buffers that finished fetching and "
+           "weren't depleted previously.");
+  });
+#endif
+
+  // The number of eligible buffers must match decoder's expectations exactly.
+  if (BuffersAvaliableToDecoderThisCycle.size() !=
+      NumBuffersDecoderCanAccessPerCycle)
+    BuffersAvaliableToDecoderThisCycle =
+        decltype(BuffersAvaliableToDecoderThisCycle)();
+
+  BytesRemaining =
+      std::accumulate(BuffersAvaliableToDecoderThisCycle.begin(),
+                      BuffersAvaliableToDecoderThisCycle.end(), unsigned(0),
+                      [](unsigned BytesRemainingSoFar, const Buffer &Buf) {
+                        return BytesRemainingSoFar + Buf.NumBytesRemaining;
+                      });
+  BytesRemaining = std::min(BytesRemaining, NumBytesDecoderCanAccessPerCycle);
+  FetchesPerformed = 0;
+}
+
+unsigned InstructionBuffer::getNumBytesRemaining() const {
+  return BytesRemaining;
+}
+
+void InstructionBuffer::consumeNumBytes(unsigned NumBytesToConsume) {
+  assert(NumBytesToConsume <= getNumBytesRemaining() &&
+         "Can't consume more bytes than avaliable.");
+
+  BytesRemaining -= NumBytesToConsume;
+  for (Buffer &Buf : BuffersAvaliableToDecoderThisCycle) {
+    unsigned NumBytesCanConsumeFromThisBuffer =
+        std::min((unsigned)Buf.NumBytesRemaining, NumBytesToConsume);
+    Buf.NumBytesRemaining -= NumBytesCanConsumeFromThisBuffer;
+    NumBytesToConsume -= NumBytesCanConsumeFromThisBuffer;
+  }
+  assert(NumBytesToConsume == 0 && "Consumption failure");
+
+  ++FetchesPerformed;
+  if (FetchesPerformed == MaxFetchesPerCycle)
+    BytesRemaining = 0; // ratelimit
+}
+
+void InstructionBuffer::cycleEnd() {
+  recalculateNumDepletedBuffers();
+  // If at least half of the buffers we're tracking are depleted, GC them.
+  if ((NumKnownDepletedBuffers * 2) >= Buffers.size()) {
+    // Erase buffers up to the first that hasn't been depleted.
+    Buffers.erase(Buffers.begin(), Buffers.begin() + NumKnownDepletedBuffers);
+    NumKnownDepletedBuffers = 0;
+  }
+}
+
+} // namespace mca
+} // namespace llvm

llvm/lib/MCA/InstrBuilder.cpp

 /// This file implements the InstrBuilder interface.
 ///
 //===----------------------------------------------------------------------===//
 
 #include "llvm/MCA/InstrBuilder.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/MC/MCInst.h"
+#include "llvm/MCA/CodeEmitter.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/WithColor.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define DEBUG_TYPE "llvm-mca"
 
 namespace llvm {
 namespace mca {
Error InstrBuilder::verifyInstrDesc(const InstrDesc &ID,
   // FIXME: see PR44797. We should revisit these checks and possibly move them
   // in CodeGenSchedule.cpp.
   StringRef Message = "found an inconsistent instruction that decodes to zero "
                       "opcodes and that consumes scheduler resources.";
   return make_error<InstructionError<MCInst>>(std::string(Message), MCI);
 }
 
 Expected<const InstrDesc &>
-InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
+InstrBuilder::createInstrDescImpl(CodeEmitter &CE, unsigned MCID,
+                                  const MCInst &MCI) {
   assert(STI.getSchedModel().hasInstrSchedModel() &&
          "Itineraries are not yet supported!");
 
   // Obtain the instruction descriptor from the opcode.
   unsigned short Opcode = MCI.getOpcode();
   const MCInstrDesc &MCDesc = MCII.get(Opcode);
   const MCSchedModel &SM = STI.getSchedModel();
 
return make_error<InstructionError<MCInst>>(
         MCI);
   }
 
   LLVM_DEBUG(dbgs() << "\n\t\tOpcode Name= " << MCII.getName(Opcode) << '\n');
   LLVM_DEBUG(dbgs() << "\t\tSchedClassID=" << SchedClassID << '\n');
 
   // Create a new empty descriptor.
   std::unique_ptr<InstrDesc> ID = std::make_unique<InstrDesc>();
+  ID->EncodingByteLength = CE.getEncoding(MCID).size();
+  assert(ID->EncodingByteLength != 0 &&
+         "Instruction with zero-byte-lenght encoding?");
   ID->NumMicroOps = SCDesc.NumMicroOps;
   ID->SchedClassID = SchedClassID;
 
   if (MCDesc.isCall() && FirstCallInst) {
     // We don't correctly model calls.
     WithColor::warning() << "found a call in the input assembly sequence.\n";
     WithColor::note() << "call instructions are not correctly modeled. "
                       << "Assume a latency of 100cy.\n";
if (!IsVariadic && !IsVariant) {
     return *Descriptors[MCI.getOpcode()];
   }
 
   VariantDescriptors[&MCI] = std::move(ID);
   return *VariantDescriptors[&MCI];
 }
 
 Expected<const InstrDesc &>
-InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
+InstrBuilder::getOrCreateInstrDesc(CodeEmitter &CE, unsigned MCID,
+                                   const MCInst &MCI) {
   if (Descriptors.find_as(MCI.getOpcode()) != Descriptors.end())
     return *Descriptors[MCI.getOpcode()];
 
   if (VariantDescriptors.find(&MCI) != VariantDescriptors.end())
     return *VariantDescriptors[&MCI];
 
-  return createInstrDescImpl(MCI);
+  return createInstrDescImpl(CE, MCID, MCI);
 }
 
 Expected<std::unique_ptr<Instruction>>
-InstrBuilder::createInstruction(const MCInst &MCI) {
-  Expected<const InstrDesc &> DescOrErr = getOrCreateInstrDesc(MCI);
+InstrBuilder::createInstruction(CodeEmitter &CE, unsigned MCID) {
+  const MCInst &MCI = CE.getInst(MCID);
+  Expected<const InstrDesc &> DescOrErr = getOrCreateInstrDesc(CE, MCID, MCI);
   if (!DescOrErr)
     return DescOrErr.takeError();
   const InstrDesc &D = *DescOrErr;
   std::unique_ptr<Instruction> NewIS = std::make_unique<Instruction>(D);
 
   // Check if this is a dependency breaking instruction.
   APInt Mask;
 

llvm/lib/MCA/Pipeline.cpp

Error Pipeline::runCycle() {
   Error Err = ErrorSuccess();
   // Update stages before we start processing new instructions.
   for (auto I = Stages.rbegin(), E = Stages.rend(); I != E && !Err; ++I) {
     const std::unique_ptr<Stage> &S = *I;
     Err = S->cycleStart();
   }
 
   // Now fetch and execute new instructions.
-  InstRef IR;
+  InstRef IR; // placeholder, not actually used.
   Stage &FirstStage = *Stages[0];
   while (!Err && FirstStage.isAvailable(IR))
     Err = FirstStage.execute(IR);
 
   // Update stages in preparation for a new cycle.
   for (const std::unique_ptr<Stage> &S : Stages) {
     Err = S->cycleEnd();
     if (Err)

llvm/lib/MCA/Stages/DecodeStage.cpp

+//===---------------------- DecodeStage.cpp ---------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the DecodeStage.
+///
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MCA/Stages/DecodeStage.h"
+#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/iterator_range.h"
+#include "llvm/MCA/HardwareUnits/InstructionBuffer.h"
+#include "llvm/MCA/SourceMgr.h"
+#include <algorithm>
+#include <cassert>
+#include <iterator>
+#include <numeric>
+#include <utility>
+
+namespace llvm {
+namespace mca {
+
+#define DEBUG_TYPE "llvm-mca"
+
+DecodeStage::DecodeStage(InstructionBuffer &Buffer_, SourceMgr &SM_)
+    : Buffer(Buffer_), SM(SM_), NumRetired(0) {}
+
+void DecodeStage::getNextInstructionFromSourceManager() {
+  assert(!CurrentInstruction && "There is already an instruction to process!");
+  if (!SM.hasNext())
+    return;
+  SourceRef SR = SM.peekNext();
+  std::unique_ptr<Instruction> Inst = std::make_unique<Instruction>(SR.second);
+  CurrentInstruction = InstRef(SR.first, Inst.get());
+  Instructions.emplace_back(std::move(Inst));
+  SM.updateNext();
+}
+
+llvm::Error DecodeStage::cycleStart() {
+  if (!CurrentInstruction)
+    getNextInstructionFromSourceManager();
+  return llvm::ErrorSuccess();
+}
+
+bool DecodeStage::microOpDecodersHaveWorkToComplete() const {
+  return MicroOpEngine.IR || std::any_of(Decoders.begin(), Decoders.end(),
+                                         [](const InstRef &IR) { return IR; });
+}
+
+bool DecodeStage::hasWorkToComplete() const {
+  return static_cast<bool>(CurrentInstruction) ||
+         microOpDecodersHaveWorkToComplete();
+}
+
+bool DecodeStage::IsMicroCoded(const InstRef &IR) {
+  // FIXME: parametrize.
+  return IR.getInstruction()->getDesc().NumMicroOps > 2;
+}
+
+InstRef DecodeStage::peekNextInstructionFromBuffer() const {
+  if (!CurrentInstruction)
+    return InstRef();
+
+  if (Buffer.getNumBytesRemaining() <
+      CurrentInstruction.getInstruction()->getEncodingByteLength())
+    return InstRef();
+
+  return CurrentInstruction;
+}
+
+bool DecodeStage::canEnqueueForMicroOpDecoding(const InstRef &IR) const {
+  // If we are currently decoding microcoded instruction,
+  // we can't start decoding *anything* else.
+  if (MicroOpEngine.IR)
+    return false;
+
+  if (IsMicroCoded(IR)) {
+    // We can not start decoding microcoded instruction until
+    // we finish decoding *all* preceding instructions.
+    return !microOpDecodersHaveWorkToComplete();
+  }
+
+  // There are only 4 decoders.
+  // FIXME: parametrize.
+  if (std::count_if(Decoders.begin(), Decoders.end(),
+                    [](const InstRef &IR) { return IR; }) >= 4)
+    return false;
+
+  // FIXME: parametrize. It can be more complex than that.
+  unsigned WouldBeNumMicroOpsTotal =
+      std::accumulate(Decoders.begin(), Decoders.end(),
+                      IR.getInstruction()->getDesc().NumMicroOps,
+                      [](unsigned NumMicroOpsSoFar, const InstRef &IR) {
+                        if (const Instruction *Instr = IR.getInstruction())
+                          NumMicroOpsSoFar += Instr->getDesc().NumMicroOps;
+                        return NumMicroOpsSoFar;
+                      });
+  // We can at most generate 4 microops per cycle.
+  // That is, we can generate 2-2/2-1-1/1-1-1-1.
+  return WouldBeNumMicroOpsTotal <= 4;
+}
+
+bool DecodeStage::isAvailable(const InstRef & /*unused*/) const {
+  InstRef IR = peekNextInstructionFromBuffer();
+  if (!IR)
+    return false;
+
+  return canEnqueueForMicroOpDecoding(IR);
+};
+
+InstRef DecodeStage::getNextInstructionFromBuffer() {
+  InstRef IR = peekNextInstructionFromBuffer();
+  assert(IR && "No next instruction?");
+  Buffer.consumeNumBytes(IR.getInstruction()->getEncodingByteLength());
+  return IR;
+}
+
+Error DecodeStage::execute(InstRef & /*unused*/) {
+  assert(isAvailable(InstRef()) &&
+         "Should not start decoding instruction unless we are ready to.");
+
+  InstRef IR = getNextInstructionFromBuffer();
+
+  // Move the program counter.
+  CurrentInstruction.invalidate();
+  getNextInstructionFromSourceManager();
+
+  if (IsMicroCoded(IR)) {
+    assert(Decoders.empty() && !MicroOpEngine.IR &&
+           "Must not start decoding microcoded instruction if the decoder is "
+           "already occupied.");
+
+    MicroOpEngine.IR = IR;
+    MicroOpEngine.MicroOpsLeftToGenerate =
+        IR.getInstruction()->getDesc().NumMicroOps;
+    return llvm::ErrorSuccess();
+  }
+
+  assert(!MicroOpEngine.IR &&
+         "Must not start decoding non-microcoded instruction if already "
+         "decoding microcoded instruction.");
+  Decoders.emplace_back(IR);
+  return llvm::ErrorSuccess();
+}
+
+Error DecodeStage::performMicroOpDecoding() {
+  if (!microOpDecodersHaveWorkToComplete())
+    return llvm::ErrorSuccess();
+
+  if (InstRef &IR = MicroOpEngine.IR) {
+    assert(Decoders.empty() &&
+           "Microcoded instruction must be decoded standalone");
+
+    // Is next stage ready to recieve all the microcodes?
+    if (!checkNextStage(IR))
+      return llvm::ErrorSuccess(); // Stall.
+
+    // Okay, start/continue generating microops.
+
+    // FIXME: is that so for BdVer2?
+    // FIXME: parametrize.
+    MicroOpEngine.MicroOpsLeftToGenerate -= 2;
+    // Did we just finish generating microops for this Microcoded instruction?
+    if (MicroOpEngine.MicroOpsLeftToGenerate > 0)
+      return llvm::ErrorSuccess(); // More microops left to generate...
+
+    // Done decoding/generating.
+    if (llvm::Error Val = moveToTheNextStage(IR))
+      return Val;
+    IR.invalidate();
+    return llvm::ErrorSuccess();
+  }
+
+  // Okay, must be a normal instruction.
+  assert(!Decoders.empty() && "Should be decoding some plain instructions.");
+  for (InstRef &IR : Decoders) {
+    if (!IR)
+      continue;
+
+    // Is next stage ready to recieve microops of this decoded instruction?
+    if (!checkNextStage(IR))
+      break; // Stall.
+    // Done decoding/generating in a single cycle.
+    if (llvm::Error Val = moveToTheNextStage(IR))
+      return Val;
+    IR.invalidate();
+  }
+
+  return llvm::ErrorSuccess();
+}
+
+Error DecodeStage::cycleEnd() {
+  if (Error E = performMicroOpDecoding())
+    return E;
+
+  // Find the first instruction which hasn't been fully decoded.
+  auto DIt = find_if(Decoders, [](const InstRef &IR) { return IR; });
+  unsigned NumDecoded = std::distance(Decoders.begin(), DIt);
+  // Erase instructions up to the first that hasn't been decoded.
+  if ((NumDecoded * 2) >= Decoders.size())
+    Decoders.erase(Decoders.begin(), DIt);
+
+  // Find the first instruction which hasn't been retired.
+  auto RRange = make_range(&Instructions[NumRetired], Instructions.end());
+  auto RIt = find_if(RRange, [](const std::unique_ptr<Instruction> &I) {
+    return !I->isRetired();
+  });
+  NumRetired = std::distance(Instructions.begin(), RIt);
+  // Erase instructions up to the first that hasn't been retired.
+  if ((NumRetired * 2) >= Instructions.size()) {
+    Instructions.erase(Instructions.begin(), RIt);
+    NumRetired = 0;
+  }
+
+  return llvm::ErrorSuccess();
+}
+
+} // namespace mca
+} // namespace llvm

llvm/lib/MCA/Stages/EntryStage.cpp

if (!SM.hasNext())
     return;
   SourceRef SR = SM.peekNext();
   std::unique_ptr<Instruction> Inst = std::make_unique<Instruction>(SR.second);
   CurrentInstruction = InstRef(SR.first, Inst.get());
   Instructions.emplace_back(std::move(Inst));
   SM.updateNext();
 }
 
-llvm::Error EntryStage::execute(InstRef & /*unused */) {
+llvm::Error EntryStage::execute(InstRef & /*unused*/) {
   assert(CurrentInstruction && "There is no instruction to process!");
   if (llvm::Error Val = moveToTheNextStage(CurrentInstruction))
     return Val;
 
   // Move the program counter.
   CurrentInstruction.invalidate();
   getNextInstruction();
   return llvm::ErrorSuccess();

llvm/lib/MCA/Stages/FetchStage.cpp

+//===--------------------- FetchStage.cpp -----------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+/// \file
+///
+/// This file defines the FetchStage.
+///
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MCA/Stages/FetchStage.h"
+#include "llvm/MCA/HardwareUnits/InstructionBuffer.h"
+#include "llvm/MCA/Instruction.h"
+#include <cassert>
+
+namespace llvm {
+namespace mca {
+
+#define DEBUG_TYPE "llvm-mca"
+
+FetchStage::FetchStage(InstructionBuffer &Buffer_) : Buffer(Buffer_) {}
+
+Error FetchStage::cycleStart() {
+  Buffer.cycleStart();
+  return llvm::ErrorSuccess();
+}
+
+bool FetchStage::hasWorkToComplete() const {
+  // This stage's sole purpose is keeping the Instruction Byte Buffer filled,
+  // so we effectively never run out of work, let other stages answer instead.
+  return false;
+}
+
+bool FetchStage::isAvailable(const InstRef & /*unused*/) const {
+  // Just passthrough the question to the next stage, is it ready?
+  return checkNextStage(InstRef());
+};
+
+Error FetchStage::execute(InstRef & /*unused*/) {
+  assert(isAvailable(InstRef()) &&
+         "Should not be executing if we don't have resources to do so.");
+
+  // Just passthrough to the next stage.
+  InstRef IR; // placeholder, not actually used.
+  if (llvm::Error Val = moveToTheNextStage(IR))
+    return Val;
+
+  return llvm::ErrorSuccess();
+}
+
+Error FetchStage::cycleEnd() {
+  Buffer.cycleEnd();
+  return llvm::ErrorSuccess();
+}
+
+} // namespace mca
+} // namespace llvm

llvm/test/tools/llvm-mca/X86/BdVer2/add-sequence.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1000 -timeline < %s | FileCheck %s
 
 add %eax, %ecx
 add %esi, %eax
 add %eax, %edx
 
 # CHECK:      Iterations:        1000
 # CHECK-NEXT: Instructions:      3000
-# CHECK-NEXT: Total Cycles:      3003
+# CHECK-NEXT: Total Cycles:      3004
 # CHECK-NEXT: Total uOps:        3000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               1.00
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %eax, %ecx
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %esi, %eax
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %eax, %edx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          01
+# CHECK-NEXT:                     0123456789          012
 # CHECK-NEXT: Index     0123456789          0123456789
 
-# CHECK:      [0,0]     DeER .    .    .    .    .    ..   addl %eax, %ecx
-# CHECK-NEXT: [0,1]     DeER .    .    .    .    .    ..   addl %esi, %eax
-# CHECK-NEXT: [0,2]     D==eER    .    .    .    .    ..   addl %eax, %edx
-# CHECK-NEXT: [1,0]     D====eER  .    .    .    .    ..   addl %eax, %ecx
-# CHECK-NEXT: [1,1]     .D=eE--R  .    .    .    .    ..   addl %esi, %eax
-# CHECK-NEXT: [1,2]     .D===eER  .    .    .    .    ..   addl %eax, %edx
-# CHECK-NEXT: [2,0]     .D=====eER.    .    .    .    ..   addl %eax, %ecx
-# CHECK-NEXT: [2,1]     .D=====eER.    .    .    .    ..   addl %esi, %eax
-# CHECK-NEXT: [2,2]     . D======eER   .    .    .    ..   addl %eax, %edx
-# CHECK-NEXT: [3,0]     . D========eER .    .    .    ..   addl %eax, %ecx
-# CHECK-NEXT: [3,1]     . D======eE--R .    .    .    ..   addl %esi, %eax
-# CHECK-NEXT: [3,2]     . D========eER .    .    .    ..   addl %eax, %edx
-# CHECK-NEXT: [4,0]     .  D=========eER    .    .    ..   addl %eax, %ecx
-# CHECK-NEXT: [4,1]     .  D=========eER    .    .    ..   addl %esi, %eax
-# CHECK-NEXT: [4,2]     .  D===========eER  .    .    ..   addl %eax, %edx
-# CHECK-NEXT: [5,0]     .  D=============eER.    .    ..   addl %eax, %ecx
-# CHECK-NEXT: [5,1]     .   D==========eE--R.    .    ..   addl %esi, %eax
-# CHECK-NEXT: [5,2]     .   D============eER.    .    ..   addl %eax, %edx
-# CHECK-NEXT: [6,0]     .   D==============eER   .    ..   addl %eax, %ecx
-# CHECK-NEXT: [6,1]     .   D==============eER   .    ..   addl %esi, %eax
-# CHECK-NEXT: [6,2]     .    D===============eER .    ..   addl %eax, %edx
-# CHECK-NEXT: [7,0]     .    D=================eER    ..   addl %eax, %ecx
-# CHECK-NEXT: [7,1]     .    D===============eE--R    ..   addl %esi, %eax
-# CHECK-NEXT: [7,2]     .    D=================eER    ..   addl %eax, %edx
-# CHECK-NEXT: [8,0]     .    .D==================eER  ..   addl %eax, %ecx
-# CHECK-NEXT: [8,1]     .    .D==================eER  ..   addl %esi, %eax
-# CHECK-NEXT: [8,2]     .    .D====================eER..   addl %eax, %edx
-# CHECK-NEXT: [9,0]     .    .D======================eER   addl %eax, %ecx
-# CHECK-NEXT: [9,1]     .    . D===================eE--R   addl %esi, %eax
-# CHECK-NEXT: [9,2]     .    . D=====================eER   addl %eax, %edx
+# CHECK:      [0,0]     .DeER.    .    .    .    .    . .   addl  %eax, %ecx
+# CHECK-NEXT: [0,1]     .DeER.    .    .    .    .    . .   addl  %esi, %eax
+# CHECK-NEXT: [0,2]     .D==eER   .    .    .    .    . .   addl  %eax, %edx
+# CHECK-NEXT: [1,0]     .D====eER .    .    .    .    . .   addl  %eax, %ecx
+# CHECK-NEXT: [1,1]     . D=eE--R .    .    .    .    . .   addl  %esi, %eax
+# CHECK-NEXT: [1,2]     . D===eER .    .    .    .    . .   addl  %eax, %edx
+# CHECK-NEXT: [2,0]     . D=====eER    .    .    .    . .   addl  %eax, %ecx
+# CHECK-NEXT: [2,1]     . D=====eER    .    .    .    . .   addl  %esi, %eax
+# CHECK-NEXT: [2,2]     .  D======eER  .    .    .    . .   addl  %eax, %edx
+# CHECK-NEXT: [3,0]     .  D========eER.    .    .    . .   addl  %eax, %ecx
+# CHECK-NEXT: [3,1]     .  D======eE--R.    .    .    . .   addl  %esi, %eax
+# CHECK-NEXT: [3,2]     .  D========eER.    .    .    . .   addl  %eax, %edx
+# CHECK-NEXT: [4,0]     .   D=========eER   .    .    . .   addl  %eax, %ecx
+# CHECK-NEXT: [4,1]     .   D=========eER   .    .    . .   addl  %esi, %eax
+# CHECK-NEXT: [4,2]     .   D===========eER .    .    . .   addl  %eax, %edx
+# CHECK-NEXT: [5,0]     .   D=============eER    .    . .   addl  %eax, %ecx
+# CHECK-NEXT: [5,1]     .    D==========eE--R    .    . .   addl  %esi, %eax
+# CHECK-NEXT: [5,2]     .    D============eER    .    . .   addl  %eax, %edx
+# CHECK-NEXT: [6,0]     .    D==============eER  .    . .   addl  %eax, %ecx
+# CHECK-NEXT: [6,1]     .    D==============eER  .    . .   addl  %esi, %eax
+# CHECK-NEXT: [6,2]     .    .D===============eER.    . .   addl  %eax, %edx
+# CHECK-NEXT: [7,0]     .    .D=================eER   . .   addl  %eax, %ecx
+# CHECK-NEXT: [7,1]     .    .D===============eE--R   . .   addl  %esi, %eax
+# CHECK-NEXT: [7,2]     .    .D=================eER   . .   addl  %eax, %edx
+# CHECK-NEXT: [8,0]     .    . D==================eER . .   addl  %eax, %ecx
+# CHECK-NEXT: [8,1]     .    . D==================eER . .   addl  %esi, %eax
+# CHECK-NEXT: [8,2]     .    . D====================eER .   addl  %eax, %edx
+# CHECK-NEXT: [9,0]     .    . D======================eER   addl  %eax, %ecx
+# CHECK-NEXT: [9,1]     .    .  D===================eE--R   addl  %esi, %eax
+# CHECK-NEXT: [9,2]     .    .  D=====================eER   addl  %eax, %edx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     10    12.0   2.0    0.0       addl %eax, %ecx
 # CHECK-NEXT: 1.     10    10.7   1.8    1.0       addl %esi, %eax
 # CHECK-NEXT: 2.     10    12.5   1.0    0.0       addl %eax, %edx
 # CHECK-NEXT:        10    11.7   1.6    0.3       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-1.s

 
 ## The AND can start immediately after the LZCNT.
 ## It doesn't need to wait for the IMUL.
 and   %rcx, %rax
 bsf   %rax, %rcx
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      900
+# CHECK-NEXT: Total Cycles:      901
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.11
 # CHECK-NEXT: IPC:               0.44
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      6     4.00                        imulq $5, %rcx, %rax
 # CHECK-NEXT:  2      2     2.00                        lzcntl  %ecx, %eax
 # CHECK-NEXT:  1      1     1.00                        andq  %rcx, %rax
 # CHECK-NEXT:  6      3     3.00                        bsfq  %rax, %rcx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01234567
+# CHECK-NEXT:                     012345678
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeER .    . .   imulq  $5, %rcx, %rax
-# CHECK-NEXT: [0,1]     DeeE----R .    . .   lzcntl %ecx, %eax
-# CHECK-NEXT: [0,2]     D==eE---R .    . .   andq %rcx, %rax
-# CHECK-NEXT: [0,3]     .D==eeeER .    . .   bsfq %rax, %rcx
-# CHECK-NEXT: [1,0]     . D====eeeeeeER. .   imulq  $5, %rcx, %rax
-# CHECK-NEXT: [1,1]     .  D======eeE-R. .   lzcntl %ecx, %eax
-# CHECK-NEXT: [1,2]     .  D========eER. .   andq %rcx, %rax
-# CHECK-NEXT: [1,3]     .   D========eeeER   bsfq %rax, %rcx
+# CHECK:      [0,0]     .DeeeeeeER.    .  .   imulq $5, %rcx, %rax
+# CHECK-NEXT: [0,1]     .DeeE----R.    .  .   lzcntl  %ecx, %eax
+# CHECK-NEXT: [0,2]     .D==eE---R.    .  .   andq  %rcx, %rax
+# CHECK-NEXT: [0,3]     .   DeeeER.    .  .   bsfq  %rax, %rcx
+# CHECK-NEXT: [1,0]     .    D==eeeeeeER  .   imulq $5, %rcx, %rax
+# CHECK-NEXT: [1,1]     .    .D====eeE-R  .   lzcntl  %ecx, %eax
+# CHECK-NEXT: [1,2]     .    .D======eER  .   andq  %rcx, %rax
+# CHECK-NEXT: [1,3]     .    .   D====eeeER   bsfq  %rax, %rcx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     3.0    0.5    0.0       imulq  $5, %rcx, %rax
-# CHECK-NEXT: 1.     2     4.0    2.0    2.5       lzcntl %ecx, %eax
-# CHECK-NEXT: 2.     2     6.0    0.0    1.5       andq %rcx, %rax
-# CHECK-NEXT: 3.     2     6.0    0.0    0.0       bsfq %rax, %rcx
-# CHECK-NEXT:        2     4.8    0.6    1.0       <total>
+# CHECK-NEXT: 0.     2     2.0    0.5    0.0       imulq  $5, %rcx, %rax
+# CHECK-NEXT: 1.     2     3.0    2.0    2.5       lzcntl %ecx, %eax
+# CHECK-NEXT: 2.     2     5.0    0.0    1.5       andq %rcx, %rax
+# CHECK-NEXT: 3.     2     3.0    0.0    0.0       bsfq %rax, %rcx
+# CHECK-NEXT:        2     3.3    0.6    1.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-2.s

 vaddps %ymm3, %ymm1, %ymm4
 vaddps %ymm3, %ymm1, %ymm4
 vaddps %ymm3, %ymm1, %ymm4
 vaddps %ymm3, %ymm1, %ymm4
 vandps %xmm4, %xmm1, %xmm0
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      1800
-# CHECK-NEXT: Total Cycles:      3203
+# CHECK-NEXT: Total Cycles:      3204
 # CHECK-NEXT: Total uOps:        3400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.06
 # CHECK-NEXT: IPC:               0.56
 # CHECK-NEXT: Block RThroughput: 25.5
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  2      5     1.00                        vaddps  %ymm3, %ymm1, %ymm4
 # CHECK-NEXT:  2      5     1.00                        vaddps  %ymm3, %ymm1, %ymm4
 # CHECK-NEXT:  2      5     1.00                        vaddps  %ymm3, %ymm1, %ymm4
 # CHECK-NEXT:  2      5     1.00                        vaddps  %ymm3, %ymm1, %ymm4
 # CHECK-NEXT:  1      2     1.00                        vandps  %xmm4, %xmm1, %xmm0
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789          0123456789
-# CHECK-NEXT: Index     0123456789          0123456789          0123456789          0123456
+# CHECK-NEXT: Index     0123456789          0123456789          0123456789          01234567
 
-# CHECK:      [0,0]     DeeeeeeeeeER   .    .    .    .    .    .    .    .    .    .    ..   vdivps  %ymm0, %ymm1, %ymm3
-# CHECK-NEXT: [0,1]     DeeeeeE----R   .    .    .    .    .    .    .    .    .    .    ..   vaddps  %xmm0, %xmm1, %xmm3
-# CHECK-NEXT: [0,2]     .D====eeeeeER  .    .    .    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,3]     .D======eeeeeER.    .    .    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,4]     . D=======eeeeeER   .    .    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,5]     . D=========eeeeeER .    .    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,6]     .  D==========eeeeeER    .    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,7]     .  D============eeeeeER  .    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,8]     .   D=============eeeeeER.    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,9]     .   D==============eeeeeER    .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,10]    .    D==============eeeeeER   .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,11]    .    D===============eeeeeER  .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,12]    .    .D===============eeeeeER .    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,13]    .    .D================eeeeeER.    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,14]    .    . D================eeeeeER    .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,15]    .    . D=================eeeeeER   .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,16]    .    .  D=================eeeeeER  .    .    .    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [0,17]    .    .  D======================eeER.    .    .    .    .    .    ..   vandps  %xmm4, %xmm1, %xmm0
-# CHECK-NEXT: [1,0]     .    .   D=======================eeeeeeeeeER .    .    .    .    ..   vdivps  %ymm0, %ymm1, %ymm3
-# CHECK-NEXT: [1,1]     .    .   D=======================eeeeeE----R .    .    .    .    ..   vaddps  %xmm0, %xmm1, %xmm3
-# CHECK-NEXT: [1,2]     .    .    D===========================eeeeeER.    .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,3]     .    .    D=============================eeeeeER   .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,4]     .    .    .D==============================eeeeeER .    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,5]     .    .    .D================================eeeeeER    .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,6]     .    .    . D=================================eeeeeER  .    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,7]     .    .    . D===================================eeeeeER.    .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,8]     .    .    .  D====================================eeeeeER   .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,9]     .    .    .  D=====================================eeeeeER  .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,10]    .    .    .   D=====================================eeeeeER .    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,11]    .    .    .   D======================================eeeeeER.    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,12]    .    .    .    D======================================eeeeeER    ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,13]    .    .    .    D=======================================eeeeeER   ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,14]    .    .    .    .D=======================================eeeeeER  ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,15]    .    .    .    .D========================================eeeeeER ..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,16]    .    .    .    . D========================================eeeeeER..   vaddps  %ymm3, %ymm1, %ymm4
-# CHECK-NEXT: [1,17]    .    .    .    . D=============================================eeER   vandps  %xmm4, %xmm1, %xmm0
+# CHECK:      [0,0]     .DeeeeeeeeeER  .    .    .    .    .    .    .    .    .    .    . .   vdivps %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: [0,1]     .DeeeeeE----R  .    .    .    .    .    .    .    .    .    .    . .   vaddps %xmm0, %xmm1, %xmm3
+# CHECK-NEXT: [0,2]     . D====eeeeeER .    .    .    .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,3]     . D======eeeeeER    .    .    .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,4]     .  D=======eeeeeER  .    .    .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,5]     .  D=========eeeeeER.    .    .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,6]     .   D==========eeeeeER   .    .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,7]     .   D============eeeeeER .    .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,8]     .    D=============eeeeeER    .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,9]     .    D==============eeeeeER   .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,10]    .    .D==============eeeeeER  .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,11]    .    .D===============eeeeeER .    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,12]    .    . D===============eeeeeER.    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,13]    .    . D================eeeeeER    .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,14]    .    .  D================eeeeeER   .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,15]    .    .  D=================eeeeeER  .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,16]    .    .   D=================eeeeeER .    .    .    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [0,17]    .    .   D======================eeER    .    .    .    .    .    . .   vandps %xmm4, %xmm1, %xmm0
+# CHECK-NEXT: [1,0]     .    .    D=======================eeeeeeeeeER.    .    .    .    . .   vdivps %ymm0, %ymm1, %ymm3
+# CHECK-NEXT: [1,1]     .    .    D=======================eeeeeE----R.    .    .    .    . .   vaddps %xmm0, %xmm1, %xmm3
+# CHECK-NEXT: [1,2]     .    .    .D===========================eeeeeER    .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,3]     .    .    .D=============================eeeeeER  .    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,4]     .    .    . D==============================eeeeeER.    .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,5]     .    .    . D================================eeeeeER   .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,6]     .    .    .  D=================================eeeeeER .    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,7]     .    .    .  D===================================eeeeeER    .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,8]     .    .    .   D====================================eeeeeER  .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,9]     .    .    .   D=====================================eeeeeER .    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,10]    .    .    .    D=====================================eeeeeER.    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,11]    .    .    .    D======================================eeeeeER    . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,12]    .    .    .    .D======================================eeeeeER   . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,13]    .    .    .    .D=======================================eeeeeER  . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,14]    .    .    .    . D=======================================eeeeeER . .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,15]    .    .    .    . D========================================eeeeeER. .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,16]    .    .    .    .  D========================================eeeeeER .   vaddps %ymm3, %ymm1, %ymm4
+# CHECK-NEXT: [1,17]    .    .    .    .  D=============================================eeER   vandps %xmm4, %xmm1, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/BdVer2/clear-super-register-3.s

 movsd  (%eax), %xmm0
 addps  %xmm0, %xmm0
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      300
-# CHECK-NEXT: Total Cycles:      655
+# CHECK-NEXT: Total Cycles:      656
 # CHECK-NEXT: Total uOps:        300
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.46
 # CHECK-NEXT: IPC:               0.46
 # CHECK-NEXT: Block RThroughput: 6.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      9     4.50                        sqrtss  %xmm0, %xmm0
 # CHECK-NEXT:  1      5     1.50    *                   movss (%eax), %xmm0
 # CHECK-NEXT:  1      5     1.00                        addps %xmm0, %xmm0
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          012
+# CHECK-NEXT: Index     0123456789          0123
 
-# CHECK:      [0,0]     D=eeeeeeeeeER  .    . .   sqrtss  %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     DeeeeeE-----R  .    . .   movss (%eax), %xmm0
-# CHECK-NEXT: [0,2]     D======eeeeeER .    . .   addps %xmm0, %xmm0
-# CHECK-NEXT: [1,0]     D===========eeeeeeeeeER   sqrtss  %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     .D==eeeeeE------------R   movss (%eax), %xmm0
-# CHECK-NEXT: [1,2]     .D=========eeeeeE-----R   addps %xmm0, %xmm0
+# CHECK:      [0,0]     .D=eeeeeeeeeER .    .  .   sqrtss %xmm0, %xmm0
+# CHECK-NEXT: [0,1]     .DeeeeeE-----R .    .  .   movss  (%eax), %xmm0
+# CHECK-NEXT: [0,2]     .D======eeeeeER.    .  .   addps  %xmm0, %xmm0
+# CHECK-NEXT: [1,0]     .D===========eeeeeeeeeER   sqrtss %xmm0, %xmm0
+# CHECK-NEXT: [1,1]     . D==eeeeeE------------R   movss  (%eax), %xmm0
+# CHECK-NEXT: [1,2]     . D=========eeeeeE-----R   addps  %xmm0, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     7.0    1.0    0.0       sqrtss %xmm0, %xmm0
 # CHECK-NEXT: 1.     2     2.0    2.0    8.5       movss  (%eax), %xmm0
 # CHECK-NEXT: 2.     2     8.5    1.5    2.5       addps  %xmm0, %xmm0
 # CHECK-NEXT:        2     5.8    1.5    3.7       <total>
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      300
-# CHECK-NEXT: Total Cycles:      655
+# CHECK-NEXT: Total Cycles:      656
 # CHECK-NEXT: Total uOps:        300
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.46
 # CHECK-NEXT: IPC:               0.46
 # CHECK-NEXT: Block RThroughput: 6.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      9     4.50                        sqrtsd  %xmm0, %xmm0
 # CHECK-NEXT:  1      5     1.50    *                   movsd (%eax), %xmm0
 # CHECK-NEXT:  1      5     1.00                        addps %xmm0, %xmm0
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          012
+# CHECK-NEXT: Index     0123456789          0123
 
-# CHECK:      [0,0]     D=eeeeeeeeeER  .    . .   sqrtsd  %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     DeeeeeE-----R  .    . .   movsd (%eax), %xmm0
-# CHECK-NEXT: [0,2]     D======eeeeeER .    . .   addps %xmm0, %xmm0
-# CHECK-NEXT: [1,0]     D===========eeeeeeeeeER   sqrtsd  %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     .D==eeeeeE------------R   movsd (%eax), %xmm0
-# CHECK-NEXT: [1,2]     .D=========eeeeeE-----R   addps %xmm0, %xmm0
+# CHECK:      [0,0]     .D=eeeeeeeeeER .    .  .   sqrtsd %xmm0, %xmm0
+# CHECK-NEXT: [0,1]     .DeeeeeE-----R .    .  .   movsd  (%eax), %xmm0
+# CHECK-NEXT: [0,2]     .D======eeeeeER.    .  .   addps  %xmm0, %xmm0
+# CHECK-NEXT: [1,0]     .D===========eeeeeeeeeER   sqrtsd %xmm0, %xmm0
+# CHECK-NEXT: [1,1]     . D==eeeeeE------------R   movsd  (%eax), %xmm0
+# CHECK-NEXT: [1,2]     . D=========eeeeeE-----R   addps  %xmm0, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     7.0    1.0    0.0       sqrtsd %xmm0, %xmm0
 # CHECK-NEXT: 1.     2     2.0    2.0    8.5       movsd  (%eax), %xmm0
 # CHECK-NEXT: 2.     2     8.5    1.5    2.5       addps  %xmm0, %xmm0
 # CHECK-NEXT:        2     5.8    1.5    3.7       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-cmp.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s
 
 # Perf stat reports an IPC of 1.97 for this block of code.
 
 # The CMP instruction doesn't depend on the value of EAX.  It can set the flags
 # without having to read the inputs.
 
 cmp %eax, %eax
 cmovae %ebx, %eax
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      3000
-# CHECK-NEXT: Total Cycles:      2253
+# CHECK-NEXT: Total Cycles:      2254
 # CHECK-NEXT: Total uOps:        3000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.33
 # CHECK-NEXT: IPC:               1.33
 # CHECK-NEXT: Block RThroughput: 1.5
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  -      -      -      -      -     1.50   1.50    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     cmpl %eax, %eax
 # CHECK-NEXT:  -      -      -      -      -     0.50   0.50    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     cmovael  %ebx, %eax
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     01234567
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DeER . .   cmpl %eax, %eax
-# CHECK-NEXT: [0,1]     D==eER .   cmovael  %ebx, %eax
-# CHECK-NEXT: [1,0]     DeE--R .   cmpl %eax, %eax
-# CHECK-NEXT: [1,1]     D===eER.   cmovael  %ebx, %eax
-# CHECK-NEXT: [2,0]     .D=eE-R.   cmpl %eax, %eax
-# CHECK-NEXT: [2,1]     .D===eER   cmovael  %ebx, %eax
+# CHECK:      [0,0]     .DeER.  .   cmpl  %eax, %eax
+# CHECK-NEXT: [0,1]     .D==eER .   cmovael %ebx, %eax
+# CHECK-NEXT: [1,0]     .DeE--R .   cmpl  %eax, %eax
+# CHECK-NEXT: [1,1]     .D===eER.   cmovael %ebx, %eax
+# CHECK-NEXT: [2,0]     . D=eE-R.   cmpl  %eax, %eax
+# CHECK-NEXT: [2,1]     . D===eER   cmovael %ebx, %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     1.3    1.3    1.0       cmpl %eax, %eax
 # CHECK-NEXT: 1.     3     3.7    0.3    0.0       cmovael  %ebx, %eax
 # CHECK-NEXT:        3     2.5    0.8    0.5       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpeq.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s
 
 # perf stat reports an IPC of 2.00 for this block of code.
 
 # All of the vector packed compares from this test are dependency breaking
 # instructions. That means, there is no RAW dependency between any of the
 # instructions, and the code can be fully parallelized in hardware.
 
 vpcmpeqb %xmm0, %xmm0, %xmm1
 vpcmpeqw %xmm1, %xmm1, %xmm2
 vpcmpeqd %xmm2, %xmm2, %xmm3
 vpcmpeqq %xmm3, %xmm3, %xmm0
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      6000
-# CHECK-NEXT: Total Cycles:      6003
+# CHECK-NEXT: Total Cycles:      6004
 # CHECK-NEXT: Total uOps:        6000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               1.00
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     1.00    -      -      -      -      -      -      -     vpcmpeqb %xmm0, %xmm0, %xmm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     1.00    -      -      -      -      -      -      -     vpcmpeqw %xmm1, %xmm1, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     1.00    -      -      -      -      -      -      -      -     vpcmpeqd %xmm2, %xmm2, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     1.00    -      -      -      -      -      -      -      -     vpcmpeqq %xmm3, %xmm3, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01234
+# CHECK-NEXT:                     012345
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.    .   .   vpcmpeqb  %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [0,1]     D==eeER   .   .   vpcmpeqw  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [0,2]     DeeE--R   .   .   vpcmpeqd  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [0,3]     D==eeER   .   .   vpcmpeqq  %xmm3, %xmm3, %xmm0
-# CHECK-NEXT: [1,0]     .D===eeER .   .   vpcmpeqb  %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [1,1]     .D=====eeER   .   vpcmpeqw  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [1,2]     .D===eeE--R   .   vpcmpeqd  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [1,3]     .D=====eeER   .   vpcmpeqq  %xmm3, %xmm3, %xmm0
-# CHECK-NEXT: [2,0]     . D======eeER .   vpcmpeqb  %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [2,1]     . D========eeER   vpcmpeqw  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [2,2]     . D======eeE--R   vpcmpeqd  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [2,3]     . D========eeER   vpcmpeqq  %xmm3, %xmm3, %xmm0
+# CHECK:      [0,0]     .DeeER    .    .   vpcmpeqb %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [0,1]     .D==eeER  .    .   vpcmpeqw %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [0,2]     .DeeE--R  .    .   vpcmpeqd %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [0,3]     .D==eeER  .    .   vpcmpeqq %xmm3, %xmm3, %xmm0
+# CHECK-NEXT: [1,0]     . D===eeER.    .   vpcmpeqb %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [1,1]     . D=====eeER   .   vpcmpeqw %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [1,2]     . D===eeE--R   .   vpcmpeqd %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [1,3]     . D=====eeER   .   vpcmpeqq %xmm3, %xmm3, %xmm0
+# CHECK-NEXT: [2,0]     .  D======eeER .   vpcmpeqb %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [2,1]     .  D========eeER   vpcmpeqw %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [2,2]     .  D======eeE--R   vpcmpeqd %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [2,3]     .  D========eeER   vpcmpeqq %xmm3, %xmm3, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     4.0    4.0    0.0       vpcmpeqb %xmm0, %xmm0, %xmm1
 # CHECK-NEXT: 1.     3     6.0    6.0    0.0       vpcmpeqw %xmm1, %xmm1, %xmm2
 # CHECK-NEXT: 2.     3     4.0    4.0    2.0       vpcmpeqd %xmm2, %xmm2, %xmm3
 # CHECK-NEXT: 3.     3     6.0    0.0    0.0       vpcmpeqq %xmm3, %xmm3, %xmm0
 # CHECK-NEXT:        3     5.0    3.5    0.5       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-pcmpgt.s

 
 vpcmpgtb %xmm0, %xmm0, %xmm1
 vpcmpgtw %xmm1, %xmm1, %xmm2
 vpcmpgtd %xmm2, %xmm2, %xmm3
 vpcmpgtq %xmm3, %xmm3, %xmm0
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      6000
-# CHECK-NEXT: Total Cycles:      1504
+# CHECK-NEXT: Total Cycles:      1505
 # CHECK-NEXT: Total uOps:        6000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    3.99
 # CHECK-NEXT: IPC:               3.99
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vpcmpgtb %xmm0, %xmm0, %xmm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vpcmpgtw %xmm1, %xmm1, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vpcmpgtd %xmm2, %xmm2, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpcmpgtq %xmm3, %xmm3, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     0123456
+# CHECK-NEXT: Index     01234567
 
-# CHECK:      [0,0]     DR   ..   vpcmpgtb  %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [0,1]     DR   ..   vpcmpgtw  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [0,2]     DR   ..   vpcmpgtd  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [0,3]     DeeER..   vpcmpgtq  %xmm3, %xmm3, %xmm0
-# CHECK-NEXT: [1,0]     .D--R..   vpcmpgtb  %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [1,1]     .D--R..   vpcmpgtw  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [1,2]     .D--R..   vpcmpgtd  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [1,3]     .DeeER.   vpcmpgtq  %xmm3, %xmm3, %xmm0
-# CHECK-NEXT: [2,0]     . D--R.   vpcmpgtb  %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [2,1]     . D--R.   vpcmpgtw  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [2,2]     . D--R.   vpcmpgtd  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [2,3]     . DeeER   vpcmpgtq  %xmm3, %xmm3, %xmm0
+# CHECK:      [0,0]     .DR  . .   vpcmpgtb %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [0,1]     .DR  . .   vpcmpgtw %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [0,2]     .DR  . .   vpcmpgtd %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [0,3]     .DeeER .   vpcmpgtq %xmm3, %xmm3, %xmm0
+# CHECK-NEXT: [1,0]     . D--R .   vpcmpgtb %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [1,1]     . D--R .   vpcmpgtw %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [1,2]     . D--R .   vpcmpgtd %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [1,3]     . DeeER.   vpcmpgtq %xmm3, %xmm3, %xmm0
+# CHECK-NEXT: [2,0]     .  D--R.   vpcmpgtb %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [2,1]     .  D--R.   vpcmpgtw %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [2,2]     .  D--R.   vpcmpgtd %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [2,3]     .  DeeER   vpcmpgtq %xmm3, %xmm3, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     0.0    0.0    1.3       vpcmpgtb %xmm0, %xmm0, %xmm1
 # CHECK-NEXT: 1.     3     0.0    0.0    1.3       vpcmpgtw %xmm1, %xmm1, %xmm2
 # CHECK-NEXT: 2.     3     0.0    0.0    1.3       vpcmpgtd %xmm2, %xmm2, %xmm3
 # CHECK-NEXT: 3.     3     1.0    1.0    0.0       vpcmpgtq %xmm3, %xmm3, %xmm0
 # CHECK-NEXT:        3     0.3    0.3    1.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s
 
 # perf stat reports an IPC of 1.00 for this code block.
 
 # Although both SBB are dependency breaking instructions, there is still an
 # implicit dependency on EFLAGS which limits the ILP. So, the hardware backend
 # can only execute one instruction per cycle.
 
 sbb %edx, %edx
 sbb %eax, %eax
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      3000
-# CHECK-NEXT: Total Cycles:      3003
+# CHECK-NEXT: Total Cycles:      3004
 # CHECK-NEXT: Total uOps:        3000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               1.00
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  -      -      -      -      -     2.00   2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     sbbl %edx, %edx
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     sbbl %eax, %eax
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     012345678
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .  .   sbbl  %edx, %edx
-# CHECK-NEXT: [0,1]     D=eER.  .   sbbl  %eax, %eax
-# CHECK-NEXT: [1,0]     D==eER  .   sbbl  %edx, %edx
-# CHECK-NEXT: [1,1]     D===eER .   sbbl  %eax, %eax
-# CHECK-NEXT: [2,0]     .D===eER.   sbbl  %edx, %edx
-# CHECK-NEXT: [2,1]     .D====eER   sbbl  %eax, %eax
+# CHECK:      [0,0]     .DeER.   .   sbbl %edx, %edx
+# CHECK-NEXT: [0,1]     .D=eER   .   sbbl %eax, %eax
+# CHECK-NEXT: [1,0]     .D==eER  .   sbbl %edx, %edx
+# CHECK-NEXT: [1,1]     .D===eER .   sbbl %eax, %eax
+# CHECK-NEXT: [2,0]     . D===eER.   sbbl %edx, %edx
+# CHECK-NEXT: [2,1]     . D====eER   sbbl %eax, %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     2.7    0.3    0.0       sbbl %edx, %edx
 # CHECK-NEXT: 1.     3     3.7    0.0    0.0       sbbl %eax, %eax
 # CHECK-NEXT:        3     3.2    0.2    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/dependency-breaking-sbb-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=3 -iterations=1500 < %s | FileCheck %s
 
 # perf stat reports a throughput of 1.51 IPC for this block of code.
 
 # The SBB does not depend on the value of register EAX. That means, it doesn't
 # have to wait for the IMUL to write-back on EAX. However, it still depends on
 # the ADD for EFLAGS.
 
 imul %edx, %eax
 add %edx, %edx
 sbb %eax, %eax
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      4500
-# CHECK-NEXT: Total Cycles:      4014
+# CHECK-NEXT: Total Cycles:      4015
 # CHECK-NEXT: Total uOps:        4500
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.12
 # CHECK-NEXT: IPC:               1.12
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -     imull  %edx, %eax
 # CHECK-NEXT:  -      -      -      -      -     1.33   0.67    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %edx, %edx
 # CHECK-NEXT:  -      -      -      -      -     1.33   0.67    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     sbbl %eax, %eax
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01234
+# CHECK-NEXT:                     012345
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     D==eeeeER .   .   imull %edx, %eax
-# CHECK-NEXT: [0,1]     DeE-----R .   .   addl  %edx, %edx
-# CHECK-NEXT: [0,2]     D===eE--R .   .   sbbl  %eax, %eax
-# CHECK-NEXT: [1,0]     D=====eeeeER  .   imull %edx, %eax
-# CHECK-NEXT: [1,1]     .DeE-------R  .   addl  %edx, %edx
-# CHECK-NEXT: [1,2]     .D====eE---R  .   sbbl  %eax, %eax
-# CHECK-NEXT: [2,0]     .D=======eeeeER   imull %edx, %eax
-# CHECK-NEXT: [2,1]     .D==eE--------R   addl  %edx, %edx
-# CHECK-NEXT: [2,2]     . D=====eE----R   sbbl  %eax, %eax
+# CHECK:      [0,0]     .D==eeeeER.    .   imull  %edx, %eax
+# CHECK-NEXT: [0,1]     .DeE-----R.    .   addl %edx, %edx
+# CHECK-NEXT: [0,2]     .D===eE--R.    .   sbbl %eax, %eax
+# CHECK-NEXT: [1,0]     .D=====eeeeER  .   imull  %edx, %eax
+# CHECK-NEXT: [1,1]     . DeE-------R  .   addl %edx, %edx
+# CHECK-NEXT: [1,2]     . D====eE---R  .   sbbl %eax, %eax
+# CHECK-NEXT: [2,0]     . D=======eeeeER   imull  %edx, %eax
+# CHECK-NEXT: [2,1]     . D==eE--------R   addl %edx, %edx
+# CHECK-NEXT: [2,2]     .  D=====eE----R   sbbl %eax, %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     5.7    2.0    0.0       imull  %edx, %eax
 # CHECK-NEXT: 1.     3     1.7    0.7    6.7       addl %edx, %edx
 # CHECK-NEXT: 2.     3     5.0    2.7    3.0       sbbl %eax, %eax
 # CHECK-NEXT:        3     4.1    1.8    3.2       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/dependent-pmuld-paddd.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=500 -timeline < %s | FileCheck %s
 
 vpmuld %xmm0, %xmm0, %xmm1
 vpaddd %xmm1, %xmm1, %xmm0
 vpaddd %xmm0, %xmm0, %xmm3
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      1500
-# CHECK-NEXT: Total Cycles:      3005
+# CHECK-NEXT: Total Cycles:      3006
 # CHECK-NEXT: Total uOps:        1500
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.50
 # CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     1.00    -     1.00    -      -      -      -      -      -      -      -     vpmuldq  %xmm0, %xmm0, %xmm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpaddd %xmm1, %xmm1, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     2.00    -      -      -      -     1.00    -      -      -      -      -      -      -     vpaddd %xmm0, %xmm0, %xmm3
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789          0123456789
-# CHECK-NEXT: Index     0123456789          0123456789          0123456789          01234
+# CHECK-NEXT: Index     0123456789          0123456789          0123456789          012345
 
-# CHECK:      [0,0]     DeeeeER   .    .    .    .    .    .    .    .    .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [0,1]     D====eeER .    .    .    .    .    .    .    .    .    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [0,2]     D======eeER    .    .    .    .    .    .    .    .    .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [1,0]     D======eeeeER  .    .    .    .    .    .    .    .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [1,1]     .D=========eeER.    .    .    .    .    .    .    .    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [1,2]     .D===========eeER   .    .    .    .    .    .    .    .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [2,0]     .D===========eeeeER .    .    .    .    .    .    .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [2,1]     .D===============eeER    .    .    .    .    .    .    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [2,2]     . D================eeER  .    .    .    .    .    .    .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [3,0]     . D================eeeeER.    .    .    .    .    .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [3,1]     . D====================eeER   .    .    .    .    .    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [3,2]     . D======================eeER .    .    .    .    .    .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [4,0]     .  D=====================eeeeER    .    .    .    .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [4,1]     .  D=========================eeER  .    .    .    .    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [4,2]     .  D===========================eeER.    .    .    .    .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [5,0]     .  D===========================eeeeER   .    .    .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [5,1]     .   D==============================eeER .    .    .    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [5,2]     .   D================================eeER    .    .    .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [6,0]     .   D================================eeeeER  .    .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [6,1]     .   D====================================eeER.    .    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [6,2]     .    D=====================================eeER   .    .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [7,0]     .    D=====================================eeeeER .    .    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [7,1]     .    D=========================================eeER    .    .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [7,2]     .    D===========================================eeER  .    .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [8,0]     .    .D==========================================eeeeER.    .   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [8,1]     .    .D==============================================eeER   .   .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [8,2]     .    .D================================================eeER .   .   vpaddd  %xmm0, %xmm0, %xmm3
-# CHECK-NEXT: [9,0]     .    .D================================================eeeeER   .   vpmuldq %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [9,1]     .    . D===================================================eeER .   vpaddd  %xmm1, %xmm1, %xmm0
-# CHECK-NEXT: [9,2]     .    . D=====================================================eeER   vpaddd  %xmm0, %xmm0, %xmm3
+# CHECK:      [0,0]     .DeeeeER  .    .    .    .    .    .    .    .    .    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [0,1]     .D====eeER.    .    .    .    .    .    .    .    .    .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [0,2]     .D======eeER   .    .    .    .    .    .    .    .    .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [1,0]     .D======eeeeER .    .    .    .    .    .    .    .    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [1,1]     . D=========eeER    .    .    .    .    .    .    .    .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [1,2]     . D===========eeER  .    .    .    .    .    .    .    .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [2,0]     . D===========eeeeER.    .    .    .    .    .    .    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [2,1]     . D===============eeER   .    .    .    .    .    .    .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [2,2]     .  D================eeER .    .    .    .    .    .    .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [3,0]     .  D================eeeeER    .    .    .    .    .    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [3,1]     .  D====================eeER  .    .    .    .    .    .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [3,2]     .  D======================eeER.    .    .    .    .    .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [4,0]     .   D=====================eeeeER   .    .    .    .    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [4,1]     .   D=========================eeER .    .    .    .    .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [4,2]     .   D===========================eeER    .    .    .    .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [5,0]     .   D===========================eeeeER  .    .    .    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [5,1]     .    D==============================eeER.    .    .    .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [5,2]     .    D================================eeER   .    .    .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [6,0]     .    D================================eeeeER .    .    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [6,1]     .    D====================================eeER    .    .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [6,2]     .    .D=====================================eeER  .    .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [7,0]     .    .D=====================================eeeeER.    .    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [7,1]     .    .D=========================================eeER   .    .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [7,2]     .    .D===========================================eeER .    .    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [8,0]     .    . D==========================================eeeeER    .    .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [8,1]     .    . D==============================================eeER  .    .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [8,2]     .    . D================================================eeER.    .   vpaddd %xmm0, %xmm0, %xmm3
+# CHECK-NEXT: [9,0]     .    . D================================================eeeeER   .   vpmuldq  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [9,1]     .    .  D===================================================eeER .   vpaddd %xmm1, %xmm1, %xmm0
+# CHECK-NEXT: [9,2]     .    .  D=====================================================eeER   vpaddd %xmm0, %xmm0, %xmm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     10    25.0   0.1    0.0       vpmuldq  %xmm0, %xmm0, %xmm1
 # CHECK-NEXT: 1.     10    28.7   0.0    0.0       vpaddd %xmm1, %xmm1, %xmm0
 # CHECK-NEXT: 2.     10    30.5   0.0    0.0       vpaddd %xmm0, %xmm0, %xmm3
 # CHECK-NEXT:        10    28.1   0.0    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/dot-product.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=300 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 vmulps   %xmm0, %xmm1, %xmm2
 vhaddps  %xmm2, %xmm2, %xmm3
 vhaddps  %xmm3, %xmm3, %xmm4
 
 # CHECK:      Iterations:        300
 # CHECK-NEXT: Instructions:      900
-# CHECK-NEXT: Total Cycles:      1709
+# CHECK-NEXT: Total Cycles:      1683
 # CHECK-NEXT: Total uOps:        2100
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.23
+# CHECK-NEXT: uOps Per Cycle:    1.25
 # CHECK-NEXT: IPC:               0.53
 # CHECK-NEXT: Block RThroughput: 5.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad

 # CHECK-NEXT: [15]  - PdFPXBR
 # CHECK-NEXT: [16.0] - PdLoad
 # CHECK-NEXT: [16.1] - PdLoad
 # CHECK-NEXT: [17]  - PdMul
 # CHECK-NEXT: [18]  - PdStore
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]
-# CHECK-NEXT:  -      -      -      -      -      -      -      -     5.50   5.50    -      -      -      -     2.00   1.00    -      -      -      -      -      -      -
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     5.52   5.48    -      -      -      -     2.00   1.00    -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
-# CHECK-NEXT:  -      -      -      -      -      -      -      -     0.49   0.51    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  -      -      -      -      -      -      -      -     2.53   2.47    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vhaddps  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT:  -      -      -      -      -      -      -      -     2.48   2.52    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vhaddps  %xmm3, %xmm3, %xmm4
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     0.50   0.50    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     2.13   2.87    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vhaddps  %xmm2, %xmm2, %xmm3
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     2.88   2.12    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vhaddps  %xmm3, %xmm3, %xmm4
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          01234
-# CHECK-NEXT: Index     0123456789          0123456789
+# CHECK-NEXT:                     0123456789          0123456789
+# CHECK-NEXT: Index     0123456789          0123456789          0
 
-# CHECK:      [0,0]     DeeeeeER  .    .    .    .    .   .   vmulps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [0,1]     D=====eeeeeeeeeeeER .    .    .   .   vhaddps %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [0,2]     .D===============eeeeeeeeeeeER.   .   vhaddps %xmm3, %xmm3, %xmm4
-# CHECK-NEXT: [1,0]     .DeeeeeE---------------------R.   .   vmulps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [1,1]     . D====eeeeeeeeeeeE----------R.   .   vhaddps %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [1,2]     .  D==============eeeeeeeeeeeER   .   vhaddps %xmm3, %xmm3, %xmm4
-# CHECK-NEXT: [2,0]     .  DeeeeeE--------------------R   .   vmulps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [2,1]     .   D======eeeeeeeeeeeE-------R   .   vhaddps %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: [2,2]     .    D================eeeeeeeeeeeER   vhaddps %xmm3, %xmm3, %xmm4
+# CHECK:      [0,0]     .DeeeeeER .    .    .    .    .    .    .   vmulps  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [0,1]     .  D===eeeeeeeeeeeER.    .    .    .    .   vhaddps %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [0,2]     .    D============eeeeeeeeeeeER    .    .   vhaddps %xmm3, %xmm3, %xmm4
+# CHECK-NEXT: [1,0]     .    .DeeeeeE-----------------R    .    .   vmulps  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [1,1]     .    .  D===eeeeeeeeeeeE------R    .    .   vhaddps %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [1,2]     .    .    D============eeeeeeeeeeeER    .   vhaddps %xmm3, %xmm3, %xmm4
+# CHECK-NEXT: [2,0]     .    .    .DeeeeeE-----------------R    .   vmulps  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [2,1]     .    .    .  D===eeeeeeeeeeeE------R    .   vhaddps %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: [2,2]     .    .    .    D============eeeeeeeeeeeER   vhaddps %xmm3, %xmm3, %xmm4
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     1.0    1.0    13.7      vmulps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1.     3     6.0    0.7    5.7       vhaddps  %xmm2, %xmm2, %xmm3
-# CHECK-NEXT: 2.     3     16.0   0.0    0.0       vhaddps  %xmm3, %xmm3, %xmm4
-# CHECK-NEXT:        3     7.7    0.6    6.4       <total>
+# CHECK-NEXT: 0.     3     1.0    1.0    11.3      vmulps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.     3     4.0    0.0    4.0       vhaddps  %xmm2, %xmm2, %xmm3
+# CHECK-NEXT: 2.     3     13.0   0.0    0.0       vhaddps  %xmm3, %xmm3, %xmm4
+# CHECK-NEXT:        3     6.0    0.3    5.1       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s
 
 vshufps $0, %xmm0, %xmm1, %xmm1
 vhaddps (%rdi), %xmm1, %xmm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      20
+# CHECK-NEXT: Total Cycles:      22
 # CHECK-NEXT: Total uOps:        5
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.25
-# CHECK-NEXT: IPC:               0.10
+# CHECK-NEXT: uOps Per Cycle:    0.23
+# CHECK-NEXT: IPC:               0.09
 # CHECK-NEXT: Block RThroughput: 3.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      2     1.00                        vshufps $0, %xmm0, %xmm1, %xmm1
 # CHECK-NEXT:  4      16    2.50    *                   vhaddps (%rdi), %xmm1, %xmm2
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     0123456789          01
 
-# CHECK:      [0,0]     DeeER.    .    .   .   vshufps  $0, %xmm0, %xmm1, %xmm1
-# CHECK-NEXT: [0,1]     .DeeeeeeeeeeeeeeeeER   vhaddps  (%rdi), %xmm1, %xmm2
+# CHECK:      [0,0]     .DeeER    .    .    ..   vshufps  $0, %xmm0, %xmm1, %xmm1
+# CHECK-NEXT: [0,1]     .  DeeeeeeeeeeeeeeeeER   vhaddps  (%rdi), %xmm1, %xmm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vshufps  $0, %xmm0, %xmm1, %xmm1
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       vhaddps  (%rdi), %xmm1, %xmm2
 # CHECK-NEXT:        1     1.0    1.0    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/hadd-read-after-ld-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s
 
 vshufps $0, %xmm0, %xmm1, %xmm1
 vhaddps (%rdi), %ymm1, %ymm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      20
+# CHECK-NEXT: Total Cycles:      25
 # CHECK-NEXT: Total uOps:        11
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.55
-# CHECK-NEXT: IPC:               0.10
+# CHECK-NEXT: uOps Per Cycle:    0.44
+# CHECK-NEXT: IPC:               0.08
 # CHECK-NEXT: Block RThroughput: 5.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      2     1.00                        vshufps $0, %xmm0, %xmm1, %xmm1
 # CHECK-NEXT:  10     16    4.00    *                   vhaddps (%rdi), %ymm1, %ymm2
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     0123456789          01234
 
-# CHECK:      [0,0]     DeeER.    .    .   .   vshufps  $0, %xmm0, %xmm1, %xmm1
-# CHECK-NEXT: [0,1]     .DeeeeeeeeeeeeeeeeER   vhaddps  (%rdi), %ymm1, %ymm2
+# CHECK:      [0,0]     .DeeER    .    .    .   .   vshufps $0, %xmm0, %xmm1, %xmm1
+# CHECK-NEXT: [0,1]     .    .DeeeeeeeeeeeeeeeeER   vhaddps (%rdi), %ymm1, %ymm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vshufps  $0, %xmm0, %xmm1, %xmm1
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       vhaddps  (%rdi), %ymm1, %ymm2
 # CHECK-NEXT:        1     1.0    1.0    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-1.s

 vpinsrq $0, %rax, %xmm0, %xmm0
 vpinsrq $1, %rax, %xmm0, %xmm0
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      1000
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        2000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -     vpinsrb  $0, %eax, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -      -     vpinsrb  $1, %eax, %xmm0, %xmm0
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      1000
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        2000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -     vpinsrw  $0, %eax, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -      -     vpinsrw  $1, %eax, %xmm0, %xmm0
 
 # CHECK:      [2] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      1000
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        2000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -     vpinsrd  $0, %eax, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -      -     vpinsrd  $1, %eax, %xmm0, %xmm0
 
 # CHECK:      [3] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      1000
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        2000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:

llvm/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-2.s

 # LLVM-MCA-BEGIN
 movq %rcx, %xmm0
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.50
 # CHECK-NEXT: IPC:               0.25
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -     vcvtsi2ss  %ecx, %xmm0, %xmm0
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.50
 # CHECK-NEXT: IPC:               0.25
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -     vcvtsi2sd  %ecx, %xmm0, %xmm0
 
 # CHECK:      [2] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.50
 # CHECK-NEXT: IPC:               0.25
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -     cvtsi2ss %ecx, %xmm0
 
 # CHECK:      [3] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      2003
+# CHECK-NEXT: Total Cycles:      2004
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.50
 # CHECK-NEXT: IPC:               0.25
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -     cvtsi2sd %ecx, %xmm0
 
 # CHECK:      [4] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      512
+# CHECK-NEXT: Total Cycles:      513
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.95
-# CHECK-NEXT: IPC:               0.98
+# CHECK-NEXT: IPC:               0.97
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   1.00    -      -      -      -     0.50   0.50    -      -      -      -      -      -      -     movd %ecx, %xmm0
 
 # CHECK:      [5] Code Region
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      500
-# CHECK-NEXT: Total Cycles:      512
+# CHECK-NEXT: Total Cycles:      513
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.95
-# CHECK-NEXT: IPC:               0.98
+# CHECK-NEXT: IPC:               0.97
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

llvm/test/tools/llvm-mca/X86/BdVer2/int-to-fpu-forwarding-3.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 add %eax, %eax
 vpinsrb $0, %eax, %xmm0, %xmm0
 vpinsrb $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Iterations:        500
 # CHECK-NEXT: Instructions:      1500
-# CHECK-NEXT: Total Cycles:      2014
+# CHECK-NEXT: Total Cycles:      2015
 # CHECK-NEXT: Total uOps:        2500
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.24
 # CHECK-NEXT: IPC:               0.74
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %eax, %eax
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -     vpinsrb  $0, %eax, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -      -      -      -      -     vpinsrb  $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          012345
+# CHECK-NEXT: Index     0123456789          0123456
 
-# CHECK:      [0,0]     DeER .    .    .    .    .   addl %eax, %eax
-# CHECK-NEXT: [0,1]     D===========eeER    .    .   vpinsrb  $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [0,2]     .D============eeER  .    .   vpinsrb  $1, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [1,0]     .DeE-------------R  .    .   addl %eax, %eax
-# CHECK-NEXT: [1,1]     . D=============eeER.    .   vpinsrb  $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [1,2]     . D===============eeER   .   vpinsrb  $1, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [2,0]     .  DeE---------------R   .   addl %eax, %eax
-# CHECK-NEXT: [2,1]     .  D================eeER .   vpinsrb  $0, %eax, %xmm0, %xmm0
-# CHECK-NEXT: [2,2]     .   D=================eeER   vpinsrb  $1, %eax, %xmm0, %xmm0
+# CHECK:      [0,0]     .DeER.    .    .    .    ..   addl  %eax, %eax
+# CHECK-NEXT: [0,1]     .D===========eeER   .    ..   vpinsrb $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [0,2]     . D============eeER .    ..   vpinsrb $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [1,0]     . DeE-------------R .    ..   addl  %eax, %eax
+# CHECK-NEXT: [1,1]     .  D=============eeER    ..   vpinsrb $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [1,2]     .  D===============eeER  ..   vpinsrb $1, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [2,0]     .   DeE---------------R  ..   addl  %eax, %eax
+# CHECK-NEXT: [2,1]     .   D================eeER..   vpinsrb $0, %eax, %xmm0, %xmm0
+# CHECK-NEXT: [2,2]     .    D=================eeER   vpinsrb $1, %eax, %xmm0, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     1.0    0.7    9.3       addl %eax, %eax
 # CHECK-NEXT: 1.     3     14.3   0.0    0.0       vpinsrb  $0, %eax, %xmm0, %xmm0
 # CHECK-NEXT: 2.     3     15.7   0.0    0.0       vpinsrb  $1, %eax, %xmm0, %xmm0
 # CHECK-NEXT:        3     10.3   0.2    3.1       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/load-store-alias.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=100 -timeline -timeline-max-iterations=1 -noalias=false < %s | FileCheck %s
 
 vmovaps (%rsi), %xmm0
 vmovaps %xmm0, (%rdi)
 vmovaps 16(%rsi), %xmm0
 vmovaps %xmm0, 16(%rdi)
 vmovaps 32(%rsi), %xmm0
 vmovaps %xmm0, 32(%rdi)
 vmovaps 48(%rsi), %xmm0
 vmovaps %xmm0, 48(%rdi)
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      800
-# CHECK-NEXT: Total Cycles:      2403
+# CHECK-NEXT: Total Cycles:      2404
 # CHECK-NEXT: Total uOps:        800
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.33
 # CHECK-NEXT: IPC:               0.33
 # CHECK-NEXT: Block RThroughput: 8.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   vmovaps  %xmm0, 16(%rdi)
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -     vmovaps  32(%rsi), %xmm0
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   vmovaps  %xmm0, 32(%rdi)
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     vmovaps  48(%rsi), %xmm0
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   vmovaps  %xmm0, 48(%rdi)
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0123456
+# CHECK-NEXT: Index     0123456789          01234567
 
-# CHECK:      [0,0]     DeeeeeER  .    .    .    ..   vmovaps (%rsi), %xmm0
-# CHECK-NEXT: [0,1]     D=====eER .    .    .    ..   vmovaps %xmm0, (%rdi)
-# CHECK-NEXT: [0,2]     D======eeeeeER .    .    ..   vmovaps 16(%rsi), %xmm0
-# CHECK-NEXT: [0,3]     D===========eER.    .    ..   vmovaps %xmm0, 16(%rdi)
-# CHECK-NEXT: [0,4]     .D===========eeeeeER.    ..   vmovaps 32(%rsi), %xmm0
-# CHECK-NEXT: [0,5]     .D================eER    ..   vmovaps %xmm0, 32(%rdi)
-# CHECK-NEXT: [0,6]     .D=================eeeeeER.   vmovaps 48(%rsi), %xmm0
-# CHECK-NEXT: [0,7]     .D======================eER   vmovaps %xmm0, 48(%rdi)
+# CHECK:      [0,0]     .DeeeeeER .    .    .    . .   vmovaps  (%rsi), %xmm0
+# CHECK-NEXT: [0,1]     .D=====eER.    .    .    . .   vmovaps  %xmm0, (%rdi)
+# CHECK-NEXT: [0,2]     .D======eeeeeER.    .    . .   vmovaps  16(%rsi), %xmm0
+# CHECK-NEXT: [0,3]     .D===========eER    .    . .   vmovaps  %xmm0, 16(%rdi)
+# CHECK-NEXT: [0,4]     . D===========eeeeeER    . .   vmovaps  32(%rsi), %xmm0
+# CHECK-NEXT: [0,5]     . D================eER   . .   vmovaps  %xmm0, 32(%rdi)
+# CHECK-NEXT: [0,6]     . D=================eeeeeER.   vmovaps  48(%rsi), %xmm0
+# CHECK-NEXT: [0,7]     . D======================eER   vmovaps  %xmm0, 48(%rdi)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/BdVer2/load-store-throughput.s

 movaps (%rdx), %xmm2
 movaps %xmm3, (%rbx)
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      306
+# CHECK-NEXT: Total Cycles:      307
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.31
-# CHECK-NEXT: IPC:               1.31
+# CHECK-NEXT: uOps Per Cycle:    1.30
+# CHECK-NEXT: IPC:               1.30
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.00           *            movb  %spl, (%rax)
 # CHECK-NEXT:  1      5     1.00    *                   movb  (%rcx), %bpl
 # CHECK-NEXT:  1      5     1.00    *                   movb  (%rdx), %sil
 # CHECK-NEXT:  1      1     1.00           *            movb  %dil, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
-# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (84.0%)
+# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (83.7%)
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              34  (11.1%)
-# CHECK-NEXT:  1,              172  (56.2%)
-# CHECK-NEXT:  2,              86  (28.1%)
+# CHECK-NEXT:  0,              35  (11.4%)
+# CHECK-NEXT:  1,              172  (56.0%)
+# CHECK-NEXT:  2,              86  (28.0%)
 # CHECK-NEXT:  4,              14  (4.6%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          5  (1.6%)
-# CHECK-NEXT:  1,          202  (66.0%)
-# CHECK-NEXT:  2,          99  (32.4%)
+# CHECK-NEXT:  0,          6  (2.0%)
+# CHECK-NEXT:  1,          202  (65.8%)
+# CHECK-NEXT:  2,          99  (32.2%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT: 0.96   0.04    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movb %spl, (%rax)
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movb (%rcx), %bpl
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movb (%rdx), %sil
 # CHECK-NEXT: 0.04   0.96    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movb %dil, (%rbx)
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .   .   movb %spl, (%rax)
-# CHECK-NEXT: [0,1]     DeeeeeER .   movb (%rcx), %bpl
-# CHECK-NEXT: [0,2]     D=eeeeeER.   movb (%rdx), %sil
-# CHECK-NEXT: [0,3]     D======eER   movb %dil, (%rbx)
+# CHECK:      [0,0]     .DeER.    .   movb  %spl, (%rax)
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movb  (%rcx), %bpl
+# CHECK-NEXT: [0,2]     .D=eeeeeER.   movb  (%rdx), %sil
+# CHECK-NEXT: [0,3]     .D======eER   movb  %dil, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movb %spl, (%rax)
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movb (%rcx), %bpl
 # CHECK-NEXT: 2.     1     2.0    2.0    0.0       movb (%rdx), %sil
 # CHECK-NEXT: 3.     1     7.0    0.0    0.0       movb %dil, (%rbx)
 # CHECK-NEXT:        1     2.8    1.0    0.0       <total>
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      306
+# CHECK-NEXT: Total Cycles:      307
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.31
-# CHECK-NEXT: IPC:               1.31
+# CHECK-NEXT: uOps Per Cycle:    1.30
+# CHECK-NEXT: IPC:               1.30
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.00           *            movw  %sp, (%rax)
 # CHECK-NEXT:  1      5     1.00    *                   movw  (%rcx), %bp
 # CHECK-NEXT:  1      5     1.00    *                   movw  (%rdx), %si
 # CHECK-NEXT:  1      1     1.00           *            movw  %di, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
-# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (84.0%)
+# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (83.7%)
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              34  (11.1%)
-# CHECK-NEXT:  1,              172  (56.2%)
-# CHECK-NEXT:  2,              86  (28.1%)
+# CHECK-NEXT:  0,              35  (11.4%)
+# CHECK-NEXT:  1,              172  (56.0%)
+# CHECK-NEXT:  2,              86  (28.0%)
 # CHECK-NEXT:  4,              14  (4.6%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          5  (1.6%)
-# CHECK-NEXT:  1,          202  (66.0%)
-# CHECK-NEXT:  2,          99  (32.4%)
+# CHECK-NEXT:  0,          6  (2.0%)
+# CHECK-NEXT:  1,          202  (65.8%)
+# CHECK-NEXT:  2,          99  (32.2%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT: 0.96   0.04    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movw %sp, (%rax)
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movw (%rcx), %bp
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movw (%rdx), %si
 # CHECK-NEXT: 0.04   0.96    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movw %di, (%rbx)
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .   .   movw %sp, (%rax)
-# CHECK-NEXT: [0,1]     DeeeeeER .   movw (%rcx), %bp
-# CHECK-NEXT: [0,2]     D=eeeeeER.   movw (%rdx), %si
-# CHECK-NEXT: [0,3]     D======eER   movw %di, (%rbx)
+# CHECK:      [0,0]     .DeER.    .   movw  %sp, (%rax)
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movw  (%rcx), %bp
+# CHECK-NEXT: [0,2]     .D=eeeeeER.   movw  (%rdx), %si
+# CHECK-NEXT: [0,3]     .D======eER   movw  %di, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movw %sp, (%rax)
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movw (%rcx), %bp
 # CHECK-NEXT: 2.     1     2.0    2.0    0.0       movw (%rdx), %si
 # CHECK-NEXT: 3.     1     7.0    0.0    0.0       movw %di, (%rbx)
 # CHECK-NEXT:        1     2.8    1.0    0.0       <total>
 
 # CHECK:      [2] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      306
+# CHECK-NEXT: Total Cycles:      307
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.31
-# CHECK-NEXT: IPC:               1.31
+# CHECK-NEXT: uOps Per Cycle:    1.30
+# CHECK-NEXT: IPC:               1.30
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.00           *            movl  %esp, (%rax)
 # CHECK-NEXT:  1      5     1.00    *                   movl  (%rcx), %ebp
 # CHECK-NEXT:  1      5     1.00    *                   movl  (%rdx), %esi
 # CHECK-NEXT:  1      1     1.00           *            movl  %edi, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
-# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (84.0%)
+# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (83.7%)
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              34  (11.1%)
-# CHECK-NEXT:  1,              172  (56.2%)
-# CHECK-NEXT:  2,              86  (28.1%)
+# CHECK-NEXT:  0,              35  (11.4%)
+# CHECK-NEXT:  1,              172  (56.0%)
+# CHECK-NEXT:  2,              86  (28.0%)
 # CHECK-NEXT:  4,              14  (4.6%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          5  (1.6%)
-# CHECK-NEXT:  1,          202  (66.0%)
-# CHECK-NEXT:  2,          99  (32.4%)
+# CHECK-NEXT:  0,          6  (2.0%)
+# CHECK-NEXT:  1,          202  (65.8%)
+# CHECK-NEXT:  2,          99  (32.2%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT: 0.96   0.04    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movl %esp, (%rax)
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movl (%rcx), %ebp
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movl (%rdx), %esi
 # CHECK-NEXT: 0.04   0.96    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movl %edi, (%rbx)
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .   .   movl %esp, (%rax)
-# CHECK-NEXT: [0,1]     DeeeeeER .   movl (%rcx), %ebp
-# CHECK-NEXT: [0,2]     D=eeeeeER.   movl (%rdx), %esi
-# CHECK-NEXT: [0,3]     D======eER   movl %edi, (%rbx)
+# CHECK:      [0,0]     .DeER.    .   movl  %esp, (%rax)
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movl  (%rcx), %ebp
+# CHECK-NEXT: [0,2]     .D=eeeeeER.   movl  (%rdx), %esi
+# CHECK-NEXT: [0,3]     .D======eER   movl  %edi, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movl %esp, (%rax)
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movl (%rcx), %ebp
 # CHECK-NEXT: 2.     1     2.0    2.0    0.0       movl (%rdx), %esi
 # CHECK-NEXT: 3.     1     7.0    0.0    0.0       movl %edi, (%rbx)
 # CHECK-NEXT:        1     2.8    1.0    0.0       <total>
 
 # CHECK:      [3] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      306
+# CHECK-NEXT: Total Cycles:      307
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.31
-# CHECK-NEXT: IPC:               1.31
+# CHECK-NEXT: uOps Per Cycle:    1.30
+# CHECK-NEXT: IPC:               1.30
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.00           *            movq  %rsp, (%rax)
 # CHECK-NEXT:  1      5     1.00    *                   movq  (%rcx), %rbp
 # CHECK-NEXT:  1      5     1.00    *                   movq  (%rdx), %rsi
 # CHECK-NEXT:  1      1     1.00           *            movq  %rdi, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
-# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (84.0%)
+# CHECK-NEXT: SCHEDQ  - Scheduler full:                            257  (83.7%)
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              34  (11.1%)
-# CHECK-NEXT:  1,              172  (56.2%)
-# CHECK-NEXT:  2,              86  (28.1%)
+# CHECK-NEXT:  0,              35  (11.4%)
+# CHECK-NEXT:  1,              172  (56.0%)
+# CHECK-NEXT:  2,              86  (28.0%)
 # CHECK-NEXT:  4,              14  (4.6%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          5  (1.6%)
-# CHECK-NEXT:  1,          202  (66.0%)
-# CHECK-NEXT:  2,          99  (32.4%)
+# CHECK-NEXT:  0,          6  (2.0%)
+# CHECK-NEXT:  1,          202  (65.8%)
+# CHECK-NEXT:  2,          99  (32.2%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT: 0.96   0.04    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movq %rsp, (%rax)
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movq (%rcx), %rbp
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movq (%rdx), %rsi
 # CHECK-NEXT: 0.04   0.96    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movq %rdi, (%rbx)
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .   .   movq %rsp, (%rax)
-# CHECK-NEXT: [0,1]     DeeeeeER .   movq (%rcx), %rbp
-# CHECK-NEXT: [0,2]     D=eeeeeER.   movq (%rdx), %rsi
-# CHECK-NEXT: [0,3]     D======eER   movq %rdi, (%rbx)
+# CHECK:      [0,0]     .DeER.    .   movq  %rsp, (%rax)
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movq  (%rcx), %rbp
+# CHECK-NEXT: [0,2]     .D=eeeeeER.   movq  (%rdx), %rsi
+# CHECK-NEXT: [0,3]     .D======eER   movq  %rdi, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movq %rsp, (%rax)
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movq (%rcx), %rbp
 # CHECK-NEXT: 2.     1     2.0    2.0    0.0       movq (%rdx), %rsi
 # CHECK-NEXT: 3.     1     7.0    0.0    0.0       movq %rdi, (%rbx)
 # CHECK-NEXT:        1     2.8    1.0    0.0       <total>
 
 # CHECK:      [4] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      554
+# CHECK-NEXT: Total Cycles:      555
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.72
 # CHECK-NEXT: IPC:               0.72
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      5     1.50    *                   movd  (%rdx), %mm2
 # CHECK-NEXT:  1      2     1.50           *      U     movd  %mm3, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            55  (9.9%)
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          437  (78.9%)
+# CHECK-NEXT: SQ      - Store queue full:                          437  (78.7%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              365  (65.9%)
+# CHECK-NEXT:  0,              366  (65.9%)
 # CHECK-NEXT:  1,              88  (15.9%)
 # CHECK-NEXT:  2,              3  (0.5%)
 # CHECK-NEXT:  3,              86  (15.5%)
 # CHECK-NEXT:  4,              12  (2.2%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          253  (45.7%)
-# CHECK-NEXT:  1,          202  (36.5%)
-# CHECK-NEXT:  2,          99  (17.9%)
+# CHECK-NEXT:  0,          254  (45.8%)
+# CHECK-NEXT:  1,          202  (36.4%)
+# CHECK-NEXT:  2,          99  (17.8%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   movd %mm0, (%rax)
 # CHECK-NEXT: 1.53   1.47    -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -     3.00    -      -     movd (%rcx), %mm1
 # CHECK-NEXT: 1.47   1.53    -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -     3.00    -      -      -     movd (%rdx), %mm2
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   movd %mm3, (%rbx)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.    .   movd  %mm0, (%rax)
-# CHECK-NEXT: [0,1]     DeeeeeER  .   movd  (%rcx), %mm1
-# CHECK-NEXT: [0,2]     D=eeeeeER .   movd  (%rdx), %mm2
-# CHECK-NEXT: [0,3]     D======eeER   movd  %mm3, (%rbx)
+# CHECK:      [0,0]     .DeeER    ..   movd %mm0, (%rax)
+# CHECK-NEXT: [0,1]     .DeeeeeER ..   movd (%rcx), %mm1
+# CHECK-NEXT: [0,2]     .D=eeeeeER..   movd (%rdx), %mm2
+# CHECK-NEXT: [0,3]     .D======eeER   movd %mm3, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movd %mm0, (%rax)
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movd (%rcx), %mm1
 # CHECK-NEXT: 2.     1     2.0    2.0    0.0       movd (%rdx), %mm2
 # CHECK-NEXT: 3.     1     7.0    0.0    0.0       movd %mm3, (%rbx)
 # CHECK-NEXT:        1     2.8    1.0    0.0       <total>
 
 # CHECK:      [5] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      405
+# CHECK-NEXT: Total Cycles:      406
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.99
 # CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.50           *            movaps  %xmm0, (%rax)
 # CHECK-NEXT:  1      5     1.50    *                   movaps  (%rcx), %xmm1
 # CHECK-NEXT:  1      5     1.50    *                   movaps  (%rdx), %xmm2
 # CHECK-NEXT:  1      1     1.50           *            movaps  %xmm3, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
-# CHECK-NEXT: SCHEDQ  - Scheduler full:                            347  (85.7%)
+# CHECK-NEXT: SCHEDQ  - Scheduler full:                            347  (85.5%)
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              131  (32.3%)
-# CHECK-NEXT:  1,              174  (43.0%)
-# CHECK-NEXT:  2,              87  (21.5%)
+# CHECK-NEXT:  0,              132  (32.5%)
+# CHECK-NEXT:  1,              174  (42.9%)
+# CHECK-NEXT:  2,              87  (21.4%)
 # CHECK-NEXT:  4,              13  (3.2%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          104  (25.7%)
-# CHECK-NEXT:  1,          202  (49.9%)
+# CHECK-NEXT:  0,          105  (25.9%)
+# CHECK-NEXT:  1,          202  (49.8%)
 # CHECK-NEXT:  2,          99  (24.4%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   movaps %xmm0, (%rax)
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -     movaps (%rcx), %xmm1
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     movaps (%rdx), %xmm2
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   movaps %xmm3, (%rbx)
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .   .   movaps %xmm0, (%rax)
-# CHECK-NEXT: [0,1]     DeeeeeER .   movaps (%rcx), %xmm1
-# CHECK-NEXT: [0,2]     D=eeeeeER.   movaps (%rdx), %xmm2
-# CHECK-NEXT: [0,3]     D======eER   movaps %xmm3, (%rbx)
+# CHECK:      [0,0]     .DeER.    .   movaps  %xmm0, (%rax)
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movaps  (%rcx), %xmm1
+# CHECK-NEXT: [0,2]     .D=eeeeeER.   movaps  (%rdx), %xmm2
+# CHECK-NEXT: [0,3]     .D======eER   movaps  %xmm3, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movaps %xmm0, (%rax)
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movaps (%rcx), %xmm1
 # CHECK-NEXT: 2.     1     2.0    2.0    0.0       movaps (%rdx), %xmm2
 # CHECK-NEXT: 3.     1     7.0    0.0    0.0       movaps %xmm3, (%rbx)
 # CHECK-NEXT:        1     2.8    1.0    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/load-throughput.s

 vmovaps (%rdx), %ymm2
 vmovaps (%rbx), %ymm3
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      406
+# CHECK-NEXT: Total Cycles:      407
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.99
-# CHECK-NEXT: IPC:               0.99
+# CHECK-NEXT: uOps Per Cycle:    0.98
+# CHECK-NEXT: IPC:               0.98
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      5     1.00    *                   movb  (%rax), %spl
 # CHECK-NEXT:  1      5     1.00    *                   movb  (%rcx), %bpl
 # CHECK-NEXT:  1      5     1.00    *                   movb  (%rdx), %sil
 # CHECK-NEXT:  1      5     1.00    *                   movb  (%rbx), %dil
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           354  (87.2%)
+# CHECK-NEXT: LQ      - Load queue full:                           354  (87.0%)
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              217  (53.4%)
-# CHECK-NEXT:  2,              178  (43.8%)
+# CHECK-NEXT:  0,              218  (53.6%)
+# CHECK-NEXT:  2,              178  (43.7%)
 # CHECK-NEXT:  4,              11  (2.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          206  (50.7%)
-# CHECK-NEXT:  2,          200  (49.3%)
+# CHECK-NEXT:  0,          207  (50.9%)
+# CHECK-NEXT:  2,          200  (49.1%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movb (%rax), %spl
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movb (%rcx), %bpl
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movb (%rdx), %sil
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movb (%rbx), %dil
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER .   movb (%rax), %spl
-# CHECK-NEXT: [0,1]     DeeeeeER .   movb (%rcx), %bpl
-# CHECK-NEXT: [0,2]     D==eeeeeER   movb (%rdx), %sil
-# CHECK-NEXT: [0,3]     D==eeeeeER   movb (%rbx), %dil
+# CHECK:      [0,0]     .DeeeeeER .   movb  (%rax), %spl
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movb  (%rcx), %bpl
+# CHECK-NEXT: [0,2]     .D==eeeeeER   movb  (%rdx), %sil
+# CHECK-NEXT: [0,3]     .D==eeeeeER   movb  (%rbx), %dil
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movb (%rax), %spl
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movb (%rcx), %bpl
 # CHECK-NEXT: 2.     1     3.0    3.0    0.0       movb (%rdx), %sil
 # CHECK-NEXT: 3.     1     3.0    3.0    0.0       movb (%rbx), %dil
 # CHECK-NEXT:        1     2.0    2.0    0.0       <total>
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      406
+# CHECK-NEXT: Total Cycles:      407
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.99
-# CHECK-NEXT: IPC:               0.99
+# CHECK-NEXT: uOps Per Cycle:    0.98
+# CHECK-NEXT: IPC:               0.98
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      5     1.00    *                   movw  (%rax), %sp
 # CHECK-NEXT:  1      5     1.00    *                   movw  (%rcx), %bp
 # CHECK-NEXT:  1      5     1.00    *                   movw  (%rdx), %si
 # CHECK-NEXT:  1      5     1.00    *                   movw  (%rbx), %di
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           354  (87.2%)
+# CHECK-NEXT: LQ      - Load queue full:                           354  (87.0%)
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              217  (53.4%)
-# CHECK-NEXT:  2,              178  (43.8%)
+# CHECK-NEXT:  0,              218  (53.6%)
+# CHECK-NEXT:  2,              178  (43.7%)
 # CHECK-NEXT:  4,              11  (2.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          206  (50.7%)
-# CHECK-NEXT:  2,          200  (49.3%)
+# CHECK-NEXT:  0,          207  (50.9%)
+# CHECK-NEXT:  2,          200  (49.1%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movw (%rax), %sp
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movw (%rcx), %bp
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movw (%rdx), %si
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movw (%rbx), %di
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER .   movw (%rax), %sp
-# CHECK-NEXT: [0,1]     DeeeeeER .   movw (%rcx), %bp
-# CHECK-NEXT: [0,2]     D==eeeeeER   movw (%rdx), %si
-# CHECK-NEXT: [0,3]     D==eeeeeER   movw (%rbx), %di
+# CHECK:      [0,0]     .DeeeeeER .   movw  (%rax), %sp
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movw  (%rcx), %bp
+# CHECK-NEXT: [0,2]     .D==eeeeeER   movw  (%rdx), %si
+# CHECK-NEXT: [0,3]     .D==eeeeeER   movw  (%rbx), %di
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movw (%rax), %sp
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movw (%rcx), %bp
 # CHECK-NEXT: 2.     1     3.0    3.0    0.0       movw (%rdx), %si
 # CHECK-NEXT: 3.     1     3.0    3.0    0.0       movw (%rbx), %di
 # CHECK-NEXT:        1     2.0    2.0    0.0       <total>
 
 # CHECK:      [2] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      406
+# CHECK-NEXT: Total Cycles:      407
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.99
-# CHECK-NEXT: IPC:               0.99
+# CHECK-NEXT: uOps Per Cycle:    0.98
+# CHECK-NEXT: IPC:               0.98
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      5     1.00    *                   movl  (%rax), %esp
 # CHECK-NEXT:  1      5     1.00    *                   movl  (%rcx), %ebp
 # CHECK-NEXT:  1      5     1.00    *                   movl  (%rdx), %esi
 # CHECK-NEXT:  1      5     1.00    *                   movl  (%rbx), %edi
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           354  (87.2%)
+# CHECK-NEXT: LQ      - Load queue full:                           354  (87.0%)
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              217  (53.4%)
-# CHECK-NEXT:  2,              178  (43.8%)
+# CHECK-NEXT:  0,              218  (53.6%)
+# CHECK-NEXT:  2,              178  (43.7%)
 # CHECK-NEXT:  4,              11  (2.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          206  (50.7%)
-# CHECK-NEXT:  2,          200  (49.3%)
+# CHECK-NEXT:  0,          207  (50.9%)
+# CHECK-NEXT:  2,          200  (49.1%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movl (%rax), %esp
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movl (%rcx), %ebp
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movl (%rdx), %esi
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movl (%rbx), %edi
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER .   movl (%rax), %esp
-# CHECK-NEXT: [0,1]     DeeeeeER .   movl (%rcx), %ebp
-# CHECK-NEXT: [0,2]     D==eeeeeER   movl (%rdx), %esi
-# CHECK-NEXT: [0,3]     D==eeeeeER   movl (%rbx), %edi
+# CHECK:      [0,0]     .DeeeeeER .   movl  (%rax), %esp
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movl  (%rcx), %ebp
+# CHECK-NEXT: [0,2]     .D==eeeeeER   movl  (%rdx), %esi
+# CHECK-NEXT: [0,3]     .D==eeeeeER   movl  (%rbx), %edi
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movl (%rax), %esp
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movl (%rcx), %ebp
 # CHECK-NEXT: 2.     1     3.0    3.0    0.0       movl (%rdx), %esi
 # CHECK-NEXT: 3.     1     3.0    3.0    0.0       movl (%rbx), %edi
 # CHECK-NEXT:        1     2.0    2.0    0.0       <total>
 
 # CHECK:      [3] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      406
+# CHECK-NEXT: Total Cycles:      407
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.99
-# CHECK-NEXT: IPC:               0.99
+# CHECK-NEXT: uOps Per Cycle:    0.98
+# CHECK-NEXT: IPC:               0.98
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      5     1.00    *                   movq  (%rax), %rsp
 # CHECK-NEXT:  1      5     1.00    *                   movq  (%rcx), %rbp
 # CHECK-NEXT:  1      5     1.00    *                   movq  (%rdx), %rsi
 # CHECK-NEXT:  1      5     1.00    *                   movq  (%rbx), %rdi
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           354  (87.2%)
+# CHECK-NEXT: LQ      - Load queue full:                           354  (87.0%)
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              217  (53.4%)
-# CHECK-NEXT:  2,              178  (43.8%)
+# CHECK-NEXT:  0,              218  (53.6%)
+# CHECK-NEXT:  2,              178  (43.7%)
 # CHECK-NEXT:  4,              11  (2.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          206  (50.7%)
-# CHECK-NEXT:  2,          200  (49.3%)
+# CHECK-NEXT:  0,          207  (50.9%)
+# CHECK-NEXT:  2,          200  (49.1%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movq (%rax), %rsp
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movq (%rcx), %rbp
 # CHECK-NEXT:  -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     movq (%rdx), %rsi
 # CHECK-NEXT: 2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     movq (%rbx), %rdi
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER .   movq (%rax), %rsp
-# CHECK-NEXT: [0,1]     DeeeeeER .   movq (%rcx), %rbp
-# CHECK-NEXT: [0,2]     D==eeeeeER   movq (%rdx), %rsi
-# CHECK-NEXT: [0,3]     D==eeeeeER   movq (%rbx), %rdi
+# CHECK:      [0,0]     .DeeeeeER .   movq  (%rax), %rsp
+# CHECK-NEXT: [0,1]     .DeeeeeER .   movq  (%rcx), %rbp
+# CHECK-NEXT: [0,2]     .D==eeeeeER   movq  (%rdx), %rsi
+# CHECK-NEXT: [0,3]     .D==eeeeeER   movq  (%rbx), %rdi
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movq (%rax), %rsp
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movq (%rcx), %rbp
 # CHECK-NEXT: 2.     1     3.0    3.0    0.0       movq (%rdx), %rsi
 # CHECK-NEXT: 3.     1     3.0    3.0    0.0       movq (%rbx), %rdi
 # CHECK-NEXT:        1     2.0    2.0    0.0       <total>
 
 # CHECK:      [4] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      605
+# CHECK-NEXT: Total Cycles:      606
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.66
 # CHECK-NEXT: IPC:               0.66
 # CHECK-NEXT: Block RThroughput: 6.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      5     1.50    *                   movd  (%rcx), %mm1
 # CHECK-NEXT:  1      5     1.50    *                   movd  (%rdx), %mm2
 # CHECK-NEXT:  1      5     1.50    *                   movd  (%rbx), %mm3
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           533  (88.1%)
+# CHECK-NEXT: LQ      - Load queue full:                           533  (88.0%)
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              416  (68.8%)
+# CHECK-NEXT:  0,              417  (68.8%)
 # CHECK-NEXT:  2,              178  (29.4%)
 # CHECK-NEXT:  4,              11  (1.8%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          405  (66.9%)
-# CHECK-NEXT:  2,          200  (33.1%)
+# CHECK-NEXT:  0,          406  (67.0%)
+# CHECK-NEXT:  2,          200  (33.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -     3.00    -      -     movd (%rax), %mm0
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -     3.00    -      -      -     movd (%rcx), %mm1
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -     3.00    -      -     movd (%rdx), %mm2
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -      -      -     3.00    -      -      -     1.00    -      -      -      -     3.00    -      -      -     movd (%rbx), %mm3
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .   movd  (%rax), %mm0
-# CHECK-NEXT: [0,1]     DeeeeeER  .   movd  (%rcx), %mm1
-# CHECK-NEXT: [0,2]     D===eeeeeER   movd  (%rdx), %mm2
-# CHECK-NEXT: [0,3]     D===eeeeeER   movd  (%rbx), %mm3
+# CHECK:      [0,0]     .DeeeeeER ..   movd (%rax), %mm0
+# CHECK-NEXT: [0,1]     .DeeeeeER ..   movd (%rcx), %mm1
+# CHECK-NEXT: [0,2]     .D===eeeeeER   movd (%rdx), %mm2
+# CHECK-NEXT: [0,3]     .D===eeeeeER   movd (%rbx), %mm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movd (%rax), %mm0
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movd (%rcx), %mm1
 # CHECK-NEXT: 2.     1     4.0    4.0    0.0       movd (%rdx), %mm2
 # CHECK-NEXT: 3.     1     4.0    4.0    0.0       movd (%rbx), %mm3
 # CHECK-NEXT:        1     2.5    2.5    0.0       <total>
 
 # CHECK:      [5] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      605
+# CHECK-NEXT: Total Cycles:      606
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.66
 # CHECK-NEXT: IPC:               0.66
 # CHECK-NEXT: Block RThroughput: 6.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      5     1.50    *                   movaps  (%rcx), %xmm1
 # CHECK-NEXT:  1      5     1.50    *                   movaps  (%rdx), %xmm2
 # CHECK-NEXT:  1      5     1.50    *                   movaps  (%rbx), %xmm3
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           533  (88.1%)
+# CHECK-NEXT: LQ      - Load queue full:                           533  (88.0%)
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              416  (68.8%)
+# CHECK-NEXT:  0,              417  (68.8%)
 # CHECK-NEXT:  2,              178  (29.4%)
 # CHECK-NEXT:  4,              11  (1.8%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          405  (66.9%)
-# CHECK-NEXT:  2,          200  (33.1%)
+# CHECK-NEXT:  0,          406  (67.0%)
+# CHECK-NEXT:  2,          200  (33.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -     movaps (%rax), %xmm0
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     movaps (%rcx), %xmm1
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -     movaps (%rdx), %xmm2
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     movaps (%rbx), %xmm3
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .   movaps  (%rax), %xmm0
-# CHECK-NEXT: [0,1]     DeeeeeER  .   movaps  (%rcx), %xmm1
-# CHECK-NEXT: [0,2]     D===eeeeeER   movaps  (%rdx), %xmm2
-# CHECK-NEXT: [0,3]     D===eeeeeER   movaps  (%rbx), %xmm3
+# CHECK:      [0,0]     .DeeeeeER ..   movaps (%rax), %xmm0
+# CHECK-NEXT: [0,1]     .DeeeeeER ..   movaps (%rcx), %xmm1
+# CHECK-NEXT: [0,2]     .D===eeeeeER   movaps (%rdx), %xmm2
+# CHECK-NEXT: [0,3]     .D===eeeeeER   movaps (%rbx), %xmm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movaps (%rax), %xmm0
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       movaps (%rcx), %xmm1
 # CHECK-NEXT: 2.     1     4.0    4.0    0.0       movaps (%rdx), %xmm2
 # CHECK-NEXT: 3.     1     4.0    4.0    0.0       movaps (%rbx), %xmm3
 # CHECK-NEXT:        1     2.5    2.5    0.0       <total>
 
 # CHECK:      [6] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      605
+# CHECK-NEXT: Total Cycles:      606
 # CHECK-NEXT: Total uOps:        800
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.32
 # CHECK-NEXT: IPC:               0.66
 # CHECK-NEXT: Block RThroughput: 6.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  2      5     1.50    *                   vmovaps (%rcx), %ymm1
 # CHECK-NEXT:  2      5     1.50    *                   vmovaps (%rdx), %ymm2
 # CHECK-NEXT:  2      5     1.50    *                   vmovaps (%rbx), %ymm3
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
-# CHECK-NEXT: LQ      - Load queue full:                           345  (57.0%)
+# CHECK-NEXT: LQ      - Load queue full:                           345  (56.9%)
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              405  (66.9%)
-# CHECK-NEXT:  4,              200  (33.1%)
+# CHECK-NEXT:  0,              406  (67.0%)
+# CHECK-NEXT:  4,              200  (33.0%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          405  (66.9%)
-# CHECK-NEXT:  4,          200  (33.1%)
+# CHECK-NEXT:  0,          406  (67.0%)
+# CHECK-NEXT:  4,          200  (33.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -     vmovaps  (%rax), %ymm0
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     vmovaps  (%rcx), %ymm1
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -     vmovaps  (%rdx), %ymm2
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     vmovaps  (%rbx), %ymm3
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .   vmovaps (%rax), %ymm0
-# CHECK-NEXT: [0,1]     DeeeeeER  .   vmovaps (%rcx), %ymm1
-# CHECK-NEXT: [0,2]     .D==eeeeeER   vmovaps (%rdx), %ymm2
-# CHECK-NEXT: [0,3]     .D==eeeeeER   vmovaps (%rbx), %ymm3
+# CHECK:      [0,0]     .DeeeeeER ..   vmovaps  (%rax), %ymm0
+# CHECK-NEXT: [0,1]     .DeeeeeER ..   vmovaps  (%rcx), %ymm1
+# CHECK-NEXT: [0,2]     . D==eeeeeER   vmovaps  (%rdx), %ymm2
+# CHECK-NEXT: [0,3]     . D==eeeeeER   vmovaps  (%rbx), %ymm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vmovaps  (%rax), %ymm0
 # CHECK-NEXT: 1.     1     1.0    1.0    0.0       vmovaps  (%rcx), %ymm1
 # CHECK-NEXT: 2.     1     3.0    3.0    0.0       vmovaps  (%rdx), %ymm2
 # CHECK-NEXT: 3.     1     3.0    3.0    0.0       vmovaps  (%rbx), %ymm3
 # CHECK-NEXT:        1     2.0    2.0    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/memcpy-like-test.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=100 -timeline -timeline-max-iterations=1 < %s | FileCheck %s
 
 vmovaps (%rsi), %xmm0
 vmovaps %xmm0, (%rdi)
 vmovaps 16(%rsi), %xmm0
 vmovaps %xmm0, 16(%rdi)
 vmovaps 32(%rsi), %xmm0
 vmovaps %xmm0, 32(%rdi)
 vmovaps 48(%rsi), %xmm0
 vmovaps %xmm0, 48(%rdi)
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      800
-# CHECK-NEXT: Total Cycles:      806
+# CHECK-NEXT: Total Cycles:      807
 # CHECK-NEXT: Total uOps:        800
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.99
 # CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 8.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT: 0.03   2.97    -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     vmovaps  16(%rsi), %xmm0
 # CHECK-NEXT: 0.01   0.99    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   vmovaps  %xmm0, 16(%rdi)
 # CHECK-NEXT:  -     3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -     vmovaps  32(%rsi), %xmm0
 # CHECK-NEXT: 0.99   0.01    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   vmovaps  %xmm0, 32(%rdi)
 # CHECK-NEXT: 3.00    -      -      -      -      -      -      -     3.00    -      -      -      -      -     1.00    -      -      -      -     3.00    -      -      -     vmovaps  48(%rsi), %xmm0
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   vmovaps  %xmm0, 48(%rdi)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123
+# CHECK-NEXT:                     01234
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .  .   vmovaps  (%rsi), %xmm0
-# CHECK-NEXT: [0,1]     D======eER.  .   vmovaps  %xmm0, (%rdi)
-# CHECK-NEXT: [0,2]     DeeeeeE--R.  .   vmovaps  16(%rsi), %xmm0
-# CHECK-NEXT: [0,3]     D=======eER  .   vmovaps  %xmm0, 16(%rdi)
-# CHECK-NEXT: [0,4]     .D==eeeeeER  .   vmovaps  32(%rsi), %xmm0
-# CHECK-NEXT: [0,5]     .D========eER.   vmovaps  %xmm0, 32(%rdi)
-# CHECK-NEXT: [0,6]     .D==eeeeeE--R.   vmovaps  48(%rsi), %xmm0
-# CHECK-NEXT: [0,7]     .D=========eER   vmovaps  %xmm0, 48(%rdi)
+# CHECK:      [0,0]     .DeeeeeER .   .   vmovaps (%rsi), %xmm0
+# CHECK-NEXT: [0,1]     .D======eER   .   vmovaps %xmm0, (%rdi)
+# CHECK-NEXT: [0,2]     .DeeeeeE--R   .   vmovaps 16(%rsi), %xmm0
+# CHECK-NEXT: [0,3]     .D=======eER  .   vmovaps %xmm0, 16(%rdi)
+# CHECK-NEXT: [0,4]     . D==eeeeeER  .   vmovaps 32(%rsi), %xmm0
+# CHECK-NEXT: [0,5]     . D========eER.   vmovaps %xmm0, 32(%rdi)
+# CHECK-NEXT: [0,6]     . D==eeeeeE--R.   vmovaps 48(%rsi), %xmm0
+# CHECK-NEXT: [0,7]     . D=========eER   vmovaps %xmm0, 48(%rdi)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/BdVer2/one-idioms.s

 vpcmpeqd  %xmm3, %xmm3, %xmm5
 vpcmpeqq  %xmm3, %xmm3, %xmm5
 vpcmpeqw  %xmm3, %xmm3, %xmm5
 
 # FIXME: their handling is broken in llvm-mca.
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      1500
-# CHECK-NEXT: Total Cycles:      1353
+# CHECK-NEXT: Total Cycles:      1354
 # CHECK-NEXT: Total uOps:        1500
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.11
 # CHECK-NEXT: IPC:               1.11
 # CHECK-NEXT: Block RThroughput: 13.5
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpcmpeqq %xmm3, %xmm3, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpcmpeqw %xmm3, %xmm3, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpcmpeqb %xmm3, %xmm3, %xmm5
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpcmpeqd %xmm3, %xmm3, %xmm5
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpcmpeqq %xmm3, %xmm3, %xmm5
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     1.00   1.00    -      -     0.50   0.50    -      -      -      -      -      -      -     vpcmpeqw %xmm3, %xmm3, %xmm5
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456
+# CHECK-NEXT:                     01234567
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.    .    ..   pcmpeqb %mm2, %mm2
-# CHECK-NEXT: [0,1]     DeeER.    .    ..   pcmpeqd %mm2, %mm2
-# CHECK-NEXT: [0,2]     D=eeER    .    ..   pcmpeqw %mm2, %mm2
-# CHECK-NEXT: [0,3]     D==eeER   .    ..   pcmpeqb %xmm2, %xmm2
-# CHECK-NEXT: [0,4]     .DeeE-R   .    ..   pcmpeqd %xmm2, %xmm2
-# CHECK-NEXT: [0,5]     .D==eeER  .    ..   pcmpeqq %xmm2, %xmm2
-# CHECK-NEXT: [0,6]     .D===eeER .    ..   pcmpeqw %xmm2, %xmm2
-# CHECK-NEXT: [0,7]     .D=====eeER    ..   vpcmpeqb  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,8]     . D===eeE-R    ..   vpcmpeqd  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,9]     . D======eeER  ..   vpcmpeqq  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,10]    . D=====eeE-R  ..   vpcmpeqw  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,11]    . D=======eeER ..   vpcmpeqb  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,12]    .  D=======eeER..   vpcmpeqd  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,13]    .  D========eeER.   vpcmpeqq  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,14]    .  D=========eeER   vpcmpeqw  %xmm3, %xmm3, %xmm5
+# CHECK:      [0,0]     .DeeER    .    . .   pcmpeqb  %mm2, %mm2
+# CHECK-NEXT: [0,1]     .DeeER    .    . .   pcmpeqd  %mm2, %mm2
+# CHECK-NEXT: [0,2]     .D=eeER   .    . .   pcmpeqw  %mm2, %mm2
+# CHECK-NEXT: [0,3]     .D==eeER  .    . .   pcmpeqb  %xmm2, %xmm2
+# CHECK-NEXT: [0,4]     . DeeE-R  .    . .   pcmpeqd  %xmm2, %xmm2
+# CHECK-NEXT: [0,5]     . D==eeER .    . .   pcmpeqq  %xmm2, %xmm2
+# CHECK-NEXT: [0,6]     . D===eeER.    . .   pcmpeqw  %xmm2, %xmm2
+# CHECK-NEXT: [0,7]     . D=====eeER   . .   vpcmpeqb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,8]     .  D===eeE-R   . .   vpcmpeqd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,9]     .  D======eeER . .   vpcmpeqq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,10]    .  D=====eeE-R . .   vpcmpeqw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,11]    .  D=======eeER. .   vpcmpeqb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,12]    .   D=======eeER .   vpcmpeqd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,13]    .   D========eeER.   vpcmpeqq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,14]    .   D=========eeER   vpcmpeqw %xmm3, %xmm3, %xmm5
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
 
 imul   %rax, %rbx
 lzcnt  %ax,  %bx
 add    %ecx, %ebx
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3
-# CHECK-NEXT: Total Cycles:      11
+# CHECK-NEXT: Total Cycles:      12
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.36
-# CHECK-NEXT: IPC:               0.27
+# CHECK-NEXT: uOps Per Cycle:    0.33
+# CHECK-NEXT: IPC:               0.25
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      6     4.00                        imulq %rax, %rbx
 # CHECK-NEXT:  2      2     2.00                        lzcntw  %ax, %bx
 # CHECK-NEXT:  1      1     1.00                        addl  %ecx, %ebx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeeER .   imulq %rax, %rbx
-# CHECK-NEXT: [0,1]     D=====eeER.   lzcntw  %ax, %bx
-# CHECK-NEXT: [0,2]     D=======eER   addl  %ecx, %ebx
+# CHECK:      [0,0]     .DeeeeeeER..   imulq  %rax, %rbx
+# CHECK-NEXT: [0,1]     .D=====eeER.   lzcntw %ax, %bx
+# CHECK-NEXT: [0,2]     .D=======eER   addl %ecx, %ebx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       imulq  %rax, %rbx
 # CHECK-NEXT: 1.     1     6.0    0.0    0.0       lzcntw %ax, %bx
 # CHECK-NEXT: 2.     1     8.0    0.0    0.0       addl %ecx, %ebx
 # CHECK-NEXT:        1     5.0    0.3    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-3.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 # perf stat reports a throughput of 1.00 IPC for this code snippet.
 
 # The ILP is limited by the false dependency on %dx. So, the mov cannot execute
 # in parallel with the add.
 
 add %cx, %dx
 mov %ax, %dx
 xor %bx, %dx
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      4500
-# CHECK-NEXT: Total Cycles:      4503
+# CHECK-NEXT: Total Cycles:      4504
 # CHECK-NEXT: Total uOps:        4500
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               1.00
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addw %cx, %dx
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movw %ax, %dx
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     xorw %bx, %dx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
+# CHECK-NEXT:                     012
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeER .    ..   addw %cx, %dx
-# CHECK-NEXT: [0,1]     D=eER.    ..   movw %ax, %dx
-# CHECK-NEXT: [0,2]     D==eER    ..   xorw %bx, %dx
-# CHECK-NEXT: [1,0]     D===eER   ..   addw %cx, %dx
-# CHECK-NEXT: [1,1]     .D===eER  ..   movw %ax, %dx
-# CHECK-NEXT: [1,2]     .D====eER ..   xorw %bx, %dx
-# CHECK-NEXT: [2,0]     .D=====eER..   addw %cx, %dx
-# CHECK-NEXT: [2,1]     .D======eER.   movw %ax, %dx
-# CHECK-NEXT: [2,2]     . D======eER   xorw %bx, %dx
+# CHECK:      [0,0]     .DeER.    . .   addw  %cx, %dx
+# CHECK-NEXT: [0,1]     .D=eER    . .   movw  %ax, %dx
+# CHECK-NEXT: [0,2]     .D==eER   . .   xorw  %bx, %dx
+# CHECK-NEXT: [1,0]     .D===eER  . .   addw  %cx, %dx
+# CHECK-NEXT: [1,1]     . D===eER . .   movw  %ax, %dx
+# CHECK-NEXT: [1,2]     . D====eER. .   xorw  %bx, %dx
+# CHECK-NEXT: [2,0]     . D=====eER .   addw  %cx, %dx
+# CHECK-NEXT: [2,1]     . D======eER.   movw  %ax, %dx
+# CHECK-NEXT: [2,2]     .  D======eER   xorw  %bx, %dx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     3.7    0.3    0.0       addw %cx, %dx
 # CHECK-NEXT: 1.     3     4.3    0.0    0.0       movw %ax, %dx
 # CHECK-NEXT: 2.     3     5.0    0.0    0.0       xorw %bx, %dx
 # CHECK-NEXT:        3     4.3    0.1    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-4.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 # perf stat reports a throughput of 0.60 IPC for this code snippet.
 
 # The lzcnt cannot execute in parallel with the imul because there is a false
 # dependency on %bx.
 
 imul %ax, %bx
 lzcnt %ax, %bx
 add %cx, %bx
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      4500
-# CHECK-NEXT: Total Cycles:      9753
+# CHECK-NEXT: Total Cycles:      9754
 # CHECK-NEXT: Total uOps:        6000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.62
 # CHECK-NEXT: IPC:               0.46
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -     imulw  %ax, %bx
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     lzcntw %ax, %bx
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addw %cx, %bx
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          01
+# CHECK-NEXT: Index     0123456789          012
 
-# CHECK:      [0,0]     DeeeeER   .    .    ..   imulw  %ax, %bx
-# CHECK-NEXT: [0,1]     D===eeER  .    .    ..   lzcntw %ax, %bx
-# CHECK-NEXT: [0,2]     D=====eER .    .    ..   addw %cx, %bx
-# CHECK-NEXT: [1,0]     .D======eeeeER .    ..   imulw  %ax, %bx
-# CHECK-NEXT: [1,1]     .D=========eeER.    ..   lzcntw %ax, %bx
-# CHECK-NEXT: [1,2]     .D===========eER    ..   addw %cx, %bx
-# CHECK-NEXT: [2,0]     . D===========eeeeER..   imulw  %ax, %bx
-# CHECK-NEXT: [2,1]     . D==============eeER.   lzcntw %ax, %bx
-# CHECK-NEXT: [2,2]     . D================eER   addw %cx, %bx
+# CHECK:      [0,0]     .DeeeeER  .    .    . .   imulw %ax, %bx
+# CHECK-NEXT: [0,1]     .D===eeER .    .    . .   lzcntw  %ax, %bx
+# CHECK-NEXT: [0,2]     .D=====eER.    .    . .   addw  %cx, %bx
+# CHECK-NEXT: [1,0]     . D======eeeeER.    . .   imulw %ax, %bx
+# CHECK-NEXT: [1,1]     . D=========eeER    . .   lzcntw  %ax, %bx
+# CHECK-NEXT: [1,2]     . D===========eER   . .   addw  %cx, %bx
+# CHECK-NEXT: [2,0]     .  D===========eeeeER .   imulw %ax, %bx
+# CHECK-NEXT: [2,1]     .  D==============eeER.   lzcntw  %ax, %bx
+# CHECK-NEXT: [2,2]     .  D================eER   addw  %cx, %bx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     6.7    0.7    0.0       imulw  %ax, %bx
 # CHECK-NEXT: 1.     3     9.7    0.0    0.0       lzcntw %ax, %bx
 # CHECK-NEXT: 2.     3     11.7   0.0    0.0       addw %cx, %bx
 # CHECK-NEXT:        3     9.3    0.2    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-5.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 # perf stat reports a throughput of 1.00 IPC for this code snippet.
 
 lzcnt %ax, %bx  ## partial register stall.
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      1500
-# CHECK-NEXT: Total Cycles:      3003
+# CHECK-NEXT: Total Cycles:      3004
 # CHECK-NEXT: Total uOps:        3000
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     lzcntw %ax, %bx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     012345678
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.  .   lzcntw  %ax, %bx
-# CHECK-NEXT: [1,0]     D==eeER .   lzcntw  %ax, %bx
-# CHECK-NEXT: [2,0]     .D===eeER   lzcntw  %ax, %bx
+# CHECK:      [0,0]     .DeeER   .   lzcntw %ax, %bx
+# CHECK-NEXT: [1,0]     .D==eeER .   lzcntw %ax, %bx
+# CHECK-NEXT: [2,0]     . D===eeER   lzcntw %ax, %bx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     2.7    1.0    0.0       lzcntw %ax, %bx

llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update-6.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1500 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 # perf stat reports a throughput of 0.60 IPC for this code snippet.
 # Each lzcnt has a false dependency on %ecx; the first lzcnt has to wait on the
 # imul. However, the folded load can start immediately.
 # The last lzcnt has a false dependency on %cx. However, even in this case, the
 # folded load can start immediately.
 
 imul %edx, %ecx
 lzcnt (%rsp), %cx
 lzcnt 2(%rsp), %cx
 
 # CHECK:      Iterations:        1500
 # CHECK-NEXT: Instructions:      4500
-# CHECK-NEXT: Total Cycles:      12003
+# CHECK-NEXT: Total Cycles:      12004
 # CHECK-NEXT: Total uOps:        7500
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.62
 # CHECK-NEXT: IPC:               0.37
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -     2.00    -     imull  %edx, %ecx
 # CHECK-NEXT:  -     3.00    -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -     3.00    -      -     lzcntw (%rsp), %cx
 # CHECK-NEXT: 3.00    -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -     3.00    -      -      -     lzcntw 2(%rsp), %cx
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0123456
+# CHECK-NEXT: Index     0123456789          01234567
 
-# CHECK:      [0,0]     DeeeeER   .    .    .    ..   imull %edx, %ecx
-# CHECK-NEXT: [0,1]     DeeeeeeER .    .    .    ..   lzcntw  (%rsp), %cx
-# CHECK-NEXT: [0,2]     .D=eeeeeeER    .    .    ..   lzcntw  2(%rsp), %cx
-# CHECK-NEXT: [1,0]     .D=======eeeeER.    .    ..   imull %edx, %ecx
-# CHECK-NEXT: [1,1]     . D======eeeeeeER   .    ..   lzcntw  (%rsp), %cx
-# CHECK-NEXT: [1,2]     . D========eeeeeeER .    ..   lzcntw  2(%rsp), %cx
-# CHECK-NEXT: [2,0]     .  D=============eeeeER  ..   imull %edx, %ecx
-# CHECK-NEXT: [2,1]     .  D=============eeeeeeER..   lzcntw  (%rsp), %cx
-# CHECK-NEXT: [2,2]     .   D==============eeeeeeER   lzcntw  2(%rsp), %cx
+# CHECK:      [0,0]     .DeeeeER  .    .    .    . .   imull  %edx, %ecx
+# CHECK-NEXT: [0,1]     .DeeeeeeER.    .    .    . .   lzcntw (%rsp), %cx
+# CHECK-NEXT: [0,2]     . D=eeeeeeER   .    .    . .   lzcntw 2(%rsp), %cx
+# CHECK-NEXT: [1,0]     . D=======eeeeER    .    . .   imull  %edx, %ecx
+# CHECK-NEXT: [1,1]     .  D======eeeeeeER  .    . .   lzcntw (%rsp), %cx
+# CHECK-NEXT: [1,2]     .  D========eeeeeeER.    . .   lzcntw 2(%rsp), %cx
+# CHECK-NEXT: [2,0]     .   D=============eeeeER . .   imull  %edx, %ecx
+# CHECK-NEXT: [2,1]     .   D=============eeeeeeER .   lzcntw (%rsp), %cx
+# CHECK-NEXT: [2,2]     .    D==============eeeeeeER   lzcntw 2(%rsp), %cx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     7.7    0.3    0.0       imull  %edx, %ecx
 # CHECK-NEXT: 1.     3     7.3    0.0    0.0       lzcntw (%rsp), %cx
 # CHECK-NEXT: 2.     3     8.7    1.0    0.0       lzcntw 2(%rsp), %cx
 # CHECK-NEXT:        3     7.9    0.4    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/partial-reg-update.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
 
 imul %ax, %cx
 add  %al, %cl
 add  %ecx, %ebx
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3
-# CHECK-NEXT: Total Cycles:      9
+# CHECK-NEXT: Total Cycles:      10
 # CHECK-NEXT: Total uOps:        3
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.33
-# CHECK-NEXT: IPC:               0.33
+# CHECK-NEXT: uOps Per Cycle:    0.30
+# CHECK-NEXT: IPC:               0.30
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      4     2.00                        imulw %ax, %cx
 # CHECK-NEXT:  1      1     1.00                        addb  %al, %cl
 # CHECK-NEXT:  1      1     1.00                        addl  %ecx, %ebx
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     012345678
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeER .   imulw %ax, %cx
-# CHECK-NEXT: [0,1]     D====eER.   addb  %al, %cl
-# CHECK-NEXT: [0,2]     D=====eER   addl  %ecx, %ebx
+# CHECK:      [0,0]     .DeeeeER .   imulw  %ax, %cx
+# CHECK-NEXT: [0,1]     .D====eER.   addb %al, %cl
+# CHECK-NEXT: [0,2]     .D=====eER   addl %ecx, %ebx
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       imulw  %ax, %cx
 # CHECK-NEXT: 1.     1     5.0    0.0    0.0       addb %al, %cl
 # CHECK-NEXT: 2.     1     6.0    0.0    0.0       addl %ecx, %ebx
 # CHECK-NEXT:        1     4.0    0.3    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/pipes-fpu.s

 vsqrtps     %xmm0, %xmm2
 
 # FPA/FPM YMM
 vaddps      %ymm0, %ymm1, %ymm2
 vsqrtps     %ymm0, %ymm2
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      800
-# CHECK-NEXT: Total Cycles:      1503
+# CHECK-NEXT: Total Cycles:      1508
 # CHECK-NEXT: Total uOps:        1500
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.00
+# CHECK-NEXT: uOps Per Cycle:    0.99
 # CHECK-NEXT: IPC:               0.53
 # CHECK-NEXT: Block RThroughput: 15.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad

 # CHECK-NEXT: [15]  - PdFPXBR
 # CHECK-NEXT: [16.0] - PdLoad
 # CHECK-NEXT: [16.1] - PdLoad
 # CHECK-NEXT: [17]  - PdMul
 # CHECK-NEXT: [18]  - PdStore
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]
-# CHECK-NEXT:  -      -      -      -      -      -      -     1.00   15.06  14.94  1.12   1.88   9.00   1.00   6.44   4.56    -      -      -      -      -      -      -
+# CHECK-NEXT:  -      -      -      -      -      -      -     1.00   15.09  14.91  1.10   1.90   9.00   1.00   6.00   5.00    -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
-# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     0.88   0.12   2.00    -     2.00   1.00    -      -      -      -      -      -      -     vpmulld  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     0.24   1.76    -      -     0.44   0.56    -      -      -      -      -      -      -     vpand  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     0.90   0.10   2.00    -     2.00   1.00    -      -      -      -      -      -      -     vpmulld  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     0.20   1.80    -      -      -     1.00    -      -      -      -      -      -      -     vpand  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -     vcvttps2dq %xmm0, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -     7.00    -     1.00    -      -      -      -      -      -      -      -     vpclmulqdq $0, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  -      -      -      -      -      -      -      -     0.52   0.48    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT:  -      -      -      -      -      -      -      -     4.50   4.50    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vsqrtps  %xmm0, %xmm2
-# CHECK-NEXT:  -      -      -      -      -      -      -      -     1.04   0.96    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     0.50   0.50    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     4.59   4.41    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vsqrtps  %xmm0, %xmm2
+# CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   1.00    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     9.00   9.00    -      -      -      -      -     2.00    -      -      -      -      -      -      -     vsqrtps  %ymm0, %ymm2
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          012
+# CHECK-NEXT:                     0123456789          01234567
 # CHECK-NEXT: Index     0123456789          0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .    .    .    .    . .   vpmulld %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [0,1]     D=eeE--R  .    .    .    .    . .   vpand %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [0,2]     D==eeeeER .    .    .    .    . .   vcvttps2dq  %xmm0, %xmm2
-# CHECK-NEXT: [0,3]     .D==eeeeeeeeeeeeER  .    .    . .   vpclmulqdq  $0, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [0,4]     . D===================eeeeeER . .   vaddps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [0,5]     . DeeeeeeeeeE---------------R . .   vsqrtps %xmm0, %xmm2
-# CHECK-NEXT: [0,6]     .  D===================eeeeeER. .   vaddps  %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [0,7]     .  DeeeeeeeeeE---------------R. .   vsqrtps %ymm0, %ymm2
-# CHECK-NEXT: [1,0]     .   D======eeeeeE------------R. .   vpmulld %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [1,1]     .   DeeE---------------------R. .   vpand %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [1,2]     .   D=eeeeE-------------------R .   vcvttps2dq  %xmm0, %xmm2
-# CHECK-NEXT: [1,3]     .    D=======eeeeeeeeeeeeE----R .   vpclmulqdq  $0, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [1,4]     .    .D==================eeeeeER.   vaddps  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: [1,5]     .    .D=====eeeeeeeeeE---------R.   vsqrtps %xmm0, %xmm2
-# CHECK-NEXT: [1,6]     .    . D==================eeeeeER   vaddps  %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [1,7]     .    . D=============eeeeeeeeeE-R   vsqrtps %ymm0, %ymm2
+# CHECK:      [0,0]     .DeeeeeER .    .    .    .    .    . .   vpmulld  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [0,1]     .D=eeE--R .    .    .    .    .    . .   vpand  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [0,2]     .D==eeeeER.    .    .    .    .    . .   vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: [0,3]     .   DeeeeeeeeeeeeER .    .    .    . .   vpclmulqdq $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [0,4]     .    DeeeeeE------R .    .    .    . .   vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [0,5]     .    DeeeeeeeeeE--R .    .    .    . .   vsqrtps  %xmm0, %xmm2
+# CHECK-NEXT: [0,6]     .    .DeeeeeE-----R .    .    .    . .   vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [0,7]     .    .D==eeeeeeeeeER.    .    .    . .   vsqrtps  %ymm0, %ymm2
+# CHECK-NEXT: [1,0]     .    . D====eeeeeE-R.    .    .    . .   vpmulld  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [1,1]     .    . DeeE--------R.    .    .    . .   vpand  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [1,2]     .    . DeeeeE------R.    .    .    . .   vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: [1,3]     .    .    D===eeeeeeeeeeeeER  .    . .   vpclmulqdq $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [1,4]     .    .    .D===eeeeeE------R  .    . .   vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: [1,5]     .    .    .D====eeeeeeeeeE-R  .    . .   vsqrtps  %xmm0, %xmm2
+# CHECK-NEXT: [1,6]     .    .    . D============eeeeeER   . .   vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [1,7]     .    .    . D==============eeeeeeeeeER   vsqrtps  %ymm0, %ymm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     2     4.0    4.0    6.0       vpmulld  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 1.     2     1.5    1.5    11.5      vpand  %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 2.     2     2.5    2.5    9.5       vcvttps2dq %xmm0, %xmm2
-# CHECK-NEXT: 3.     2     5.5    5.5    2.0       vpclmulqdq $0, %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 4.     2     19.5   19.5   0.0       vaddps %xmm0, %xmm1, %xmm2
-# CHECK-NEXT: 5.     2     3.5    3.5    12.0      vsqrtps  %xmm0, %xmm2
-# CHECK-NEXT: 6.     2     19.5   19.5   0.0       vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: 7.     2     7.5    7.5    8.0       vsqrtps  %ymm0, %ymm2
-# CHECK-NEXT:        2     7.9    7.9    6.1       <total>
+# CHECK-NEXT: 0.     2     3.0    3.0    0.5       vpmulld  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 1.     2     1.5    1.5    5.0       vpand  %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 2.     2     2.0    2.0    3.0       vcvttps2dq %xmm0, %xmm2
+# CHECK-NEXT: 3.     2     2.5    2.5    0.0       vpclmulqdq $0, %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 4.     2     2.5    2.5    6.0       vaddps %xmm0, %xmm1, %xmm2
+# CHECK-NEXT: 5.     2     3.0    3.0    1.5       vsqrtps  %xmm0, %xmm2
+# CHECK-NEXT: 6.     2     7.0    7.0    2.5       vaddps %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: 7.     2     9.0    9.0    0.0       vsqrtps  %ymm0, %ymm2
+# CHECK-NEXT:        2     3.8    3.8    2.3       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/pr37790.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -lqueue=2 -iterations=2 -resource-pressure=false -timeline -timeline-max-cycles=104 < %s | FileCheck %s
 
 int3
 stmxcsr (%rsp)
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      4
-# CHECK-NEXT: Total Cycles:      205
+# CHECK-NEXT: Total Cycles:      206
 # CHECK-NEXT: Total uOps:        6
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.03
 # CHECK-NEXT: IPC:               0.02
 # CHECK-NEXT: Block RThroughput: 18.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      100   0.50    *      *      U     int3
 # CHECK-NEXT:  2      1     18.00          *      U     stmxcsr (%rsp)
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789          0123456789          0123456789          0123456789
 # CHECK-NEXT: Index     0123456789          0123456789          0123456789          0123456789          0123456789          0123
 
-# CHECK:      [0,0]     DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER.   int3
-# CHECK-NEXT: [0,1]     D====================================================================================================eER   stmxcsr  (%rsp)
+# CHECK:      [0,0]     .DeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER   int3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     51.5   0.5    0.0       int3
 # CHECK-NEXT: 1.     2     151.0  0.0    0.0       stmxcsr  (%rsp)
 # CHECK-NEXT:        2     101.3  0.3    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/rank.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 add %eax, %ecx
 add %eax, %edx
 add %eax, %ebx
 add %edx, %esi
 add %ebx, %eax
 add %edx, %esi
 add %ebx, %eax
 add %ebx, %eax
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      800
-# CHECK-NEXT: Total Cycles:      803
+# CHECK-NEXT: Total Cycles:      804
 # CHECK-NEXT: Total uOps:        800
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.00
 # CHECK-NEXT: IPC:               1.00
 # CHECK-NEXT: Block RThroughput: 8.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %edx, %esi
 # CHECK-NEXT:  -      -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %ebx, %eax
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %edx, %esi
 # CHECK-NEXT:  -      -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %ebx, %eax
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     addl %ebx, %eax
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0123456
+# CHECK-NEXT: Index     0123456789          01234567
 
-# CHECK:      [0,0]     DeER .    .    .    .    ..   addl  %eax, %ecx
-# CHECK-NEXT: [0,1]     DeER .    .    .    .    ..   addl  %eax, %edx
-# CHECK-NEXT: [0,2]     D==eER    .    .    .    ..   addl  %eax, %ebx
-# CHECK-NEXT: [0,3]     D==eER    .    .    .    ..   addl  %edx, %esi
-# CHECK-NEXT: [0,4]     .D===eER  .    .    .    ..   addl  %ebx, %eax
-# CHECK-NEXT: [0,5]     .D===eER  .    .    .    ..   addl  %edx, %esi
-# CHECK-NEXT: [0,6]     .D=====eER.    .    .    ..   addl  %ebx, %eax
-# CHECK-NEXT: [0,7]     .D======eER    .    .    ..   addl  %ebx, %eax
-# CHECK-NEXT: [1,0]     . D========eER .    .    ..   addl  %eax, %ecx
-# CHECK-NEXT: [1,1]     . D======eE--R .    .    ..   addl  %eax, %edx
-# CHECK-NEXT: [1,2]     . D=======eE-R .    .    ..   addl  %eax, %ebx
-# CHECK-NEXT: [1,3]     . D=========eER.    .    ..   addl  %edx, %esi
-# CHECK-NEXT: [1,4]     .  D=========eER    .    ..   addl  %ebx, %eax
-# CHECK-NEXT: [1,5]     .  D==========eER   .    ..   addl  %edx, %esi
-# CHECK-NEXT: [1,6]     .  D===========eER  .    ..   addl  %ebx, %eax
-# CHECK-NEXT: [1,7]     .  D============eER .    ..   addl  %ebx, %eax
-# CHECK-NEXT: [2,0]     .   D==============eER   ..   addl  %eax, %ecx
-# CHECK-NEXT: [2,1]     .   D============eE--R   ..   addl  %eax, %edx
-# CHECK-NEXT: [2,2]     .   D=============eE-R   ..   addl  %eax, %ebx
-# CHECK-NEXT: [2,3]     .   D===============eER  ..   addl  %edx, %esi
-# CHECK-NEXT: [2,4]     .    D===============eER ..   addl  %ebx, %eax
-# CHECK-NEXT: [2,5]     .    D================eER..   addl  %edx, %esi
-# CHECK-NEXT: [2,6]     .    D=================eER.   addl  %ebx, %eax
-# CHECK-NEXT: [2,7]     .    D==================eER   addl  %ebx, %eax
+# CHECK:      [0,0]     .DeER.    .    .    .    . .   addl %eax, %ecx
+# CHECK-NEXT: [0,1]     .DeER.    .    .    .    . .   addl %eax, %edx
+# CHECK-NEXT: [0,2]     .D==eER   .    .    .    . .   addl %eax, %ebx
+# CHECK-NEXT: [0,3]     .D==eER   .    .    .    . .   addl %edx, %esi
+# CHECK-NEXT: [0,4]     . D===eER .    .    .    . .   addl %ebx, %eax
+# CHECK-NEXT: [0,5]     . D===eER .    .    .    . .   addl %edx, %esi
+# CHECK-NEXT: [0,6]     . D=====eER    .    .    . .   addl %ebx, %eax
+# CHECK-NEXT: [0,7]     . D======eER   .    .    . .   addl %ebx, %eax
+# CHECK-NEXT: [1,0]     .  D========eER.    .    . .   addl %eax, %ecx
+# CHECK-NEXT: [1,1]     .  D======eE--R.    .    . .   addl %eax, %edx
+# CHECK-NEXT: [1,2]     .  D=======eE-R.    .    . .   addl %eax, %ebx
+# CHECK-NEXT: [1,3]     .  D=========eER    .    . .   addl %edx, %esi
+# CHECK-NEXT: [1,4]     .   D=========eER   .    . .   addl %ebx, %eax
+# CHECK-NEXT: [1,5]     .   D==========eER  .    . .   addl %edx, %esi
+# CHECK-NEXT: [1,6]     .   D===========eER .    . .   addl %ebx, %eax
+# CHECK-NEXT: [1,7]     .   D============eER.    . .   addl %ebx, %eax
+# CHECK-NEXT: [2,0]     .    D==============eER  . .   addl %eax, %ecx
+# CHECK-NEXT: [2,1]     .    D============eE--R  . .   addl %eax, %edx
+# CHECK-NEXT: [2,2]     .    D=============eE-R  . .   addl %eax, %ebx
+# CHECK-NEXT: [2,3]     .    D===============eER . .   addl %edx, %esi
+# CHECK-NEXT: [2,4]     .    .D===============eER. .   addl %ebx, %eax
+# CHECK-NEXT: [2,5]     .    .D================eER .   addl %edx, %esi
+# CHECK-NEXT: [2,6]     .    .D=================eER.   addl %ebx, %eax
+# CHECK-NEXT: [2,7]     .    .D==================eER   addl %ebx, %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/BdVer2/rcu-statistics.s

# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -resource-pressure=false -retire-stats -iterations=1 < %s | FileCheck %s
   vaddps  %xmm0, %xmm1, %xmm2
   vaddps  %xmm0, %xmm1, %xmm2
   vaddps  %xmm0, %xmm1, %xmm2
   vaddps  %xmm0, %xmm1, %xmm2
   vaddps  %xmm0, %xmm1, %xmm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      16
-# CHECK-NEXT: Total Cycles:      22
+# CHECK-NEXT: Total Cycles:      23
 # CHECK-NEXT: Total uOps:        16
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.73
-# CHECK-NEXT: IPC:               0.73
+# CHECK-NEXT: uOps Per Cycle:    0.70
+# CHECK-NEXT: IPC:               0.70
 # CHECK-NEXT: Block RThroughput: 15.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT:  1      5     1.00                        vaddps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      5     1.00                        vaddps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      5     1.00                        vaddps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      5     1.00                        vaddps  %xmm0, %xmm1, %xmm2
 # CHECK-NEXT:  1      5     1.00                        vaddps  %xmm0, %xmm1, %xmm2
 
 # CHECK:      Retire Control Unit - number of cycles where we saw N instructions retired:
 # CHECK-NEXT: [# retired], [# cycles]
-# CHECK-NEXT:  0,           11  (50.0%)
-# CHECK-NEXT:  1,           9  (40.9%)
-# CHECK-NEXT:  3,           1  (4.5%)
-# CHECK-NEXT:  4,           1  (4.5%)
+# CHECK-NEXT:  0,           12  (52.2%)
+# CHECK-NEXT:  1,           9  (39.1%)
+# CHECK-NEXT:  3,           1  (4.3%)
+# CHECK-NEXT:  4,           1  (4.3%)
 
 # CHECK:      Total ROB Entries:                128
 # CHECK-NEXT: Max Used ROB Entries:             16  ( 12.5% )
 # CHECK-NEXT: Average Used ROB Entries per cy:  9  ( 7.0% )

llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s
 
 # The vmul can start executing 3cy in advance. That is beause the first use
 # operand (i.e. %xmm1) is a ReadAfterLd. That means, the memory operand is
 # evaluated before %xmm1.
 
 vaddps  %xmm0, %xmm0, %xmm1
 vmulps  (%rdi), %xmm1, %xmm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      13
+# CHECK-NEXT: Total Cycles:      14
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.15
-# CHECK-NEXT: IPC:               0.15
+# CHECK-NEXT: uOps Per Cycle:    0.14
+# CHECK-NEXT: IPC:               0.14
 # CHECK-NEXT: Block RThroughput: 1.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      5     1.00                        vaddps  %xmm0, %xmm0, %xmm1
 # CHECK-NEXT:  1      10    1.50    *                   vmulps  (%rdi), %xmm1, %xmm2
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012
+# CHECK-NEXT:                     0123
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  . .   vaddps  %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [0,1]     DeeeeeeeeeeER   vmulps  (%rdi), %xmm1, %xmm2
+# CHECK:      [0,0]     .DeeeeeER .  .   vaddps %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [0,1]     .DeeeeeeeeeeER   vmulps (%rdi), %xmm1, %xmm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vaddps %xmm0, %xmm0, %xmm1
 # CHECK-NEXT: 1.     1     1.0    0.0    0.0       vmulps (%rdi), %xmm1, %xmm2
 # CHECK-NEXT:        1     1.0    0.5    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=0 -timeline < %s | FileCheck %s
 
   imull  %esi
   imull  (%rdi)
 
 # The second integer multiply can start at cycle 2 because the implicit reads
 # can start after the load operand is evaluated.
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      15
+# CHECK-NEXT: Total Cycles:      16
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.13
 # CHECK-NEXT: IPC:               0.13
 # CHECK-NEXT: Block RThroughput: 8.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      4     4.00                        imull %esi
 # CHECK-NEXT:  1      8     4.00    *                   imull (%rdi)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01234
+# CHECK-NEXT:                     012345
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeER   .   .   imull %esi
-# CHECK-NEXT: [0,1]     D====eeeeeeeeER   imull (%rdi)
+# CHECK:      [0,0]     .DeeeeER  .    .   imull  %esi
+# CHECK-NEXT: [0,1]     .D====eeeeeeeeER   imull  (%rdi)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       imull  %esi
 # CHECK-NEXT: 1.     1     5.0    4.0    0.0       imull  (%rdi)
 # CHECK-NEXT:        1     3.0    2.5    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/read-advance-3.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=0 -timeline -dispatch=3 < %s | FileCheck %s
 
   add %rdi, %rsi
   add (%rsp), %rsi
   add %rdx, %r8
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3
-# CHECK-NEXT: Total Cycles:      8
+# CHECK-NEXT: Total Cycles:      9
 # CHECK-NEXT: Total uOps:        3
 
 # CHECK:      Dispatch Width:    3
-# CHECK-NEXT: uOps Per Cycle:    0.38
-# CHECK-NEXT: IPC:               0.38
+# CHECK-NEXT: uOps Per Cycle:    0.33
+# CHECK-NEXT: IPC:               0.33
 # CHECK-NEXT: Block RThroughput: 3.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      1     1.00                        addq  %rdi, %rsi
 # CHECK-NEXT:  1      5     1.50    *                   addq  (%rsp), %rsi
 # CHECK-NEXT:  1      1     1.00                        addq  %rdx, %r8
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     01234567
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DeER . .   addq %rdi, %rsi
-# CHECK-NEXT: [0,1]     DeeeeeER   addq (%rsp), %rsi
-# CHECK-NEXT: [0,2]     D==eE--R   addq %rdx, %r8
+# CHECK:      [0,0]     .DeER.  .   addq  %rdi, %rsi
+# CHECK-NEXT: [0,1]     .DeeeeeER   addq  (%rsp), %rsi
+# CHECK-NEXT: [0,2]     .D==eE--R   addq  %rdx, %r8
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       addq %rdi, %rsi
 # CHECK-NEXT: 1.     1     1.0    0.0    0.0       addq (%rsp), %rsi
 # CHECK-NEXT: 2.     1     3.0    3.0    2.0       addq %rdx, %r8
 # CHECK-NEXT:        1     1.7    1.3    0.7       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 # The register move from XMM0 to XMM1 can be eliminated at register renaming
 # stage. So, it should not consume pipeline resources.
 
 vxorps %xmm0, %xmm0, %xmm0
 vmovaps %xmm0, %xmm1
 vaddps %xmm1, %xmm1, %xmm2
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      9
-# CHECK-NEXT: Total Cycles:      13
+# CHECK-NEXT: Total Cycles:      14
 # CHECK-NEXT: Total uOps:        9
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.69
-# CHECK-NEXT: IPC:               0.69
+# CHECK-NEXT: uOps Per Cycle:    0.64
+# CHECK-NEXT: IPC:               0.64
 # CHECK-NEXT: Block RThroughput: 1.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vxorps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.67   1.33    -      -      -      -     0.33   0.67    -      -      -      -      -      -      -     vmovaps  %xmm0, %xmm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.67   0.33    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %xmm1, %xmm1, %xmm2
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012
+# CHECK-NEXT:                     0123
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DR   .    . .   vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     DeER .    . .   vmovaps %xmm0, %xmm1
-# CHECK-NEXT: [0,2]     D=eeeeeER . .   vaddps  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [1,0]     D-------R . .   vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     .D=eE---R . .   vmovaps %xmm0, %xmm1
-# CHECK-NEXT: [1,2]     .D===eeeeeER.   vaddps  %xmm1, %xmm1, %xmm2
-# CHECK-NEXT: [2,0]     .D---------R.   vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,1]     .D=eE------R.   vmovaps %xmm0, %xmm1
-# CHECK-NEXT: [2,2]     . D===eeeeeER   vaddps  %xmm1, %xmm1, %xmm2
+# CHECK:      [0,0]     .DR  .    .  .   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [0,1]     .DeER.    .  .   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [0,2]     .D=eeeeeER.  .   vaddps %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [1,0]     .D-------R.  .   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,1]     . D=eE---R.  .   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [1,2]     . D===eeeeeER.   vaddps %xmm1, %xmm1, %xmm2
+# CHECK-NEXT: [2,0]     . D---------R.   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,1]     . D=eE------R.   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [2,2]     .  D===eeeeeER   vaddps %xmm1, %xmm1, %xmm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     0.0    0.0    5.3       vxorps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT: 1.     3     1.7    1.7    3.0       vmovaps  %xmm0, %xmm1
 # CHECK-NEXT: 2.     3     3.3    1.0    0.0       vaddps %xmm1, %xmm1, %xmm2
 # CHECK-NEXT:        3     1.7    0.9    2.8       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 pxor %mm0, %mm0
 movq %mm0, %mm1
 
 xorps %xmm0, %xmm0
 movaps %xmm0, %xmm1
 movups %xmm1, %xmm2
 movapd %xmm2, %xmm3
 movupd %xmm3, %xmm4
 movdqa %xmm4, %xmm5
 movdqu %xmm5, %xmm0
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      27
-# CHECK-NEXT: Total Cycles:      17
+# CHECK-NEXT: Total Cycles:      18
 # CHECK-NEXT: Total uOps:        27
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.59
-# CHECK-NEXT: IPC:               1.59
+# CHECK-NEXT: uOps Per Cycle:    1.50
+# CHECK-NEXT: IPC:               1.50
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -      -     0.67   0.33    -      -      -      -      -      -      -     movaps %xmm0, %xmm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00    -      -      -      -      -     0.33   0.67    -      -      -      -      -      -      -     movups %xmm1, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -      -     0.67   0.33    -      -      -      -      -      -      -     movapd %xmm2, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00    -      -      -      -      -     0.33   0.67    -      -      -      -      -      -      -     movupd %xmm3, %xmm4
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     0.67   0.33    -      -     0.67   0.33    -      -      -      -      -      -      -     movdqa %xmm4, %xmm5
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     0.67   1.33    -      -     0.33   0.67    -      -      -      -      -      -      -     movdqu %xmm5, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456
+# CHECK-NEXT:                     01234567
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DR   .    .    ..   pxor  %mm0, %mm0
-# CHECK-NEXT: [0,1]     DeeER.    .    ..   movq  %mm0, %mm1
-# CHECK-NEXT: [0,2]     D---R.    .    ..   xorps %xmm0, %xmm0
-# CHECK-NEXT: [0,3]     DeE-R.    .    ..   movaps  %xmm0, %xmm1
-# CHECK-NEXT: [0,4]     .DeER.    .    ..   movups  %xmm1, %xmm2
-# CHECK-NEXT: [0,5]     .D=eER    .    ..   movapd  %xmm2, %xmm3
-# CHECK-NEXT: [0,6]     .D==eER   .    ..   movupd  %xmm3, %xmm4
-# CHECK-NEXT: [0,7]     .D===eER  .    ..   movdqa  %xmm4, %xmm5
-# CHECK-NEXT: [0,8]     . D===eER .    ..   movdqu  %xmm5, %xmm0
-# CHECK-NEXT: [1,0]     . D-----R .    ..   pxor  %mm0, %mm0
-# CHECK-NEXT: [1,1]     . DeeE--R .    ..   movq  %mm0, %mm1
-# CHECK-NEXT: [1,2]     . D-----R .    ..   xorps %xmm0, %xmm0
-# CHECK-NEXT: [1,3]     .  D=eE--R.    ..   movaps  %xmm0, %xmm1
-# CHECK-NEXT: [1,4]     .  D==eE-R.    ..   movups  %xmm1, %xmm2
-# CHECK-NEXT: [1,5]     .  D===eER.    ..   movapd  %xmm2, %xmm3
-# CHECK-NEXT: [1,6]     .  D====eER    ..   movupd  %xmm3, %xmm4
-# CHECK-NEXT: [1,7]     .   D====eER   ..   movdqa  %xmm4, %xmm5
-# CHECK-NEXT: [1,8]     .   D=====eER  ..   movdqu  %xmm5, %xmm0
-# CHECK-NEXT: [2,0]     .   D-------R  ..   pxor  %mm0, %mm0
-# CHECK-NEXT: [2,1]     .   D==eeE--R  ..   movq  %mm0, %mm1
-# CHECK-NEXT: [2,2]     .    D------R  ..   xorps %xmm0, %xmm0
-# CHECK-NEXT: [2,3]     .    D===eE--R ..   movaps  %xmm0, %xmm1
-# CHECK-NEXT: [2,4]     .    D====eE-R ..   movups  %xmm1, %xmm2
-# CHECK-NEXT: [2,5]     .    D=====eER ..   movapd  %xmm2, %xmm3
-# CHECK-NEXT: [2,6]     .    .D=====eER..   movupd  %xmm3, %xmm4
-# CHECK-NEXT: [2,7]     .    .D======eER.   movdqa  %xmm4, %xmm5
-# CHECK-NEXT: [2,8]     .    .D=======eER   movdqu  %xmm5, %xmm0
+# CHECK:      [0,0]     .DR  .    .    . .   pxor %mm0, %mm0
+# CHECK-NEXT: [0,1]     .DeeER    .    . .   movq %mm0, %mm1
+# CHECK-NEXT: [0,2]     .D---R    .    . .   xorps  %xmm0, %xmm0
+# CHECK-NEXT: [0,3]     .DeE-R    .    . .   movaps %xmm0, %xmm1
+# CHECK-NEXT: [0,4]     . DeER    .    . .   movups %xmm1, %xmm2
+# CHECK-NEXT: [0,5]     . D=eER   .    . .   movapd %xmm2, %xmm3
+# CHECK-NEXT: [0,6]     . D==eER  .    . .   movupd %xmm3, %xmm4
+# CHECK-NEXT: [0,7]     . D===eER .    . .   movdqa %xmm4, %xmm5
+# CHECK-NEXT: [0,8]     .  D===eER.    . .   movdqu %xmm5, %xmm0
+# CHECK-NEXT: [1,0]     .  D-----R.    . .   pxor %mm0, %mm0
+# CHECK-NEXT: [1,1]     .  DeeE--R.    . .   movq %mm0, %mm1
+# CHECK-NEXT: [1,2]     .  D-----R.    . .   xorps  %xmm0, %xmm0
+# CHECK-NEXT: [1,3]     .   D=eE--R    . .   movaps %xmm0, %xmm1
+# CHECK-NEXT: [1,4]     .   D==eE-R    . .   movups %xmm1, %xmm2
+# CHECK-NEXT: [1,5]     .   D===eER    . .   movapd %xmm2, %xmm3
+# CHECK-NEXT: [1,6]     .   D====eER   . .   movupd %xmm3, %xmm4
+# CHECK-NEXT: [1,7]     .    D====eER  . .   movdqa %xmm4, %xmm5
+# CHECK-NEXT: [1,8]     .    D=====eER . .   movdqu %xmm5, %xmm0
+# CHECK-NEXT: [2,0]     .    D-------R . .   pxor %mm0, %mm0
+# CHECK-NEXT: [2,1]     .    D==eeE--R . .   movq %mm0, %mm1
+# CHECK-NEXT: [2,2]     .    .D------R . .   xorps  %xmm0, %xmm0
+# CHECK-NEXT: [2,3]     .    .D===eE--R. .   movaps %xmm0, %xmm1
+# CHECK-NEXT: [2,4]     .    .D====eE-R. .   movups %xmm1, %xmm2
+# CHECK-NEXT: [2,5]     .    .D=====eER. .   movapd %xmm2, %xmm3
+# CHECK-NEXT: [2,6]     .    . D=====eER .   movupd %xmm3, %xmm4
+# CHECK-NEXT: [2,7]     .    . D======eER.   movdqa %xmm4, %xmm5
+# CHECK-NEXT: [2,8]     .    . D=======eER   movdqu %xmm5, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-3.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 vxorps  %xmm0, %xmm0, %xmm0
 vmovaps %xmm0, %xmm1
 vmovups %xmm1, %xmm2
 vmovapd %xmm2, %xmm3
 vmovupd %xmm3, %xmm4
 vmovdqa %xmm4, %xmm5
 vmovdqu %xmm5, %xmm0
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      21
-# CHECK-NEXT: Total Cycles:      17
+# CHECK-NEXT: Total Cycles:      18
 # CHECK-NEXT: Total uOps:        21
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.24
-# CHECK-NEXT: IPC:               1.24
+# CHECK-NEXT: uOps Per Cycle:    1.17
+# CHECK-NEXT: IPC:               1.17
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -      -     0.67   0.33    -      -      -      -      -      -      -     vmovaps  %xmm0, %xmm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00    -      -      -      -      -     1.00    -      -      -      -      -      -      -      -     vmovups  %xmm1, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmovapd  %xmm2, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00    -      -      -      -      -     1.00    -      -      -      -      -      -      -      -     vmovupd  %xmm3, %xmm4
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     1.00    -      -      -      -      -      -      -     vmovdqa  %xmm4, %xmm5
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     0.33   0.67    -      -      -      -      -      -      -     vmovdqu  %xmm5, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456
+# CHECK-NEXT:                     01234567
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DR   .    .    ..   vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     DeER .    .    ..   vmovaps %xmm0, %xmm1
-# CHECK-NEXT: [0,2]     D=eER.    .    ..   vmovups %xmm1, %xmm2
-# CHECK-NEXT: [0,3]     D==eER    .    ..   vmovapd %xmm2, %xmm3
-# CHECK-NEXT: [0,4]     .D==eER   .    ..   vmovupd %xmm3, %xmm4
-# CHECK-NEXT: [0,5]     .D===eER  .    ..   vmovdqa %xmm4, %xmm5
-# CHECK-NEXT: [0,6]     .D====eER .    ..   vmovdqu %xmm5, %xmm0
-# CHECK-NEXT: [1,0]     .D------R .    ..   vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     . D==eE-R .    ..   vmovaps %xmm0, %xmm1
-# CHECK-NEXT: [1,2]     . D===eER .    ..   vmovups %xmm1, %xmm2
-# CHECK-NEXT: [1,3]     . D====eER.    ..   vmovapd %xmm2, %xmm3
-# CHECK-NEXT: [1,4]     . D=====eER    ..   vmovupd %xmm3, %xmm4
-# CHECK-NEXT: [1,5]     .  D=====eER   ..   vmovdqa %xmm4, %xmm5
-# CHECK-NEXT: [1,6]     .  D======eER  ..   vmovdqu %xmm5, %xmm0
-# CHECK-NEXT: [2,0]     .  D--------R  ..   vxorps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,1]     .  D=====eE-R  ..   vmovaps %xmm0, %xmm1
-# CHECK-NEXT: [2,2]     .   D=====eER  ..   vmovups %xmm1, %xmm2
-# CHECK-NEXT: [2,3]     .   D======eER ..   vmovapd %xmm2, %xmm3
-# CHECK-NEXT: [2,4]     .   D=======eER..   vmovupd %xmm3, %xmm4
-# CHECK-NEXT: [2,5]     .   D========eER.   vmovdqa %xmm4, %xmm5
-# CHECK-NEXT: [2,6]     .    D========eER   vmovdqu %xmm5, %xmm0
+# CHECK:      [0,0]     .DR  .    .    . .   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [0,1]     .DeER.    .    . .   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [0,2]     .D=eER    .    . .   vmovups  %xmm1, %xmm2
+# CHECK-NEXT: [0,3]     .D==eER   .    . .   vmovapd  %xmm2, %xmm3
+# CHECK-NEXT: [0,4]     . D==eER  .    . .   vmovupd  %xmm3, %xmm4
+# CHECK-NEXT: [0,5]     . D===eER .    . .   vmovdqa  %xmm4, %xmm5
+# CHECK-NEXT: [0,6]     . D====eER.    . .   vmovdqu  %xmm5, %xmm0
+# CHECK-NEXT: [1,0]     . D------R.    . .   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,1]     .  D==eE-R.    . .   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [1,2]     .  D===eER.    . .   vmovups  %xmm1, %xmm2
+# CHECK-NEXT: [1,3]     .  D====eER    . .   vmovapd  %xmm2, %xmm3
+# CHECK-NEXT: [1,4]     .  D=====eER   . .   vmovupd  %xmm3, %xmm4
+# CHECK-NEXT: [1,5]     .   D=====eER  . .   vmovdqa  %xmm4, %xmm5
+# CHECK-NEXT: [1,6]     .   D======eER . .   vmovdqu  %xmm5, %xmm0
+# CHECK-NEXT: [2,0]     .   D--------R . .   vxorps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,1]     .   D=====eE-R . .   vmovaps  %xmm0, %xmm1
+# CHECK-NEXT: [2,2]     .    D=====eER . .   vmovups  %xmm1, %xmm2
+# CHECK-NEXT: [2,3]     .    D======eER. .   vmovapd  %xmm2, %xmm3
+# CHECK-NEXT: [2,4]     .    D=======eER .   vmovupd  %xmm3, %xmm4
+# CHECK-NEXT: [2,5]     .    D========eER.   vmovdqa  %xmm4, %xmm5
+# CHECK-NEXT: [2,6]     .    .D========eER   vmovdqu  %xmm5, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     0.0    0.0    4.7       vxorps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT: 1.     3     3.3    3.3    0.7       vmovaps  %xmm0, %xmm1
 # CHECK-NEXT: 2.     3     4.0    0.0    0.0       vmovups  %xmm1, %xmm2
 # CHECK-NEXT: 3.     3     5.0    0.0    0.0       vmovapd  %xmm2, %xmm3
 # CHECK-NEXT: 4.     3     5.7    0.0    0.0       vmovupd  %xmm3, %xmm4
 # CHECK-NEXT: 5.     3     6.3    0.0    0.0       vmovdqa  %xmm4, %xmm5
 # CHECK-NEXT: 6.     3     7.0    0.0    0.0       vmovdqu  %xmm5, %xmm0
 # CHECK-NEXT:        3     4.5    0.5    0.8       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-4.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 xor %eax, %eax
 mov %eax, %ebx
 mov %ebx, %ecx
 mov %ecx, %edx
 mov %edx, %eax
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      15
-# CHECK-NEXT: Total Cycles:      15
+# CHECK-NEXT: Total Cycles:      16
 # CHECK-NEXT: Total uOps:        15
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.00
-# CHECK-NEXT: IPC:               1.00
+# CHECK-NEXT: uOps Per Cycle:    0.94
+# CHECK-NEXT: IPC:               0.94
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     xorl %eax, %eax
 # CHECK-NEXT:  -      -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl %eax, %ebx
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl %ebx, %ecx
 # CHECK-NEXT:  -      -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl %ecx, %edx
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movl %edx, %eax
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01234
+# CHECK-NEXT:                     012345
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DR   .    .   .   xorl  %eax, %eax
-# CHECK-NEXT: [0,1]     DeER .    .   .   movl  %eax, %ebx
-# CHECK-NEXT: [0,2]     D=eER.    .   .   movl  %ebx, %ecx
-# CHECK-NEXT: [0,3]     D==eER    .   .   movl  %ecx, %edx
-# CHECK-NEXT: [0,4]     .D==eER   .   .   movl  %edx, %eax
-# CHECK-NEXT: [1,0]     .D----R   .   .   xorl  %eax, %eax
-# CHECK-NEXT: [1,1]     .D===eER  .   .   movl  %eax, %ebx
-# CHECK-NEXT: [1,2]     .D====eER .   .   movl  %ebx, %ecx
-# CHECK-NEXT: [1,3]     . D====eER.   .   movl  %ecx, %edx
-# CHECK-NEXT: [1,4]     . D=====eER   .   movl  %edx, %eax
-# CHECK-NEXT: [2,0]     . D-------R   .   xorl  %eax, %eax
-# CHECK-NEXT: [2,1]     . D======eER  .   movl  %eax, %ebx
-# CHECK-NEXT: [2,2]     .  D======eER .   movl  %ebx, %ecx
-# CHECK-NEXT: [2,3]     .  D=======eER.   movl  %ecx, %edx
-# CHECK-NEXT: [2,4]     .  D========eER   movl  %edx, %eax
+# CHECK:      [0,0]     .DR  .    .    .   xorl %eax, %eax
+# CHECK-NEXT: [0,1]     .DeER.    .    .   movl %eax, %ebx
+# CHECK-NEXT: [0,2]     .D=eER    .    .   movl %ebx, %ecx
+# CHECK-NEXT: [0,3]     .D==eER   .    .   movl %ecx, %edx
+# CHECK-NEXT: [0,4]     . D==eER  .    .   movl %edx, %eax
+# CHECK-NEXT: [1,0]     . D----R  .    .   xorl %eax, %eax
+# CHECK-NEXT: [1,1]     . D===eER .    .   movl %eax, %ebx
+# CHECK-NEXT: [1,2]     . D====eER.    .   movl %ebx, %ecx
+# CHECK-NEXT: [1,3]     .  D====eER    .   movl %ecx, %edx
+# CHECK-NEXT: [1,4]     .  D=====eER   .   movl %edx, %eax
+# CHECK-NEXT: [2,0]     .  D-------R   .   xorl %eax, %eax
+# CHECK-NEXT: [2,1]     .  D======eER  .   movl %eax, %ebx
+# CHECK-NEXT: [2,2]     .   D======eER .   movl %ebx, %ecx
+# CHECK-NEXT: [2,3]     .   D=======eER.   movl %ecx, %edx
+# CHECK-NEXT: [2,4]     .   D========eER   movl %edx, %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     0.0    0.0    3.7       xorl %eax, %eax
 # CHECK-NEXT: 1.     3     4.0    4.0    0.0       movl %eax, %ebx
 # CHECK-NEXT: 2.     3     4.7    0.0    0.0       movl %ebx, %ecx
 # CHECK-NEXT: 3.     3     5.3    0.0    0.0       movl %ecx, %edx
 # CHECK-NEXT: 4.     3     6.0    0.0    0.0       movl %edx, %eax
 # CHECK-NEXT:        3     4.0    0.8    0.7       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/reg-move-elimination-5.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=3 -timeline -register-file-stats < %s | FileCheck %s
 
 xor %rax, %rax
 mov %rax, %rbx
 mov %rbx, %rcx
 mov %rcx, %rdx
 mov %rdx, %rax
 
 # CHECK:      Iterations:        3
 # CHECK-NEXT: Instructions:      15
-# CHECK-NEXT: Total Cycles:      15
+# CHECK-NEXT: Total Cycles:      16
 # CHECK-NEXT: Total uOps:        15
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.00
-# CHECK-NEXT: IPC:               1.00
+# CHECK-NEXT: uOps Per Cycle:    0.94
+# CHECK-NEXT: IPC:               0.94
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     xorq %rax, %rax
 # CHECK-NEXT:  -      -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq %rax, %rbx
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq %rbx, %rcx
 # CHECK-NEXT:  -      -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq %rcx, %rdx
 # CHECK-NEXT:  -      -      -      -      -     2.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     movq %rdx, %rax
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01234
+# CHECK-NEXT:                     012345
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DR   .    .   .   xorq  %rax, %rax
-# CHECK-NEXT: [0,1]     DeER .    .   .   movq  %rax, %rbx
-# CHECK-NEXT: [0,2]     D=eER.    .   .   movq  %rbx, %rcx
-# CHECK-NEXT: [0,3]     D==eER    .   .   movq  %rcx, %rdx
-# CHECK-NEXT: [0,4]     .D==eER   .   .   movq  %rdx, %rax
-# CHECK-NEXT: [1,0]     .D----R   .   .   xorq  %rax, %rax
-# CHECK-NEXT: [1,1]     .D===eER  .   .   movq  %rax, %rbx
-# CHECK-NEXT: [1,2]     .D====eER .   .   movq  %rbx, %rcx
-# CHECK-NEXT: [1,3]     . D====eER.   .   movq  %rcx, %rdx
-# CHECK-NEXT: [1,4]     . D=====eER   .   movq  %rdx, %rax
-# CHECK-NEXT: [2,0]     . D-------R   .   xorq  %rax, %rax
-# CHECK-NEXT: [2,1]     . D======eER  .   movq  %rax, %rbx
-# CHECK-NEXT: [2,2]     .  D======eER .   movq  %rbx, %rcx
-# CHECK-NEXT: [2,3]     .  D=======eER.   movq  %rcx, %rdx
-# CHECK-NEXT: [2,4]     .  D========eER   movq  %rdx, %rax
+# CHECK:      [0,0]     .DR  .    .    .   xorq %rax, %rax
+# CHECK-NEXT: [0,1]     .DeER.    .    .   movq %rax, %rbx
+# CHECK-NEXT: [0,2]     .D=eER    .    .   movq %rbx, %rcx
+# CHECK-NEXT: [0,3]     .D==eER   .    .   movq %rcx, %rdx
+# CHECK-NEXT: [0,4]     . D==eER  .    .   movq %rdx, %rax
+# CHECK-NEXT: [1,0]     . D----R  .    .   xorq %rax, %rax
+# CHECK-NEXT: [1,1]     . D===eER .    .   movq %rax, %rbx
+# CHECK-NEXT: [1,2]     . D====eER.    .   movq %rbx, %rcx
+# CHECK-NEXT: [1,3]     .  D====eER    .   movq %rcx, %rdx
+# CHECK-NEXT: [1,4]     .  D=====eER   .   movq %rdx, %rax
+# CHECK-NEXT: [2,0]     .  D-------R   .   xorq %rax, %rax
+# CHECK-NEXT: [2,1]     .  D======eER  .   movq %rax, %rbx
+# CHECK-NEXT: [2,2]     .   D======eER .   movq %rbx, %rcx
+# CHECK-NEXT: [2,3]     .   D=======eER.   movq %rcx, %rdx
+# CHECK-NEXT: [2,4]     .   D========eER   movq %rdx, %rax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     0.0    0.0    3.7       xorq %rax, %rax
 # CHECK-NEXT: 1.     3     4.0    4.0    0.0       movq %rax, %rbx
 # CHECK-NEXT: 2.     3     4.7    0.0    0.0       movq %rbx, %rcx
 # CHECK-NEXT: 3.     3     5.3    0.0    0.0       movq %rcx, %rdx
 # CHECK-NEXT: 4.     3     6.0    0.0    0.0       movq %rdx, %rax
 # CHECK-NEXT:        3     4.0    0.8    0.7       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/register-files-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=5 -instruction-info=false -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s
 
 vaddps %xmm0, %xmm0, %xmm0
 vmulps %xmm0, %xmm0, %xmm0
 
 # CHECK:      Iterations:        5
 # CHECK-NEXT: Instructions:      10
-# CHECK-NEXT: Total Cycles:      53
+# CHECK-NEXT: Total Cycles:      54
 # CHECK-NEXT: Total uOps:        10
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.19
 # CHECK-NEXT: IPC:               0.19
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              50  (94.3%)
+# CHECK-NEXT:  0,              51  (94.4%)
 # CHECK-NEXT:  2,              1  (1.9%)
-# CHECK-NEXT:  4,              2  (3.8%)
+# CHECK-NEXT:  4,              2  (3.7%)
 
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    10
 # CHECK-NEXT: Max number of mappings used:         10
 
 # CHECK:      *  Register File #1 -- PdFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     160
 # CHECK-NEXT:    Total number of mappings created: 10

 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   1.00    -      -      -      -     1.00   1.00    -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00    -      -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps %xmm0, %xmm0, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          0123456789          012
+# CHECK-NEXT:                     0123456789          0123456789          0123
 # CHECK-NEXT: Index     0123456789          0123456789          0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .    .    .    .    .    .    .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     D=====eeeeeER  .    .    .    .    .    .    .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,0]     D==========eeeeeER  .    .    .    .    .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     D===============eeeeeER  .    .    .    .    .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,0]     .D===================eeeeeER  .    .    .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,1]     .D========================eeeeeER  .    .    .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [3,0]     .D=============================eeeeeER  .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [3,1]     .D==================================eeeeeER  .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [4,0]     . D======================================eeeeeER  . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [4,1]     . D===========================================eeeeeER   vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [0,0]     .DeeeeeER .    .    .    .    .    .    .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [0,1]     .D=====eeeeeER .    .    .    .    .    .    .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,0]     .D==========eeeeeER .    .    .    .    .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,1]     .D===============eeeeeER .    .    .    .    .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,0]     . D===================eeeeeER .    .    .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,1]     . D========================eeeeeER .    .    .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [3,0]     . D=============================eeeeeER .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [3,1]     . D==================================eeeeeER .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [4,0]     .  D======================================eeeeeER .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [4,1]     .  D===========================================eeeeeER   vmulps %xmm0, %xmm0, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     5     20.2   0.2    0.0       vaddps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT: 1.     5     25.2   0.0    0.0       vmulps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT:        5     22.7   0.1    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/register-files-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -register-file-size=5 -iterations=5 -instruction-info=false -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s
 
 vaddps %xmm0, %xmm0, %xmm0
 vmulps %xmm0, %xmm0, %xmm0
 
 # CHECK:      Iterations:        5
 # CHECK-NEXT: Instructions:      10
-# CHECK-NEXT: Total Cycles:      53
+# CHECK-NEXT: Total Cycles:      54
 # CHECK-NEXT: Total uOps:        10
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.19
 # CHECK-NEXT: IPC:               0.19
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
-# CHECK-NEXT: RAT     - Register unavailable:                      26  (49.1%)
+# CHECK-NEXT: RAT     - Register unavailable:                      26  (48.1%)
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              46  (86.8%)
-# CHECK-NEXT:  1,              6  (11.3%)
+# CHECK-NEXT:  0,              47  (87.0%)
+# CHECK-NEXT:  1,              6  (11.1%)
 # CHECK-NEXT:  4,              1  (1.9%)
 
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    10
 # CHECK-NEXT: Max number of mappings used:         5
 
 # CHECK:      *  Register File #1 -- PdFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     160

 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   1.00    -      -      -      -     1.00   1.00    -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     1.00    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00    -      -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps %xmm0, %xmm0, %xmm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          0123456789          012
+# CHECK-NEXT:                     0123456789          0123456789          0123
 # CHECK-NEXT: Index     0123456789          0123456789          0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .    .    .    .    .    .    .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [0,1]     D=====eeeeeER  .    .    .    .    .    .    .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,0]     D==========eeeeeER  .    .    .    .    .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [1,1]     D===============eeeeeER  .    .    .    .    .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,0]     .D===================eeeeeER  .    .    .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [2,1]     .    . D==================eeeeeER  .    .    .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [3,0]     .    .    . D==================eeeeeER  .    .    . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [3,1]     .    .    .    . D==================eeeeeER  .    . .   vmulps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [4,0]     .    .    .    .    . D==================eeeeeER  . .   vaddps  %xmm0, %xmm0, %xmm0
-# CHECK-NEXT: [4,1]     .    .    .    .    .    . D==================eeeeeER   vmulps  %xmm0, %xmm0, %xmm0
+# CHECK:      [0,0]     .DeeeeeER .    .    .    .    .    .    .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [0,1]     .D=====eeeeeER .    .    .    .    .    .    .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,0]     .D==========eeeeeER .    .    .    .    .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [1,1]     .D===============eeeeeER .    .    .    .    .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,0]     . D===================eeeeeER .    .    .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [2,1]     .    .  D==================eeeeeER .    .    .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [3,0]     .    .    .  D==================eeeeeER .    .    .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [3,1]     .    .    .    .  D==================eeeeeER .    .  .   vmulps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [4,0]     .    .    .    .    .  D==================eeeeeER .  .   vaddps %xmm0, %xmm0, %xmm0
+# CHECK-NEXT: [4,1]     .    .    .    .    .    .  D==================eeeeeER   vmulps %xmm0, %xmm0, %xmm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     5     14.0   0.2    0.0       vaddps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT: 1.     5     15.8   0.0    0.0       vmulps %xmm0, %xmm0, %xmm0
 # CHECK-NEXT:        5     14.9   0.1    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -register-file-size=5 -iterations=2 -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s
 
 idiv %eax
 
 # CHECK:      Iterations:        2
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      42
+# CHECK-NEXT: Total Cycles:      43
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.10
+# CHECK-NEXT: uOps Per Cycle:    0.09
 # CHECK-NEXT: IPC:               0.05
 # CHECK-NEXT: Block RThroughput: 25.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  2      14    25.00                 U     idivl %eax
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
-# CHECK-NEXT: RAT     - Register unavailable:                      16  (38.1%)
+# CHECK-NEXT: RAT     - Register unavailable:                      16  (37.2%)
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              40  (95.2%)
-# CHECK-NEXT:  2,              2  (4.8%)
+# CHECK-NEXT:  0,              41  (95.3%)
+# CHECK-NEXT:  2,              2  (4.7%)
 
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    6
 # CHECK-NEXT: Max number of mappings used:         3
 
 # CHECK:      *  Register File #1 -- PdFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     160
 # CHECK-NEXT:    Total number of mappings created: 0

 # CHECK-NEXT:  -      -      -      -     25.00   -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -     25.00   -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     idivl  %eax
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789
-# CHECK-NEXT: Index     0123456789          0123456789          01
+# CHECK-NEXT: Index     0123456789          0123456789          012
 
-# CHECK:      [0,0]     DeeeeeeeeeeeeeeER   .    .    .    .    ..   idivl  %eax
-# CHECK-NEXT: [1,0]     .    .    .    .D=========eeeeeeeeeeeeeeER   idivl  %eax
+# CHECK:      [0,0]     .DeeeeeeeeeeeeeeER  .    .    .    .    . .   idivl %eax
+# CHECK-NEXT: [1,0]     .    .    .    . D=========eeeeeeeeeeeeeeER   idivl %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     5.5    5.5    0.0       idivl  %eax

llvm/test/tools/llvm-mca/X86/BdVer2/register-files-4.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=22 -dispatch-stats -register-file-stats -resource-pressure=false -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 idiv %eax
 
 # CHECK:      Iterations:        22
 # CHECK-NEXT: Instructions:      22
-# CHECK-NEXT: Total Cycles:      542
+# CHECK-NEXT: Total Cycles:      543
 # CHECK-NEXT: Total uOps:        44
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.08
 # CHECK-NEXT: IPC:               0.04
 # CHECK-NEXT: Block RThroughput: 25.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              531  (98.0%)
+# CHECK-NEXT:  0,              532  (98.0%)
 # CHECK-NEXT:  4,              11  (2.0%)
 
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    66
 # CHECK-NEXT: Max number of mappings used:         66
 
 # CHECK:      *  Register File #1 -- PdFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     160
 # CHECK-NEXT:    Total number of mappings created: 0
 # CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      *  Register File #2 -- PdIntegerPRF:
 # CHECK-NEXT:    Number of physical registers:     96
 # CHECK-NEXT:    Total number of mappings created: 66
 # CHECK-NEXT:    Max number of mappings used:      66
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789          0123456789
-# CHECK-NEXT: Index     0123456789          0123456789          0123456789          0123456
+# CHECK-NEXT: Index     0123456789          0123456789          0123456789          01234567
 
-# CHECK:      [0,0]     DeeeeeeeeeeeeeeER   .    .    .    .    .    .    .    .    .    ..   idivl %eax
-# CHECK-NEXT: [1,0]     D=========================eeeeeeeeeeeeeeER   .    .    .    .    ..   idivl %eax
-# CHECK-NEXT: [2,0]     .D=================================================eeeeeeeeeeeeeeER   idivl %eax
+# CHECK:      [0,0]     .DeeeeeeeeeeeeeeER  .    .    .    .    .    .    .    .    .    . .   idivl  %eax
+# CHECK-NEXT: [1,0]     .D=========================eeeeeeeeeeeeeeER  .    .    .    .    . .   idivl  %eax
+# CHECK-NEXT: [2,0]     . D=================================================eeeeeeeeeeeeeeER   idivl  %eax
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     25.7   7.7    0.0       idivl  %eax

llvm/test/tools/llvm-mca/X86/BdVer2/register-files-5.s

# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=false -instruction-info=false -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s
   vaddps %ymm2, %ymm0, %ymm15
   vaddps %ymm3, %ymm0, %ymm2
   vaddps %ymm3, %ymm0, %ymm4
   vaddps %ymm3, %ymm0, %ymm5
   vaddps %ymm3, %ymm0, %ymm6
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      33
-# CHECK-NEXT: Total Cycles:      48
+# CHECK-NEXT: Total Cycles:      49
 # CHECK-NEXT: Total uOps:        66
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.38
-# CHECK-NEXT: IPC:               0.69
+# CHECK-NEXT: uOps Per Cycle:    1.35
+# CHECK-NEXT: IPC:               0.67
 # CHECK-NEXT: Block RThroughput: 41.0
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
 # CHECK-NEXT: SQ      - Store queue full:                          0
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              31  (64.6%)
-# CHECK-NEXT:  2,              1  (2.1%)
-# CHECK-NEXT:  4,              16  (33.3%)
+# CHECK-NEXT:  0,              32  (65.3%)
+# CHECK-NEXT:  2,              1  (2.0%)
+# CHECK-NEXT:  4,              16  (32.7%)
 
 # CHECK:      Register File statistics:
 # CHECK-NEXT: Total number of mappings created:    66
 # CHECK-NEXT: Max number of mappings used:         54
 
 # CHECK:      *  Register File #1 -- PdFpuPRF:
 # CHECK-NEXT:    Number of physical registers:     160
 # CHECK-NEXT:    Total number of mappings created: 66
 # CHECK-NEXT:    Max number of mappings used:      54
 
 # CHECK:      *  Register File #2 -- PdIntegerPRF:
 # CHECK-NEXT:    Number of physical registers:     96
 # CHECK-NEXT:    Total number of mappings created: 0
 # CHECK-NEXT:    Max number of mappings used:      0
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789
-# CHECK-NEXT: Index     0123456789          0123456789          01234567
+# CHECK-NEXT: Index     0123456789          0123456789          012345678
 
-# CHECK:      [0,0]     DeeeeeeeeeER   .    .    .    .    .    .    . .   vdivps %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [0,1]     DeeeeeE----R   .    .    .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm2
-# CHECK-NEXT: [0,2]     .D=eeeeeE--R   .    .    .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm3
-# CHECK-NEXT: [0,3]     .D===eeeeeER   .    .    .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm4
-# CHECK-NEXT: [0,4]     . D====eeeeeER .    .    .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm5
-# CHECK-NEXT: [0,5]     . D======eeeeeER    .    .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm6
-# CHECK-NEXT: [0,6]     .  D=======eeeeeER  .    .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm7
-# CHECK-NEXT: [0,7]     .  D===========eeeeeER   .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm8
-# CHECK-NEXT: [0,8]     .   D============eeeeeER .    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm9
-# CHECK-NEXT: [0,9]     .   D==============eeeeeER    .    .    .    . .   vaddps %ymm0, %ymm0, %ymm10
-# CHECK-NEXT: [0,10]    .    D==============eeeeeER   .    .    .    . .   vaddps %ymm0, %ymm0, %ymm11
-# CHECK-NEXT: [0,11]    .    D===============eeeeeER  .    .    .    . .   vaddps %ymm0, %ymm0, %ymm12
-# CHECK-NEXT: [0,12]    .    .D===============eeeeeER .    .    .    . .   vaddps %ymm0, %ymm0, %ymm13
-# CHECK-NEXT: [0,13]    .    .D=================eeeeeER    .    .    . .   vaddps %ymm0, %ymm0, %ymm14
-# CHECK-NEXT: [0,14]    .    . D=================eeeeeER   .    .    . .   vaddps %ymm0, %ymm0, %ymm15
-# CHECK-NEXT: [0,15]    .    . D=====eeeeeE------------R   .    .    . .   vaddps %ymm2, %ymm0, %ymm0
-# CHECK-NEXT: [0,16]    .    .  D==============eeeeeE--R   .    .    . .   vaddps %ymm2, %ymm0, %ymm3
-# CHECK-NEXT: [0,17]    .    .  D=================eeeeeER  .    .    . .   vaddps %ymm2, %ymm0, %ymm4
-# CHECK-NEXT: [0,18]    .    .   D=================eeeeeER .    .    . .   vaddps %ymm2, %ymm0, %ymm5
-# CHECK-NEXT: [0,19]    .    .   D==================eeeeeER.    .    . .   vaddps %ymm2, %ymm0, %ymm6
-# CHECK-NEXT: [0,20]    .    .    D==================eeeeeER    .    . .   vaddps %ymm2, %ymm0, %ymm7
-# CHECK-NEXT: [0,21]    .    .    D===================eeeeeER   .    . .   vaddps %ymm2, %ymm0, %ymm8
-# CHECK-NEXT: [0,22]    .    .    .D===================eeeeeER  .    . .   vaddps %ymm2, %ymm0, %ymm9
-# CHECK-NEXT: [0,23]    .    .    .D====================eeeeeER .    . .   vaddps %ymm2, %ymm0, %ymm10
-# CHECK-NEXT: [0,24]    .    .    . D====================eeeeeER.    . .   vaddps %ymm2, %ymm0, %ymm11
-# CHECK-NEXT: [0,25]    .    .    . D=====================eeeeeER    . .   vaddps %ymm2, %ymm0, %ymm12
-# CHECK-NEXT: [0,26]    .    .    .  D=====================eeeeeER   . .   vaddps %ymm2, %ymm0, %ymm13
-# CHECK-NEXT: [0,27]    .    .    .  D======================eeeeeER  . .   vaddps %ymm2, %ymm0, %ymm14
-# CHECK-NEXT: [0,28]    .    .    .   D======================eeeeeER . .   vaddps %ymm2, %ymm0, %ymm15
-# CHECK-NEXT: [0,29]    .    .    .   D=======================eeeeeER. .   vaddps %ymm3, %ymm0, %ymm2
-# CHECK-NEXT: [0,30]    .    .    .    D=======================eeeeeER .   vaddps %ymm3, %ymm0, %ymm4
-# CHECK-NEXT: [0,31]    .    .    .    D========================eeeeeER.   vaddps %ymm3, %ymm0, %ymm5
-# CHECK-NEXT: [0,32]    .    .    .    .D========================eeeeeER   vaddps %ymm3, %ymm0, %ymm6
+# CHECK:      [0,0]     .DeeeeeeeeeER  .    .    .    .    .    .    .  .   vdivps  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [0,1]     .DeeeeeE----R  .    .    .    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm2
+# CHECK-NEXT: [0,2]     . D=eeeeeE--R  .    .    .    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm3
+# CHECK-NEXT: [0,3]     . D===eeeeeER  .    .    .    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm4
+# CHECK-NEXT: [0,4]     .  D====eeeeeER.    .    .    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm5
+# CHECK-NEXT: [0,5]     .  D======eeeeeER   .    .    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm6
+# CHECK-NEXT: [0,6]     .   D=======eeeeeER .    .    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm7
+# CHECK-NEXT: [0,7]     .   D===========eeeeeER  .    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm8
+# CHECK-NEXT: [0,8]     .    D============eeeeeER.    .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm9
+# CHECK-NEXT: [0,9]     .    D==============eeeeeER   .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm10
+# CHECK-NEXT: [0,10]    .    .D==============eeeeeER  .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm11
+# CHECK-NEXT: [0,11]    .    .D===============eeeeeER .    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm12
+# CHECK-NEXT: [0,12]    .    . D===============eeeeeER.    .    .    .  .   vaddps  %ymm0, %ymm0, %ymm13
+# CHECK-NEXT: [0,13]    .    . D=================eeeeeER   .    .    .  .   vaddps  %ymm0, %ymm0, %ymm14
+# CHECK-NEXT: [0,14]    .    .  D=================eeeeeER  .    .    .  .   vaddps  %ymm0, %ymm0, %ymm15
+# CHECK-NEXT: [0,15]    .    .  D=====eeeeeE------------R  .    .    .  .   vaddps  %ymm2, %ymm0, %ymm0
+# CHECK-NEXT: [0,16]    .    .   D==============eeeeeE--R  .    .    .  .   vaddps  %ymm2, %ymm0, %ymm3
+# CHECK-NEXT: [0,17]    .    .   D=================eeeeeER .    .    .  .   vaddps  %ymm2, %ymm0, %ymm4
+# CHECK-NEXT: [0,18]    .    .    D=================eeeeeER.    .    .  .   vaddps  %ymm2, %ymm0, %ymm5
+# CHECK-NEXT: [0,19]    .    .    D==================eeeeeER    .    .  .   vaddps  %ymm2, %ymm0, %ymm6
+# CHECK-NEXT: [0,20]    .    .    .D==================eeeeeER   .    .  .   vaddps  %ymm2, %ymm0, %ymm7
+# CHECK-NEXT: [0,21]    .    .    .D===================eeeeeER  .    .  .   vaddps  %ymm2, %ymm0, %ymm8
+# CHECK-NEXT: [0,22]    .    .    . D===================eeeeeER .    .  .   vaddps  %ymm2, %ymm0, %ymm9
+# CHECK-NEXT: [0,23]    .    .    . D====================eeeeeER.    .  .   vaddps  %ymm2, %ymm0, %ymm10
+# CHECK-NEXT: [0,24]    .    .    .  D====================eeeeeER    .  .   vaddps  %ymm2, %ymm0, %ymm11
+# CHECK-NEXT: [0,25]    .    .    .  D=====================eeeeeER   .  .   vaddps  %ymm2, %ymm0, %ymm12
+# CHECK-NEXT: [0,26]    .    .    .   D=====================eeeeeER  .  .   vaddps  %ymm2, %ymm0, %ymm13
+# CHECK-NEXT: [0,27]    .    .    .   D======================eeeeeER .  .   vaddps  %ymm2, %ymm0, %ymm14
+# CHECK-NEXT: [0,28]    .    .    .    D======================eeeeeER.  .   vaddps  %ymm2, %ymm0, %ymm15
+# CHECK-NEXT: [0,29]    .    .    .    D=======================eeeeeER  .   vaddps  %ymm3, %ymm0, %ymm2
+# CHECK-NEXT: [0,30]    .    .    .    .D=======================eeeeeER .   vaddps  %ymm3, %ymm0, %ymm4
+# CHECK-NEXT: [0,31]    .    .    .    .D========================eeeeeER.   vaddps  %ymm3, %ymm0, %ymm5
+# CHECK-NEXT: [0,32]    .    .    .    . D========================eeeeeER   vaddps  %ymm3, %ymm0, %ymm6
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/BdVer2/scheduler-queue-usage.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -scheduler-stats < %s | FileCheck %s
 
 vmulps (%rsi), %xmm0, %xmm0
 add  %rsi, %rsi
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      13
+# CHECK-NEXT: Total Cycles:      14
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.15
-# CHECK-NEXT: IPC:               0.15
+# CHECK-NEXT: uOps Per Cycle:    0.14
+# CHECK-NEXT: IPC:               0.14
 # CHECK-NEXT: Block RThroughput: 1.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      10    1.50    *                   vmulps  (%rsi), %xmm0, %xmm0
 # CHECK-NEXT:  1      1     1.00                        addq  %rsi, %rsi
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          12  (92.3%)
-# CHECK-NEXT:  2,          1  (7.7%)
+# CHECK-NEXT:  0,          13  (92.9%)
+# CHECK-NEXT:  2,          1  (7.1%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

llvm/test/tools/llvm-mca/X86/BdVer2/simple-test.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=100 < %s | FileCheck %s
 
 add %edi, %eax
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      100
-# CHECK-NEXT: Total Cycles:      103
+# CHECK-NEXT: Total Cycles:      104
 # CHECK-NEXT: Total uOps:        100
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.97
-# CHECK-NEXT: IPC:               0.97
+# CHECK-NEXT: uOps Per Cycle:    0.96
+# CHECK-NEXT: IPC:               0.96
 # CHECK-NEXT: Block RThroughput: 1.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

llvm/test/tools/llvm-mca/X86/BdVer2/store-throughput.s

 vmovaps %ymm2, (%rdx)
 vmovaps %ymm3, (%rbx)
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      403
+# CHECK-NEXT: Total Cycles:      404
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.99
 # CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      1     1.00           *            movb  %sil, (%rdx)
 # CHECK-NEXT:  1      1     1.00           *            movb  %dil, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          371  (92.1%)
+# CHECK-NEXT: SQ      - Store queue full:                          371  (91.8%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              24  (6.0%)
-# CHECK-NEXT:  1,              372  (92.3%)
+# CHECK-NEXT:  0,              25  (6.2%)
+# CHECK-NEXT:  1,              372  (92.1%)
 # CHECK-NEXT:  4,              7  (1.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          3  (0.7%)
-# CHECK-NEXT:  1,          400  (99.3%)
+# CHECK-NEXT:  0,          4  (1.0%)
+# CHECK-NEXT:  1,          400  (99.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movb %spl, (%rax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movb %bpl, (%rcx)
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movb %sil, (%rdx)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movb %dil, (%rbx)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     0123456
+# CHECK-NEXT: Index     01234567
 
-# CHECK:      [0,0]     DeER ..   movb  %spl, (%rax)
-# CHECK-NEXT: [0,1]     D=eER..   movb  %bpl, (%rcx)
-# CHECK-NEXT: [0,2]     D==eER.   movb  %sil, (%rdx)
-# CHECK-NEXT: [0,3]     D===eER   movb  %dil, (%rbx)
+# CHECK:      [0,0]     .DeER. .   movb %spl, (%rax)
+# CHECK-NEXT: [0,1]     .D=eER .   movb %bpl, (%rcx)
+# CHECK-NEXT: [0,2]     .D==eER.   movb %sil, (%rdx)
+# CHECK-NEXT: [0,3]     .D===eER   movb %dil, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movb %spl, (%rax)
 # CHECK-NEXT: 1.     1     2.0    0.0    0.0       movb %bpl, (%rcx)
 # CHECK-NEXT: 2.     1     3.0    0.0    0.0       movb %sil, (%rdx)
 # CHECK-NEXT: 3.     1     4.0    0.0    0.0       movb %dil, (%rbx)
 # CHECK-NEXT:        1     2.5    0.3    0.0       <total>
 
 # CHECK:      [1] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      403
+# CHECK-NEXT: Total Cycles:      404
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.99
 # CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      1     1.00           *            movw  %si, (%rdx)
 # CHECK-NEXT:  1      1     1.00           *            movw  %di, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          371  (92.1%)
+# CHECK-NEXT: SQ      - Store queue full:                          371  (91.8%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              24  (6.0%)
-# CHECK-NEXT:  1,              372  (92.3%)
+# CHECK-NEXT:  0,              25  (6.2%)
+# CHECK-NEXT:  1,              372  (92.1%)
 # CHECK-NEXT:  4,              7  (1.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          3  (0.7%)
-# CHECK-NEXT:  1,          400  (99.3%)
+# CHECK-NEXT:  0,          4  (1.0%)
+# CHECK-NEXT:  1,          400  (99.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movw %sp, (%rax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movw %bp, (%rcx)
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movw %si, (%rdx)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movw %di, (%rbx)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     0123456
+# CHECK-NEXT: Index     01234567
 
-# CHECK:      [0,0]     DeER ..   movw  %sp, (%rax)
-# CHECK-NEXT: [0,1]     D=eER..   movw  %bp, (%rcx)
-# CHECK-NEXT: [0,2]     D==eER.   movw  %si, (%rdx)
-# CHECK-NEXT: [0,3]     D===eER   movw  %di, (%rbx)
+# CHECK:      [0,0]     .DeER. .   movw %sp, (%rax)
+# CHECK-NEXT: [0,1]     .D=eER .   movw %bp, (%rcx)
+# CHECK-NEXT: [0,2]     .D==eER.   movw %si, (%rdx)
+# CHECK-NEXT: [0,3]     .D===eER   movw %di, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movw %sp, (%rax)
 # CHECK-NEXT: 1.     1     2.0    0.0    0.0       movw %bp, (%rcx)
 # CHECK-NEXT: 2.     1     3.0    0.0    0.0       movw %si, (%rdx)
 # CHECK-NEXT: 3.     1     4.0    0.0    0.0       movw %di, (%rbx)
 # CHECK-NEXT:        1     2.5    0.3    0.0       <total>
 
 # CHECK:      [2] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      403
+# CHECK-NEXT: Total Cycles:      404
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.99
 # CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      1     1.00           *            movl  %esi, (%rdx)
 # CHECK-NEXT:  1      1     1.00           *            movl  %edi, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          371  (92.1%)
+# CHECK-NEXT: SQ      - Store queue full:                          371  (91.8%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              24  (6.0%)
-# CHECK-NEXT:  1,              372  (92.3%)
+# CHECK-NEXT:  0,              25  (6.2%)
+# CHECK-NEXT:  1,              372  (92.1%)
 # CHECK-NEXT:  4,              7  (1.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          3  (0.7%)
-# CHECK-NEXT:  1,          400  (99.3%)
+# CHECK-NEXT:  0,          4  (1.0%)
+# CHECK-NEXT:  1,          400  (99.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movl %esp, (%rax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movl %ebp, (%rcx)
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movl %esi, (%rdx)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movl %edi, (%rbx)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     0123456
+# CHECK-NEXT: Index     01234567
 
-# CHECK:      [0,0]     DeER ..   movl  %esp, (%rax)
-# CHECK-NEXT: [0,1]     D=eER..   movl  %ebp, (%rcx)
-# CHECK-NEXT: [0,2]     D==eER.   movl  %esi, (%rdx)
-# CHECK-NEXT: [0,3]     D===eER   movl  %edi, (%rbx)
+# CHECK:      [0,0]     .DeER. .   movl %esp, (%rax)
+# CHECK-NEXT: [0,1]     .D=eER .   movl %ebp, (%rcx)
+# CHECK-NEXT: [0,2]     .D==eER.   movl %esi, (%rdx)
+# CHECK-NEXT: [0,3]     .D===eER   movl %edi, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movl %esp, (%rax)
 # CHECK-NEXT: 1.     1     2.0    0.0    0.0       movl %ebp, (%rcx)
 # CHECK-NEXT: 2.     1     3.0    0.0    0.0       movl %esi, (%rdx)
 # CHECK-NEXT: 3.     1     4.0    0.0    0.0       movl %edi, (%rbx)
 # CHECK-NEXT:        1     2.5    0.3    0.0       <total>
 
 # CHECK:      [3] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      403
+# CHECK-NEXT: Total Cycles:      404
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.99
 # CHECK-NEXT: IPC:               0.99
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      1     1.00           *            movq  %rsi, (%rdx)
 # CHECK-NEXT:  1      1     1.00           *            movq  %rdi, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          371  (92.1%)
+# CHECK-NEXT: SQ      - Store queue full:                          371  (91.8%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              24  (6.0%)
-# CHECK-NEXT:  1,              372  (92.3%)
+# CHECK-NEXT:  0,              25  (6.2%)
+# CHECK-NEXT:  1,              372  (92.1%)
 # CHECK-NEXT:  4,              7  (1.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          3  (0.7%)
-# CHECK-NEXT:  1,          400  (99.3%)
+# CHECK-NEXT:  0,          4  (1.0%)
+# CHECK-NEXT:  1,          400  (99.0%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movq %rsp, (%rax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movq %rbp, (%rcx)
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movq %rsi, (%rdx)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     1.00   movq %rdi, (%rbx)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     0123456
+# CHECK-NEXT: Index     01234567
 
-# CHECK:      [0,0]     DeER ..   movq  %rsp, (%rax)
-# CHECK-NEXT: [0,1]     D=eER..   movq  %rbp, (%rcx)
-# CHECK-NEXT: [0,2]     D==eER.   movq  %rsi, (%rdx)
-# CHECK-NEXT: [0,3]     D===eER   movq  %rdi, (%rbx)
+# CHECK:      [0,0]     .DeER. .   movq %rsp, (%rax)
+# CHECK-NEXT: [0,1]     .D=eER .   movq %rbp, (%rcx)
+# CHECK-NEXT: [0,2]     .D==eER.   movq %rsi, (%rdx)
+# CHECK-NEXT: [0,3]     .D===eER   movq %rdi, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movq %rsp, (%rax)
 # CHECK-NEXT: 1.     1     2.0    0.0    0.0       movq %rbp, (%rcx)
 # CHECK-NEXT: 2.     1     3.0    0.0    0.0       movq %rsi, (%rdx)
 # CHECK-NEXT: 3.     1     4.0    0.0    0.0       movq %rdi, (%rbx)
 # CHECK-NEXT:        1     2.5    0.3    0.0       <total>
 
 # CHECK:      [4] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      803
+# CHECK-NEXT: Total Cycles:      804
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.50
 # CHECK-NEXT: IPC:               0.50
 # CHECK-NEXT: Block RThroughput: 6.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      2     1.50           *      U     movd  %mm2, (%rdx)
 # CHECK-NEXT:  1      2     1.50           *      U     movd  %mm3, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          748  (93.2%)
+# CHECK-NEXT: SQ      - Store queue full:                          748  (93.0%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              422  (52.6%)
-# CHECK-NEXT:  1,              374  (46.6%)
+# CHECK-NEXT:  0,              423  (52.6%)
+# CHECK-NEXT:  1,              374  (46.5%)
 # CHECK-NEXT:  2,              1  (0.1%)
 # CHECK-NEXT:  4,              6  (0.7%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          403  (50.2%)
+# CHECK-NEXT:  0,          404  (50.2%)
 # CHECK-NEXT:  1,          400  (49.8%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   movd %mm0, (%rax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   movd %mm1, (%rcx)
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   movd %mm2, (%rdx)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   movd %mm3, (%rbx)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0
+# CHECK-NEXT:                     01
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.    .   movd  %mm0, (%rax)
-# CHECK-NEXT: [0,1]     D==eeER   .   movd  %mm1, (%rcx)
-# CHECK-NEXT: [0,2]     D====eeER .   movd  %mm2, (%rdx)
-# CHECK-NEXT: [0,3]     D======eeER   movd  %mm3, (%rbx)
+# CHECK:      [0,0]     .DeeER    ..   movd %mm0, (%rax)
+# CHECK-NEXT: [0,1]     .D==eeER  ..   movd %mm1, (%rcx)
+# CHECK-NEXT: [0,2]     .D====eeER..   movd %mm2, (%rdx)
+# CHECK-NEXT: [0,3]     .D======eeER   movd %mm3, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movd %mm0, (%rax)
 # CHECK-NEXT: 1.     1     3.0    0.0    0.0       movd %mm1, (%rcx)
 # CHECK-NEXT: 2.     1     5.0    0.0    0.0       movd %mm2, (%rdx)
 # CHECK-NEXT: 3.     1     7.0    0.0    0.0       movd %mm3, (%rbx)
 # CHECK-NEXT:        1     4.0    0.3    0.0       <total>
 
 # CHECK:      [5] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      602
+# CHECK-NEXT: Total Cycles:      603
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.66
 # CHECK-NEXT: IPC:               0.66
 # CHECK-NEXT: Block RThroughput: 6.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  1      1     1.50           *            movaps  %xmm2, (%rdx)
 # CHECK-NEXT:  1      1     1.50           *            movaps  %xmm3, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          559  (92.9%)
+# CHECK-NEXT: SQ      - Store queue full:                          559  (92.7%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              222  (36.9%)
-# CHECK-NEXT:  1,              373  (62.0%)
+# CHECK-NEXT:  0,              223  (37.0%)
+# CHECK-NEXT:  1,              373  (61.9%)
 # CHECK-NEXT:  3,              1  (0.2%)
 # CHECK-NEXT:  4,              6  (1.0%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          202  (33.6%)
-# CHECK-NEXT:  1,          400  (66.4%)
+# CHECK-NEXT:  0,          203  (33.7%)
+# CHECK-NEXT:  1,          400  (66.3%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 
 # CHECK:       [1]            [2]        [3]        [4]

 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   movaps %xmm0, (%rax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   movaps %xmm1, (%rcx)
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     1.00    -      -      -     3.00    -      -      -      -     1.00   movaps %xmm2, (%rdx)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     1.00    -      -     3.00    -      -      -      -      -     1.00   movaps %xmm3, (%rbx)
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     01234567
+# CHECK-NEXT: Index     012345678
 
-# CHECK:      [0,0]     DeER . .   movaps %xmm0, (%rax)
-# CHECK-NEXT: [0,1]     D=eER. .   movaps %xmm1, (%rcx)
-# CHECK-NEXT: [0,2]     D===eER.   movaps %xmm2, (%rdx)
-# CHECK-NEXT: [0,3]     D====eER   movaps %xmm3, (%rbx)
+# CHECK:      [0,0]     .DeER.  .   movaps  %xmm0, (%rax)
+# CHECK-NEXT: [0,1]     .D=eER  .   movaps  %xmm1, (%rcx)
+# CHECK-NEXT: [0,2]     .D===eER.   movaps  %xmm2, (%rdx)
+# CHECK-NEXT: [0,3]     .D====eER   movaps  %xmm3, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       movaps %xmm0, (%rax)
 # CHECK-NEXT: 1.     1     2.0    0.0    0.0       movaps %xmm1, (%rcx)
 # CHECK-NEXT: 2.     1     4.0    1.0    0.0       movaps %xmm2, (%rdx)
 # CHECK-NEXT: 3.     1     5.0    0.0    0.0       movaps %xmm3, (%rbx)
 # CHECK-NEXT:        1     3.0    0.5    0.0       <total>
 
 # CHECK:      [6] Code Region
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      400
-# CHECK-NEXT: Total Cycles:      7170
+# CHECK-NEXT: Total Cycles:      7172
 # CHECK-NEXT: Total uOps:        1600
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    0.22
 # CHECK-NEXT: IPC:               0.06
 # CHECK-NEXT: Block RThroughput: 72.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  4      1     18.00          *            vmovaps %ymm0, (%rax)
 # CHECK-NEXT:  4      1     18.00          *            vmovaps %ymm1, (%rcx)
 # CHECK-NEXT:  4      1     18.00          *            vmovaps %ymm2, (%rdx)
 # CHECK-NEXT:  4      1     18.00          *            vmovaps %ymm3, (%rbx)
 
 # CHECK:      Dynamic Dispatch Stall Cycles:
 # CHECK-NEXT: RAT     - Register unavailable:                      0
 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
-# CHECK-NEXT: SCHEDQ  - Scheduler full:                            5777  (80.6%)
+# CHECK-NEXT: SCHEDQ  - Scheduler full:                            5568  (77.6%)
 # CHECK-NEXT: LQ      - Load queue full:                           0
-# CHECK-NEXT: SQ      - Store queue full:                          561  (7.8%)
+# CHECK-NEXT: SQ      - Store queue full:                          372  (5.2%)
 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
 
 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
 # CHECK-NEXT: [# dispatched], [# cycles]
-# CHECK-NEXT:  0,              6770  (94.4%)
+# CHECK-NEXT:  0,              6772  (94.4%)
 # CHECK-NEXT:  4,              400  (5.6%)
 
 # CHECK:      Schedulers - number of cycles where we saw N micro opcodes issued:
 # CHECK-NEXT: [# issued], [# cycles]
-# CHECK-NEXT:  0,          6770  (94.4%)
+# CHECK-NEXT:  0,          6772  (94.4%)
 # CHECK-NEXT:  4,          400  (5.6%)
 
 # CHECK:      Scheduler's queue usage:
 # CHECK-NEXT: [1] Resource name.
 # CHECK-NEXT: [2] Average number of used buffer entries.
 # CHECK-NEXT: [3] Maximum number of used buffer entries.
 # CHECK-NEXT: [4] Total number of buffer entries.
 

 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     36.00   -      -      -      -     1.00   vmovaps  %ymm0, (%rax)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     36.00   -      -      -      -      -     1.00   vmovaps  %ymm1, (%rcx)
 # CHECK-NEXT:  -     1.00    -      -      -      -      -      -      -      -      -      -      -     2.00    -      -      -     36.00   -      -      -      -     1.00   vmovaps  %ymm2, (%rdx)
 # CHECK-NEXT: 1.00    -      -      -      -      -      -      -      -      -      -      -      -     2.00    -      -     36.00   -      -      -      -      -     1.00   vmovaps  %ymm3, (%rbx)
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789
-# CHECK-NEXT: Index     0123456789          0123456789          01
+# CHECK-NEXT: Index     0123456789          0123456789          0123
 
-# CHECK:      [0,0]     DeER .    .    .    .    .    .    .    ..   vmovaps  %ymm0, (%rax)
-# CHECK-NEXT: [0,1]     .D=eER    .    .    .    .    .    .    ..   vmovaps  %ymm1, (%rcx)
-# CHECK-NEXT: [0,2]     . D==================================eER..   vmovaps  %ymm2, (%rdx)
-# CHECK-NEXT: [0,3]     .  D===================================eER   vmovaps  %ymm3, (%rbx)
+# CHECK:      [0,0]     . DeER    .    .    .    .    .    .    .  .   vmovaps  %ymm0, (%rax)
+# CHECK-NEXT: [0,1]     .   DeER  .    .    .    .    .    .    .  .   vmovaps  %ymm1, (%rcx)
+# CHECK-NEXT: [0,2]     .    .D================================eER .   vmovaps  %ymm2, (%rdx)
+# CHECK-NEXT: [0,3]     .    .  D================================eER   vmovaps  %ymm3, (%rbx)
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vmovaps  %ymm0, (%rax)
-# CHECK-NEXT: 1.     1     2.0    1.0    0.0       vmovaps  %ymm1, (%rcx)
-# CHECK-NEXT: 2.     1     35.0   33.0   0.0       vmovaps  %ymm2, (%rdx)
-# CHECK-NEXT: 3.     1     36.0   1.0    0.0       vmovaps  %ymm3, (%rbx)
-# CHECK-NEXT:        1     18.5   9.0    0.0       <total>
+# CHECK-NEXT: 1.     1     1.0    1.0    0.0       vmovaps  %ymm1, (%rcx)
+# CHECK-NEXT: 2.     1     33.0   33.0   0.0       vmovaps  %ymm2, (%rdx)
+# CHECK-NEXT: 3.     1     33.0   1.0    0.0       vmovaps  %ymm3, (%rbx)
+# CHECK-NEXT:        1     17.0   9.0    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/vbroadcast-operand-latency.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=3 < %s | FileCheck %s
 
 leaq 8(%rsp, %rdi, 2), %rax
 vbroadcastss (%rax), %ymm0
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      200
-# CHECK-NEXT: Total Cycles:      206
+# CHECK-NEXT: Total Cycles:      207
 # CHECK-NEXT: Total uOps:        300
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.46
+# CHECK-NEXT: uOps Per Cycle:    1.45
 # CHECK-NEXT: IPC:               0.97
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad

 # CHECK-NEXT: 0.50   0.50    -      -      -     1.00   1.00    -     2.00   2.00    -      -      -      -     1.00   1.00    -      -      -     0.50   0.50    -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -     1.00   1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     leaq 8(%rsp,%rdi,2), %rax
 # CHECK-NEXT: 0.50   0.50    -      -      -      -      -      -     2.00   2.00    -      -      -      -     1.00   1.00    -      -      -     0.50   0.50    -      -     vbroadcastss (%rax), %ymm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     012
+# CHECK-NEXT:                     0123
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeER.    . .   leaq  8(%rsp,%rdi,2), %rax
-# CHECK-NEXT: [0,1]     DeeeeeeER . .   vbroadcastss  (%rax), %ymm0
-# CHECK-NEXT: [1,0]     DeeE----R . .   leaq  8(%rsp,%rdi,2), %rax
-# CHECK-NEXT: [1,1]     .DeeeeeeER. .   vbroadcastss  (%rax), %ymm0
-# CHECK-NEXT: [2,0]     .D=eeE---R. .   leaq  8(%rsp,%rdi,2), %rax
-# CHECK-NEXT: [2,1]     . D==eeeeeeER   vbroadcastss  (%rax), %ymm0
+# CHECK:      [0,0]     .DeeER    .  .   leaq 8(%rsp,%rdi,2), %rax
+# CHECK-NEXT: [0,1]     .DeeeeeeER.  .   vbroadcastss (%rax), %ymm0
+# CHECK-NEXT: [1,0]     .DeeE----R.  .   leaq 8(%rsp,%rdi,2), %rax
+# CHECK-NEXT: [1,1]     . DeeeeeeER  .   vbroadcastss (%rax), %ymm0
+# CHECK-NEXT: [2,0]     . D=eeE---R  .   leaq 8(%rsp,%rdi,2), %rax
+# CHECK-NEXT: [2,1]     .  D==eeeeeeER   vbroadcastss (%rax), %ymm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     1.3    1.3    2.3       leaq 8(%rsp,%rdi,2), %rax
 # CHECK-NEXT: 1.     3     1.7    1.0    0.0       vbroadcastss (%rax), %ymm0
 # CHECK-NEXT:        3     1.5    1.2    1.2       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s
 
 vaddps %xmm0, %xmm0, %xmm1
 vandps (%rdi), %xmm1, %xmm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      10
+# CHECK-NEXT: Total Cycles:      11
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.20
-# CHECK-NEXT: IPC:               0.20
+# CHECK-NEXT: uOps Per Cycle:    0.18
+# CHECK-NEXT: IPC:               0.18
 # CHECK-NEXT: Block RThroughput: 1.5
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      5     1.00                        vaddps  %xmm0, %xmm0, %xmm1
 # CHECK-NEXT:  1      7     1.50    *                   vandps  (%rdi), %xmm1, %xmm2
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER .   vaddps %xmm0, %xmm0, %xmm1
-# CHECK-NEXT: [0,1]     DeeeeeeeER   vandps (%rdi), %xmm1, %xmm2
+# CHECK:      [0,0]     .DeeeeeER .   vaddps  %xmm0, %xmm0, %xmm1
+# CHECK-NEXT: [0,1]     .DeeeeeeeER   vandps  (%rdi), %xmm1, %xmm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vaddps %xmm0, %xmm0, %xmm1
 # CHECK-NEXT: 1.     1     1.0    0.0    0.0       vandps (%rdi), %xmm1, %xmm2
 # CHECK-NEXT:        1     1.0    0.5    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/vec-logic-read-after-ld-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s
 
 vaddps %ymm0, %ymm0, %ymm1
 vandps (%rdi), %ymm1, %ymm2
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      10
+# CHECK-NEXT: Total Cycles:      11
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    0.40
-# CHECK-NEXT: IPC:               0.20
+# CHECK-NEXT: uOps Per Cycle:    0.36
+# CHECK-NEXT: IPC:               0.18
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  2      5     1.00                        vaddps  %ymm0, %ymm0, %ymm1
 # CHECK-NEXT:  2      7     1.50    *                   vandps  (%rdi), %ymm1, %ymm2
 
 # CHECK:      Timeline view:
+# CHECK-NEXT:                     0
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER .   vaddps %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [0,1]     DeeeeeeeER   vandps (%rdi), %ymm1, %ymm2
+# CHECK:      [0,0]     .DeeeeeER .   vaddps  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [0,1]     .DeeeeeeeER   vandps  (%rdi), %ymm1, %ymm2
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     1.0    1.0    0.0       vaddps %ymm0, %ymm0, %ymm1
 # CHECK-NEXT: 1.     1     1.0    0.0    0.0       vandps (%rdi), %ymm1, %ymm2
 # CHECK-NEXT:        1     1.0    0.5    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-1.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=2 < %s | FileCheck %s
 
   vmulps  %ymm0, %ymm1, %ymm2
   vfrczpd %xmm1, %xmm2
   vmulps  %ymm2, %ymm3, %ymm4
   vaddps  %ymm4, %ymm5, %ymm6
   vmulps  %ymm6, %ymm3, %ymm4
   vaddps  %ymm4, %ymm5, %ymm0
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      600
-# CHECK-NEXT: Total Cycles:      550
+# CHECK-NEXT: Total Cycles:      551
 # CHECK-NEXT: Total uOps:        1200
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    2.18
 # CHECK-NEXT: IPC:               1.09
 # CHECK-NEXT: Block RThroughput: 5.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -     1.00    -     2.00    -      -      -      -      -      -      -     vfrczpd  %xmm1, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.98   1.02    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps %ymm2, %ymm3, %ymm4
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.02   0.98    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm4, %ymm5, %ymm6
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.02   0.98    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps %ymm6, %ymm3, %ymm4
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   1.00    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm4, %ymm5, %ymm0
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789          0123456789
-# CHECK-NEXT: Index     0123456789          0123456789
+# CHECK-NEXT: Index     0123456789          0123456789          0
 
-# CHECK:      [0,0]     DeeeeeER  .    .    .    .    .    .   .   vmulps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [0,1]     D=eeeeeeeeeeER .    .    .    .    .   .   vfrczpd  %xmm1, %xmm2
-# CHECK-NEXT: [0,2]     .D==========eeeeeER .    .    .    .   .   vmulps %ymm2, %ymm3, %ymm4
-# CHECK-NEXT: [0,3]     .D===============eeeeeER .    .    .   .   vaddps %ymm4, %ymm5, %ymm6
-# CHECK-NEXT: [0,4]     . D===================eeeeeER .    .   .   vmulps %ymm6, %ymm3, %ymm4
-# CHECK-NEXT: [0,5]     . D========================eeeeeER .   .   vaddps %ymm4, %ymm5, %ymm0
-# CHECK-NEXT: [1,0]     .  D============================eeeeeER.   vmulps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [1,1]     .  DeeeeeeeeeeE-----------------------R.   vfrczpd  %xmm1, %xmm2
-# CHECK-NEXT: [1,2]     .   D==========eeeeeE-----------------R.   vmulps %ymm2, %ymm3, %ymm4
-# CHECK-NEXT: [1,3]     .   D===============eeeeeE------------R.   vaddps %ymm4, %ymm5, %ymm6
-# CHECK-NEXT: [1,4]     .    D===================eeeeeE--------R   vmulps %ymm6, %ymm3, %ymm4
-# CHECK-NEXT: [1,5]     .    D========================eeeeeE---R   vaddps %ymm4, %ymm5, %ymm0
+# CHECK:      [0,0]     .DeeeeeER .    .    .    .    .    .    .   vmulps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [0,1]     .D=eeeeeeeeeeER.    .    .    .    .    .   vfrczpd %xmm1, %xmm2
+# CHECK-NEXT: [0,2]     . D==========eeeeeER.    .    .    .    .   vmulps  %ymm2, %ymm3, %ymm4
+# CHECK-NEXT: [0,3]     . D===============eeeeeER.    .    .    .   vaddps  %ymm4, %ymm5, %ymm6
+# CHECK-NEXT: [0,4]     .  D===================eeeeeER.    .    .   vmulps  %ymm6, %ymm3, %ymm4
+# CHECK-NEXT: [0,5]     .  D========================eeeeeER.    .   vaddps  %ymm4, %ymm5, %ymm0
+# CHECK-NEXT: [1,0]     .   D============================eeeeeER.   vmulps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [1,1]     .   DeeeeeeeeeeE-----------------------R.   vfrczpd %xmm1, %xmm2
+# CHECK-NEXT: [1,2]     .    D==========eeeeeE-----------------R.   vmulps  %ymm2, %ymm3, %ymm4
+# CHECK-NEXT: [1,3]     .    D===============eeeeeE------------R.   vaddps  %ymm4, %ymm5, %ymm6
+# CHECK-NEXT: [1,4]     .    .D===================eeeeeE--------R   vmulps  %ymm6, %ymm3, %ymm4
+# CHECK-NEXT: [1,5]     .    .D========================eeeeeE---R   vaddps  %ymm4, %ymm5, %ymm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     15.0   0.5    0.0       vmulps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT: 1.     2     1.5    1.5    11.5      vfrczpd  %xmm1, %xmm2
 # CHECK-NEXT: 2.     2     11.0   0.5    8.5       vmulps %ymm2, %ymm3, %ymm4
 # CHECK-NEXT: 3.     2     16.0   0.0    6.0       vaddps %ymm4, %ymm5, %ymm6
 # CHECK-NEXT: 4.     2     20.0   0.0    4.0       vmulps %ymm6, %ymm3, %ymm4
 # CHECK-NEXT: 5.     2     25.0   0.0    1.5       vaddps %ymm4, %ymm5, %ymm0
 # CHECK-NEXT:        2     14.8   0.4    5.3       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/xop-super-registers-2.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -timeline -timeline-max-iterations=2 < %s | FileCheck %s
 
   vmulps     %ymm0, %ymm1, %ymm2
   vpermil2pd $15, %xmm3, %xmm5, %xmm1, %xmm2
   vmulps     %ymm2, %ymm3, %ymm4
   vaddps     %ymm4, %ymm5, %ymm6
   vmulps     %ymm6, %ymm3, %ymm4
   vaddps     %ymm4, %ymm5, %ymm0
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      600
-# CHECK-NEXT: Total Cycles:      614
+# CHECK-NEXT: Total Cycles:      615
 # CHECK-NEXT: Total uOps:        1100
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.79
 # CHECK-NEXT: IPC:               0.98
 # CHECK-NEXT: Block RThroughput: 6.0
 
 # CHECK:      Instruction Info:

 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.58   0.42    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.44   1.56    -      -      -      -     0.61   0.39    -      -      -      -      -      -      -     vpermil2pd $15, %xmm3, %xmm5, %xmm1, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.58   0.42    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps %ymm2, %ymm3, %ymm4
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.40   1.60    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm4, %ymm5, %ymm6
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.58   0.42    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vmulps %ymm6, %ymm3, %ymm4
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.42   1.58    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm4, %ymm5, %ymm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          01
+# CHECK-NEXT:                     0123456789          012
 # CHECK-NEXT: Index     0123456789          0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .    .    .    .    ..   vmulps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [0,1]     DeeeE--R  .    .    .    .    ..   vpermil2pd $15, %xmm3, %xmm5, %xmm1, %xmm2
-# CHECK-NEXT: [0,2]     .D==eeeeeER    .    .    .    ..   vmulps %ymm2, %ymm3, %ymm4
-# CHECK-NEXT: [0,3]     .D=======eeeeeER    .    .    ..   vaddps %ymm4, %ymm5, %ymm6
-# CHECK-NEXT: [0,4]     . D===========eeeeeER    .    ..   vmulps %ymm6, %ymm3, %ymm4
-# CHECK-NEXT: [0,5]     . D================eeeeeER    ..   vaddps %ymm4, %ymm5, %ymm0
-# CHECK-NEXT: [1,0]     .  D====================eeeeeER.   vmulps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [1,1]     .  DeeeE----------------------R.   vpermil2pd $15, %xmm3, %xmm5, %xmm1, %xmm2
-# CHECK-NEXT: [1,2]     .   D==eeeeeE-----------------R.   vmulps %ymm2, %ymm3, %ymm4
-# CHECK-NEXT: [1,3]     .   D=======eeeeeE------------R.   vaddps %ymm4, %ymm5, %ymm6
-# CHECK-NEXT: [1,4]     .    D===========eeeeeE--------R   vmulps %ymm6, %ymm3, %ymm4
-# CHECK-NEXT: [1,5]     .    D================eeeeeE---R   vaddps %ymm4, %ymm5, %ymm0
+# CHECK:      [0,0]     .DeeeeeER .    .    .    .    . .   vmulps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [0,1]     .DeeeE--R .    .    .    .    . .   vpermil2pd  $15, %xmm3, %xmm5, %xmm1, %xmm2
+# CHECK-NEXT: [0,2]     . D==eeeeeER   .    .    .    . .   vmulps  %ymm2, %ymm3, %ymm4
+# CHECK-NEXT: [0,3]     . D=======eeeeeER   .    .    . .   vaddps  %ymm4, %ymm5, %ymm6
+# CHECK-NEXT: [0,4]     .  D===========eeeeeER   .    . .   vmulps  %ymm6, %ymm3, %ymm4
+# CHECK-NEXT: [0,5]     .  D================eeeeeER   . .   vaddps  %ymm4, %ymm5, %ymm0
+# CHECK-NEXT: [1,0]     .   D====================eeeeeER.   vmulps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [1,1]     .   DeeeE----------------------R.   vpermil2pd  $15, %xmm3, %xmm5, %xmm1, %xmm2
+# CHECK-NEXT: [1,2]     .    D==eeeeeE-----------------R.   vmulps  %ymm2, %ymm3, %ymm4
+# CHECK-NEXT: [1,3]     .    D=======eeeeeE------------R.   vaddps  %ymm4, %ymm5, %ymm6
+# CHECK-NEXT: [1,4]     .    .D===========eeeeeE--------R   vmulps  %ymm6, %ymm3, %ymm4
+# CHECK-NEXT: [1,5]     .    .D================eeeeeE---R   vaddps  %ymm4, %ymm5, %ymm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     2     11.0   0.5    0.0       vmulps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT: 1.     2     1.0    1.0    12.0      vpermil2pd $15, %xmm3, %xmm5, %xmm1, %xmm2
 # CHECK-NEXT: 2.     2     3.0    0.0    8.5       vmulps %ymm2, %ymm3, %ymm4
 # CHECK-NEXT: 3.     2     8.0    0.0    6.0       vaddps %ymm4, %ymm5, %ymm6
 # CHECK-NEXT: 4.     2     12.0   0.0    4.0       vmulps %ymm6, %ymm3, %ymm4
 # CHECK-NEXT: 5.     2     17.0   0.0    1.5       vaddps %ymm4, %ymm5, %ymm0
 # CHECK-NEXT:        2     8.7    0.3    5.3       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms-avx-256.s

 vperm2f128 $136, %ymm0, %ymm0, %ymm1
 vaddps  %ymm1, %ymm1, %ymm0
 # LLVM-MCA-END
 
 # CHECK:      [0] Code Region - ZERO-IDIOM-1
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      300
-# CHECK-NEXT: Total Cycles:      354
+# CHECK-NEXT: Total Cycles:      355
 # CHECK-NEXT: Total uOps:        600
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.69
 # CHECK-NEXT: IPC:               0.85
 # CHECK-NEXT: Block RThroughput: 3.5
 
 # CHECK:      Instruction Info:

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.98   1.02    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm0, %ymm0, %ymm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   1.00    -      -      -      -     0.98   1.02    -      -      -      -      -      -      -     vxorps %ymm1, %ymm1, %ymm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.53   1.47    -      -      -      -     0.02   1.98    -      -      -      -      -      -      -     vblendps $2, %ymm1, %ymm2, %ymm3
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123
+# CHECK-NEXT:                     01234
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .  .   vaddps %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [0,1]     DeeE---R  .  .   vxorps %ymm1, %ymm1, %ymm1
-# CHECK-NEXT: [0,2]     .D=eeE-R  .  .   vblendps $2, %ymm1, %ymm2, %ymm3
-# CHECK-NEXT: [1,0]     .D=eeeeeER.  .   vaddps %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [1,1]     . D==eeE-R.  .   vxorps %ymm1, %ymm1, %ymm1
-# CHECK-NEXT: [1,2]     . D====eeER  .   vblendps $2, %ymm1, %ymm2, %ymm3
-# CHECK-NEXT: [2,0]     .  D==eeeeeER.   vaddps %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [2,1]     .  D====eeE-R.   vxorps %ymm1, %ymm1, %ymm1
-# CHECK-NEXT: [2,2]     .   D=====eeER   vblendps $2, %ymm1, %ymm2, %ymm3
+# CHECK:      [0,0]     .DeeeeeER .   .   vaddps  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [0,1]     .DeeE---R .   .   vxorps  %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,2]     . D=eeE-R .   .   vblendps  $2, %ymm1, %ymm2, %ymm3
+# CHECK-NEXT: [1,0]     . D=eeeeeER   .   vaddps  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [1,1]     .  D==eeE-R   .   vxorps  %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [1,2]     .  D====eeER  .   vblendps  $2, %ymm1, %ymm2, %ymm3
+# CHECK-NEXT: [2,0]     .   D==eeeeeER.   vaddps  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [2,1]     .   D====eeE-R.   vxorps  %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [2,2]     .    D=====eeER   vblendps  $2, %ymm1, %ymm2, %ymm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     2.0    2.0    0.0       vaddps %ymm0, %ymm0, %ymm1
 # CHECK-NEXT: 1.     3     3.0    3.0    1.7       vxorps %ymm1, %ymm1, %ymm1
 # CHECK-NEXT: 2.     3     4.3    0.0    0.3       vblendps $2, %ymm1, %ymm2, %ymm3
 # CHECK-NEXT:        3     3.1    1.7    0.7       <total>
 
 # CHECK:      [1] Code Region - ZERO-IDIOM-2
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      300
-# CHECK-NEXT: Total Cycles:      354
+# CHECK-NEXT: Total Cycles:      355
 # CHECK-NEXT: Total uOps:        600
 
 # CHECK:      Dispatch Width:    4
 # CHECK-NEXT: uOps Per Cycle:    1.69
 # CHECK-NEXT: IPC:               0.85
 # CHECK-NEXT: Block RThroughput: 3.5
 
 # CHECK:      Instruction Info:

 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     0.98   1.02    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddpd %ymm0, %ymm0, %ymm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   1.00    -      -      -      -     0.98   1.02    -      -      -      -      -      -      -     vxorpd %ymm1, %ymm1, %ymm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     1.53   1.47    -      -      -      -     0.02   1.98    -      -      -      -      -      -      -     vblendpd $2, %ymm1, %ymm2, %ymm3
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123
+# CHECK-NEXT:                     01234
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  .  .   vaddpd %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [0,1]     DeeE---R  .  .   vxorpd %ymm1, %ymm1, %ymm1
-# CHECK-NEXT: [0,2]     .D=eeE-R  .  .   vblendpd $2, %ymm1, %ymm2, %ymm3
-# CHECK-NEXT: [1,0]     .D=eeeeeER.  .   vaddpd %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [1,1]     . D==eeE-R.  .   vxorpd %ymm1, %ymm1, %ymm1
-# CHECK-NEXT: [1,2]     . D====eeER  .   vblendpd $2, %ymm1, %ymm2, %ymm3
-# CHECK-NEXT: [2,0]     .  D==eeeeeER.   vaddpd %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [2,1]     .  D====eeE-R.   vxorpd %ymm1, %ymm1, %ymm1
-# CHECK-NEXT: [2,2]     .   D=====eeER   vblendpd $2, %ymm1, %ymm2, %ymm3
+# CHECK:      [0,0]     .DeeeeeER .   .   vaddpd  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [0,1]     .DeeE---R .   .   vxorpd  %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [0,2]     . D=eeE-R .   .   vblendpd  $2, %ymm1, %ymm2, %ymm3
+# CHECK-NEXT: [1,0]     . D=eeeeeER   .   vaddpd  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [1,1]     .  D==eeE-R   .   vxorpd  %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [1,2]     .  D====eeER  .   vblendpd  $2, %ymm1, %ymm2, %ymm3
+# CHECK-NEXT: [2,0]     .   D==eeeeeER.   vaddpd  %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [2,1]     .   D====eeE-R.   vxorpd  %ymm1, %ymm1, %ymm1
+# CHECK-NEXT: [2,2]     .    D=====eeER   vblendpd  $2, %ymm1, %ymm2, %ymm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     2.0    2.0    0.0       vaddpd %ymm0, %ymm0, %ymm1
 # CHECK-NEXT: 1.     3     3.0    3.0    1.7       vxorpd %ymm1, %ymm1, %ymm1
 # CHECK-NEXT: 2.     3     4.3    0.0    0.3       vblendpd $2, %ymm1, %ymm2, %ymm3
 # CHECK-NEXT:        3     3.1    1.7    0.7       <total>
 
 # CHECK:      [2] Code Region - ZERO-IDIOM-3
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      200
-# CHECK-NEXT: Total Cycles:      206
+# CHECK-NEXT: Total Cycles:      207
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.94
+# CHECK-NEXT: uOps Per Cycle:    1.93
 # CHECK-NEXT: IPC:               0.97
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad

 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00   2.00    -      -      -      -     1.00   2.00    -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00    -      -      -      -      -      -     2.00    -      -      -      -      -      -      -     vandnps  %ymm2, %ymm2, %ymm3
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
+# CHECK-NEXT:                     012
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  ..   vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [0,1]     DeeE---R  ..   vandnps  %ymm2, %ymm2, %ymm3
-# CHECK-NEXT: [1,0]     .D=eeeeeER..   vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [1,1]     .D=eeE---R..   vandnps  %ymm2, %ymm2, %ymm3
-# CHECK-NEXT: [2,0]     . D==eeeeeER   vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [2,1]     . D==eeE---R   vandnps  %ymm2, %ymm2, %ymm3
+# CHECK:      [0,0]     .DeeeeeER . .   vaddps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [0,1]     .DeeE---R . .   vandnps %ymm2, %ymm2, %ymm3
+# CHECK-NEXT: [1,0]     . D=eeeeeER .   vaddps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [1,1]     . D=eeE---R .   vandnps %ymm2, %ymm2, %ymm3
+# CHECK-NEXT: [2,0]     .  D==eeeeeER   vaddps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [2,1]     .  D==eeE---R   vandnps %ymm2, %ymm2, %ymm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     2.0    2.0    0.0       vaddps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT: 1.     3     2.0    2.0    3.0       vandnps  %ymm2, %ymm2, %ymm3
 # CHECK-NEXT:        3     2.0    2.0    1.5       <total>
 
 # CHECK:      [3] Code Region - ZERO-IDIOM-4
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      200
-# CHECK-NEXT: Total Cycles:      206
+# CHECK-NEXT: Total Cycles:      207
 # CHECK-NEXT: Total uOps:        400
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.94
+# CHECK-NEXT: uOps Per Cycle:    1.93
 # CHECK-NEXT: IPC:               0.97
 # CHECK-NEXT: Block RThroughput: 2.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad

 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00   2.00    -      -      -      -     1.00   2.00    -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     2.00    -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00    -      -      -      -      -      -     2.00    -      -      -      -      -      -      -     vandnps  %ymm2, %ymm2, %ymm3
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
+# CHECK-NEXT:                     012
 # CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeeeeER  ..   vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [0,1]     DeeE---R  ..   vandnps  %ymm2, %ymm2, %ymm3
-# CHECK-NEXT: [1,0]     .D=eeeeeER..   vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [1,1]     .D=eeE---R..   vandnps  %ymm2, %ymm2, %ymm3
-# CHECK-NEXT: [2,0]     . D==eeeeeER   vaddps %ymm0, %ymm1, %ymm2
-# CHECK-NEXT: [2,1]     . D==eeE---R   vandnps  %ymm2, %ymm2, %ymm3
+# CHECK:      [0,0]     .DeeeeeER . .   vaddps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [0,1]     .DeeE---R . .   vandnps %ymm2, %ymm2, %ymm3
+# CHECK-NEXT: [1,0]     . D=eeeeeER .   vaddps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [1,1]     . D=eeE---R .   vandnps %ymm2, %ymm2, %ymm3
+# CHECK-NEXT: [2,0]     .  D==eeeeeER   vaddps  %ymm0, %ymm1, %ymm2
+# CHECK-NEXT: [2,1]     .  D==eeE---R   vandnps %ymm2, %ymm2, %ymm3
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     3     2.0    2.0    0.0       vaddps %ymm0, %ymm1, %ymm2
 # CHECK-NEXT: 1.     3     2.0    2.0    3.0       vandnps  %ymm2, %ymm2, %ymm3
 # CHECK-NEXT:        3     2.0    2.0    1.5       <total>
 
 # CHECK:      [4] Code Region - ZERO-IDIOM-5
 
 # CHECK:      Iterations:        100
 # CHECK-NEXT: Instructions:      200
-# CHECK-NEXT: Total Cycles:      903
+# CHECK-NEXT: Total Cycles:      907
 # CHECK-NEXT: Total uOps:        1000
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    1.11
+# CHECK-NEXT: uOps Per Cycle:    1.10
 # CHECK-NEXT: IPC:               0.22
 # CHECK-NEXT: Block RThroughput: 4.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad

 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00   6.00    -      -      -      -     1.00   1.00    -      -      -      -      -      -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -     6.00    -      -      -      -      -     1.00    -      -      -      -      -      -      -     vperm2f128 $136, %ymm0, %ymm0, %ymm1
 # CHECK-NEXT:  -      -      -      -      -      -      -      -     2.00    -      -      -      -      -     1.00    -      -      -      -      -      -      -      -     vaddps %ymm1, %ymm1, %ymm0
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789
+# CHECK-NEXT:                     0123456789          0123
 # CHECK-NEXT: Index     0123456789          0123456789
 
-# CHECK:      [0,0]     DeeeeER   .    .    .    .   .   vperm2f128 $136, %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [0,1]     . D==eeeeeER   .    .    .   .   vaddps %ymm1, %ymm1, %ymm0
-# CHECK-NEXT: [1,0]     .  D======eeeeER    .    .   .   vperm2f128 $136, %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [1,1]     .    D========eeeeeER    .   .   vaddps %ymm1, %ymm1, %ymm0
-# CHECK-NEXT: [2,0]     .    .D============eeeeER.   .   vperm2f128 $136, %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: [2,1]     .    .  D==============eeeeeER   vaddps %ymm1, %ymm1, %ymm0
+# CHECK:      [0,0]     .   DeeeeER    .    .    .    .  .   vperm2f128 $136, %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [0,1]     .    .D==eeeeeER    .    .    .  .   vaddps %ymm1, %ymm1, %ymm0
+# CHECK-NEXT: [1,0]     .    .    D===eeeeER.    .    .  .   vperm2f128 $136, %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [1,1]     .    .    . D=====eeeeeER.    .  .   vaddps %ymm1, %ymm1, %ymm0
+# CHECK-NEXT: [2,0]     .    .    .    .D======eeeeER .  .   vperm2f128 $136, %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: [2,1]     .    .    .    .  D========eeeeeER   vaddps %ymm1, %ymm1, %ymm0
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     3     7.0    0.3    0.0       vperm2f128 $136, %ymm0, %ymm0, %ymm1
-# CHECK-NEXT: 1.     3     9.0    0.0    0.0       vaddps %ymm1, %ymm1, %ymm0
-# CHECK-NEXT:        3     8.0    0.2    0.0       <total>
+# CHECK-NEXT: 0.     3     4.0    0.3    0.0       vperm2f128 $136, %ymm0, %ymm0, %ymm1
+# CHECK-NEXT: 1.     3     6.0    0.0    0.0       vaddps %ymm1, %ymm1, %ymm0
+# CHECK-NEXT:        3     5.0    0.2    0.0       <total>

llvm/test/tools/llvm-mca/X86/BdVer2/zero-idioms.s

 vpxor  %xmm3, %xmm3, %xmm3
 
 vxorps %xmm4, %xmm4, %xmm5
 vxorpd %xmm1, %xmm1, %xmm3
 vpxor  %xmm3, %xmm3, %xmm5
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      71
-# CHECK-NEXT: Total Cycles:      31
+# CHECK-NEXT: Total Cycles:      32
 # CHECK-NEXT: Total uOps:        71
 
 # CHECK:      Dispatch Width:    4
-# CHECK-NEXT: uOps Per Cycle:    2.29
-# CHECK-NEXT: IPC:               2.29
+# CHECK-NEXT: uOps Per Cycle:    2.22
+# CHECK-NEXT: IPC:               2.22
 # CHECK-NEXT: Block RThroughput: 17.8
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     pxor %mm2, %mm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     pxor %xmm2, %xmm2
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vpxor  %xmm3, %xmm3, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vxorps %xmm4, %xmm4, %xmm5
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vxorpd %xmm1, %xmm1, %xmm3
 # CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     vpxor  %xmm3, %xmm3, %xmm5
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789          0
+# CHECK-NEXT:                     0123456789          01
 # CHECK-NEXT: Index     0123456789          0123456789
 
-# CHECK:      [0,0]     DR   .    .    .    .    .    .   subl  %eax, %eax
-# CHECK-NEXT: [0,1]     DR   .    .    .    .    .    .   subq  %rax, %rax
-# CHECK-NEXT: [0,2]     DR   .    .    .    .    .    .   xorl  %eax, %eax
-# CHECK-NEXT: [0,3]     DR   .    .    .    .    .    .   xorq  %rax, %rax
-# CHECK-NEXT: [0,4]     .DR  .    .    .    .    .    .   pcmpgtb %mm2, %mm2
-# CHECK-NEXT: [0,5]     .DR  .    .    .    .    .    .   pcmpgtd %mm2, %mm2
-# CHECK-NEXT: [0,6]     .DR  .    .    .    .    .    .   pcmpgtw %mm2, %mm2
-# CHECK-NEXT: [0,7]     .DR  .    .    .    .    .    .   pcmpgtb %xmm2, %xmm2
-# CHECK-NEXT: [0,8]     . DR .    .    .    .    .    .   pcmpgtd %xmm2, %xmm2
-# CHECK-NEXT: [0,9]     . DeeER   .    .    .    .    .   pcmpgtq %xmm2, %xmm2
-# CHECK-NEXT: [0,10]    . D---R   .    .    .    .    .   pcmpgtw %xmm2, %xmm2
-# CHECK-NEXT: [0,11]    . D---R   .    .    .    .    .   vpcmpgtb  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,12]    .  D--R   .    .    .    .    .   vpcmpgtd  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,13]    .  DeeER  .    .    .    .    .   vpcmpgtq  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,14]    .  D---R  .    .    .    .    .   vpcmpgtw  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,15]    .  D---R  .    .    .    .    .   vpcmpgtb  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,16]    .   D--R  .    .    .    .    .   vpcmpgtd  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,17]    .   DeeER .    .    .    .    .   vpcmpgtq  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,18]    .   D---R .    .    .    .    .   vpcmpgtw  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,19]    .   D---R .    .    .    .    .   psubb %mm2, %mm2
-# CHECK-NEXT: [0,20]    .    D--R .    .    .    .    .   psubd %mm2, %mm2
-# CHECK-NEXT: [0,21]    .    D---R.    .    .    .    .   psubq %mm2, %mm2
-# CHECK-NEXT: [0,22]    .    D---R.    .    .    .    .   psubw %mm2, %mm2
-# CHECK-NEXT: [0,23]    .    D---R.    .    .    .    .   psubb %xmm2, %xmm2
-# CHECK-NEXT: [0,24]    .    .D--R.    .    .    .    .   psubd %xmm2, %xmm2
-# CHECK-NEXT: [0,25]    .    .D---R    .    .    .    .   psubq %xmm2, %xmm2
-# CHECK-NEXT: [0,26]    .    .D---R    .    .    .    .   psubw %xmm2, %xmm2
-# CHECK-NEXT: [0,27]    .    .D---R    .    .    .    .   vpsubb  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,28]    .    . D--R    .    .    .    .   vpsubd  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,29]    .    . D---R   .    .    .    .   vpsubq  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,30]    .    . D---R   .    .    .    .   vpsubw  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,31]    .    . D---R   .    .    .    .   vpsubb  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,32]    .    .  D--R   .    .    .    .   vpsubd  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,33]    .    .  D---R  .    .    .    .   vpsubq  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,34]    .    .  D---R  .    .    .    .   vpsubw  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,35]    .    .  DeeER  .    .    .    .   psubsb  %mm2, %mm2
-# CHECK-NEXT: [0,36]    .    .   DeeER .    .    .    .   psubsw  %mm2, %mm2
-# CHECK-NEXT: [0,37]    .    .   DeeER .    .    .    .   psubsb  %xmm2, %xmm2
-# CHECK-NEXT: [0,38]    .    .   D=eeER.    .    .    .   psubsw  %xmm2, %xmm2
-# CHECK-NEXT: [0,39]    .    .   D==eeER    .    .    .   vpsubsb %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,40]    .    .    D==eeER   .    .    .   vpsubsw %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,41]    .    .    D===eeER  .    .    .   vpsubsb %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,42]    .    .    D====eeER .    .    .   vpsubsw %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,43]    .    .    D=====eeER.    .    .   psubusb %mm2, %mm2
-# CHECK-NEXT: [0,44]    .    .    .D=====eeER    .    .   psubusw %mm2, %mm2
-# CHECK-NEXT: [0,45]    .    .    .D=====eeER    .    .   psubusb %xmm2, %xmm2
-# CHECK-NEXT: [0,46]    .    .    .D======eeER   .    .   psubusw %xmm2, %xmm2
-# CHECK-NEXT: [0,47]    .    .    .D=======eeER  .    .   vpsubusb  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,48]    .    .    . D=======eeER .    .   vpsubusw  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,49]    .    .    . D========eeER.    .   vpsubsb %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,50]    .    .    . D=========eeER    .   vpsubsw %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,51]    .    .    . D------------R    .   andnps  %xmm0, %xmm0
-# CHECK-NEXT: [0,52]    .    .    .  D-----------R    .   andnpd  %xmm1, %xmm1
-# CHECK-NEXT: [0,53]    .    .    .  D-----------R    .   vandnps %xmm2, %xmm2, %xmm2
-# CHECK-NEXT: [0,54]    .    .    .  D------------R   .   vandnpd %xmm1, %xmm1, %xmm1
-# CHECK-NEXT: [0,55]    .    .    .  D------------R   .   pandn %mm2, %mm2
-# CHECK-NEXT: [0,56]    .    .    .   D-----------R   .   pandn %xmm2, %xmm2
-# CHECK-NEXT: [0,57]    .    .    .   D-----------R   .   vpandn  %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,58]    .    .    .   D------------R  .   vandnps %xmm2, %xmm2, %xmm5
-# CHECK-NEXT: [0,59]    .    .    .   D------------R  .   vandnpd %xmm1, %xmm1, %xmm5
-# CHECK-NEXT: [0,60]    .    .    .    D-----------R  .   vpandn  %xmm3, %xmm3, %xmm5
-# CHECK-NEXT: [0,61]    .    .    .    D-----------R  .   xorps %xmm0, %xmm0
-# CHECK-NEXT: [0,62]    .    .    .    D------------R .   xorpd %xmm1, %xmm1
-# CHECK-NEXT: [0,63]    .    .    .    D------------R .   vxorps  %xmm2, %xmm2, %xmm2
-# CHECK-NEXT: [0,64]    .    .    .    .D-----------R .   vxorpd  %xmm1, %xmm1, %xmm1
-# CHECK-NEXT: [0,65]    .    .    .    .D-----------R .   pxor  %mm2, %mm2
-# CHECK-NEXT: [0,66]    .    .    .    .D------------R.   pxor  %xmm2, %xmm2
-# CHECK-NEXT: [0,67]    .    .    .    .D------------R.   vpxor %xmm3, %xmm3, %xmm3
-# CHECK-NEXT: [0,68]    .    .    .    . D-----------R.   vxorps  %xmm4, %xmm4, %xmm5
-# CHECK-NEXT: [0,69]    .    .    .    . D-----------R.   vxorpd  %xmm1, %xmm1, %xmm3
-# CHECK-NEXT: [0,70]    .    .    .    . D------------R   vpxor %xmm3, %xmm3, %xmm5
+# CHECK:      [0,0]     .DR  .    .    .    .    .    ..   subl %eax, %eax
+# CHECK-NEXT: [0,1]     .DR  .    .    .    .    .    ..   subq %rax, %rax
+# CHECK-NEXT: [0,2]     .DR  .    .    .    .    .    ..   xorl %eax, %eax
+# CHECK-NEXT: [0,3]     .DR  .    .    .    .    .    ..   xorq %rax, %rax
+# CHECK-NEXT: [0,4]     . DR .    .    .    .    .    ..   pcmpgtb  %mm2, %mm2
+# CHECK-NEXT: [0,5]     . DR .    .    .    .    .    ..   pcmpgtd  %mm2, %mm2
+# CHECK-NEXT: [0,6]     . DR .    .    .    .    .    ..   pcmpgtw  %mm2, %mm2
+# CHECK-NEXT: [0,7]     . DR .    .    .    .    .    ..   pcmpgtb  %xmm2, %xmm2
+# CHECK-NEXT: [0,8]     .  DR.    .    .    .    .    ..   pcmpgtd  %xmm2, %xmm2
+# CHECK-NEXT: [0,9]     .  DeeER  .    .    .    .    ..   pcmpgtq  %xmm2, %xmm2
+# CHECK-NEXT: [0,10]    .  D---R  .    .    .    .    ..   pcmpgtw  %xmm2, %xmm2
+# CHECK-NEXT: [0,11]    .  D---R  .    .    .    .    ..   vpcmpgtb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,12]    .   D--R  .    .    .    .    ..   vpcmpgtd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,13]    .   DeeER .    .    .    .    ..   vpcmpgtq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,14]    .   D---R .    .    .    .    ..   vpcmpgtw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,15]    .   D---R .    .    .    .    ..   vpcmpgtb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,16]    .    D--R .    .    .    .    ..   vpcmpgtd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,17]    .    DeeER.    .    .    .    ..   vpcmpgtq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,18]    .    D---R.    .    .    .    ..   vpcmpgtw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,19]    .    D---R.    .    .    .    ..   psubb  %mm2, %mm2
+# CHECK-NEXT: [0,20]    .    .D--R.    .    .    .    ..   psubd  %mm2, %mm2
+# CHECK-NEXT: [0,21]    .    .D---R    .    .    .    ..   psubq  %mm2, %mm2
+# CHECK-NEXT: [0,22]    .    .D---R    .    .    .    ..   psubw  %mm2, %mm2
+# CHECK-NEXT: [0,23]    .    .D---R    .    .    .    ..   psubb  %xmm2, %xmm2
+# CHECK-NEXT: [0,24]    .    . D--R    .    .    .    ..   psubd  %xmm2, %xmm2
+# CHECK-NEXT: [0,25]    .    . D---R   .    .    .    ..   psubq  %xmm2, %xmm2
+# CHECK-NEXT: [0,26]    .    . D---R   .    .    .    ..   psubw  %xmm2, %xmm2
+# CHECK-NEXT: [0,27]    .    . D---R   .    .    .    ..   vpsubb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,28]    .    .  D--R   .    .    .    ..   vpsubd %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,29]    .    .  D---R  .    .    .    ..   vpsubq %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,30]    .    .  D---R  .    .    .    ..   vpsubw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,31]    .    .  D---R  .    .    .    ..   vpsubb %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,32]    .    .   D--R  .    .    .    ..   vpsubd %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,33]    .    .   D---R .    .    .    ..   vpsubq %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,34]    .    .   D---R .    .    .    ..   vpsubw %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,35]    .    .   DeeER .    .    .    ..   psubsb %mm2, %mm2
+# CHECK-NEXT: [0,36]    .    .    DeeER.    .    .    ..   psubsw %mm2, %mm2
+# CHECK-NEXT: [0,37]    .    .    DeeER.    .    .    ..   psubsb %xmm2, %xmm2
+# CHECK-NEXT: [0,38]    .    .    D=eeER    .    .    ..   psubsw %xmm2, %xmm2
+# CHECK-NEXT: [0,39]    .    .    D==eeER   .    .    ..   vpsubsb  %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,40]    .    .    .D==eeER  .    .    ..   vpsubsw  %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,41]    .    .    .D===eeER .    .    ..   vpsubsb  %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,42]    .    .    .D====eeER.    .    ..   vpsubsw  %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,43]    .    .    .D=====eeER    .    ..   psubusb  %mm2, %mm2
+# CHECK-NEXT: [0,44]    .    .    . D=====eeER   .    ..   psubusw  %mm2, %mm2
+# CHECK-NEXT: [0,45]    .    .    . D=====eeER   .    ..   psubusb  %xmm2, %xmm2
+# CHECK-NEXT: [0,46]    .    .    . D======eeER  .    ..   psubusw  %xmm2, %xmm2
+# CHECK-NEXT: [0,47]    .    .    . D=======eeER .    ..   vpsubusb %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,48]    .    .    .  D=======eeER.    ..   vpsubusw %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,49]    .    .    .  D========eeER    ..   vpsubsb  %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,50]    .    .    .  D=========eeER   ..   vpsubsw  %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,51]    .    .    .  D------------R   ..   andnps %xmm0, %xmm0
+# CHECK-NEXT: [0,52]    .    .    .   D-----------R   ..   andnpd %xmm1, %xmm1
+# CHECK-NEXT: [0,53]    .    .    .   D-----------R   ..   vandnps  %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,54]    .    .    .   D------------R  ..   vandnpd  %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,55]    .    .    .   D------------R  ..   pandn  %mm2, %mm2
+# CHECK-NEXT: [0,56]    .    .    .    D-----------R  ..   pandn  %xmm2, %xmm2
+# CHECK-NEXT: [0,57]    .    .    .    D-----------R  ..   vpandn %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,58]    .    .    .    D------------R ..   vandnps  %xmm2, %xmm2, %xmm5
+# CHECK-NEXT: [0,59]    .    .    .    D------------R ..   vandnpd  %xmm1, %xmm1, %xmm5
+# CHECK-NEXT: [0,60]    .    .    .    .D-----------R ..   vpandn %xmm3, %xmm3, %xmm5
+# CHECK-NEXT: [0,61]    .    .    .    .D-----------R ..   xorps  %xmm0, %xmm0
+# CHECK-NEXT: [0,62]    .    .    .    .D------------R..   xorpd  %xmm1, %xmm1
+# CHECK-NEXT: [0,63]    .    .    .    .D------------R..   vxorps %xmm2, %xmm2, %xmm2
+# CHECK-NEXT: [0,64]    .    .    .    . D-----------R..   vxorpd %xmm1, %xmm1, %xmm1
+# CHECK-NEXT: [0,65]    .    .    .    . D-----------R..   pxor %mm2, %mm2
+# CHECK-NEXT: [0,66]    .    .    .    . D------------R.   pxor %xmm2, %xmm2
+# CHECK-NEXT: [0,67]    .    .    .    . D------------R.   vpxor  %xmm3, %xmm3, %xmm3
+# CHECK-NEXT: [0,68]    .    .    .    .  D-----------R.   vxorps %xmm4, %xmm4, %xmm5
+# CHECK-NEXT: [0,69]    .    .    .    .  D-----------R.   vxorpd %xmm1, %xmm1, %xmm3
+# CHECK-NEXT: [0,70]    .    .    .    .  D------------R   vpxor  %xmm3, %xmm3, %xmm5
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]

llvm/test/tools/llvm-mca/X86/bextr-read-after-ld.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=HASWELL
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=broadwell -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDWELL
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=SKYLAKE
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BDVER2
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=BTVER2
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER1
 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -timeline -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER2
 
 add     %edi, %esi
 bextrl  %esi, (%rdi), %eax
 
 # ALL:          Iterations:        1
 # ALL-NEXT:     Instructions:      2
 
-# BDVER2-NEXT:  Total Cycles:      9
+# BDVER2-NEXT:  Total Cycles:      10
 # BDVER2-NEXT:  Total uOps:        3
 
 # BDWELL-NEXT:  Total Cycles:      10
 # BDWELL-NEXT:  Total uOps:        4
 
 # BTVER2-NEXT:  Total Cycles:      7
 # BTVER2-NEXT:  Total uOps:        2
 
 # HASWELL-NEXT: Total Cycles:      10
 # HASWELL-NEXT: Total uOps:        4
 
 # SKYLAKE-NEXT: Total Cycles:      10
 # SKYLAKE-NEXT: Total uOps:        4
 
 # ZNVER1-NEXT:  Total Cycles:      8
 # ZNVER1-NEXT:  Total uOps:        3
 
 # ZNVER2-NEXT:  Total Cycles:      8
 # ZNVER2-NEXT:  Total uOps:        3
 
 # BDVER2:       Dispatch Width:    4
-# BDVER2-NEXT:  uOps Per Cycle:    0.33
-# BDVER2-NEXT:  IPC:               0.22
+# BDVER2-NEXT:  uOps Per Cycle:    0.30
+# BDVER2-NEXT:  IPC:               0.20
 # BDVER2-NEXT:  Block RThroughput: 2.0
 
 # BDWELL:       Dispatch Width:    4
 # BDWELL-NEXT:  uOps Per Cycle:    0.40
 # BDWELL-NEXT:  IPC:               0.20
 # BDWELL-NEXT:  Block RThroughput: 1.0
 
 # BTVER2:       Dispatch Width:    2

 # ZNVER1-NEXT:   1      1     0.25                        addl  %edi, %esi
 # ZNVER1-NEXT:   2      5     0.50    *                   bextrl  %esi, (%rdi), %eax
 
 # ZNVER2-NEXT:   1      1     0.25                        addl  %edi, %esi
 # ZNVER2-NEXT:   2      5     0.33    *                   bextrl  %esi, (%rdi), %eax
 
 # ALL:          Timeline view:
 
-# BDVER2-NEXT:  Index     012345678
+# BDVER2-NEXT:  Index     0123456789
 # BDWELL-NEXT:  Index     0123456789
 # BTVER2-NEXT:  Index     0123456
 # HASWELL-NEXT: Index     0123456789
 # SKYLAKE-NEXT: Index     0123456789
 # ZNVER1-NEXT:  Index     01234567
 # ZNVER2-NEXT:  Index     01234567
 
-# BDVER2:       [0,0]     DeER .  .   addl  %edi, %esi
-# BDVER2-NEXT:  [0,1]     DeeeeeeER   bextrl  %esi, (%rdi), %eax
+# BDVER2:       [0,0]     .DeER.   .   addl %edi, %esi
+# BDVER2-NEXT:  [0,1]     .DeeeeeeER   bextrl %esi, (%rdi), %eax
 
 # BDWELL:       [0,0]     DeER .   .   addl %edi, %esi
 # BDWELL-NEXT:  [0,1]     DeeeeeeeER   bextrl %esi, (%rdi), %eax
 
 # BTVER2:       [0,0]     DeER ..   addl  %edi, %esi
 # BTVER2-NEXT:  [0,1]     DeeeeER   bextrl  %esi, (%rdi), %eax
 
 # HASWELL:      [0,0]     DeER .   .   addl %edi, %esi

llvm/test/tools/llvm-mca/X86/cpus.s

 # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=SKX %s
 # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=SKX-AVX512 %s
 # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=slm -resource-pressure=false -instruction-info=false < %s | FileCheck --check-prefix=ALL --check-prefix=SLM %s
 
 add %edi, %eax
 
 # ALL:              Iterations:        100
 # ALL-NEXT:         Instructions:      100
-# ALL-NEXT:         Total Cycles:      103
+
+# BARCELONA-NEXT:   Total Cycles:      103
+# BDVER2-NEXT:      Total Cycles:      104
+# BROADWELL-NEXT:   Total Cycles:      103
+# BTVER2-NEXT:      Total Cycles:      103
+# HASWELL-NEXT:     Total Cycles:      103
+# IVYBRIDGE-NEXT:   Total Cycles:      103
+# KNL-NEXT:         Total Cycles:      103
+# SANDYBRIDGE-NEXT: Total Cycles:      103
+# SKX-NEXT:         Total Cycles:      103
+# SKX-AVX512-NEXT:  Total Cycles:      103
+# SLM-NEXT:         Total Cycles:      103
+# ZNVER1-NEXT:      Total Cycles:      103
+# ZNVER2-NEXT:      Total Cycles:      103
+
 # ALL-NEXT:         Total uOps:        100
 
 # BARCELONA:        Dispatch Width:    4
 # BARCELONA-NEXT:   uOps Per Cycle:    0.97
 # BARCELONA-NEXT:   IPC:               0.97
 # BARCELONA-NEXT:   Block RThroughput: 0.3
 
 # BDVER2:           Dispatch Width:    4
-# BDVER2-NEXT:      uOps Per Cycle:    0.97
-# BDVER2-NEXT:      IPC:               0.97
+# BDVER2-NEXT:      uOps Per Cycle:    0.96
+# BDVER2-NEXT:      IPC:               0.96
 # BDVER2-NEXT:      Block RThroughput: 1.0
 
 # BROADWELL:        Dispatch Width:    4
 # BROADWELL-NEXT:   uOps Per Cycle:    0.97
 # BROADWELL-NEXT:   IPC:               0.97
 # BROADWELL-NEXT:   Block RThroughput: 0.3
 
 # BTVER2:           Dispatch Width:    2

llvm/test/tools/llvm-mca/X86/read-after-ld-1.s

 vaddps  (%rax), %xmm1, %xmm1
 
 # ALL:            Iterations:        1
 # ALL-NEXT:       Instructions:      2
 
 # BARCELONA-NEXT: Total Cycles:      20
 # BARCELONA-NEXT: Total uOps:        3
 
-# BDVER2-NEXT:    Total Cycles:      17
+# BDVER2-NEXT:    Total Cycles:      18
 # BDVER2-NEXT:    Total uOps:        2
 
 # BDWELL-NEXT:    Total Cycles:      17
 # BDWELL-NEXT:    Total uOps:        3
 
 # BTVER2-NEXT:    Total Cycles:      25
 # BTVER2-NEXT:    Total uOps:        2
 

 # ZNVER2-NEXT:    Total uOps:        2
 
 # BARCELONA:      Dispatch Width:    4
 # BARCELONA-NEXT: uOps Per Cycle:    0.15
 # BARCELONA-NEXT: IPC:               0.10
 # BARCELONA-NEXT: Block RThroughput: 14.0
 
 # BDVER2:         Dispatch Width:    4
-# BDVER2-NEXT:    uOps Per Cycle:    0.12
-# BDVER2-NEXT:    IPC:               0.12
+# BDVER2-NEXT:    uOps Per Cycle:    0.11
+# BDVER2-NEXT:    IPC:               0.11
 # BDVER2-NEXT:    Block RThroughput: 5.0
 
 # BDWELL:         Dispatch Width:    4
 # BDWELL-NEXT:    uOps Per Cycle:    0.18
 # BDWELL-NEXT:    IPC:               0.12
 # BDWELL-NEXT:    Block RThroughput: 5.0
 
 # BTVER2:         Dispatch Width:    2

 # ZNVER2-NEXT:    IPC:               0.10
 # ZNVER2-NEXT:    Block RThroughput: 1.0
 
 # ALL:            Timeline view:
 
 # BARCELONA-NEXT:                     0123456789
 # BARCELONA-NEXT: Index     0123456789
 
-# BDVER2-NEXT:                        0123456
+# BDVER2-NEXT:                        01234567
 # BDVER2-NEXT:    Index     0123456789
 
 # BDWELL-NEXT:                        0123456
 # BDWELL-NEXT:    Index     0123456789
 
 # BTVER2-NEXT:                        0123456789
 # BTVER2-NEXT:    Index     0123456789          01234
 

 # ZNVER1-NEXT:    Index     0123456789
 
 # ZNVER2-NEXT:                        0123456789
 # ZNVER2-NEXT:    Index     0123456789          0
 
 # BARCELONA:      [0,0]     DeeeeeeeeeeeeeeER  .   vdivps %xmm0, %xmm1, %xmm1
 # BARCELONA-NEXT: [0,1]     D========eeeeeeeeeER   vaddps (%rax), %xmm1, %xmm1
 
-# BDVER2:         [0,0]     DeeeeeeeeeER   ..   vdivps  %xmm0, %xmm1, %xmm1
-# BDVER2-NEXT:    [0,1]     D====eeeeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1
+# BDVER2:         [0,0]     .DeeeeeeeeeER  . .   vdivps %xmm0, %xmm1, %xmm1
+# BDVER2-NEXT:    [0,1]     .D====eeeeeeeeeeER   vaddps (%rax), %xmm1, %xmm1
 
 # BDWELL:         [0,0]     DeeeeeeeeeeeER ..   vdivps  %xmm0, %xmm1, %xmm1
 # BDWELL-NEXT:    [0,1]     D======eeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1
 
 # BTVER2:         [0,0]     DeeeeeeeeeeeeeeeeeeeER  .   vdivps  %xmm0, %xmm1, %xmm1
 # BTVER2-NEXT:    [0,1]     D==============eeeeeeeeER   vaddps  (%rax), %xmm1, %xmm1
 
 # HASWELL:        [0,0]     DeeeeeeeeeeeeeER  .   vdivps  %xmm0, %xmm1, %xmm1

llvm/test/tools/llvm-mca/X86/scheduler-queue-usage.s

 # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SKX %s
 # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SKX-AVX512 %s
 # RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=slm -iterations=1 -all-stats=false -all-views=false -scheduler-stats < %s | FileCheck --check-prefixes=ALL,SLM %s
 
 xor %eax, %ebx
 
 # ALL:             Schedulers - number of cycles where we saw N micro opcodes issued:
 # ALL-NEXT:        [# issued], [# cycles]
-# ALL-NEXT:         0,          3  (75.0%)
-# ALL-NEXT:         1,          1  (25.0%)
+
+# BARCELONA-NEXT:   0,          3  (75.0%)
+# BARCELONA-NEXT:   1,          1  (25.0%)
+
+# BDVER2-NEXT:      0,          4  (80.0%)
+# BDVER2-NEXT:      1,          1  (20.0%)
+
+# BDW-NEXT:         0,          3  (75.0%)
+# BDW-NEXT:         1,          1  (25.0%)
+
+# BTVER2-NEXT:      0,          3  (75.0%)
+# BTVER2-NEXT:      1,          1  (25.0%)
+
+# HSW-NEXT:         0,          3  (75.0%)
+# HSW-NEXT:         1,          1  (25.0%)
+
+# IVB-NEXT:         0,          3  (75.0%)
+# IVB-NEXT:         1,          1  (25.0%)
+
+# KNL-NEXT:         0,          3  (75.0%)
+# KNL-NEXT:         1,          1  (25.0%)
+
+# SKX-NEXT:         0,          3  (75.0%)
+# SKX-NEXT:         1,          1  (25.0%)
+
+# SKX-AVX512-NEXT:  0,          3  (75.0%)
+# SKX-AVX512-NEXT:  1,          1  (25.0%)
+
+# SLM-NEXT:         0,          3  (75.0%)
+# SLM-NEXT:         1,          1  (25.0%)
+
+# SNB-NEXT:         0,          3  (75.0%)
+# SNB-NEXT:         1,          1  (25.0%)
+
+# ZNVER1-NEXT:      0,          3  (75.0%)
+# ZNVER1-NEXT:      1,          1  (25.0%)
+
+# ZNVER2-NEXT:      0,          3  (75.0%)
+# ZNVER2-NEXT:      1,          1  (25.0%)
 
 # BARCELONA:       Scheduler's queue usage:
 # BARCELONA-NEXT:  [1] Resource name.
 # BARCELONA-NEXT:  [2] Average number of used buffer entries.
 # BARCELONA-NEXT:  [3] Maximum number of used buffer entries.
 # BARCELONA-NEXT:  [4] Total number of buffer entries.
 
 # BDVER2:          Scheduler's queue usage:

llvm/test/tools/llvm-mca/X86/sqrt-rsqrt-rcp-memop.s

 
 # ALL:            [0] Code Region - test_sqrtss
 
 # ALL:            Timeline view:
 
 # BARCELONA-NEXT:                     0123456789
 # BARCELONA-NEXT: Index     0123456789          0123
 
-# BDVER2-NEXT:                        012345678
+# BDVER2-NEXT:                        0123456789
 # BDVER2-NEXT:    Index     0123456789
 
 # BROADWELL-NEXT:                     0123456789
 # BROADWELL-NEXT: Index     0123456789
 
 # BTVER2-NEXT:                        0123456789          0
 # BTVER2-NEXT:    Index     0123456789          0123456789
 
 # HASWELL-NEXT:                       0123456789
 # HASWELL-NEXT:   Index     0123456789
 
 # SKYLAKE-NEXT:                       0123456789
 # SKYLAKE-NEXT:   Index     0123456789          0
 
 # ZNVER1-NEXT:                        0123456789          0
 # ZNVER1-NEXT:    Index     0123456789          0123456789
 
 # ZNVER2-NEXT:                        0123456789          0
 # ZNVER2-NEXT:    Index     0123456789          0123456789
 
 # BARCELONA:      [0,0]     DeER .    .    .    .  .   leaq 8(%rsp,%rdi,2), %rax
 # BARCELONA-NEXT: [0,1]     D=eeeeeeeeeeeeeeeeeeeeER   sqrtss (%rax), %xmm1
 
-# BDVER2:         [0,0]     DeeER.    .    .  .   leaq  8(%rsp,%rdi,2), %rax
-# BDVER2-NEXT:    [0,1]     D==eeeeeeeeeeeeeeER   sqrtss  (%rax), %xmm1
+# BDVER2:         [0,0]     .DeeER    .    .   .   leaq 8(%rsp,%rdi,2), %rax
+# BDVER2-NEXT:    [0,1]     .D==eeeeeeeeeeeeeeER   sqrtss (%rax), %xmm1
 
 # BROADWELL:      [0,0]     DeER .    .    .   .   leaq 8(%rsp,%rdi,2), %rax
 # BROADWELL-NEXT: [0,1]     D=eeeeeeeeeeeeeeeeER   sqrtss (%rax), %xmm1
 
 # BTVER2:         [0,0]     DeeER.    .    .    .    .    .   leaq  8(%rsp,%rdi,2), %rax
 # BTVER2-NEXT:    [0,1]     D==eeeeeeeeeeeeeeeeeeeeeeeeeeER   sqrtss  (%rax), %xmm1
 
 # HASWELL:        [0,0]     DeER .    .    .   .   leaq 8(%rsp,%rdi,2), %rax

 
 # ALL:            [1] Code Region - test_sqrtsd
 
 # ALL:            Timeline view:
 
 # BARCELONA-NEXT:                     0123456789          0
 # BARCELONA-NEXT: Index     0123456789          0123456789
 
-# BDVER2-NEXT:                        012345678
+# BDVER2-NEXT:                        0123456789
 # BDVER2-NEXT:    Index     0123456789
 
 # BROADWELL-NEXT:                     0123456789
 # BROADWELL-NEXT: Index     0123456789          01234
 
 # BTVER2-NEXT:                        0123456789          0123456
 # BTVER2-NEXT:    Index     0123456789          0123456789
 
 # HASWELL-NEXT:                       0123456789
 # HASWELL-NEXT:   Index     0123456789          01234
 
 # SKYLAKE-NEXT:                       0123456789
 # SKYLAKE-NEXT:   Index     0123456789          0123456
 
 # ZNVER1-NEXT:                        0123456789          0
 # ZNVER1-NEXT:    Index     0123456789          0123456789
 
 # ZNVER2-NEXT:                        0123456789          0
 # ZNVER2-NEXT:    Index     0123456789          0123456789
 
 # BARCELONA:      [0,0]     DeER .    .    .    .    .    .   leaq  8(%rsp,%rdi,2), %rax
 # BARCELONA-NEXT: [0,1]     D=eeeeeeeeeeeeeeeeeeeeeeeeeeeER   sqrtsd  (%rax), %xmm1
 
-# BDVER2:         [0,0]     DeeER.    .    .  .   leaq  8(%rsp,%rdi,2), %rax
-# BDVER2-NEXT:    [0,1]     D==eeeeeeeeeeeeeeER   sqrtsd  (%rax), %xmm1
+# BDVER2:         [0,0]     .DeeER    .    .   .   leaq 8(%rsp,%rdi,2), %rax
+# BDVER2-NEXT:    [0,1]     .D==eeeeeeeeeeeeeeER   sqrtsd (%rax), %xmm1
 
 # BROADWELL:      [0,0]     DeER .    .    .    .   .   leaq  8(%rsp,%rdi,2), %rax
 # BROADWELL-NEXT: [0,1]     D=eeeeeeeeeeeeeeeeeeeeeER   sqrtsd  (%rax), %xmm1
 
 # BTVER2:         [0,0]     DeeER.    .    .    .    .    .    ..   leaq  8(%rsp,%rdi,2), %rax
 # BTVER2-NEXT:    [0,1]     D==eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeER   sqrtsd  (%rax), %xmm1
 
 # HASWELL:        [0,0]     DeER .    .    .    .   .   leaq  8(%rsp,%rdi,2), %rax

 # ZNVER2-NEXT:    1.     1     2.0    0.0    0.0       sqrtsd (%rax), %xmm1
 # ZNVER2-NEXT:           1     1.5    0.5    0.0       <total>
 
 # ALL:            [2] Code Region - test_rsqrtss
 
 # ALL:            Timeline view:
 
 # BARCELONA-NEXT:                     01234
-# BDVER2-NEXT:                        01234
+# BDVER2-NEXT:                        012345
 # BROADWELL-NEXT:                     0123
 # BTVER2-NEXT:                        01
 # HASWELL-NEXT:                       0123
 # SKYLAKE-NEXT:                       012
 # ZNVER1-NEXT:                        012345
 # ZNVER2-NEXT:                        012345
 
 # ALL-NEXT:       Index     0123456789
 
 # BARCELONA:      [0,0]     DeER .    .   .   leaq  8(%rsp,%rdi,2), %rax
 # BARCELONA-NEXT: [0,1]     D=eeeeeeeeeeeER   rsqrtss (%rax), %xmm1
 
-# BDVER2:         [0,0]     DeeER.    .   .   leaq  8(%rsp,%rdi,2), %rax
-# BDVER2-NEXT:    [0,1]     D==eeeeeeeeeeER   rsqrtss (%rax), %xmm1
+# BDVER2:         [0,0]     .DeeER    .    .   leaq 8(%rsp,%rdi,2), %rax
+# BDVER2-NEXT:    [0,1]     .D==eeeeeeeeeeER   rsqrtss  (%rax), %xmm1
 
 # BROADWELL:      [0,0]     DeER .    .  .   leaq 8(%rsp,%rdi,2), %rax
 # BROADWELL-NEXT: [0,1]     D=eeeeeeeeeeER   rsqrtss  (%rax), %xmm1
 
 # BTVER2:         [0,0]     DeeER.    ..   leaq 8(%rsp,%rdi,2), %rax
 # BTVER2-NEXT:    [0,1]     D==eeeeeeeER   rsqrtss  (%rax), %xmm1
 
 # HASWELL:        [0,0]     DeER .    .  .   leaq 8(%rsp,%rdi,2), %rax

 # ZNVER2-NEXT:    1.     1     2.0    0.0    0.0       rsqrtss  (%rax), %xmm1
 # ZNVER2-NEXT:           1     1.5    0.5    0.0       <total>
 
 # ALL:            [3] Code Region - test_rcp
 
 # ALL:            Timeline view:
 
 # BARCELONA-NEXT:                     01234
-# BDVER2-NEXT:                        01234
+# BDVER2-NEXT:                        012345
 # BROADWELL-NEXT:                     0123
 # BTVER2-NEXT:                        01
 # HASWELL-NEXT:                       0123
 # SKYLAKE-NEXT:                       012
 # ZNVER1-NEXT:                        012345
 # ZNVER2-NEXT:                        012345
 
 # ALL-NEXT:       Index     0123456789
 
 # BARCELONA:      [0,0]     DeER .    .   .   leaq  8(%rsp,%rdi,2), %rax
 # BARCELONA-NEXT: [0,1]     D=eeeeeeeeeeeER   rcpss (%rax), %xmm1
 
-# BDVER2:         [0,0]     DeeER.    .   .   leaq  8(%rsp,%rdi,2), %rax
-# BDVER2-NEXT:    [0,1]     D==eeeeeeeeeeER   rcpss (%rax), %xmm1
+# BDVER2:         [0,0]     .DeeER    .    .   leaq 8(%rsp,%rdi,2), %rax
+# BDVER2-NEXT:    [0,1]     .D==eeeeeeeeeeER   rcpss  (%rax), %xmm1
 
 # BROADWELL:      [0,0]     DeER .    .  .   leaq 8(%rsp,%rdi,2), %rax
 # BROADWELL-NEXT: [0,1]     D=eeeeeeeeeeER   rcpss  (%rax), %xmm1
 
 # BTVER2:         [0,0]     DeeER.    ..   leaq 8(%rsp,%rdi,2), %rax
 # BTVER2-NEXT:    [0,1]     D==eeeeeeeER   rcpss  (%rax), %xmm1
 
 # HASWELL:        [0,0]     DeER .    .  .   leaq 8(%rsp,%rdi,2), %rax

llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-1.s

 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER2
 
 vaddps %xmm0, %xmm0, %xmm1
 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
 
 # ALL:          Iterations:        1
 # ALL-NEXT:     Instructions:      2
 
-# BDVER2-NEXT:  Total Cycles:      10
+# BDVER2-NEXT:  Total Cycles:      11
 # BDVER2-NEXT:  Total uOps:        2
 
 # BDWELL-NEXT:  Total Cycles:      10
 # BDWELL-NEXT:  Total uOps:        4
 
 # BTVER2-NEXT:  Total Cycles:      11
 # BTVER2-NEXT:  Total uOps:        4
 

 
 # ZNVER1-NEXT:  Total Cycles:      11
 # ZNVER1-NEXT:  Total uOps:        2
 
 # ZNVER2-NEXT:  Total Cycles:      11
 # ZNVER2-NEXT:  Total uOps:        2
 
 # BDVER2:       Dispatch Width:    4
-# BDVER2-NEXT:  uOps Per Cycle:    0.20
-# BDVER2-NEXT:  IPC:               0.20
+# BDVER2-NEXT:  uOps Per Cycle:    0.18
+# BDVER2-NEXT:  IPC:               0.18
 # BDVER2-NEXT:  Block RThroughput: 2.0
 
 # BDWELL:       Dispatch Width:    4
 # BDWELL-NEXT:  uOps Per Cycle:    0.40
 # BDWELL-NEXT:  IPC:               0.20
 # BDWELL-NEXT:  Block RThroughput: 2.0
 
 # BTVER2:       Dispatch Width:    2

 # ZNVER1-NEXT:  Block RThroughput: 1.0
 
 # ZNVER2:       Dispatch Width:    4
 # ZNVER2-NEXT:  uOps Per Cycle:    0.18
 # ZNVER2-NEXT:  IPC:               0.18
 # ZNVER2-NEXT:  Block RThroughput: 1.0
 
 # BDVER2:       Timeline view:
+# BDVER2-NEXT:                      0
 # BDVER2-NEXT:  Index     0123456789
 
 # BDWELL:       Timeline view:
 # BDWELL-NEXT:  Index     0123456789
 
 # BTVER2:       Timeline view:
 # BTVER2-NEXT:                      0
 # BTVER2-NEXT:  Index     0123456789

 # ZNVER1:       Timeline view:
 # ZNVER1-NEXT:                      0
 # ZNVER1-NEXT:  Index     0123456789
 
 # ZNVER2:       Timeline view:
 # ZNVER2-NEXT:                      0
 # ZNVER2-NEXT:  Index     0123456789
 
-# BDVER2:       [0,0]     DeeeeeER .   vaddps %xmm0, %xmm0, %xmm1
-# BDVER2-NEXT:  [0,1]     DeeeeeeeER   vblendvps  %xmm1, (%rdi), %xmm2, %xmm3
+# BDVER2:       [0,0]     .DeeeeeER .   vaddps  %xmm0, %xmm0, %xmm1
+# BDVER2-NEXT:  [0,1]     .DeeeeeeeER   vblendvps %xmm1, (%rdi), %xmm2, %xmm3
 
 # BDWELL:       [0,0]     DeeeER   .   vaddps %xmm0, %xmm0, %xmm1
 # BDWELL-NEXT:  [0,1]     DeeeeeeeER   vblendvps  %xmm1, (%rdi), %xmm2, %xmm3
 
 # BTVER2:       [0,0]     DeeeER    .   vaddps  %xmm0, %xmm0, %xmm1
 # BTVER2-NEXT:  [0,1]     .DeeeeeeeER   vblendvps %xmm1, (%rdi), %xmm2, %xmm3
 
 # HASWELL:      [0,0]     DeeeER    .   vaddps  %xmm0, %xmm0, %xmm1

llvm/test/tools/llvm-mca/X86/variable-blend-read-after-ld-2.s

 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -timeline -instruction-info=false -resource-pressure=false < %s | FileCheck %s -check-prefix=ALL -check-prefix=ZNVER2
 
 vaddps %xmm0, %xmm0, %xmm2
 vblendvps %xmm1, (%rdi), %xmm2, %xmm3
 
 # ALL:          Iterations:        1
 # ALL-NEXT:     Instructions:      2
 
-# BDVER2-NEXT:  Total Cycles:      10
+# BDVER2-NEXT:  Total Cycles:      11
 # BDVER2-NEXT:  Total uOps:        2
 
 # BDWELL-NEXT:  Total Cycles:      10
 # BDWELL-NEXT:  Total uOps:        4
 
 # BTVER2-NEXT:  Total Cycles:      11
 # BTVER2-NEXT:  Total uOps:        4
 

 
 # ZNVER1-NEXT:  Total Cycles:      11
 # ZNVER1-NEXT:  Total uOps:        2
 
 # ZNVER2-NEXT:  Total Cycles:      11
 # ZNVER2-NEXT:  Total uOps:        2
 
 # BDVER2:       Dispatch Width:    4
-# BDVER2-NEXT:  uOps Per Cycle:    0.20
-# BDVER2-NEXT:  IPC:               0.20
+# BDVER2-NEXT:  uOps Per Cycle:    0.18
+# BDVER2-NEXT:  IPC:               0.18
 # BDVER2-NEXT:  Block RThroughput: 2.0
 
 # BDWELL:       Dispatch Width:    4
 # BDWELL-NEXT:  uOps Per Cycle:    0.40
 # BDWELL-NEXT:  IPC:               0.20
 # BDWELL-NEXT:  Block RThroughput: 2.0
 
 # BTVER2:       Dispatch Width:    2

 # ZNVER1-NEXT:  Block RThroughput: 1.0
 
 # ZNVER2:       Dispatch Width:    4
 # ZNVER2-NEXT:  uOps Per Cycle:    0.18
 # ZNVER2-NEXT:  IPC:               0.18
 # ZNVER2-NEXT:  Block RThroughput: 1.0
 
 # BDVER2:       Timeline view:
+# BDVER2-NEXT:                      0
 # BDVER2-NEXT:  Index     0123456789
 
 # BDWELL:       Timeline view:
 # BDWELL-NEXT:  Index     0123456789
 
 # BTVER2:       Timeline view:
 # BTVER2-NEXT:                      0
 # BTVER2-NEXT:  Index     0123456789

 # ZNVER1:       Timeline view:
 # ZNVER1-NEXT:                      0
 # ZNVER1-NEXT:  Index     0123456789
 
 # ZNVER2:       Timeline view:
 # ZNVER2-NEXT:                      0
 # ZNVER2-NEXT:  Index     0123456789
 
-# BDVER2:       [0,0]     DeeeeeER .   vaddps %xmm0, %xmm0, %xmm2
-# BDVER2-NEXT:  [0,1]     DeeeeeeeER   vblendvps  %xmm1, (%rdi), %xmm2, %xmm3
+# BDVER2:       [0,0]     .DeeeeeER .   vaddps  %xmm0, %xmm0, %xmm2
+# BDVER2-NEXT:  [0,1]     .DeeeeeeeER   vblendvps %xmm1, (%rdi), %xmm2, %xmm3
 
 # BDWELL:       [0,0]     DeeeER   .   vaddps %xmm0, %xmm0, %xmm2
 # BDWELL-NEXT:  [0,1]     DeeeeeeeER   vblendvps  %xmm1, (%rdi), %xmm2, %xmm3
 
 # BTVER2:       [0,0]     DeeeER    .   vaddps  %xmm0, %xmm0, %xmm2
 # BTVER2-NEXT:  [0,1]     .DeeeeeeeER   vblendvps %xmm1, (%rdi), %xmm2, %xmm3
 
 # HASWELL:      [0,0]     DeeeER    .   vaddps  %xmm0, %xmm0, %xmm2

llvm/tools/llvm-mca/llvm-mca.cpp

 #include "Views/DispatchStatistics.h"
 #include "Views/InstructionInfoView.h"
 #include "Views/RegisterFileStatistics.h"
 #include "Views/ResourcePressureView.h"
 #include "Views/RetireControlUnitStatistics.h"
 #include "Views/SchedulerStatistics.h"
 #include "Views/SummaryView.h"
 #include "Views/TimelineView.h"
+#include "llvm/ADT/Sequence.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCTargetOptionsCommandFlags.inc"
if (Region->startLoc().isValid() || Region->endLoc().isValid()) {
         TOF->os() << " - " << Desc;
       TOF->os() << "\n\n";
     }
 
     // Lower the MCInst sequence into an mca::Instruction sequence.
     ArrayRef<MCInst> Insts = Region->getInstructions();
     mca::CodeEmitter CE(*STI, *MAB, *MCE, Insts);
     std::vector<std::unique_ptr<mca::Instruction>> LoweredSequence;
-    for (const MCInst &MCI : Insts) {
+    for (unsigned MCID : llvm::seq(0U, (unsigned)Insts.size())) {
       Expected<std::unique_ptr<mca::Instruction>> Inst =
-          IB.createInstruction(MCI);
+          IB.createInstruction(CE, MCID);
       if (!Inst) {
         if (auto NewE = handleErrors(
                 Inst.takeError(),
                 [&IP, &STI](const mca::InstructionError<MCInst> &IE) {
                   std::string InstructionStr;
                   raw_string_ostream SS(InstructionStr);
                   WithColor::error() << IE.Message << '\n';
                   IP->printInst(&IE.Inst, 0, "", *STI, SS);