Clean up assembler CFI directives

[scott.linder]

Summary

• Support emitting .cfi_undefined in CodeGen. This will be used by AMDGPU.
• Emit register names in assembly for .cfi_undefined, .cfi_register, and .cfi_return_column

[echristo]

I think this is OK. Would you mind splitting out the undefined change from the register name change when committing?

Thanks!

llvm/lib/MC/MCAsmStreamer.cpp

 void MCAsmStreamer::emitCFISignalFrame() {
   MCStreamer::emitCFISignalFrame();
   OS << "\t.cfi_signal_frame";
   EmitEOL();
 }
 
 void MCAsmStreamer::emitCFIUndefined(int64_t Register) {
   MCStreamer::emitCFIUndefined(Register);
-  OS << "\t.cfi_undefined " << Register;
+  OS << "\t.cfi_undefined ";
+  EmitRegisterName(Register);
   EmitEOL();
 }
 
 void MCAsmStreamer::emitCFIRegister(int64_t Register1, int64_t Register2) {
   MCStreamer::emitCFIRegister(Register1, Register2);
-  OS << "\t.cfi_register " << Register1 << ", " << Register2;
+  OS << "\t.cfi_register ";
+  EmitRegisterName(Register1);
+  OS << ", ";
+  EmitRegisterName(Register2);
   EmitEOL();
 }
 
 void MCAsmStreamer::emitCFIWindowSave() {
   MCStreamer::emitCFIWindowSave();
   OS << "\t.cfi_window_save";
   EmitEOL();
 }
 
 void MCAsmStreamer::emitCFINegateRAState() {
   MCStreamer::emitCFINegateRAState();
   OS << "\t.cfi_negate_ra_state";
   EmitEOL();
 }
 
 void MCAsmStreamer::emitCFIReturnColumn(int64_t Register) {
   MCStreamer::emitCFIReturnColumn(Register);
-  OS << "\t.cfi_return_column " << Register;
+  OS << "\t.cfi_return_column ";
+  EmitRegisterName(Register);
   EmitEOL();
 }
 
 void MCAsmStreamer::emitCFIBKeyFrame() {
   MCStreamer::emitCFIBKeyFrame();
   OS << "\t.cfi_b_key_frame";
   EmitEOL();
 }

llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=sparc   < %s | FileCheck %s --check-prefix=V8
 ; RUN: llc -march=sparcv9 < %s | FileCheck %s --check-prefix=SPARC64
 
 ; (this should ideally be doing "add 4+7; and -8", instead of
 ;  "add 7; and -8; add 8"; see comments in LowerDYNAMIC_STACKALLOC)
 
 define void @variable_alloca_with_adj_call_stack(i32 %num) {
 ; V8-LABEL: variable_alloca_with_adj_call_stack:
 ; V8:         .cfi_startproc
 ; V8-NEXT:  ! %bb.0: ! %entry
 ; V8-NEXT:    save %sp, -96, %sp
 ; V8-NEXT:    .cfi_def_cfa_register %fp
 ; V8-NEXT:    .cfi_window_save
-; V8-NEXT:    .cfi_register 15, 31
+; V8-NEXT:    .cfi_register %o7, %i7
 ; V8-NEXT:    add %i0, 7, %i0
 ; V8-NEXT:    and %i0, -8, %i0
 ; V8-NEXT:    sub %sp, %i0, %i0
 ; V8-NEXT:    add %i0, -8, %sp
 ; V8-NEXT:    add %i0, 88, %o0
 ; V8-NEXT:    add %sp, -16, %sp
 ; V8-NEXT:    st %o0, [%sp+104]
 ; V8-NEXT:    st %o0, [%sp+100]

 ; V8-NEXT:    restore
 ;
 ; SPARC64-LABEL: variable_alloca_with_adj_call_stack:
 ; SPARC64:         .cfi_startproc
 ; SPARC64-NEXT:  ! %bb.0: ! %entry
 ; SPARC64-NEXT:    save %sp, -128, %sp
 ; SPARC64-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC64-NEXT:    .cfi_window_save
-; SPARC64-NEXT:    .cfi_register 15, 31
+; SPARC64-NEXT:    .cfi_register %o7, %i7
 ; SPARC64-NEXT:    srl %i0, 0, %i0
 ; SPARC64-NEXT:    add %i0, 15, %i0
 ; SPARC64-NEXT:    sethi 4194303, %i1
 ; SPARC64-NEXT:    or %i1, 1008, %i1
 ; SPARC64-NEXT:    sethi 0, %i2
 ; SPARC64-NEXT:    or %i2, 1, %i2
 ; SPARC64-NEXT:    sllx %i2, 32, %i2
 ; SPARC64-NEXT:    or %i2, %i1, %i1

llvm/test/CodeGen/SPARC/exception.ll

 @.cst1 = private unnamed_addr constant [14 x i8] c"catched float\00", align 64
 
 ; V8ABS-LABEL: main:
 ; V8ABS:        .cfi_startproc
 ; V8ABS:        .cfi_personality 0, __gxx_personality_v0
 ; V8ABS:        .cfi_lsda 0,
 ; V8ABS:        .cfi_def_cfa_register {{30|%fp}}
 ; V8ABS:        .cfi_window_save
-; V8ABS:        .cfi_register 15, 31
+; V8ABS:        .cfi_register %o7, %i7
 
 ; V8ABS:        call __cxa_throw
 ; V8ABS:        call __cxa_throw
 
 ; V8ABS:        call __cxa_begin_catch
 ; V8ABS:        call __cxa_end_catch
 
 ; V8ABS:        call __cxa_begin_catch
 ; V8ABS:        call __cxa_end_catch
 
 ; V8ABS:        .cfi_endproc
 
 ; V8PIC-LABEL: main:
 ; V8PIC:        .cfi_startproc
 ; V8PIC:        .cfi_personality 155, DW.ref.__gxx_personality_v0
 ; V8PIC:        .cfi_lsda 27,
 ; V8PIC:        .cfi_def_cfa_register {{30|%fp}}
 ; V8PIC:        .cfi_window_save
-; V8PIC:        .cfi_register 15, 31
+; V8PIC:        .cfi_register %o7, %i7
 ; V8PIC:        .section .gcc_except_table
 ; V8PIC-NOT:    .section
 ; V8PIC:        .word %r_disp32(.L_ZTIi.DW.stub)
 ; V8PIC:        .data
 ; V8PIC: .L_ZTIi.DW.stub:
 ; V8PIC-NEXT:   .word _ZTIi
 
 
 ; V9ABS-LABEL: main:
 ; V9ABS:        .cfi_startproc
 ; V9ABS:        .cfi_personality 0, __gxx_personality_v0
 ; V9ABS:        .cfi_lsda 27,
 ; V9ABS:        .cfi_def_cfa_register {{30|%fp}}
 ; V9ABS:        .cfi_window_save
-; V9ABS:        .cfi_register 15, 31
+; V9ABS:        .cfi_register %o7, %i7
 ; V9ABS:        .section .gcc_except_table
 ; V9ABS-NOT:    .section
 ; V9ABS:        .xword _ZTIi
 
 ; V9PIC-LABEL: main:
 ; V9PIC:        .cfi_startproc
 ; V9PIC:        .cfi_personality 155, DW.ref.__gxx_personality_v0
 ; V9PIC:        .cfi_lsda 27,
 ; V9PIC:        .cfi_def_cfa_register {{30|%fp}}
 ; V9PIC:        .cfi_window_save
-; V9PIC:        .cfi_register 15, 31
+; V9PIC:        .cfi_register %o7, %i7
 ; V9PIC:        .section .gcc_except_table
 ; V9PIC-NOT:    .section
 ; V9PIC:        .word %r_disp32(.L_ZTIi.DW.stub)
 ; V9PIC:        .data
 ; V9PIC: .L_ZTIi.DW.stub:
 ; V9PIC-NEXT:   .xword _ZTIi
 
 define i32 @main(i32 %argc, i8** nocapture readnone %argv) unnamed_addr #0 personality i32 (i32, i64, i8*, i8*)* @__gxx_personality_v0 {

llvm/test/CodeGen/SPARC/reserved-regs.ll

 ; RUN: llc -march=sparc -verify-machineinstrs < %s | FileCheck %s
 
 @g = common global [32 x i32] zeroinitializer, align 16
 @h = common global [16 x i64] zeroinitializer, align 16
 
 ;; Ensures that we don't use registers which are supposed to be reserved.
 
 ; CHECK-LABEL: use_all_i32_regs:
 ; CHECK: save %sp
+; CHECK: .cfi_register %o7, %i7
 ; CHECK-NOT: %g0
 ; CHECK-NOT: %g1
 ; CHECK-NOT: %g5
 ; CHECK-NOT: %g6
 ; CHECK-NOT: %g7
 ; CHECK-NOT: %o6
 ; CHECK-NOT: %i6
 ; CHECK-NOT: %i7
entry:
   store volatile i32 %31, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 30), align 8
   store volatile i32 %0, i32* getelementptr inbounds ([32 x i32], [32 x i32]* @g, i64 0, i64 31), align 4
   ret void
 }
 
 
 ; CHECK-LABEL: use_all_i64_regs:
 ; CHECK: save %sp
+; CHECK: .cfi_register %o7, %i7
 ; CHECK-NOT: %g0
 ; CHECK-NOT: %g1
 ; CHECK-NOT: %g4
 ; CHECK-NOT: %g5
 ; CHECK-NOT: %g6
 ; CHECK-NOT: %g7
 ; CHECK-NOT: %o6
 ; CHECK-NOT: %o7

llvm/test/CodeGen/SPARC/umulo-128-legalisation-lowering.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC
 ; RUN: llc < %s -mtriple=sparc64-unknown-linux-gnu | FileCheck %s --check-prefixes=SPARC64
 
 define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; SPARC-LABEL: muloti_test:
 ; SPARC:         .cfi_startproc
 ; SPARC-NEXT:  ! %bb.0: ! %start
 ; SPARC-NEXT:    save %sp, -128, %sp
 ; SPARC-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC-NEXT:    .cfi_window_save
-; SPARC-NEXT:    .cfi_register 15, 31
+; SPARC-NEXT:    .cfi_register %o7, %i7
 ; SPARC-NEXT:    ld [%fp+92], %l3
 ; SPARC-NEXT:    ld [%fp+96], %g2
 ; SPARC-NEXT:    umul %i2, %i5, %g3
 ; SPARC-NEXT:    rd %y, %g4
 ; SPARC-NEXT:    st %g4, [%fp+-20] ! 4-byte Folded Spill
 ; SPARC-NEXT:    umul %i4, %i3, %g4
 ; SPARC-NEXT:    rd %y, %l0
 ; SPARC-NEXT:    st %l0, [%fp+-24] ! 4-byte Folded Spill

 ;
 ; SPARC64-LABEL: muloti_test:
 ; SPARC64:         .cfi_startproc
 ; SPARC64-NEXT:    .register %g2, #scratch
 ; SPARC64-NEXT:  ! %bb.0: ! %start
 ; SPARC64-NEXT:    save %sp, -176, %sp
 ; SPARC64-NEXT:    .cfi_def_cfa_register %fp
 ; SPARC64-NEXT:    .cfi_window_save
-; SPARC64-NEXT:    .cfi_register 15, 31
+; SPARC64-NEXT:    .cfi_register %o7, %i7
 ; SPARC64-NEXT:    srax %i2, 63, %o0
 ; SPARC64-NEXT:    srax %i1, 63, %o2
 ; SPARC64-NEXT:    mov %i2, %o1
 ; SPARC64-NEXT:    call __multi3
 ; SPARC64-NEXT:    mov %i1, %o3
 ; SPARC64-NEXT:    mov %o0, %i4
 ; SPARC64-NEXT:    mov %o1, %i5
 ; SPARC64-NEXT:    srax %i0, 63, %o0

llvm/test/MC/X86/return-column.s

g:
   .type g,@function
 h:
   .cfi_startproc
   .cfi_return_column 65
   .cfi_endproc
 
 // CHECK-ASM-ROUNDTRIP-LABEL: f:
 // CHECK-ASM-ROUNDTRIP: .cfi_startproc
-// CHECK-ASM-ROUNDTRIP-NEXT: .cfi_return_column 0
+// CHECK-ASM-ROUNDTRIP-NEXT: .cfi_return_column %eax
 // CHECK-ASM-ROUNDTRIP: .cfi_endproc
 
 // CHECK-EH_FRAME: 00000000 00000014 00000000 CIE
 // CHECK-EH_FRAME:   Return address column: 0
 
 // CHECK-EH_FRAME: 0000002c 00000014 00000000 CIE
 // CHECK-EH_FRAME:   Return address column: 65
 
 // CHECK-EH_FRAME-NOT: ........ 00000014 00000000 CIE