GlobalISel: Extend narrowing to G_ASHR

[foad]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1480

"32" should be "31" here, but in any case this whole clause makes no sense to me. Why would shifting a 64-bit value right by 31 leave the low half unchanged?

1485

Why not generalize this to:

(G_ASHR i64:x, 63) for C >= 32 ->
  G_MERGE_VALUES (G_ASHR hi_32(x), C-32), (G_ASHR hi_32(x), 31)

?

[foad]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1485

I meant (G_ASHR i64:x, C) of course.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1480

I broke this when I did a cleanup pass, this should just be HalfSize

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1485

I copied this from the existing AMDGPUTargetLowering::performSrlCombine, I'm not sure why this restricts it to the one shift case

[arsenm]

Fix bug and generalize

[foad]

Is it really worth splitting ashr into three separate cases? Can't CSE and constant folding do it all for you?

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1482

Low half of result should be high half of input. Both comment and code are wrong here.

1485

32 should be 63 in comment.

[arsenm]

In D74322#1867403, @foad wrote:

Is it really worth splitting ashr into three separate cases? Can't CSE and constant folding do it all for you?

I feel weird relying on such things, especially when I can see the cases. If I just delete the special case, it does not manage to take care of it

[arsenm]

Fix comment

[foad]

In D74322#1871279, @arsenm wrote:

In D74322#1867403, @foad wrote:

Is it really worth splitting ashr into three separate cases? Can't CSE and constant folding do it all for you?

I feel weird relying on such things, especially when I can see the cases. If I just delete the special case, it does not manage to take care of it

I guess it's up to you, but given that we already have a constant folding MIR builder it seems silly to write (and test and review) extra code to handle cases that it could handle for you. I was a bit surprised that we're not already using it. I had to tweak Combiner::combineMachineInstrs to create a ConstantFoldingMIRBuilder instead of plain MachineIRBuilder, but then your new tests still pass even if I delete the "NarrowShiftAmt == 0" special cases for all of shl, lshr and ashr.

[foad]

In D74322#1871587, @foad wrote:

I had to tweak Combiner::combineMachineInstrs to create a ConstantFoldingMIRBuilder instead of plain MachineIRBuilder, but then your new tests still pass even if I delete the "NarrowShiftAmt == 0" special cases for all of shl, lshr and ashr.

Sorry, forget that, I was testing the wrong thing.

[foad]

In D74322#1871587, @foad wrote:

I guess it's up to you, but given that we already have a constant folding MIR builder it seems silly to write (and test and review) extra code to handle cases that it could handle for you.

I was wrong. ConstantFoldingMIRBuilder only handles genuine constant folding like 3+4. It doesn't simplify degenerate cases like adding or shifting by 0.

LGTM.

[foad]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1482

Actually this still needs fixing; LGTM apart from that.

[arsenm]

0e2eb357e0471bbac81f18097e5ad761ae1431f0

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

bool CombinerHelper::applyCombineMulToShl(MachineInstr &MI,
   Observer.changedInstr(MI);
   return true;
 }
 
 bool CombinerHelper::matchCombineShiftToUnmerge(MachineInstr &MI,
                                                 unsigned TargetShiftSize,
                                                 unsigned &ShiftVal) {
   assert((MI.getOpcode() == TargetOpcode::G_SHL ||
-          MI.getOpcode() == TargetOpcode::G_LSHR) && "Expected a shift");
+          MI.getOpcode() == TargetOpcode::G_LSHR ||
+          MI.getOpcode() == TargetOpcode::G_ASHR) && "Expected a shift");
 
   LLT Ty = MRI.getType(MI.getOperand(0).getReg());
   if (Ty.isVector()) // TODO:
     return false;
 
   // Don't narrow further than the requested size.
   unsigned Size = Ty.getSizeInBits();
   if (Size <= TargetShiftSize)

 
 bool CombinerHelper::applyCombineShiftToUnmerge(MachineInstr &MI,
                                                 const unsigned &ShiftVal) {
   Register DstReg = MI.getOperand(0).getReg();
   Register SrcReg = MI.getOperand(1).getReg();
   LLT Ty = MRI.getType(SrcReg);
   unsigned Size = Ty.getSizeInBits();
   unsigned HalfSize = Size / 2;
-
   assert(ShiftVal >= HalfSize);
+
   LLT HalfTy = LLT::scalar(HalfSize);
 
   Builder.setInstr(MI);
   auto Unmerge = Builder.buildUnmerge(HalfTy, SrcReg);
   unsigned NarrowShiftAmt = ShiftVal - HalfSize;
 
   if (MI.getOpcode() == TargetOpcode::G_LSHR) {
     Register Narrowed = Unmerge.getReg(1);
 
     //  dst = G_LSHR s64:x, C for C >= 32
     // =>
     //   lo, hi = G_UNMERGE_VALUES x
     //   dst = G_MERGE_VALUES (G_LSHR hi, C - 32), 0
 
     if (NarrowShiftAmt != 0) {
       Narrowed = Builder.buildLShr(HalfTy, Narrowed,
         Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0);
     }
 
     auto Zero = Builder.buildConstant(HalfTy, 0);
     Builder.buildMerge(DstReg, { Narrowed, Zero });
-  } else {
+  } else if (MI.getOpcode() == TargetOpcode::G_SHL) {
     Register Narrowed = Unmerge.getReg(0);
     //  dst = G_SHL s64:x, C for C >= 32
     // =>
     //   lo, hi = G_UNMERGE_VALUES x
     //   dst = G_MERGE_VALUES 0, (G_SHL hi, C - 32)
-
-    // TODO: ashr
-    assert(MI.getOpcode() == TargetOpcode::G_SHL);
-
     if (NarrowShiftAmt != 0) {
       Narrowed = Builder.buildShl(HalfTy, Narrowed,
         Builder.buildConstant(HalfTy, NarrowShiftAmt)).getReg(0);
     }
 
     auto Zero = Builder.buildConstant(HalfTy, 0);
     Builder.buildMerge(DstReg, { Zero, Narrowed });
+  } else {
+    assert(MI.getOpcode() == TargetOpcode::G_ASHR);
+    auto Hi = Builder.buildAShr(
+      HalfTy, Unmerge.getReg(1),
+      Builder.buildConstant(HalfTy, HalfSize - 1));
+
+    if (ShiftVal == HalfSize) {
+      // (G_ASHR i64:x, 32) ->
+      //   G_MERGE_VALUES lo_32(x), (G_ASHR hi_32(x), 31)
+      Builder.buildMerge(DstReg, { Unmerge.getReg(0), Hi });
+    } else if (ShiftVal == Size - 1) {
+      // Don't need a second shift.
+      // (G_ASHR i64:x, 63) ->
+      //   %narrowed = (G_ASHR hi_32(x), 31)
+      //   G_MERGE_VALUES %narrowed, %narrowed
+      Builder.buildMerge(DstReg, { Hi, Hi });
+    } else {
+      auto Lo = Builder.buildAShr(
+        HalfTy, Unmerge.getReg(1),
+        Builder.buildConstant(HalfTy, ShiftVal - HalfSize));
+
+      // (G_ASHR i64:x, C) ->, for C >= 32
+      //   G_MERGE_VALUES (G_ASHR hi_32(x), C - 32), (G_ASHR hi_32(x), 31)
+      Builder.buildMerge(DstReg, { Lo, Hi });
+    }
   }
 
   MI.eraseFromParent();
   return true;
 }
 
 bool CombinerHelper::tryCombineShiftToUnmerge(MachineInstr &MI,
                                               unsigned TargetShiftAmount) {

llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

bool AMDGPUPreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
   CombinerHelper Helper(Observer, B, KB, MDT);
 
   if (Generated.tryCombineAll(Observer, MI, B, Helper))
     return true;
 
   switch (MI.getOpcode()) {
   case TargetOpcode::G_SHL:
   case TargetOpcode::G_LSHR:
+  case TargetOpcode::G_ASHR:
     // On some subtargets, 64-bit shift is a quarter rate instruction. In the
     // common case, splitting this into a move and a 32-bit shift is faster and
     // the same code size.
     return Helper.tryCombineShiftToUnmerge(MI, 32);
   case TargetOpcode::G_CONCAT_VECTORS:
     return Helper.tryCombineConcatVectors(MI);
   case TargetOpcode::G_SHUFFLE_VECTOR:
     return Helper.tryCombineShuffleVector(MI);

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-ashr-narrow.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            narrow_ashr_s64_32_s64amt
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_s64_32_s64amt
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[ASHR]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s64) = G_CONSTANT i64 32
+    %2:_(s64) = G_ASHR %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name:            narrow_ashr_s64_32
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_s64_32
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[UV]](s32), [[ASHR]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_CONSTANT i32 32
+    %2:_(s64) = G_ASHR %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name:            narrow_ashr_s64_33
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_s64_33
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C1]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR1]](s32), [[ASHR]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_CONSTANT i32 33
+    %2:_(s64) = G_ASHR %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name:            narrow_ashr_s64_31
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_s64_31
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_CONSTANT i32 31
+    %2:_(s64) = G_ASHR %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name:            narrow_ashr_s64_63
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_s64_63
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[UV1]], [[C]](s32)
+    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[ASHR]](s32), [[ASHR]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[MV]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_CONSTANT i32 63
+    %2:_(s64) = G_ASHR %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name:            narrow_ashr_s64_64
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_s64_64
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_CONSTANT i32 64
+    %2:_(s64) = G_ASHR %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name:            narrow_ashr_s64_65
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_s64_65
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s32)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](s64)
+    %0:_(s64) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_CONSTANT i32 65
+    %2:_(s64) = G_ASHR %0, %1
+    $vgpr0_vgpr1 = COPY %2
+...
+
+---
+name:            narrow_ashr_s32_16
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: narrow_ashr_s32_16
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
+    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_CONSTANT i32 16
+    %2:_(s32) = G_ASHR %0, %1
+    $vgpr0 = COPY %2
+...
+
+---
+name:            narrow_ashr_s32_17
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: narrow_ashr_s32_17
+    ; CHECK: liveins: $vgpr0
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
+    ; CHECK: $vgpr0 = COPY [[ASHR]](s32)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s32) = G_CONSTANT i32 17
+    %2:_(s32) = G_ASHR %0, %1
+    $vgpr0 = COPY %2
+...
+
+---
+name:            narrow_ashr_v2s32_17
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+
+    ; CHECK-LABEL: name: narrow_ashr_v2s32_17
+    ; CHECK: liveins: $vgpr0_vgpr1
+    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
+    ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
+    ; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s32>) = G_ASHR [[COPY]], [[BUILD_VECTOR]](<2 x s32>)
+    ; CHECK: $vgpr0_vgpr1 = COPY [[ASHR]](<2 x s32>)
+    %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_CONSTANT i32 17
+    %2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1
+    %3:_(<2 x s32>) = G_ASHR %0, %2
+    $vgpr0_vgpr1 = COPY %3
+...