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Differential D74188

GlobalISel: Fix lowering of G_CTLZ/G_CTTZ
ClosedPublic

Authored by arsenm on Feb 6 2020, 6:19 PM.

Details

Reviewers
aemerson
paquette
aditya_nandakumar
Petar.Avramovic
dsanders
Summary

The type passed to lower was invalid, so I'm not sure how this was
even working before. The source and destination type also do not have
to match, so make sure to use the right ones.

Diff Detail

Event Timeline

arsenm created this revision.Feb 6 2020, 6:19 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 6 2020, 6:19 PM
Herald added subscribers: kerbowa, volkan, hiraditya and 4 others. · View Herald Transcript
nhaehnle removed a subscriber: nhaehnle.Feb 7 2020, 1:44 AM
Petar.Avramovic accepted this revision.Feb 7 2020, 3:44 AM

LGTM

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
4113–4114

long line

This revision is now accepted and ready to land.Feb 7 2020, 3:44 AM
arsenm closed this revision.Feb 7 2020, 6:58 AM
arsenm marked an inline comment as done.

8de2dad9e0d729663f83d80f9a9e9b98ef41992e

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
50 lines
Target/
AMDGPU/
27 lines
2 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
123 lines
102 lines
ARM/
GlobalISel/
4 lines

Diff 243067

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 4,071 Lines • ▼ Show 20 LinesLegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
case TargetOpcode::G_CTLZ_ZERO_UNDEF: { case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
// This trivially expands to CTLZ. // This trivially expands to CTLZ.
Observer.changingInstr(MI); Observer.changingInstr(MI);
MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
} }
case TargetOpcode::G_CTLZ: { case TargetOpcode::G_CTLZ: {
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg(); Register SrcReg = MI.getOperand(1).getReg();
unsigned Len = Ty.getSizeInBits(); LLT DstTy = MRI.getType(DstReg);
if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) { LLT SrcTy = MRI.getType(SrcReg);
unsigned Len = SrcTy.getSizeInBits();
if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
// If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
auto MIBCtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(Ty, SrcReg); auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg);
auto MIBZero = MIRBuilder.buildConstant(Ty, 0); auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0);
auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto ICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ,
auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), SrcTy.changeElementSize(1),
SrcReg, MIBZero); SrcReg, ZeroSrc);
MIRBuilder.buildSelect(MI.getOperand(0), MIBICmp, MIBLen, MIBCtlzZU); auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
// for now, we do this: // for now, we do this:
// NewLen = NextPowerOf2(Len); // NewLen = NextPowerOf2(Len);
// x = x | (x >> 1); // x = x | (x >> 1);
// x = x | (x >> 2); // x = x | (x >> 2);
// ... // ...
// x = x | (x >>16); // x = x | (x >>16);
// x = x | (x >>32); // for 64-bit input // x = x | (x >>32); // for 64-bit input
// Upto NewLen/2 // Upto NewLen/2
// return Len - popcount(x); // return Len - popcount(x);
// //
// Ref: "Hacker's Delight" by Henry Warren // Ref: "Hacker's Delight" by Henry Warren
Register Op = SrcReg; Register Op = SrcReg;
unsigned NewLen = PowerOf2Ceil(Len); unsigned NewLen = PowerOf2Ceil(Len);
for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i); auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i);
auto MIBOp = auto MIBOp =
MIRBuilder.buildOr(Ty, Op, MIRBuilder.buildLShr(Ty, Op, MIBShiftAmt)); MIRBuilder.buildOr(SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt));
Petar.AvramovicUnsubmitted
Done
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long line

Petar.Avramovic: long line
Op = MIBOp.getReg(0); Op = MIBOp.getReg(0);
} }
auto MIBPop = MIRBuilder.buildCTPOP(Ty, Op); auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op);
MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(Ty, Len), MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len),
MIBPop); MIBPop);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
case TargetOpcode::G_CTTZ_ZERO_UNDEF: { case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
// This trivially expands to CTTZ. // This trivially expands to CTTZ.
Observer.changingInstr(MI); Observer.changingInstr(MI);
MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
} }
case TargetOpcode::G_CTTZ: { case TargetOpcode::G_CTTZ: {
Register DstReg = MI.getOperand(0).getReg();
Register SrcReg = MI.getOperand(1).getReg(); Register SrcReg = MI.getOperand(1).getReg();
unsigned Len = Ty.getSizeInBits(); LLT DstTy = MRI.getType(DstReg);
if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) { LLT SrcTy = MRI.getType(SrcReg);
unsigned Len = SrcTy.getSizeInBits();
if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
// If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
// zero. // zero.
auto MIBCttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(Ty, SrcReg); auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg);
auto MIBZero = MIRBuilder.buildConstant(Ty, 0); auto Zero = MIRBuilder.buildConstant(SrcTy, 0);
auto MIBLen = MIRBuilder.buildConstant(Ty, Len); auto ICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ,
auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), DstTy.changeElementSize(1),
SrcReg, MIBZero); SrcReg, Zero);
MIRBuilder.buildSelect(MI.getOperand(0), MIBICmp, MIBLen, MIBCttzZU); auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
// for now, we use: { return popcount(~x & (x - 1)); } // for now, we use: { return popcount(~x & (x - 1)); }
// unless the target has ctlz but not ctpop, in which case we use: // unless the target has ctlz but not ctpop, in which case we use:
// { return 32 - nlz(~x & (x-1)); } // { return 32 - nlz(~x & (x-1)); }
// Ref: "Hacker's Delight" by Henry Warren // Ref: "Hacker's Delight" by Henry Warren
auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1); auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
▲ Show 20 Lines • Show All 800 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Show First 20 Lines • Show All 460 Lines • ▼ Show 20 Lines else
FMad.customFor({S32}); FMad.customFor({S32});
FMad.scalarize(0) FMad.scalarize(0)
.lower(); .lower();
getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT}) getActionDefinitionsBuilder({G_SEXT, G_ZEXT, G_ANYEXT})
.legalFor({{S64, S32}, {S32, S16}, {S64, S16}, .legalFor({{S64, S32}, {S32, S16}, {S64, S16},
{S32, S1}, {S64, S1}, {S16, S1}}) {S32, S1}, {S64, S1}, {S16, S1}})
.scalarize(0) .scalarize(0)
.clampScalar(0, S32, S64); .clampScalar(0, S32, S64)
.widenScalarToNextPow2(1, 32);
// TODO: Split s1->s64 during regbankselect for VALU. // TODO: Split s1->s64 during regbankselect for VALU.
auto &IToFP = getActionDefinitionsBuilder({G_SITOFP, G_UITOFP}) auto &IToFP = getActionDefinitionsBuilder({G_SITOFP, G_UITOFP})
.legalFor({{S32, S32}, {S64, S32}, {S16, S32}}) .legalFor({{S32, S32}, {S64, S32}, {S16, S32}})
.lowerFor({{S32, S64}}) .lowerFor({{S32, S64}})
.lowerIf(typeIs(1, S1)) .lowerIf(typeIs(1, S1))
.customFor({{S64, S64}}); .customFor({{S64, S64}});
if (ST.has16BitInsts()) if (ST.has16BitInsts())
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 LinesAMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
if (ST.has16BitInsts()) if (ST.has16BitInsts())
ExpOps.customFor({{S32}, {S16}}); ExpOps.customFor({{S32}, {S16}});
else else
ExpOps.customFor({S32}); ExpOps.customFor({S32});
ExpOps.clampScalar(0, MinScalarFPTy, S32) ExpOps.clampScalar(0, MinScalarFPTy, S32)
.scalarize(0); .scalarize(0);
// The 64-bit versions produce 32-bit results, but only on the SALU. // The 64-bit versions produce 32-bit results, but only on the SALU.
getActionDefinitionsBuilder({G_CTLZ, G_CTLZ_ZERO_UNDEF, getActionDefinitionsBuilder(G_CTPOP)
G_CTTZ, G_CTTZ_ZERO_UNDEF, .legalFor({{S32, S32}, {S32, S64}})
G_CTPOP}) .clampScalar(0, S32, S32)
.clampScalar(1, S32, S64)
.scalarize(0)
.widenScalarToNextPow2(0, 32)
.widenScalarToNextPow2(1, 32);
// The hardware instructions return a different result on 0 than the generic
// instructions expect. The hardware produces -1, but these produce the
// bitwidth.
getActionDefinitionsBuilder({G_CTLZ, G_CTTZ})
.scalarize(0)
.clampScalar(0, S32, S32)
.clampScalar(1, S32, S64)
.widenScalarToNextPow2(0, 32)
.widenScalarToNextPow2(1, 32)
.lower();
// The 64-bit versions produce 32-bit results, but only on the SALU.
getActionDefinitionsBuilder({G_CTLZ_ZERO_UNDEF, G_CTTZ_ZERO_UNDEF})
.legalFor({{S32, S32}, {S32, S64}}) .legalFor({{S32, S32}, {S32, S64}})
.clampScalar(0, S32, S32) .clampScalar(0, S32, S32)
.clampScalar(1, S32, S64) .clampScalar(1, S32, S64)
.scalarize(0) .scalarize(0)
.widenScalarToNextPow2(0, 32) .widenScalarToNextPow2(0, 32)
.widenScalarToNextPow2(1, 32); .widenScalarToNextPow2(1, 32);
// TODO: Expand for > s32 // TODO: Expand for > s32
▲ Show 20 Lines • Show All 2,990 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

Show First 20 Lines • Show All 2,937 Lines • ▼ Show 20 Lines case AMDGPU::G_CONCAT_VECTORS: {
// Op1 and Dst should use the same register bank. // Op1 and Dst should use the same register bank.
for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i) for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i)
OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize); OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
break; break;
} }
case AMDGPU::G_BITCAST: case AMDGPU::G_BITCAST:
case AMDGPU::G_INTTOPTR: case AMDGPU::G_INTTOPTR:
case AMDGPU::G_PTRTOINT: case AMDGPU::G_PTRTOINT:
case AMDGPU::G_CTLZ:
case AMDGPU::G_CTLZ_ZERO_UNDEF: case AMDGPU::G_CTLZ_ZERO_UNDEF:
case AMDGPU::G_CTTZ:
case AMDGPU::G_CTTZ_ZERO_UNDEF: case AMDGPU::G_CTTZ_ZERO_UNDEF:
case AMDGPU::G_CTPOP: case AMDGPU::G_CTPOP:
case AMDGPU::G_BSWAP: case AMDGPU::G_BSWAP:
case AMDGPU::G_BITREVERSE: case AMDGPU::G_BITREVERSE:
case AMDGPU::G_FABS: case AMDGPU::G_FABS:
case AMDGPU::G_FNEG: { case AMDGPU::G_FNEG: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI); unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
▲ Show 20 Lines • Show All 714 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: ctlz_s32_s32 name: ctlz_s32_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ctlz_s32_s32 ; CHECK-LABEL: name: ctlz_s32_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[CTLZ]](s32) ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTLZ %0 %1:_(s32) = G_CTLZ %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: ctlz_s32_s64 name: ctlz_s32_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctlz_s32_s64 ; CHECK-LABEL: name: ctlz_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s64) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
; CHECK: $vgpr0 = COPY [[CTLZ]](s32) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CTLZ %0 %1:_(s32) = G_CTLZ %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: ctlz_s64_s64 name: ctlz_s64_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctlz_s64_s64 ; CHECK-LABEL: name: ctlz_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s64) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ]](s32) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SELECT]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_CTLZ %0 %1:_(s64) = G_CTLZ %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: ctlz_s16_s32 name: ctlz_s16_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ctlz_s16_s32 ; CHECK-LABEL: name: ctlz_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[COPY]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: $vgpr0 = COPY [[AND]](s32) ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTLZ %0 %1:_(s16) = G_CTLZ %0
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: ctlz_s16_s16 name: ctlz_s16_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ctlz_s16_s16 ; CHECK-LABEL: name: ctlz_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTLZ %1 %2:_(s16) = G_CTLZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: ctlz_v2s32_v2s32 name: ctlz_v2s32_v2s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctlz_v2s32_v2s32 ; CHECK-LABEL: name: ctlz_v2s32_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[UV]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV]](s32)
; CHECK: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[UV1]](s32) ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ]](s32), [[CTLZ1]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV1]](s32)
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[C]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[CTLZ_ZERO_UNDEF1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_CTLZ %0 %1:_(<2 x s32>) = G_CTLZ %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: ctlz_v2s32_v2s64 name: ctlz_v2s32_v2s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3 liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: ctlz_v2s32_v2s64 ; CHECK-LABEL: name: ctlz_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[UV]](s64) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV]](s64)
; CHECK: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[UV1]](s64) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTLZ]](s32), [[CTLZ1]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s64), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[UV1]](s64)
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s64), [[C]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[CTLZ_ZERO_UNDEF1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s32>) = G_CTLZ %0 %1:_(<2 x s32>) = G_CTLZ %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: ctlz_v2s16_v2s16 name: ctlz_v2s16_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ctlz_v2s16_v2s16 ; CHECK-LABEL: name: ctlz_v2s16_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C]] ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C3]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[CTLZ1:%[0-9]+]]:_(s32) = G_CTLZ [[AND1]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND1]](s32)
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[CTLZ1]], [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND1]](s32), [[C2]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C3]], [[CTLZ_ZERO_UNDEF1]]
; CHECK: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SELECT1]], [[C]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32)
Show All 10 Linesbody: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: ctlz_s7_s7 ; CHECK-LABEL: name: ctlz_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s32) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 25 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[CTLZ]], [[C1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s32), [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 25
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[C3]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTLZ %1 %2:_(s7) = G_CTLZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: ctlz_s33_s33 name: ctlz_s33_s33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctlz_s33_s33 ; CHECK-LABEL: name: ctlz_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[AND]](s64) ; CHECK: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTLZ_ZERO_UNDEF [[AND]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTLZ]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 31 ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AND]](s64), [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C2]], [[CTLZ_ZERO_UNDEF]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SELECT]](s32)
; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s64) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[ZEXT]](s64)
; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64) ; CHECK: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]] ; CHECK: [[USUBO:%[0-9]+]]:_(s32), [[USUBO1:%[0-9]+]]:_(s1) = G_USUBO [[UV]], [[UV2]]
; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]] ; CHECK: [[USUBE:%[0-9]+]]:_(s32), [[USUBE1:%[0-9]+]]:_(s1) = G_USUBE [[UV1]], [[UV3]], [[USUBO1]]
; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32) ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64) ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64) ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C4]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64) ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0 %1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTLZ %1 %2:_(s33) = G_CTLZ %1
%3:_(s64) = G_ANYEXT %2 %3:_(s64) = G_ANYEXT %2
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...
# ---
# name: ctlz_v2s7_v2s7
# body: |
# bb.0:
# liveins: $vgpr0
# %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
# %1:_(<2 x s7>) = G_TRUNC %0
# %2:_(<2 x s7>) = G_CTLZ %1
# %3:_(<2 x s32>) = G_ANYEXT %2
# $vgpr0_vgpr1 = COPY %3
# ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
--- ---
name: cttz_s32_s32 name: cttz_s32_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: cttz_s32_s32 ; CHECK-LABEL: name: cttz_s32_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: $vgpr0 = COPY [[CTTZ]](s32) ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTTZ %0 %1:_(s32) = G_CTTZ %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: cttz_s32_s64 name: cttz_s32_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_s32_s64 ; CHECK-LABEL: name: cttz_s32_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s64) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
; CHECK: $vgpr0 = COPY [[CTTZ]](s32) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
; CHECK: $vgpr0 = COPY [[SELECT]](s32)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s32) = G_CTTZ %0 %1:_(s32) = G_CTTZ %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: cttz_s64_s64 name: cttz_s64_s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_s64_s64 ; CHECK-LABEL: name: cttz_s64_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s64) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ]](s32) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SELECT]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_CTTZ %0 %1:_(s64) = G_CTTZ %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: cttz_s16_s32 name: cttz_s16_s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: cttz_s16_s32 ; CHECK-LABEL: name: cttz_s16_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[COPY]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; CHECK: $vgpr0 = COPY [[AND]](s32) ; CHECK: $vgpr0 = COPY [[AND]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_CTTZ %0 %1:_(s16) = G_CTTZ %0
%2:_(s32) = G_ZEXT %1 %2:_(s32) = G_ZEXT %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: cttz_s16_s16 name: cttz_s16_s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: cttz_s16_s16 ; CHECK-LABEL: name: cttz_s16_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]]
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[OR]](s32), [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C3]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s16) = G_TRUNC %0 %1:_(s16) = G_TRUNC %0
%2:_(s16) = G_CTTZ %1 %2:_(s16) = G_CTTZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: cttz_v2s32_v2s32 name: cttz_v2s32_v2s32
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_v2s32_v2s32 ; CHECK-LABEL: name: cttz_v2s32_v2s32
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[UV]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s32)
; CHECK: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[UV1]](s32) ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTTZ]](s32), [[CTTZ1]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s32), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s32)
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s32), [[C]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[CTTZ_ZERO_UNDEF1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(<2 x s32>) = G_CTTZ %0 %1:_(<2 x s32>) = G_CTTZ %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: cttz_v2s32_v2s64 name: cttz_v2s32_v2s64
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3 liveins: $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK-LABEL: name: cttz_v2s32_v2s64 ; CHECK-LABEL: name: cttz_v2s32_v2s64
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>) ; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[UV]](s64) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV]](s64)
; CHECK: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[UV1]](s64) ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[CTTZ]](s32), [[CTTZ1]](s32) ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV]](s64), [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C1]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[UV1]](s64)
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[UV1]](s64), [[C]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C1]], [[CTTZ_ZERO_UNDEF1]]
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[SELECT]](s32), [[SELECT1]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) ; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3 %0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
%1:_(<2 x s32>) = G_CTTZ %0 %1:_(<2 x s32>) = G_CTTZ %0
$vgpr0_vgpr1 = COPY %1 $vgpr0_vgpr1 = COPY %1
... ...
--- ---
name: cttz_v2s16_v2s16 name: cttz_v2s16_v2s16
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; CHECK-LABEL: name: cttz_v2s16_v2s16 ; CHECK-LABEL: name: cttz_v2s16_v2s16
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; CHECK: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[BITCAST]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C1]]
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536 ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C2]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C2]]
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[OR]](s32), [[C3]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C4]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C1]]
; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[C2]] ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[C2]]
; CHECK: [[CTTZ1:%[0-9]+]]:_(s32) = G_CTTZ [[OR1]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF1:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR1]](s32)
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[CTTZ1]](s32) ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[OR1]](s32), [[C3]]
; CHECK: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s1), [[C4]], [[CTTZ_ZERO_UNDEF1]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SELECT1]](s32)
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C1]]
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32) ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]] ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C1]]
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32) ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND3]], [[C]](s32)
; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]] ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[SHL]]
; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32) ; CHECK: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR2]](s32)
; CHECK: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; CHECK: $vgpr0 = COPY [[BITCAST1]](<2 x s16>)
Show All 11 Lines bb.0:
; CHECK-LABEL: name: cttz_s7_s7 ; CHECK-LABEL: name: cttz_s7_s7
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 128
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]] ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[C1]]
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s32) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s32)
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[CTTZ]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[OR]](s32), [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C3]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: $vgpr0 = COPY [[AND1]](s32) ; CHECK: $vgpr0 = COPY [[AND1]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s7) = G_TRUNC %0 %1:_(s7) = G_TRUNC %0
%2:_(s7) = G_CTTZ %1 %2:_(s7) = G_CTTZ %1
%3:_(s32) = G_ZEXT %2 %3:_(s32) = G_ZEXT %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: cttz_s33_s33 name: cttz_s33_s33
body: | body: |
bb.0: bb.0:
liveins: $vgpr0_vgpr1 liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_s33_s33 ; CHECK-LABEL: name: cttz_s33_s33
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591 ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934591
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934592 ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8589934592
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]] ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[C1]]
; CHECK: [[CTTZ:%[0-9]+]]:_(s32) = G_CTTZ [[OR]](s64) ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:_(s32) = G_CTTZ_ZERO_UNDEF [[OR]](s64)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[OR]](s64), [[C2]]
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 64
; CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[C3]], [[CTTZ_ZERO_UNDEF]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[SELECT]](s32)
; CHECK: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295
; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64) ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64)
; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64) ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C4]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]]
; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64) ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64)
; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1 %0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s33) = G_TRUNC %0 %1:_(s33) = G_TRUNC %0
%2:_(s33) = G_CTTZ %1 %2:_(s33) = G_CTTZ %1
%3:_(s64) = G_ANYEXT %2 %3:_(s64) = G_ANYEXT %2
$vgpr0_vgpr1 = COPY %3 $vgpr0_vgpr1 = COPY %3
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz.mir

  • This file was deleted.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: ctlz_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: ctlz_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[CTLZ:%[0-9]+]]:sgpr(s32) = G_CTLZ [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_CTLZ %0
...
---
name: ctlz_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: ctlz_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[CTLZ:%[0-9]+]]:vgpr(s32) = G_CTLZ [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTLZ %0
...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz.mir

  • This file was deleted.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: cttz_i32_s
legalized: true
body: |
bb.0:
liveins: $sgpr0
; CHECK-LABEL: name: cttz_i32_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[CTTZ:%[0-9]+]]:sgpr(s32) = G_CTTZ [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_CTTZ %0
...
---
name: cttz_i32_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: cttz_i32_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[CTTZ:%[0-9]+]]:vgpr(s32) = G_CTTZ [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_CTTZ %0
...

llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir

Show All 30 Lines bb.0:
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
; LIBCALLS: ADJCALLSTACKDOWN ; LIBCALLS: ADJCALLSTACKDOWN
; LIBCALLS: $r0 = COPY [[X]] ; LIBCALLS: $r0 = COPY [[X]]
; LIBCALLS: BL &__clzsi2, {{.*}}, implicit $r0, implicit-def $r0 ; LIBCALLS: BL &__clzsi2, {{.*}}, implicit $r0, implicit-def $r0
; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = COPY $r0 ; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = COPY $r0
; LIBCALLS: ADJCALLSTACKUP ; LIBCALLS: ADJCALLSTACKUP
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
; LIBCALLS: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; LIBCALLS: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; LIBCALLS: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; LIBCALLS: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[X]](s32), [[ZERO]] ; LIBCALLS: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[X]](s32), [[ZERO]]
; LIBCALLS: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; LIBCALLS: [[R:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[BITS]], [[COUNT]] ; LIBCALLS: [[R:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[BITS]], [[COUNT]]
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
%1(s32) = G_CTLZ %0 %1(s32) = G_CTLZ %0
; CHECK: $r0 = COPY [[R]] ; CHECK: $r0 = COPY [[R]]
$r0 = COPY %1(s32) $r0 = COPY %1(s32)
BX_RET 14, $noreg, implicit $r0 BX_RET 14, $noreg, implicit $r0
... ...
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines bb.0:
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
; LIBCALLS: ADJCALLSTACKDOWN ; LIBCALLS: ADJCALLSTACKDOWN
; LIBCALLS: $r0 = COPY [[X32]] ; LIBCALLS: $r0 = COPY [[X32]]
; LIBCALLS: BL &__clzsi2, {{.*}}, implicit $r0, implicit-def $r0 ; LIBCALLS: BL &__clzsi2, {{.*}}, implicit $r0, implicit-def $r0
; LIBCALLS: [[UNDEFCOUNT:%[0-9]+]]:_(s32) = COPY $r0 ; LIBCALLS: [[UNDEFCOUNT:%[0-9]+]]:_(s32) = COPY $r0
; LIBCALLS: ADJCALLSTACKUP ; LIBCALLS: ADJCALLSTACKUP
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
; LIBCALLS: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; LIBCALLS: [[ZERO:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; LIBCALLS: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; LIBCALLS: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), [[ZERO]] ; LIBCALLS: [[CMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), {{%[0-9]+}}(s32), [[ZERO]]
; LIBCALLS: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[BITS]], [[UNDEFCOUNT]] ; LIBCALLS: [[COUNT:%[0-9]+]]:_(s32) = G_SELECT [[CMP]](s1), [[BITS]], [[UNDEFCOUNT]]
; LIBCALLS-NOT: G_CTLZ ; LIBCALLS-NOT: G_CTLZ
; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; CHECK: [[BITDIFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]] ; CHECK: [[R32:%[0-9]+]]:_(s32) = G_SUB [[COUNT]], [[BITDIFF]]
%2(s16) = G_CTLZ %1 %2(s16) = G_CTLZ %1
; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]] ; CHECK: [[RAGAIN:%[0-9]+]]:_(s32) = COPY [[R32]]
; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]] ; CHECK: [[SHIFTEDR:%[0-9]+]]:_(s32) = G_SHL [[RAGAIN]], [[BITDIFF]]
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir