[ARM][ASMParser] Refuse equal RdHi/RdLo for s/umlal, smlsl, s/umull, umaal

[DavidSpickett]

llvm/test/MC/ARM/equal-rdhi-rdlo-diagnostics.s

7

Label not needed.

[ostannard]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

7978

You should just be able to compare RdHi and RdLo directly here, none of these registers have any sub-registers. Doing it this was doesn't really make sense, because isSubRegisterEq is an asymmetric operation.

llvm/test/MC/ARM/equal-rdhi-rdlo-diagnostics.s

3

You can redirect the stderr of the llvm-mc command to stdout with 2>&1, and pipe it into FIleCheck without needing a temporary file.

9

It's better to include the line number (using @LINE) of the error message in the check line, so that if one of these fails FileCheck will point to the failing one. The other test in this patch (v8_IT_manual.s) is a good example.

[Pierre-vh]

I've updated the patch in accordance with your comments

[ostannard]

LGTM

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool ARMAsmParser::validateInstruction(MCInst &Inst,
   case ARM::MVE_VMOV_q_rr: {
     if (Operands[2]->getReg() != Operands[4]->getReg())
       return Error (Operands[2]->getStartLoc(), "Q-registers must be the same");
     if (static_cast<ARMOperand &>(*Operands[3]).getVectorIndex() !=
         static_cast<ARMOperand &>(*Operands[5]).getVectorIndex() + 2)
       return Error (Operands[3]->getStartLoc(), "Q-register indexes must be 2 and 0 or 3 and 1");
     break;
   }
+  case ARM::UMAAL:
+  case ARM::UMLAL:
+  case ARM::UMULL:
+  case ARM::t2UMAAL:
+  case ARM::t2UMLAL:
+  case ARM::t2UMULL:
+  case ARM::SMLAL:
+  case ARM::SMLALBB:
+  case ARM::SMLALBT:
+  case ARM::SMLALD:
+  case ARM::SMLALDX:
+  case ARM::SMLALTB:
+  case ARM::SMLALTT:
+  case ARM::SMLSLD:
+  case ARM::SMLSLDX:
+  case ARM::SMULL:
+  case ARM::t2SMLAL:
+  case ARM::t2SMLALBB:
+  case ARM::t2SMLALBT:
+  case ARM::t2SMLALD:
+  case ARM::t2SMLALDX:
+  case ARM::t2SMLALTB:
+  case ARM::t2SMLALTT:
+  case ARM::t2SMLSLD:
+  case ARM::t2SMLSLDX:
+  case ARM::t2SMULL: {
+    unsigned RdHi = Inst.getOperand(0).getReg();
+    unsigned RdLo = Inst.getOperand(1).getReg();
+    if(RdHi == RdLo) {
+      return Error(Loc,
+                   "unpredictable instruction, RdHi and RdLo must be different");
+    }
+    break;
+  }
   }
 
   return false;
 }
 
 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
   switch(Opc) {
   default: llvm_unreachable("unexpected opcode!");

llvm/test/MC/ARM/equal-rdhi-rdlo-diagnostics.s

+@ RUN: not llvm-mc -triple thumbv7m-eabi -mattr=+dsp < %s 2>&1 | FileCheck %s
+@ RUN: not llvm-mc -triple armv8 -mattr=+dsp < %s 2>&1 | FileCheck %s
+
+  smlal   r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlalbb   r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlalbt   r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlaltb   r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlaltt   r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlald   r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlaldx   r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlsld  r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smlsldx  r1, r1, r3, r4
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  smull   r1, r1, r2, r3
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  umull   r1, r1, r2, r3
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  umlal   r1, r1, r2, r3
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different
+  umaal   r1, r1, r2, r3
+@ CHECK: [[@LINE-1]]:{{[0-9]+}}: error: unpredictable instruction, RdHi and RdLo must be different

llvm/test/MC/ARM/v8_IT_manual.s

 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
 mlage r0, r12, r0, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
 mlage r0, lr, r0, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r0, r0
+smullge r0, r1, r0, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r1, r0
+smullge r0, r1, r1, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r2, r0
+smullge r0, r1, r2, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r3, r0
+smullge r0, r1, r3, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r4, r0
+smullge r0, r1, r4, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r5, r0
+smullge r0, r1, r5, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r6, r0
+smullge r0, r1, r6, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r7, r0
+smullge r0, r1, r7, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r8, r0
+smullge r0, r1, r8, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r9, r0
+smullge r0, r1, r9, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r10, r0
+smullge r0, r1, r10, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r11, r0
+smullge r0, r1, r11, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, r12, r0
+smullge r0, r1, r12, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smullge r0, r0, lr, r0
+smullge r0, r1, lr, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r0, r0
+umullge r0, r1, r0, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r1, r0
+umullge r0, r1, r1, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r2, r0
+umullge r0, r1, r2, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r3, r0
+umullge r0, r1, r3, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r4, r0
+umullge r0, r1, r4, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r5, r0
+umullge r0, r1, r5, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r6, r0
+umullge r0, r1, r6, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r7, r0
+umullge r0, r1, r7, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r8, r0
+umullge r0, r1, r8, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r9, r0
+umullge r0, r1, r9, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r10, r0
+umullge r0, r1, r10, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r11, r0
+umullge r0, r1, r11, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, r12, r0
+umullge r0, r1, r12, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umullge r0, r0, lr, r0
+umullge r0, r1, lr, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r0, r0
+smlalge r0, r1, r0, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r1, r0
+smlalge r0, r1, r1, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r2, r0
+smlalge r0, r1, r2, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r3, r0
+smlalge r0, r1, r3, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r4, r0
+smlalge r0, r1, r4, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r5, r0
+smlalge r0, r1, r5, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r6, r0
+smlalge r0, r1, r6, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r7, r0
+smlalge r0, r1, r7, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r8, r0
+smlalge r0, r1, r8, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r9, r0
+smlalge r0, r1, r9, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r10, r0
+smlalge r0, r1, r10, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r11, r0
+smlalge r0, r1, r11, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, r12, r0
+smlalge r0, r1, r12, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-smlalge r0, r0, lr, r0
+smlalge r0, r1, lr, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r0, r0
+umlalge r0, r1, r0, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r1, r0
+umlalge r0, r1, r1, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r2, r0
+umlalge r0, r1, r2, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r3, r0
+umlalge r0, r1, r3, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r4, r0
+umlalge r0, r1, r4, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r5, r0
+umlalge r0, r1, r5, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r6, r0
+umlalge r0, r1, r6, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r7, r0
+umlalge r0, r1, r7, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r8, r0
+umlalge r0, r1, r8, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r9, r0
+umlalge r0, r1, r9, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r10, r0
+umlalge r0, r1, r10, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r11, r0
+umlalge r0, r1, r11, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, r12, r0
+umlalge r0, r1, r12, r0
 @ CHECK: :[[@LINE+2]]:1: warning: deprecated instruction in IT block
 it ge
-umlalge r0, r0, lr, r0
+umlalge r0, r1, lr, r0