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Differential D73774

[VE] (fp)trunc+store & load+(fp)ext isel
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Authored by simoll on Jan 31 2020, 3:49 AM.

Details

Reviewers
arsenm
craig.topper
rengolin
k-ishizaka
Commits
rGbe9fe6aa8bd5: [VE] (fp)trunc+store & load+(fp)ext isel
Summary

load+sext/zext/fpext and (fp)trunc+store isel legalization and tests

Diff Detail

Event Timeline

simoll created this revision.Jan 31 2020, 3:49 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 31 2020, 3:49 AM
Herald added subscribers: llvm-commits, hiraditya, wdng. · View Herald Transcript
simoll edited the summary of this revision. (Show Details)Jan 31 2020, 3:49 AM
merge_guards_bot added a subscriber: merge_guards_bot.Jan 31 2020, 4:10 AM

Unit tests: pass. 62358 tests passed, 0 failed and 842 were skipped.

clang-tidy: fail. clang-tidy found 1 errors and 0 warnings. 0 of them are added as review comments below (why?).

clang-format: pass.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.

Harbormaster failed remote builds in B45430: Diff 241677!Jan 31 2020, 4:13 AM
arsenm added inline comments.Jan 31 2020, 8:09 AM
llvm/test/CodeGen/VE/fp_extload_truncstore.ll
23

Might as well check the combination with half too

simoll marked an inline comment as done.Feb 3 2020, 1:41 AM
simoll added inline comments.
llvm/test/CodeGen/VE/fp_extload_truncstore.ll
23

Half conversion will require external function calls first since half conversion will be expanded for the VE.

arsenm accepted this revision.Feb 3 2020, 7:19 AM
This revision is now accepted and ready to land.Feb 3 2020, 7:19 AM
Closed by commit rGbe9fe6aa8bd5: [VE] (fp)trunc+store & load+(fp)ext isel (authored by kaz7, committed by simoll). · Explain WhyFeb 3 2020, 8:11 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
VE/
19 lines
test/
CodeGen/
VE/
23 lines
360 lines
74 lines

Diff 241677

llvm/lib/Target/VE/VEISelLowering.cpp

Show First 20 Lines • Show All 491 Lines • ▼ Show 20 LinesVETargetLowering::VETargetLowering(const TargetMachine &TM,
setBooleanVectorContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent);
// Set up the register classes. // Set up the register classes.
addRegisterClass(MVT::i32, &VE::I32RegClass); addRegisterClass(MVT::i32, &VE::I32RegClass);
addRegisterClass(MVT::i64, &VE::I64RegClass); addRegisterClass(MVT::i64, &VE::I64RegClass);
addRegisterClass(MVT::f32, &VE::F32RegClass); addRegisterClass(MVT::f32, &VE::F32RegClass);
addRegisterClass(MVT::f64, &VE::I64RegClass); addRegisterClass(MVT::f64, &VE::I64RegClass);
/// Load & Store {
// Turn FP extload into load/fpextend
for (MVT VT : MVT::fp_valuetypes()) {
setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
}
// VE doesn't have i1 sign extending load
for (MVT VT : MVT::integer_valuetypes()) {
setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
setTruncStoreAction(VT, MVT::i1, Expand);
}
// Turn FP truncstore into trunc + store.
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
/// } Load & Store
// Custom legalize address nodes into LO/HI parts. // Custom legalize address nodes into LO/HI parts.
MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
setOperationAction(ISD::BlockAddress, PtrVT, Custom); setOperationAction(ISD::BlockAddress, PtrVT, Custom);
setOperationAction(ISD::GlobalAddress, PtrVT, Custom); setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
// VE has no REM or DIVREM operations. // VE has no REM or DIVREM operations.
for (MVT IntVT : MVT::integer_valuetypes()) { for (MVT IntVT : MVT::integer_valuetypes()) {
setOperationAction(ISD::UREM, IntVT, Expand); setOperationAction(ISD::UREM, IntVT, Expand);
▲ Show 20 Lines • Show All 110 Lines • Show Last 20 Lines

llvm/test/CodeGen/VE/fp_extload_truncstore.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define double @func_fp32fp64(float* %a) {
; CHECK-LABEL: func_fp32fp64:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ldu %s0, (,%s0)
; CHECK-NEXT: cvt.d.s %s0, %s0
; CHECK-NEXT: or %s11, 0, %s9
%a.val = load float, float* %a, align 4
%a.asd = fpext float %a.val to double
ret double %a.asd
}
define void @func_fp64fp32(float* %fl.ptr, double %val) {
; CHECK-LABEL: func_fp64fp32:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: cvt.s.d %s1, %s1
; CHECK-NEXT: stu %s1, (,%s0)
; CHECK-NEXT: or %s11, 0, %s9
%val.asf = fptrunc double %val to float
store float %val.asf, float* %fl.ptr
ret void
}
arsenmUnsubmitted
Not Done
ReplyInline Actions

Might as well check the combination with half too

arsenm: Might as well check the combination with half too
simollAuthorUnsubmitted
Done
ReplyInline Actions

Half conversion will require external function calls first since half conversion will be expanded for the VE.

simoll: Half conversion will require external function calls first since half conversion will be…

llvm/test/CodeGen/VE/sext_zext_load.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define signext i16 @func1() {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.sx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = sext i8 %a.val to i16
ret i16 %a.conv
}
define i32 @func2() {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.sx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = sext i8 %a.val to i32
ret i32 %a.conv
}
define i64 @func3() {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.sx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = sext i8 %a.val to i64
ret i64 %a.conv
}
define zeroext i16 @func5() {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.sx %s0, 191(,%s11)
; CHECK-NEXT: and %s0, %s0, (48)0
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = sext i8 %a.val to i16
ret i16 %a.conv
}
define i32 @func6() {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.sx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = sext i8 %a.val to i32
ret i32 %a.conv
}
define i64 @func7() {
; CHECK-LABEL: func7:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.sx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = sext i8 %a.val to i64
ret i64 %a.conv
}
define signext i16 @func9() {
; CHECK-LABEL: func9:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = zext i8 %a.val to i16
ret i16 %a.conv
}
define i32 @func10() {
; CHECK-LABEL: func10:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = zext i8 %a.val to i32
ret i32 %a.conv
}
define i64 @func11() {
; CHECK-LABEL: func11:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = zext i8 %a.val to i64
ret i64 %a.conv
}
define zeroext i16 @func13() {
; CHECK-LABEL: func13:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = zext i8 %a.val to i16
ret i16 %a.conv
}
define zeroext i16 @func14() {
; CHECK-LABEL: func14:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = zext i8 %a.val to i16
ret i16 %a.conv
}
define i64 @func15() {
; CHECK-LABEL: func15:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i8, align 1
%a.val = load i8, i8* %a, align 1
%a.conv = zext i8 %a.val to i64
ret i64 %a.conv
}
define i32 @func17() {
; CHECK-LABEL: func17:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.sx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.val = load i16, i16* %a, align 2
%a.conv = sext i16 %a.val to i32
ret i32 %a.conv
}
define i64 @func18() {
; CHECK-LABEL: func18:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.sx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.val = load i16, i16* %a, align 2
%a.conv = sext i16 %a.val to i64
ret i64 %a.conv
}
define zeroext i16 @func20() {
; CHECK-LABEL: func20:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.zx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.conv = load i16, i16* %a, align 2
ret i16 %a.conv
}
define i64 @func21() {
; CHECK-LABEL: func21:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.sx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.val = load i16, i16* %a, align 2
%a.conv = sext i16 %a.val to i64
ret i64 %a.conv
}
define i32 @func23() {
; CHECK-LABEL: func23:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.zx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.val = load i16, i16* %a, align 2
%a.conv = zext i16 %a.val to i32
ret i32 %a.conv
}
define i64 @func24() {
; CHECK-LABEL: func24:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.zx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.val = load i16, i16* %a, align 2
%a.conv = zext i16 %a.val to i64
ret i64 %a.conv
}
define zeroext i16 @func26() {
; CHECK-LABEL: func26:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.zx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.conv = load i16, i16* %a, align 2
ret i16 %a.conv
}
define i64 @func27() {
; CHECK-LABEL: func27:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld2b.zx %s0, 190(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i16, align 2
%a.val = load i16, i16* %a, align 2
%a.conv = zext i16 %a.val to i64
ret i64 %a.conv
}
define i64 @func29() {
; CHECK-LABEL: func29:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ldl.sx %s0, 188(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i32, align 4
%a.val = load i32, i32* %a, align 4
%a.conv = sext i32 %a.val to i64
ret i64 %a.conv
}
define i64 @func31() {
; CHECK-LABEL: func31:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ldl.sx %s0, 188(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i32, align 4
%a.val = load i32, i32* %a, align 4
%a.conv = sext i32 %a.val to i64
ret i64 %a.conv
}
define i64 @func33() {
; CHECK-LABEL: func33:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ldl.zx %s0, 188(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i32, align 4
%a.val = load i32, i32* %a, align 4
%a.conv = zext i32 %a.val to i64
ret i64 %a.conv
}
define i64 @func35() {
; CHECK-LABEL: func35:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ldl.zx %s0, 188(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i32, align 4
%a.val = load i32, i32* %a, align 4
%a.conv = zext i32 %a.val to i64
ret i64 %a.conv
}
define signext i8 @func37() {
; CHECK-LABEL: func37:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: sra.w.sx %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = sext i1 %a.val to i8
ret i8 %a.conv
}
define signext i16 @func38() {
; CHECK-LABEL: func38:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: sra.w.sx %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = sext i1 %a.val to i16
ret i16 %a.conv
}
define signext i32 @func39() {
; CHECK-LABEL: func39:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: sla.w.sx %s0, %s0, 31
; CHECK-NEXT: sra.w.sx %s0, %s0, 31
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = sext i1 %a.val to i32
ret i32 %a.conv
}
define signext i64 @func40() {
; CHECK-LABEL: func40:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: sll %s0, %s0, 63
; CHECK-NEXT: sra.l %s0, %s0, 63
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = sext i1 %a.val to i64
ret i64 %a.conv
}
define signext i8 @func42() {
; CHECK-LABEL: func42:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = zext i1 %a.val to i8
ret i8 %a.conv
}
define signext i16 @func43() {
; CHECK-LABEL: func43:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = zext i1 %a.val to i16
ret i16 %a.conv
}
define signext i32 @func44() {
; CHECK-LABEL: func44:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = zext i1 %a.val to i32
ret i32 %a.conv
}
define signext i64 @func45() {
; CHECK-LABEL: func45:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: ld1b.zx %s0, 191(,%s11)
; CHECK-NEXT: or %s11, 0, %s9
%a = alloca i1, align 1
%a.val = load i1, i1* %a, align 1
%a.conv = zext i1 %a.val to i64
ret i64 %a.conv
}

llvm/test/CodeGen/VE/truncstore.ll

  • This file was added.
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
define void @func0(i1 signext %p, i8* %a) {
; CHECK-LABEL: func0:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st1b %s0, (,%s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i1 %p to i8
store i8 %p.conv, i8* %a, align 2
ret void
}
define void @func1(i8 signext %p, i16* %a) {
; CHECK-LABEL: func1:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: st2b %s0, (,%s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i8 %p to i16
store i16 %p.conv, i16* %a, align 2
ret void
}
define void @func2(i8 signext %p, i32* %a) {
; CHECK-LABEL: func2:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: stl %s0, (,%s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i8 %p to i32
store i32 %p.conv, i32* %a, align 4
ret void
}
define void @func3(i8 signext %p, i64* %a) {
; CHECK-LABEL: func3:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: st %s0, (,%s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i8 %p to i64
store i64 %p.conv, i64* %a, align 8
ret void
}
define void @func5(i16 signext %p, i32* %a) {
; CHECK-LABEL: func5:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: stl %s0, (,%s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i16 %p to i32
store i32 %p.conv, i32* %a, align 4
ret void
}
define void @func6(i16 signext %p, i64* %a) {
; CHECK-LABEL: func6:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: st %s0, (,%s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i16 %p to i64
store i64 %p.conv, i64* %a, align 8
ret void
}
define void @func8(i32 %p, i64* %a) {
; CHECK-LABEL: func8:
; CHECK: .LBB{{[0-9]+}}_2:
; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1
; CHECK-NEXT: st %s0, (,%s1)
; CHECK-NEXT: or %s11, 0, %s9
%p.conv = sext i32 %p to i64
store i64 %p.conv, i64* %a, align 8
ret void
}