[InstCombine] Process newly inserted instructions in the correct order

[nikic]

Summary

InstCombine operates on the basic premise that the operands of the currently processed instruction have already been simplified. It achieves this by pushing instructions to the worklist in reverse program order, so that instructions are popped off in program order. The worklist management in the main combining loop also makes sure to uphold this invariant.

However, the same is not true for all the code that is performing manual worklist management. The largest problem (addressed in this patch) are instructions inserted by InstCombine's IRBuilder. These will be pushed onto the worklist in order of insertion (generally matching program order), which means that a) the users of the original instruction will be visited first, as they are pushed later in the main loop and b) the newly inserted instructions will be visited in reverse program order.

This causes a number of problems: First, folds operate on instructions that have not had their operands simplified, which may result in optimizations being missed (ran into this in https://reviews.llvm.org/D72048#1800424, which was the original motivation for this patch). Additionally, this increases the amount of folds InstCombine has to perform, both within one iteration, and by increasing the number of total iterations.

This patch addresses the issue by adding a Worklist.AddDeferred() method, which is used for instructions inserted by IRBuilder. These will only be added to the real worklist after the combine finished, and in reverse order, so they will end up processed in program order. I should note that the same should also be done to nearly all other uses of Worklist.Add(), but I'm starting with just this occurrence, which has by far the largest test fallout.

Most of the test changes are due to https://bugs.llvm.org/show_bug.cgi?id=44521 or other cases where we don't canonicalize something. These are neutral. There are also a couple of regressions that I will highlight in comments...

[nikic]

llvm/test/Transforms/InstCombine/div.ll

403

Here (a shl nsw 31) sdiv INT_MIN is folded to zext ((a shl nsw 31) == INT_MIN). Previously the zext was visited first and this was folded to and. Now the comparison is visited first, which is folded to a == -1. At that point, the zext cannot be folded to and anymore, because we've lost information.

I don't think we can really do anything about this, unless we want to drop the equality fold, which I don't think we want. The new IR also doesn't look particularly bad, depending on how the result is going to be used.

llvm/test/Transforms/InstCombine/getelementptr.ll

222

This issue is tracked at https://bugs.llvm.org/show_bug.cgi?id=44588. I got the impression that @spatel is planning to work on this at some point, but if desired I can also look into fixing this regression first.

[spatel]

llvm/test/Transforms/InstCombine/getelementptr.ll

222

I took a look at that, and I think we need an analysis enhancement first:
D73549

[nikic]

Rebase over D73575.

[nikic]

Rebase over D73647.

[nikic]

llvm/test/Transforms/InstCombine/getelementptr.ll

222

D73575 and D73647 have addressed this regression. We now get a marginally better result here.

[lebedev.ri]

I agree test changes look harmless now.
The internal changes seem good, but please wait for more review.

[spatel]

LGTM

llvm/include/llvm/Transforms/InstCombine/InstCombineWorklist.h

30

typo: combined -> combine

59

Could take this opportunity to correct all of the ill-formatted 'FunctionNames' to 'functionNames'.

[nikic]

llvm/include/llvm/Transforms/InstCombine/InstCombineWorklist.h

59

I was planning to do a mass rename of the various Add methods, I'll roll the style change into that one.

[maxim-kuvyrkov]

Hi Nikita,

This patch regresses one of the top-3 hot functions in 444.namd (from SPEC CPU2006). It slows down that function by 23% (from 94 seconds to 116 seconds) and increases its code size by 13% (from 2588 bytes to 2920 bytes). This happens at -Oz on aarch64-linux-gnu. Since this happens at -Oz, code size regression is more interesting than the performance regression.

Would you please check if _ZN20ComputeNonbondedUtil16calc_pair_energyEP9no hits a corner case or something? And whether this can be avoided?

444.namd,[.] _ZN20ComputeNonbondedUtil26calc_pair_energy_full,100,101,1417,1422,4120,4156
444.namd,[.] _ZN20ComputeNonbondedUtil19calc_pair_fullelectEP,101,100,1232,1240,3588,3576
444.namd,[.] _ZN20ComputeNonbondedUtil16calc_pair_energyEP9no,123,113,941,1158,2588,2920

Let me know if you need help reproducing this. I have linux perf profiles, preprocessed source and compiled assembly handy.

Thanks!

[nikic]

@maxim-kuvyrkov: Thanks for the report. Having the preprocessed source would be great. If you have an idea which part of the generated assembly could be related to the slowdown, that would of course be great to know as well.

Regressions from this change are not entirely unexpected, as it may expose missing folds that previously worked "by accident".

llvm/include/llvm/Transforms/InstCombine/InstCombineWorklist.h

 
 namespace llvm {
 
 /// InstCombineWorklist - This is the worklist management logic for
 /// InstCombine.
 class InstCombineWorklist {
   SmallVector<Instruction *, 256> Worklist;
   DenseMap<Instruction *, unsigned> WorklistMap;
+  /// These instructions will be added in reverse order after the current
+  /// combined has finished. This means that these instructions will be visited
+  /// in the order they have been added.
+  SmallSetVector<Instruction *, 16> Deferred;
 
 public:
   InstCombineWorklist() = default;
 
   InstCombineWorklist(InstCombineWorklist &&) = default;
   InstCombineWorklist &operator=(InstCombineWorklist &&) = default;
 
   bool isEmpty() const { return Worklist.empty(); }
void Add(Instruction *I) {
     }
   }
 
   void AddValue(Value *V) {
     if (Instruction *I = dyn_cast<Instruction>(V))
       Add(I);
   }
 
+  void AddDeferred(Instruction *I) {
+    if (Deferred.insert(I))
+      LLVM_DEBUG(dbgs() << "IC: ADD DEFERRED: " << *I << '\n');
+  }
+
+  void AddDeferredInstructions() {
+    for (Instruction *I : reverse(Deferred))
+      Add(I);
+    Deferred.clear();
+  }
+
   /// AddInitialGroup - Add the specified batch of stuff in reverse order.
   /// which should only be done when the worklist is empty and when the group
   /// has no duplicates.
   void AddInitialGroup(ArrayRef<Instruction *> List) {
     assert(Worklist.empty() && "Worklist must be empty to add initial group");
     Worklist.reserve(List.size()+16);
     WorklistMap.reserve(List.size());
     LLVM_DEBUG(dbgs() << "IC: ADDING: " << List.size()
public:
   void Remove(Instruction *I) {
     DenseMap<Instruction*, unsigned>::iterator It = WorklistMap.find(I);
     if (It == WorklistMap.end()) return; // Not in worklist.
 
     // Don't bother moving everything down, just null out the slot.
     Worklist[It->second] = nullptr;
 
     WorklistMap.erase(It);
+    Deferred.remove(I);
   }
 
   Instruction *RemoveOne() {
     Instruction *I = Worklist.pop_back_val();
     WorklistMap.erase(I);
     return I;
   }
 
   /// AddUsersToWorkList - When an instruction is simplified, add all users of
   /// the instruction to the work lists because they might get more simplified
   /// now.
   ///
   void AddUsersToWorkList(Instruction &I) {
     for (User *U : I.users())
       Add(cast<Instruction>(U));
   }
 
 
   /// Zap - check that the worklist is empty and nuke the backing store for
   /// the map if it is large.
   void Zap() {
     assert(WorklistMap.empty() && "Worklist empty, but map not?");
+    assert(Deferred.empty() && "Deferred instructions left over");
 
     // Do an explicit clear, this shrinks the map if needed.
     WorklistMap.clear();
   }
 };
 
 } // end namespace llvm.
 
 #undef DEBUG_TYPE
 
 #endif

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

if (Instruction *Result = visit(*I)) {
           eraseInstFromFunction(*I);
         } else {
           Worklist.AddUsersToWorkList(*I);
           Worklist.Add(I);
         }
       }
       MadeIRChange = true;
     }
+    Worklist.AddDeferredInstructions();
   }
 
   Worklist.Zap();
   return MadeIRChange;
 }
 
 /// Walk the function in depth-first order, adding all reachable code to the
 /// worklist.
if (EnableExpensiveCombines.getNumOccurrences())
     ExpensiveCombines = EnableExpensiveCombines;
   MaxIterations = std::min(MaxIterations, LimitMaxIterations.getValue());
 
   /// Builder - This is an IRBuilder that automatically inserts new
   /// instructions into the worklist when they are created.
   IRBuilder<TargetFolder, IRBuilderCallbackInserter> Builder(
       F.getContext(), TargetFolder(DL),
       IRBuilderCallbackInserter([&Worklist, &AC](Instruction *I) {
-        Worklist.Add(I);
+        Worklist.AddDeferred(I);
         if (match(I, m_Intrinsic<Intrinsic::assume>()))
           AC.registerAssumption(cast<CallInst>(I));
       }));
 
   // Lower dbg.declare intrinsics otherwise their value may be clobbered
   // by instcombiner.
   bool MadeIRChange = false;
   if (ShouldLowerDbgDeclare)

llvm/test/Transforms/InstCombine/canonicalize-clamp-like-pattern-between-negative-and-positive-thresholds.ll

 ; Basic pattern. There is no 'and', so lower threshold is 0 (inclusive).
 ; The upper threshold is 127 (inclusive).
 ; There are 2 icmp's so for scalars there are 4 possible combinations.
 ; The constant in %t0 has to be between the thresholds, i.e 128 <= Ct0 <= 0.
 
 define i32 @t0_ult_slt_128(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t0_ult_slt_128(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 128
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = add i32 %x, 16
   %t3 = icmp ult i32 %t2, 144
   %r = select i1 %t3, i32 %x, i32 %t1
   ret i32 %r
 }
 define i32 @t1_ult_slt_0(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t1_ult_slt_0(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, -16
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = add i32 %x, 16
   %t3 = icmp ult i32 %t2, 144
   %r = select i1 %t3, i32 %x, i32 %t1
   ret i32 %r
 }
 
 define i32 @t2_ult_sgt_128(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t2_ult_sgt_128(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, 127
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = add i32 %x, 16
   %t3 = icmp ult i32 %t2, 144
   %r = select i1 %t3, i32 %x, i32 %t1
   ret i32 %r
 }
 define i32 @t3_ult_sgt_neg1(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t3_ult_sgt_neg1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, -17
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = add i32 %x, 16
   %t3 = icmp ult i32 %t2, 144
   %r = select i1 %t3, i32 %x, i32 %t1
   ret i32 %r
 }
 
 define i32 @t4_ugt_slt_128(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t4_ugt_slt_128(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 128
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = add i32 %x, 16
   %t3 = icmp ugt i32 %t2, 143
   %r = select i1 %t3, i32 %t1, i32 %x
   ret i32 %r
 }
 define i32 @t5_ugt_slt_0(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t5_ugt_slt_0(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, -16
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = add i32 %x, 16
   %t3 = icmp ugt i32 %t2, 143
   %r = select i1 %t3, i32 %t1, i32 %x
   ret i32 %r
 }
 
 define i32 @t6_ugt_sgt_128(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t6_ugt_sgt_128(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, 127
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = add i32 %x, 16
   %t3 = icmp ugt i32 %t2, 143
   %r = select i1 %t3, i32 %t1, i32 %x
   ret i32 %r
 }
 define i32 @t7_ugt_sgt_neg1(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t7_ugt_sgt_neg1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, -17
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = add i32 %x, 16
   %t3 = icmp ugt i32 %t2, 143
   %r = select i1 %t3, i32 %t1, i32 %x
   ret i32 %r

 ; FIXME: if %t0 could be reused then it's less restrictive.
 
 ; This one is ok.
 define i32 @t10_oneuse0(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t10_oneuse0(
 ; CHECK-NEXT:    [[T0:%.*]] = icmp slt i32 [[X:%.*]], 64
 ; CHECK-NEXT:    call void @use1(i1 [[T0]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 64
   call void @use1(i1 %t0)
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = add i32 %x, 16
   %t3 = icmp ult i32 %t2, 144
   %r = select i1 %t3, i32 %x, i32 %t1

 }
 
 ; This one is ok.
 define i32 @t12_oneuse2(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t12_oneuse2(
 ; CHECK-NEXT:    [[T2:%.*]] = add i32 [[X:%.*]], 16
 ; CHECK-NEXT:    call void @use32(i32 [[T2]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X]], -16
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 128
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 127
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 64
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = add i32 %x, 16
   call void @use32(i32 %t2)
   %t3 = icmp ult i32 %t2, 144
   %r = select i1 %t3, i32 %x, i32 %t1

 
 ;-------------------------------------------------------------------------------
 
 ; Vectors
 
 define <2 x i32> @t20_ult_slt_vec_splat(<2 x i32> %x, <2 x i32> %replacement_low, <2 x i32> %replacement_high) {
 ; CHECK-LABEL: @t20_ult_slt_vec_splat(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 -16, i32 -16>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> [[X]], <i32 128, i32 128>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i32> [[X]], <i32 127, i32 127>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[REPLACEMENT_LOW:%.*]], <2 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[REPLACEMENT_HIGH:%.*]], <2 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %t0 = icmp slt <2 x i32> %x, <i32 128, i32 128>
   %t1 = select <2 x i1> %t0, <2 x i32> %replacement_low, <2 x i32> %replacement_high
   %t2 = add <2 x i32> %x, <i32 16, i32 16>
   %t3 = icmp ult <2 x i32> %t2, <i32 144, i32 144>
   %r = select <2 x i1> %t3, <2 x i32> %x, <2 x i32> %t1
   ret <2 x i32> %r
 }
 define <2 x i32> @t21_ult_slt_vec_nonsplat(<2 x i32> %x, <2 x i32> %replacement_low, <2 x i32> %replacement_high) {
 ; CHECK-LABEL: @t21_ult_slt_vec_nonsplat(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], <i32 -16, i32 -8>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> [[X]], <i32 128, i32 256>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i32> [[X]], <i32 127, i32 255>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[REPLACEMENT_LOW:%.*]], <2 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[REPLACEMENT_HIGH:%.*]], <2 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %t0 = icmp slt <2 x i32> %x, <i32 128, i32 64>
   %t1 = select <2 x i1> %t0, <2 x i32> %replacement_low, <2 x i32> %replacement_high
   %t2 = add <2 x i32> %x, <i32 16, i32 8>
   %t3 = icmp ult <2 x i32> %t2, <i32 144, i32 264>
   %r = select <2 x i1> %t3, <2 x i32> %x, <2 x i32> %t1
   ret <2 x i32> %r
;
   ret <2 x i32> %r
 }
 
 define <2 x i32> @t23_ult_sge(<2 x i32> %x, <2 x i32> %replacement_low, <2 x i32> %replacement_high) {
 ; CHECK-LABEL: @t23_ult_sge(
 ; CHECK-NEXT:    [[T0:%.*]] = icmp sge <2 x i32> [[X:%.*]], <i32 128, i32 -2147483648>
 ; CHECK-NEXT:    call void @use2xi1(<2 x i1> [[T0]])
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[X]], <i32 -16, i32 -2147483648>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> [[X]], <i32 128, i32 2147483647>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i32> [[X]], <i32 127, i32 2147483646>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[REPLACEMENT_LOW:%.*]], <2 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[REPLACEMENT_HIGH:%.*]], <2 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %t0 = icmp sge <2 x i32> %x, <i32 128, i32 -2147483648>
   call void @use2xi1(<2 x i1> %t0)
   %t1 = select <2 x i1> %t0, <2 x i32> %replacement_high, <2 x i32> %replacement_low
   %t2 = add <2 x i32> %x, <i32 16, i32 -2147483648>
   %t3 = icmp ult <2 x i32> %t2, <i32 144, i32 -1>
   %r = select <2 x i1> %t3, <2 x i32> %x, <2 x i32> %t1
   ret <2 x i32> %r
 }

llvm/test/Transforms/InstCombine/canonicalize-clamp-like-pattern-between-zero-and-positive-threshold.ll

 ; Basic pattern. There is no 'and', so lower threshold is 0 (inclusive).
 ; The upper threshold is 65535 (inclusive).
 ; There are 2 icmp's so for scalars there are 4 possible combinations.
 ; The constant in %t0 has to be between the thresholds, i.e 65536 <= Ct0 <= 0.
 
 define i32 @t0_ult_slt_65536(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t0_ult_slt_65536(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 65536
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = icmp ult i32 %x, 65536
   %r = select i1 %t2, i32 %x, i32 %t1
   ret i32 %r
 }
 define i32 @t1_ult_slt_0(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t1_ult_slt_0(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 0
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = icmp ult i32 %x, 65536
   %r = select i1 %t2, i32 %x, i32 %t1
   ret i32 %r
 }
 
 define i32 @t2_ult_sgt_65536(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t2_ult_sgt_65536(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, 65535
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = icmp ult i32 %x, 65536
   %r = select i1 %t2, i32 %x, i32 %t1
   ret i32 %r
 }
 define i32 @t3_ult_sgt_neg1(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t3_ult_sgt_neg1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, -1
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = icmp ult i32 %x, 65536
   %r = select i1 %t2, i32 %x, i32 %t1
   ret i32 %r
 }
 
 define i32 @t4_ugt_slt_65536(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t4_ugt_slt_65536(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 65536
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = icmp ugt i32 %x, 65535
   %r = select i1 %t2, i32 %t1, i32 %x
   ret i32 %r
 }
 define i32 @t5_ugt_slt_0(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t5_ugt_slt_0(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp slt i32 %x, 0
   %t1 = select i1 %t0, i32 %replacement_low, i32 %replacement_high
   %t2 = icmp ugt i32 %x, 65535
   %r = select i1 %t2, i32 %t1, i32 %x
   ret i32 %r
 }
 
 define i32 @t6_ugt_sgt_65536(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t6_ugt_sgt_65536(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, 65535
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = icmp ugt i32 %x, 65535
   %r = select i1 %t2, i32 %t1, i32 %x
   ret i32 %r
 }
 define i32 @t7_ugt_sgt_neg1(i32 %x, i32 %replacement_low, i32 %replacement_high) {
 ; CHECK-LABEL: @t7_ugt_sgt_neg1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt i32 [[X]], 65536
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt i32 [[X]], 65535
 ; CHECK-NEXT:    [[TMP3:%.*]] = select i1 [[TMP1]], i32 [[REPLACEMENT_LOW:%.*]], i32 [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[TMP3]], i32 [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select i1 [[TMP2]], i32 [[REPLACEMENT_HIGH:%.*]], i32 [[TMP3]]
 ; CHECK-NEXT:    ret i32 [[R]]
 ;
   %t0 = icmp sgt i32 %x, -1
   %t1 = select i1 %t0, i32 %replacement_high, i32 %replacement_low
   %t2 = icmp ugt i32 %x, 65535
   %r = select i1 %t2, i32 %t1, i32 %x
   ret i32 %r
 }

 
 ;-------------------------------------------------------------------------------
 
 ; Vectors
 
 define <2 x i32> @t17_ult_slt_vec_splat(<2 x i32> %x, <2 x i32> %replacement_low, <2 x i32> %replacement_high) {
 ; CHECK-LABEL: @t17_ult_slt_vec_splat(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> [[X]], <i32 65536, i32 65536>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i32> [[X]], <i32 65535, i32 65535>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[REPLACEMENT_LOW:%.*]], <2 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[REPLACEMENT_HIGH:%.*]], <2 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %t0 = icmp slt <2 x i32> %x, <i32 65536, i32 65536>
   %t1 = select <2 x i1> %t0, <2 x i32> %replacement_low, <2 x i32> %replacement_high
   %t2 = icmp ult <2 x i32> %x, <i32 65536, i32 65536>
   %r = select <2 x i1> %t2, <2 x i32> %x, <2 x i32> %t1
   ret <2 x i32> %r
 }
 define <2 x i32> @t18_ult_slt_vec_nonsplat(<2 x i32> %x, <2 x i32> %replacement_low, <2 x i32> %replacement_high) {
 ; CHECK-LABEL: @t18_ult_slt_vec_nonsplat(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <2 x i32> [[X]], <i32 65536, i32 32768>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <2 x i32> [[X]], <i32 65535, i32 32767>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[REPLACEMENT_LOW:%.*]], <2 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[TMP3]], <2 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <2 x i1> [[TMP2]], <2 x i32> [[REPLACEMENT_HIGH:%.*]], <2 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <2 x i32> [[R]]
 ;
   %t0 = icmp slt <2 x i32> %x, <i32 65536, i32 32768>
   %t1 = select <2 x i1> %t0, <2 x i32> %replacement_low, <2 x i32> %replacement_high
   %t2 = icmp ult <2 x i32> %x, <i32 65536, i32 32768>
   %r = select <2 x i1> %t2, <2 x i32> %x, <2 x i32> %t1
   ret <2 x i32> %r
 }
 
 define <3 x i32> @t19_ult_slt_vec_undef0(<3 x i32> %x, <3 x i32> %replacement_low, <3 x i32> %replacement_high) {
 ; CHECK-LABEL: @t19_ult_slt_vec_undef0(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <3 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <3 x i32> [[X]], <i32 65536, i32 65536, i32 65536>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <3 x i32> [[X]], <i32 65535, i32 65535, i32 65535>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <3 x i1> [[TMP1]], <3 x i32> [[REPLACEMENT_LOW:%.*]], <3 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP2]], <3 x i32> [[TMP3]], <3 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP2]], <3 x i32> [[REPLACEMENT_HIGH:%.*]], <3 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <3 x i32> [[R]]
 ;
   %t0 = icmp slt <3 x i32> %x, <i32 65536, i32 undef, i32 65536>
   %t1 = select <3 x i1> %t0, <3 x i32> %replacement_low, <3 x i32> %replacement_high
   %t2 = icmp ult <3 x i32> %x, <i32 65536, i32 65536, i32 65536>
   %r = select <3 x i1> %t2, <3 x i32> %x, <3 x i32> %t1
   ret <3 x i32> %r
 }
 define <3 x i32> @t20_ult_slt_vec_undef1(<3 x i32> %x, <3 x i32> %replacement_low, <3 x i32> %replacement_high) {
 ; CHECK-LABEL: @t20_ult_slt_vec_undef1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <3 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <3 x i32> [[X]], <i32 65536, i32 undef, i32 65536>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <3 x i32> [[X]], <i32 65535, i32 65535, i32 65535>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <3 x i1> [[TMP1]], <3 x i32> [[REPLACEMENT_LOW:%.*]], <3 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP2]], <3 x i32> [[TMP3]], <3 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP2]], <3 x i32> [[REPLACEMENT_HIGH:%.*]], <3 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <3 x i32> [[R]]
 ;
   %t0 = icmp slt <3 x i32> %x, <i32 65536, i32 65537, i32 65536>
   %t1 = select <3 x i1> %t0, <3 x i32> %replacement_low, <3 x i32> %replacement_high
   %t2 = icmp ult <3 x i32> %x, <i32 65536, i32 undef, i32 65536>
   %r = select <3 x i1> %t2, <3 x i32> %x, <3 x i32> %t1
   ret <3 x i32> %r
 }
 define <3 x i32> @t21_ult_slt_vec_undef2(<3 x i32> %x, <3 x i32> %replacement_low, <3 x i32> %replacement_high) {
 ; CHECK-LABEL: @t21_ult_slt_vec_undef2(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <3 x i32> [[X:%.*]], zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp slt <3 x i32> [[X]], <i32 65536, i32 undef, i32 65536>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp sgt <3 x i32> [[X]], <i32 65535, i32 65535, i32 65535>
 ; CHECK-NEXT:    [[TMP3:%.*]] = select <3 x i1> [[TMP1]], <3 x i32> [[REPLACEMENT_LOW:%.*]], <3 x i32> [[X]]
-; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP2]], <3 x i32> [[TMP3]], <3 x i32> [[REPLACEMENT_HIGH:%.*]]
+; CHECK-NEXT:    [[R:%.*]] = select <3 x i1> [[TMP2]], <3 x i32> [[REPLACEMENT_HIGH:%.*]], <3 x i32> [[TMP3]]
 ; CHECK-NEXT:    ret <3 x i32> [[R]]
 ;
   %t0 = icmp slt <3 x i32> %x, <i32 65536, i32 undef, i32 65536>
   %t1 = select <3 x i1> %t0, <3 x i32> %replacement_low, <3 x i32> %replacement_high
   %t2 = icmp ult <3 x i32> %x, <i32 65536, i32 undef, i32 65536>
   %r = select <3 x i1> %t2, <3 x i32> %x, <3 x i32> %t1
   ret <3 x i32> %r
 }

llvm/test/Transforms/InstCombine/demorgan.ll

;
   %and   = and <2 x i32> %notX, %notY
   ret <2 x i32> %and
 }
 
 define i32 @PR28476(i32 %x, i32 %y) {
 ; CHECK-LABEL: @PR28476(
 ; CHECK-NEXT:    [[CMP0:%.*]] = icmp eq i32 [[X:%.*]], 0
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[Y:%.*]], 0
-; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[CMP1]], [[CMP0]]
+; CHECK-NEXT:    [[TMP1:%.*]] = or i1 [[CMP0]], [[CMP1]]
 ; CHECK-NEXT:    [[COND:%.*]] = zext i1 [[TMP1]] to i32
 ; CHECK-NEXT:    ret i32 [[COND]]
 ;
   %cmp0 = icmp ne i32 %x, 0
   %cmp1 = icmp ne i32 %y, 0
   %and = and i1 %cmp0, %cmp1
   %zext = zext i1 %and to i32
   %cond = xor i32 %zext, 1

llvm/test/Transforms/InstCombine/div.ll

 ;
   %mul = mul nuw i32 %a, 36
   %div = udiv i32 %mul, 3
   ret i32 %div
 }
 
 define i32 @test29(i32 %a) {
 ; CHECK-LABEL: @test29(
-; CHECK-NEXT:    [[MUL_LOBIT:%.*]] = and i32 [[A:%.*]], 1
-; CHECK-NEXT:    ret i32 [[MUL_LOBIT]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp eq i32 [[A:%.*]], -1
+; CHECK-NEXT:    [[DIV:%.*]] = zext i1 [[TMP1]] to i32
+; CHECK-NEXT:    ret i32 [[DIV]]
 ;
   %mul = shl nsw i32 %a, 31
   %div = sdiv i32 %mul, -2147483648
   ret i32 %div
 }
 
 define i32 @test30(i32 %a) {
 ; CHECK-LABEL: @test30(

llvm/test/Transforms/InstCombine/getelementptr.ll

;
   %C = icmp eq <2 x i32*> %A, %B
   ret <2 x i1> %C
 }
 
 define <2 x i1> @test13_vector2(i64 %X, <2 x %S*> %P) nounwind {
 ; CHECK-LABEL: @test13_vector2(
 ; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> undef, i64 [[X:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[DOTSPLATINSERT]], <i64 2, i64 undef>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], <i64 -4, i64 -4>
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], <i64 -4, i64 undef>
 ; CHECK-NEXT:    [[C:%.*]] = shufflevector <2 x i1> [[TMP2]], <2 x i1> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %A = getelementptr inbounds %S, <2 x %S*> %P, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 1>, i64 %X
   %B = getelementptr inbounds %S, <2 x %S*> %P, <2 x i64> <i64 0, i64 0>, <2 x i32> <i32 0, i32 0>
   %C = icmp eq <2 x i32*> %A, %B
   ret <2 x i1> %C
 }
 
 ; This is a test of icmp + shl nuw in disguise - 4611... is 0x3fff...
 define <2 x i1> @test13_vector3(i64 %X, <2 x %S*> %P) nounwind {
 ; CHECK-LABEL: @test13_vector3(
 ; CHECK-NEXT:    [[DOTSPLATINSERT:%.*]] = insertelement <2 x i64> undef, i64 [[X:%.*]], i32 0
 ; CHECK-NEXT:    [[TMP1:%.*]] = shl <2 x i64> [[DOTSPLATINSERT]], <i64 2, i64 undef>
-; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq <2 x i64> [[TMP1]], <i64 4, i64 4>
-; CHECK-NEXT:    [[C:%.*]] = shufflevector <2 x i1> [[TMP2]], <2 x i1> undef, <2 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i64> [[TMP1]], <i64 4, i64 undef>
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp eq <2 x i64> [[TMP2]], <i64 8, i64 8>
+; CHECK-NEXT:    [[C:%.*]] = shufflevector <2 x i1> [[TMP3]], <2 x i1> undef, <2 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <2 x i1> [[C]]
 ;
   %A = getelementptr inbounds %S, <2 x %S*> %P, <2 x i64> zeroinitializer, <2 x i32> <i32 1, i32 1>, i64 %X
   %B = getelementptr inbounds %S, <2 x %S*> %P, <2 x i64> <i64 0, i64 0>, <2 x i32> <i32 1, i32 1>, i64 1
   %C = icmp eq <2 x i32*> %A, %B
   ret <2 x i1> %C
 }
 
;
   %C = icmp eq i32* %A, %B
   ret i1 %C
 }
 
 
 @G = external global [3 x i8]
 define i8* @test14(i32 %idx) {
 ; CHECK-LABEL: @test14(
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext i32 [[IDX:%.*]] to i64
-; CHECK-NEXT:    [[TMP:%.*]] = getelementptr [3 x i8], [3 x i8]* @G, i64 0, i64 [[ZEXT]]
+; CHECK-NEXT:    [[IDX2:%.*]] = zext i32 [[IDX:%.*]] to i64
+; CHECK-NEXT:    [[TMP:%.*]] = getelementptr [3 x i8], [3 x i8]* @G, i64 0, i64 [[IDX2]]
 ; CHECK-NEXT:    ret i8* [[TMP]]
 ;
-  %zext = zext i32 %idx to i64
-  %tmp = getelementptr i8, i8* getelementptr ([3 x i8], [3 x i8]* @G, i32 0, i32 0), i64 %zext
+  %idx2 = zext i32 %idx to i64
+  %tmp = getelementptr i8, i8* getelementptr ([3 x i8], [3 x i8]* @G, i32 0, i32 0), i64 %idx2
   ret i8* %tmp
 }
 
 
 ; Test folding of constantexpr geps into normal geps.
 @Array = external global [40 x i32]
 define i32 *@test15(i64 %X) {
 ; CHECK-LABEL: @test15(

llvm/test/Transforms/InstCombine/load.ll

 }
 
 ; Check that we canonicalize loads which are only stored to use integer types
 ; when there is a valid integer type.
 
 define void @test16(i8* %x, i8* %a, i8* %b, i8* %c) {
 ; CHECK-LABEL: @test16(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[C_CAST:%.*]] = bitcast i8* [[C:%.*]] to i32*
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; CHECK-NEXT:    [[X11:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[A:%.*]] to i32*
 ; CHECK-NEXT:    store i32 [[X11]], i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8* [[B:%.*]] to i32*
 ; CHECK-NEXT:    store i32 [[X11]], i32* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X]] to i32*
 ; CHECK-NEXT:    [[X22:%.*]] = load i32, i32* [[TMP3]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8* [[B]] to i32*
 ; CHECK-NEXT:    store i32 [[X22]], i32* [[TMP4]], align 4
-; CHECK-NEXT:    store i32 [[X22]], i32* [[C_CAST]], align 4
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8* [[C:%.*]] to i32*
+; CHECK-NEXT:    store i32 [[X22]], i32* [[TMP5]], align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %x.cast = bitcast i8* %x to float*
   %a.cast = bitcast i8* %a to float*
   %b.cast = bitcast i8* %b to float*
   %c.cast = bitcast i8* %c to i32*
 
   %x1 = load float, float* %x.cast
   store float %x1, float* %a.cast
   store float %x1, float* %b.cast
 
   %x2 = load float, float* %x.cast
   store float %x2, float* %b.cast
   %x2.cast = bitcast float %x2 to i32
   store i32 %x2.cast, i32* %c.cast
 
   ret void
 }
 
 define void @test16-vect(i8* %x, i8* %a, i8* %b, i8* %c) {
 ; CHECK-LABEL: @test16-vect(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[C_CAST:%.*]] = bitcast i8* [[C:%.*]] to i32*
 ; CHECK-NEXT:    [[TMP0:%.*]] = bitcast i8* [[X:%.*]] to i32*
 ; CHECK-NEXT:    [[X11:%.*]] = load i32, i32* [[TMP0]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = bitcast i8* [[A:%.*]] to i32*
 ; CHECK-NEXT:    store i32 [[X11]], i32* [[TMP1]], align 4
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i8* [[B:%.*]] to i32*
 ; CHECK-NEXT:    store i32 [[X11]], i32* [[TMP2]], align 4
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i8* [[X]] to i32*
 ; CHECK-NEXT:    [[X22:%.*]] = load i32, i32* [[TMP3]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = bitcast i8* [[B]] to i32*
 ; CHECK-NEXT:    store i32 [[X22]], i32* [[TMP4]], align 4
-; CHECK-NEXT:    store i32 [[X22]], i32* [[C_CAST]], align 4
+; CHECK-NEXT:    [[TMP5:%.*]] = bitcast i8* [[C:%.*]] to i32*
+; CHECK-NEXT:    store i32 [[X22]], i32* [[TMP5]], align 4
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %x.cast = bitcast i8* %x to <4 x i8>*
   %a.cast = bitcast i8* %a to <4 x i8>*
   %b.cast = bitcast i8* %b to <4 x i8>*
   %c.cast = bitcast i8* %c to i32*
 

llvm/test/Transforms/InstCombine/logical-select.ll

;
   %a1 = and i32 %tval, %bitmask
   %a2 = and i32 %not_bitmask, %fval
   %sel = or i32 %a1, %a2
   ret i32 %sel
 }
 
 define <4 x i8> @allSignBits_vec(<4 x i8> %cond, <4 x i8> %tval, <4 x i8> %fval) {
 ; CHECK-LABEL: @allSignBits_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i8> [[COND:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i8> [[FVAL:%.*]], <4 x i8> [[TVAL:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i8> [[COND:%.*]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i8> [[TVAL:%.*]], <4 x i8> [[FVAL:%.*]]
 ; CHECK-NEXT:    ret <4 x i8> [[TMP2]]
 ;
   %bitmask = ashr <4 x i8> %cond, <i8 7, i8 7, i8 7, i8 7>
   %not_bitmask = xor <4 x i8> %bitmask, <i8 -1, i8 -1, i8 -1, i8 -1>
   %a1 = and <4 x i8> %tval, %bitmask
   %a2 = and <4 x i8> %fval, %not_bitmask
   %sel = or <4 x i8> %a2, %a1
   ret <4 x i8> %sel

llvm/test/Transforms/InstCombine/max-of-nots.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -instcombine < %s | FileCheck %s
 
 define <2 x i32> @umin_of_nots(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @umin_of_nots(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult <2 x i32> [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt <2 x i32> [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[X]], <2 x i32> [[Y]]
 ; CHECK-NEXT:    [[MIN:%.*]] = xor <2 x i32> [[TMP2]], <i32 -1, i32 -1>
 ; CHECK-NEXT:    ret <2 x i32> [[MIN]]
 ;
   %notx = xor <2 x i32> %x, <i32 -1, i32 -1>
   %noty = xor <2 x i32> %y, <i32 -1, i32 -1>
   %cmp = icmp ult <2 x i32> %notx, %noty
   %min = select <2 x i1> %cmp, <2 x i32> %notx, <2 x i32> %noty
   ret <2 x i32> %min
 }
 
 define <2 x i32> @smin_of_nots(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @smin_of_nots(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <2 x i32> [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <2 x i32> [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[X]], <2 x i32> [[Y]]
 ; CHECK-NEXT:    [[MIN:%.*]] = xor <2 x i32> [[TMP2]], <i32 -1, i32 -1>
 ; CHECK-NEXT:    ret <2 x i32> [[MIN]]
 ;
   %notx = xor <2 x i32> %x, <i32 -1, i32 -1>
   %noty = xor <2 x i32> %y, <i32 -1, i32 -1>
   %cmp = icmp sle <2 x i32> %notx, %noty
   %min = select <2 x i1> %cmp, <2 x i32> %notx, <2 x i32> %noty
   ret <2 x i32> %min
 }
 
 define i32 @compute_min_2(i32 %x, i32 %y) {
 ; CHECK-LABEL: @compute_min_2(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 [[Y]]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %not_x = sub i32 -1, %x
   %not_y = sub i32 -1, %y
   %cmp = icmp sgt i32 %not_x, %not_y
   %not_min = select i1 %cmp, i32 %not_x, i32 %not_y
   %min = sub i32 -1, %not_min
   ret i32 %min
 }
 
 declare void @extra_use(i8)
 define i8 @umin_not_1_extra_use(i8 %x, i8 %y) {
 ; CHECK-LABEL: @umin_not_1_extra_use(
 ; CHECK-NEXT:    [[NX:%.*]] = xor i8 [[X:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[X]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[Y:%.*]], [[X]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[Y]], i8 [[X]]
 ; CHECK-NEXT:    [[MINXY:%.*]] = xor i8 [[TMP2]], -1
 ; CHECK-NEXT:    call void @extra_use(i8 [[NX]])
 ; CHECK-NEXT:    ret i8 [[MINXY]]
 ;
   %nx = xor i8 %x, -1
   %ny = xor i8 %y, -1
   %cmpxy = icmp ult i8 %nx, %ny
;
   call void @extra_use(i8 %ny)
   ret i8 %minxy
 }
 
 ; PR35834 - https://bugs.llvm.org/show_bug.cgi?id=35834
 
 define i8 @umin3_not(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @umin3_not(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[Z:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 [[Z]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ugt i8 [[TMP2]], [[Y:%.*]]
 ; CHECK-NEXT:    [[R_V:%.*]] = select i1 [[TMP3]], i8 [[TMP2]], i8 [[Y]]
 ; CHECK-NEXT:    [[R:%.*]] = xor i8 [[R_V]], -1
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
   %nx = xor i8 %x, -1
   %ny = xor i8 %y, -1
   %nz = xor i8 %z, -1
   %cmpyx = icmp ult i8 %y, %x
   %cmpxz = icmp ult i8 %nx, %nz
   %minxz = select i1 %cmpxz, i8 %nx, i8 %nz
   %cmpyz = icmp ult i8 %ny, %nz
   %minyz = select i1 %cmpyz, i8 %ny, i8 %nz
   %r = select i1 %cmpyx, i8 %minxz, i8 %minyz
   ret i8 %r
 }
 
 ; PR35875 - https://bugs.llvm.org/show_bug.cgi?id=35875
 
 define i8 @umin3_not_more_uses(i8 %x, i8 %y, i8 %z) {
 ; CHECK-LABEL: @umin3_not_more_uses(
 ; CHECK-NEXT:    [[NX:%.*]] = xor i8 [[X:%.*]], -1
 ; CHECK-NEXT:    [[NY:%.*]] = xor i8 [[Y:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[X]], [[Z:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[Z:%.*]], [[X]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[Z]], i8 [[X]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp ugt i8 [[TMP2]], [[Y]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i8 [[TMP2]], i8 [[Y]]
 ; CHECK-NEXT:    [[R:%.*]] = xor i8 [[TMP4]], -1
 ; CHECK-NEXT:    call void @extra_use(i8 [[NX]])
 ; CHECK-NEXT:    call void @extra_use(i8 [[NY]])
 ; CHECK-NEXT:    ret i8 [[R]]
 ;
;
   call void @use8(i8 %xn)
   call void @use8(i8 %yn)
   call void @use8(i8 %zn)
   ret i8 %minxyz
 }
 
 define i32 @compute_min_3(i32 %x, i32 %y, i32 %z) {
 ; CHECK-LABEL: @compute_min_3(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 [[Y]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt i32 [[TMP2]], [[Z:%.*]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 [[Z]]
 ; CHECK-NEXT:    ret i32 [[TMP4]]
 ;
   %not_x = sub i32 -1, %x
   %not_y = sub i32 -1, %y
   %not_z = sub i32 -1, %z

 }
 
 define i32 @max_of_nots(i32 %x, i32 %y) {
 ; CHECK-LABEL: @max_of_nots(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[Y:%.*]], 0
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[Y]], i32 0
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt i32 [[TMP2]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 [[X]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor i32 [[TMP4]], -1
-; CHECK-NEXT:    ret i32 [[TMP5]]
+; CHECK-NEXT:    [[SMAX96:%.*]] = xor i32 [[TMP4]], -1
+; CHECK-NEXT:    ret i32 [[SMAX96]]
 ;
   %c0 = icmp sgt i32 %y, 0
   %xor_y = xor i32 %y, -1
   %s0 = select i1 %c0, i32 %xor_y, i32 -1
   %xor_x = xor i32 %x, -1
   %c1 = icmp slt i32 %s0, %xor_x
   %smax96 = select i1 %c1, i32 %xor_x, i32 %s0
   ret i32 %smax96

 }
 
 define <2 x i32> @max_of_nots_vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @max_of_nots_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <2 x i32> [[Y:%.*]], zeroinitializer
 ; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i32> [[Y]], <2 x i32> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt <2 x i32> [[TMP2]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP2]], <2 x i32> [[X]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor <2 x i32> [[TMP4]], <i32 -1, i32 -1>
-; CHECK-NEXT:    ret <2 x i32> [[TMP5]]
+; CHECK-NEXT:    [[SMAX96:%.*]] = xor <2 x i32> [[TMP4]], <i32 -1, i32 -1>
+; CHECK-NEXT:    ret <2 x i32> [[SMAX96]]
 ;
   %c0 = icmp sgt <2 x i32> %y, zeroinitializer
   %xor_y = xor <2 x i32> %y, <i32 -1, i32 -1>
   %s0 = select <2 x i1> %c0, <2 x i32> %xor_y, <2 x i32> <i32 -1, i32 -1>
   %xor_x = xor <2 x i32> %x, <i32 -1, i32 -1>
   %c1 = icmp slt <2 x i32> %s0, %xor_x
   %smax96 = select <2 x i1> %c1, <2 x i32> %xor_x, <2 x i32> %s0
   ret <2 x i32> %smax96
 }
 
 define <2 x i37> @max_of_nots_weird_type_vec(<2 x i37> %x, <2 x i37> %y) {
 ; CHECK-LABEL: @max_of_nots_weird_type_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <2 x i37> [[Y:%.*]], zeroinitializer
 ; CHECK-NEXT:    [[TMP2:%.*]] = select <2 x i1> [[TMP1]], <2 x i37> [[Y]], <2 x i37> zeroinitializer
 ; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt <2 x i37> [[TMP2]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP4:%.*]] = select <2 x i1> [[TMP3]], <2 x i37> [[TMP2]], <2 x i37> [[X]]
-; CHECK-NEXT:    [[TMP5:%.*]] = xor <2 x i37> [[TMP4]], <i37 -1, i37 -1>
-; CHECK-NEXT:    ret <2 x i37> [[TMP5]]
+; CHECK-NEXT:    [[SMAX96:%.*]] = xor <2 x i37> [[TMP4]], <i37 -1, i37 -1>
+; CHECK-NEXT:    ret <2 x i37> [[SMAX96]]
 ;
   %c0 = icmp sgt <2 x i37> %y, zeroinitializer
   %xor_y = xor <2 x i37> %y, <i37 -1, i37 -1>
   %s0 = select <2 x i1> %c0, <2 x i37> %xor_y, <2 x i37> <i37 -1, i37 -1>
   %xor_x = xor <2 x i37> %x, <i37 -1, i37 -1>
   %c1 = icmp slt <2 x i37> %s0, %xor_x
   %smax96 = select <2 x i1> %c1, <2 x i37> %xor_x, <2 x i37> %s0
   ret <2 x i37> %smax96

llvm/test/Transforms/InstCombine/or.ll

;
   ret <2 x i16> %D
 }
 
 ; PR3266 & PR5276
 define i1 @test25(i32 %A, i32 %B) {
 ; CHECK-LABEL: @test25(
 ; CHECK-NEXT:    [[C:%.*]] = icmp ne i32 [[A:%.*]], 0
 ; CHECK-NEXT:    [[D:%.*]] = icmp ne i32 [[B:%.*]], 57
-; CHECK-NEXT:    [[F:%.*]] = and i1 [[D]], [[C]]
+; CHECK-NEXT:    [[F:%.*]] = and i1 [[C]], [[D]]
 ; CHECK-NEXT:    ret i1 [[F]]
 ;
   %C = icmp eq i32 %A, 0
   %D = icmp eq i32 %B, 57
   %E = or i1 %C, %D
   %F = xor i1 %E, -1
   ret i1 %F
 }
;
   %neg.i = xor <4 x i32> %and.i135, <i32 -1, i32 -1, i32 -1, i32 -1>
   %and.i = and <4 x i32> %vecinit6.i191, %neg.i
   %or.i = or <4 x i32> %and.i, %and.i129
   ret <4 x i32> %or.i
 }
 
 define i1 @test33(i1 %X, i1 %Y) {
 ; CHECK-LABEL: @test33(
-; CHECK-NEXT:    [[B:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[B]]
+; CHECK-NEXT:    [[A:%.*]] = or i1 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i1 [[A]]
 ;
   %a = or i1 %X, %Y
   %b = or i1 %a, %X
   ret i1 %b
 }
 
 define i32 @test34(i32 %X, i32 %Y) {
 ; CHECK-LABEL: @test34(
-; CHECK-NEXT:    [[B:%.*]] = or i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT:    ret i32 [[B]]
+; CHECK-NEXT:    [[A:%.*]] = or i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    ret i32 [[A]]
 ;
   %a = or i32 %X, %Y
   %b = or i32 %Y, %a
   ret i32 %b
 }
 
 define i32 @test35(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test35(

llvm/test/Transforms/InstCombine/pr38915.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -instcombine -S | FileCheck %s
 
 define i32 @PR38915(i32 %x, i32 %y, i32 %z) {
 ; CHECK-LABEL: @PR38915(
 ; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[Y:%.*]], -1
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[M1N:%.*]] = select i1 [[TMP3]], i32 [[TMP1]], i32 [[TMP2]]
 ; CHECK-NEXT:    [[C2:%.*]] = icmp sgt i32 [[M1N]], [[Z:%.*]]
 ; CHECK-NEXT:    [[M2:%.*]] = select i1 [[C2]], i32 [[M1N]], i32 [[Z]]
 ; CHECK-NEXT:    [[M2N:%.*]] = xor i32 [[M2]], -1
 ; CHECK-NEXT:    ret i32 [[M2N]]
 ;
   %xn = sub i32 0, %x
   %yn = sub i32 0, %y
   %c1 = icmp sgt i32 %xn, %yn
   %m1 = select i1 %c1, i32 %xn, i32 %yn
   %m1n = xor i32 %m1, -1
   %c2 = icmp sgt i32 %m1n, %z
   %m2 = select i1 %c2, i32 %m1n, i32 %z
   %m2n = xor i32 %m2, -1
   ret i32 %m2n
 }

llvm/test/Transforms/InstCombine/pr44245.ll

 ; CHECK-LABEL: @test_2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[WHILE_COND:%.*]]
 ; CHECK:       while.cond:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[COND_TRUE133:%.*]], label [[COND_FALSE138:%.*]]
 ; CHECK:       cond.true133:
-; CHECK-NEXT:    store %type_3* undef, %type_3** null, align 536870912
 ; CHECK-NEXT:    br label [[COND_END144:%.*]]
 ; CHECK:       cond.false138:
-; CHECK-NEXT:    store %type_3* undef, %type_3** null, align 536870912
 ; CHECK-NEXT:    br label [[COND_END144]]
 ; CHECK:       cond.end144:
+; CHECK-NEXT:    store %type_3* undef, %type_3** null, align 536870912
 ; CHECK-NEXT:    br label [[WHILE_COND]]
 ;
 entry:
   br label %while.cond
 
 while.cond:                                       ; preds = %cond.end144, %entry
   %link.0 = phi %type_2* [ undef, %entry ], [ %cond145, %cond.end144 ]
   %os115 = bitcast %type_2* %link.0 to %type_3*

llvm/test/Transforms/InstCombine/select-cmp-br.ll

 
 define void @test1(%C* %arg) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
 ; CHECK-NEXT:    [[M:%.*]] = load i64*, i64** [[TMP]], align 8
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
 ; CHECK-NEXT:    [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
-; CHECK-NEXT:    [[NOT_TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
 ; CHECK-NEXT:    [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
-; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP71]], [[NOT_TMP5]]
+; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP71]]
 ; CHECK-NEXT:    br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb8:
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
 ; CHECK-NEXT:    tail call void @bar(%struct.S* [[TMP9]])
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb10:

 
 define void @test3(%C* %arg) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[C:%.*]], %C* [[ARG:%.*]], i64 0, i32 0, i32 0
 ; CHECK-NEXT:    [[M:%.*]] = load i64*, i64** [[TMP]], align 8
 ; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 1, i32 0, i32 0
 ; CHECK-NEXT:    [[N:%.*]] = load i64*, i64** [[TMP1]], align 8
-; CHECK-NEXT:    [[NOT_TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp ne i64* [[M]], [[N]]
 ; CHECK-NEXT:    [[TMP71:%.*]] = icmp eq %C* [[ARG]], null
-; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP71]], [[NOT_TMP5]]
+; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP71]]
 ; CHECK-NEXT:    br i1 [[TMP7]], label [[BB10:%.*]], label [[BB8:%.*]]
 ; CHECK:       bb:
 ; CHECK-NEXT:    ret void
 ; CHECK:       bb8:
 ; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[C]], %C* [[ARG]], i64 0, i32 0
 ; CHECK-NEXT:    tail call void @bar(%struct.S* [[TMP9]])
 ; CHECK-NEXT:    br label [[BB:%.*]]
 ; CHECK:       bb10:

llvm/test/Transforms/InstCombine/select-pr39595.ll

 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define i32 @foo(i32 %x, i32 %y) {
 ; CHECK-LABEL: foo
-; CHECK:      [[TMP1:%.*]] = icmp ult i32 %y, %x
+; CHECK:      [[TMP1:%.*]] = icmp ugt i32 %x, %y
 ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 %x, i32 %y, !prof ![[$MD0:[0-9]+]]
 ; CHECK-NEXT: [[TMP3:%.*]] = xor i32 [[TMP2]], -1
 ; CHECK-NEXT: ret i32 [[TMP3:%.*]]
 ; CHECK-DAG:  !0 = !{!"branch_weights", i32 6, i32 1}
 
   %1 = xor i32 %x, -1
   %2 = xor i32 %y, -1
   %3 = icmp ugt i32 %1, %2
   %4 = select i1 %3, i32 %2, i32 %1, !prof !1
   ret i32 %4
 }
 
 !1 = !{!"branch_weights", i32 1, i32 6}

llvm/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -instcombine %s -S -o - | FileCheck %s
 
 ; Clamp negative to zero:
 ; E.g., clamp0 implemented in a shifty way, could be optimized as v > 0 ? v : 0, where sub hasNoSignedWrap.
 ; int32 clamp0(int32 v) {
 ;   return ((-(v) >> 31) & (v));
 ; }
 ;
 
 ; Scalar Types
 
 define i8 @sub_ashr_and_i8(i8 %x, i8 %y) {
 ; CHECK-LABEL: @sub_ashr_and_i8(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 0
 ; CHECK-NEXT:    ret i8 [[AND]]
 ;
   %sub = sub nsw i8 %y, %x
   %shr = ashr i8 %sub, 7
   %and = and i8 %shr, %x
   ret i8 %and
 }
 
 define i16 @sub_ashr_and_i16(i16 %x, i16 %y) {
 ; CHECK-LABEL: @sub_ashr_and_i16(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i16 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i16 [[X]], i16 0
 ; CHECK-NEXT:    ret i16 [[AND]]
 ;
 
   %sub = sub nsw i16 %y, %x
   %shr = ashr i16 %sub, 15
   %and = and i16 %shr, %x
   ret i16 %and
 }
 
 define i32 @sub_ashr_and_i32(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sub_ashr_and_i32(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %and = and i32 %shr, %x
   ret i32 %and
 }
 
 define i64 @sub_ashr_and_i64(i64 %x, i64 %y) {
 ; CHECK-LABEL: @sub_ashr_and_i64(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i64 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i64 [[X]], i64 0
 ; CHECK-NEXT:    ret i64 [[AND]]
 ;
   %sub = sub nsw i64 %y, %x
   %shr = ashr i64 %sub, 63
   %and = and i64 %shr, %x
   ret i64 %and
 }
 
 ; nuw nsw
 
 define i32 @sub_ashr_and_i32_nuw_nsw(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sub_ashr_and_i32_nuw_nsw(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nuw nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %and = and i32 %shr, %x
   ret i32 %and
 }
 
 ; Commute
 
 define i32 @sub_ashr_and_i32_commute(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sub_ashr_and_i32_commute(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %and = and i32 %x, %shr  ; commute %x and %shr
   ret i32 %and
 }
 
 ; Vector Types
 
 define <4 x i32> @sub_ashr_and_i32_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @sub_ashr_and_i32_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x i32> [[AND]]
 ;
   %sub = sub nsw <4 x i32> %y, %x
   %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
   %and = and <4 x i32> %shr, %x
   ret <4 x i32> %and
 }
 
 define <4 x i32> @sub_ashr_and_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @sub_ashr_and_i32_vec_nuw_nsw(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x i32> [[AND]]
 ;
   %sub = sub nuw nsw <4 x i32> %y, %x
   %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
   %and = and <4 x i32> %shr, %x
   ret <4 x i32> %and
 }
 
 define <4 x i32> @sub_ashr_and_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @sub_ashr_and_i32_vec_commute(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
 ; CHECK-NEXT:    ret <4 x i32> [[AND]]
 ;
   %sub = sub nsw <4 x i32> %y, %x
   %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
   %and = and <4 x i32> %x, %shr  ; commute %x and %shr
   ret <4 x i32> %and
 }
;
   store i32 %sub, i32* %p
   %shr = ashr i32 %sub, 31
   %and = and i32 %shr, %x
   ret i32 %and
 }
 
 define i32 @sub_ashr_and_i32_extra_use_and(i32 %x, i32 %y, i32* %p) {
 ; CHECK-LABEL: @sub_ashr_and_i32_extra_use_and(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
 ; CHECK-NEXT:    store i32 [[AND]], i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    ret i32 [[AND]]
 ;
   %sub = sub nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %and = and i32 %shr, %x
   store i32 %and, i32* %p

llvm/test/Transforms/InstCombine/sub-ashr-or-to-icmp-select.ll

;
   %shr = ashr i32 %sub, 31
   %or = or i32 %shr, %x
   %and = and i32 %or, 255
   ret i32 %and
 }
 
 define i8 @sub_ashr_or_i8(i8 %x, i8 %y) {
 ; CHECK-LABEL: @sub_ashr_or_i8(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i8 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i8 -1, i8 [[X]]
 ; CHECK-NEXT:    ret i8 [[OR]]
 ;
   %sub = sub nsw i8 %y, %x
   %shr = ashr i8 %sub, 7
   %or = or i8 %shr, %x
   ret i8 %or
 }
 
 define i16 @sub_ashr_or_i16(i16 %x, i16 %y) {
 ; CHECK-LABEL: @sub_ashr_or_i16(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i16 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i16 -1, i16 [[X]]
 ; CHECK-NEXT:    ret i16 [[OR]]
 ;
   %sub = sub nsw i16 %y, %x
   %shr = ashr i16 %sub, 15
   %or = or i16 %shr, %x
   ret i16 %or
 }
 
 define i32 @sub_ashr_or_i32(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sub_ashr_or_i32(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %or = or i32 %shr, %x
   ret i32 %or
 }
 
 define i64 @sub_ashr_or_i64(i64 %x, i64 %y) {
 ; CHECK-LABEL: @sub_ashr_or_i64(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i64 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i64 -1, i64 [[X]]
 ; CHECK-NEXT:    ret i64 [[OR]]
 ;
   %sub = sub nsw i64 %y, %x
   %shr = ashr i64 %sub, 63
   %or = or i64 %shr, %x
   ret i64 %or
 }
 
 ; nuw nsw
 
 define i32 @sub_ashr_or_i32_nuw_nsw(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sub_ashr_or_i32_nuw_nsw(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nuw nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %or = or i32 %shr, %x
   ret i32 %or
 }
 
 ; Commute
 
 define i32 @sub_ashr_or_i32_commute(i32 %x, i32 %y) {
 ; CHECK-LABEL: @sub_ashr_or_i32_commute(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %or = or i32 %x, %shr  ; commute %shr and %x
   ret i32 %or
 }
 
 ; Vector Types
 
 define <4 x i32> @sub_ashr_or_i32_vec(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @sub_ashr_or_i32_vec(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[X]]
 ; CHECK-NEXT:    ret <4 x i32> [[OR]]
 ;
   %sub = sub nsw <4 x i32> %y, %x
   %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
   %or = or <4 x i32> %shr, %x
   ret <4 x i32> %or
 }
 
 define <4 x i32> @sub_ashr_or_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @sub_ashr_or_i32_vec_nuw_nsw(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[X]]
 ; CHECK-NEXT:    ret <4 x i32> [[OR]]
 ;
   %sub = sub nuw nsw <4 x i32> %y, %x
   %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
   %or = or <4 x i32> %shr, %x
   ret <4 x i32> %or
 }
 
 define <4 x i32> @sub_ashr_or_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) {
 ; CHECK-LABEL: @sub_ashr_or_i32_vec_commute(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> [[X]]
 ; CHECK-NEXT:    ret <4 x i32> [[OR]]
 ;
   %sub = sub nsw <4 x i32> %y, %x
   %shr = ashr <4 x i32> %sub, <i32 31, i32 31, i32 31, i32 31>
   %or = or <4 x i32> %x, %shr
   ret <4 x i32> %or
 }
;
   store i32 %sub, i32* %p
   %shr = ashr i32 %sub, 31
   %or = or i32 %shr, %x
   ret i32 %or
 }
 
 define i32 @sub_ashr_or_i32_extra_use_or(i32 %x, i32 %y, i32* %p) {
 ; CHECK-LABEL: @sub_ashr_or_i32_extra_use_or(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[OR:%.*]] = select i1 [[TMP1]], i32 -1, i32 [[X]]
 ; CHECK-NEXT:    store i32 [[OR]], i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
   %sub = sub nsw i32 %y, %x
   %shr = ashr i32 %sub, 31
   %or = or i32 %shr, %x
   store i32 %or, i32* %p

llvm/test/Transforms/InstCombine/sub-gep.ll

;
   %i2 = ptrtoint i32* %p1 to i64
   %d = sub nuw i64 %i2, %i1
   ret i64 %d
 }
 
 ; The sub and shl here could be nuw, but this is harder to handle.
 define i64 @test_inbounds_nuw_two_gep([0 x i32]* %base, i64 %idx, i64 %idx2) {
 ; CHECK-LABEL: @test_inbounds_nuw_two_gep(
-; CHECK-NEXT:    [[P2_IDX1:%.*]] = sub i64 [[IDX2:%.*]], [[IDX:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = shl i64 [[P2_IDX1]], 2
-; CHECK-NEXT:    ret i64 [[TMP1]]
+; CHECK-NEXT:    [[TMP1:%.*]] = sub i64 [[IDX2:%.*]], [[IDX:%.*]]
+; CHECK-NEXT:    [[DIFF_NEG:%.*]] = shl i64 [[TMP1]], 2
+; CHECK-NEXT:    ret i64 [[DIFF_NEG]]
 ;
   %p1 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx
   %p2 = getelementptr inbounds [0 x i32], [0 x i32]* %base, i64 0, i64 %idx2
   %i1 = ptrtoint i32* %p1 to i64
   %i2 = ptrtoint i32* %p2 to i64
   %d = sub nuw i64 %i2, %i1
   ret i64 %d
 }
 
 define i64 @test_inbounds_nuw_multi_index([0 x [2 x i32]]* %base, i64 %idx, i64 %idx2) {
 ; CHECK-LABEL: @test_inbounds_nuw_multi_index(
 ; CHECK-NEXT:    [[P2_IDX:%.*]] = shl nsw i64 [[IDX:%.*]], 3
 ; CHECK-NEXT:    [[P2_IDX1:%.*]] = shl nsw i64 [[IDX2:%.*]], 2
-; CHECK-NEXT:    [[P2_OFFS2:%.*]] = add i64 [[P2_IDX]], [[P2_IDX1]]
+; CHECK-NEXT:    [[P2_OFFS2:%.*]] = add i64 [[P2_IDX1]], [[P2_IDX]]
 ; CHECK-NEXT:    ret i64 [[P2_OFFS2]]
 ;
   %p1 = getelementptr inbounds [0 x [2 x i32]], [0 x [2 x i32]]* %base, i64 0, i64 0, i64 0
   %p2 = getelementptr inbounds [0 x [2 x i32]], [0 x [2 x i32]]* %base, i64 0, i64 %idx, i64 %idx2
   %i1 = ptrtoint i32* %p1 to i64
   %i2 = ptrtoint i32* %p2 to i64
   %d = sub nuw i64 %i2, %i1
   ret i64 %d
 }

llvm/test/Transforms/InstCombine/sub-minmax.ll

;
   %l1 = select i1 %l0, i32 %not, i32 31
   %x = sub i32 %not, %l1
   call void @use32(i32 %l1)
   ret i32 %x
 }
 
 define i32 @max_bi_na_minus_na_use(i32 %A, i32 %Bi) {
 ; CHECK-LABEL: @max_bi_na_minus_na_use(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[A:%.*]], [[BI:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[BI:%.*]], [[A:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[BI]], i32 [[A]]
 ; CHECK-NEXT:    [[L1:%.*]] = xor i32 [[TMP2]], -1
 ; CHECK-NEXT:    [[X:%.*]] = sub i32 [[A]], [[TMP2]]
 ; CHECK-NEXT:    call void @use32(i32 [[L1]])
 ; CHECK-NEXT:    ret i32 [[X]]
 ;
   %not = xor i32 %A, -1
   %B = xor i32 %Bi, -1
   %l0 = icmp ult i32 %B, %not
   %l1 = select i1 %l0, i32 %B, i32 %not
   %x = sub i32 %l1, %not
   call void @use32(i32 %l1)
   ret i32 %x
 }
 
 define i32 @na_minus_max_bi_na_use(i32 %A, i32 %Bi) {
 ; CHECK-LABEL: @na_minus_max_bi_na_use(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[A:%.*]], [[BI:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[BI:%.*]], [[A:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[BI]], i32 [[A]]
 ; CHECK-NEXT:    [[L1:%.*]] = xor i32 [[TMP2]], -1
 ; CHECK-NEXT:    [[X:%.*]] = sub i32 [[TMP2]], [[A]]
 ; CHECK-NEXT:    call void @use32(i32 [[L1]])
 ; CHECK-NEXT:    ret i32 [[X]]
 ;
   %not = xor i32 %A, -1
   %B = xor i32 %Bi, -1
;
   call void @use32(i32 %l1)
   call void @use32(i32 %not)
   ret i32 %x
 }
 
 define i32 @max_bi_na_minus_na_use2(i32 %A, i32 %Bi) {
 ; CHECK-LABEL: @max_bi_na_minus_na_use2(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[A]], [[BI:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[BI:%.*]], [[A]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[BI]], i32 [[A]]
 ; CHECK-NEXT:    [[L1:%.*]] = xor i32 [[TMP2]], -1
 ; CHECK-NEXT:    [[X:%.*]] = sub i32 [[A]], [[TMP2]]
 ; CHECK-NEXT:    call void @use32(i32 [[L1]])
 ; CHECK-NEXT:    call void @use32(i32 [[NOT]])
 ; CHECK-NEXT:    ret i32 [[X]]
 ;
   %not = xor i32 %A, -1
   %B = xor i32 %Bi, -1
   %l0 = icmp ult i32 %B, %not
   %l1 = select i1 %l0, i32 %B, i32 %not
   %x = sub i32 %l1, %not
   call void @use32(i32 %l1)
   call void @use32(i32 %not)
   ret i32 %x
 }
 
 define i32 @na_minus_max_bi_na_use2(i32 %A, i32 %Bi) {
 ; CHECK-LABEL: @na_minus_max_bi_na_use2(
 ; CHECK-NEXT:    [[NOT:%.*]] = xor i32 [[A:%.*]], -1
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[A]], [[BI:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[BI:%.*]], [[A]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[BI]], i32 [[A]]
 ; CHECK-NEXT:    [[L1:%.*]] = xor i32 [[TMP2]], -1
 ; CHECK-NEXT:    [[X:%.*]] = sub i32 [[TMP2]], [[A]]
 ; CHECK-NEXT:    call void @use32(i32 [[L1]])
 ; CHECK-NEXT:    call void @use32(i32 [[NOT]])
 ; CHECK-NEXT:    ret i32 [[X]]
 ;
   %not = xor i32 %A, -1
   %B = xor i32 %Bi, -1
   %l0 = icmp ult i32 %B, %not
   %l1 = select i1 %l0, i32 %B, i32 %not
   %x = sub i32 %not, %l1
   call void @use32(i32 %l1)
   call void @use32(i32 %not)
   ret i32 %x
 }
 
 define i8 @umin_not_sub(i8 %x, i8 %y) {
 ; CHECK-LABEL: @umin_not_sub(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 [[Y]]
 ; CHECK-NEXT:    [[MINXY:%.*]] = xor i8 [[TMP2]], -1
 ; CHECK-NEXT:    [[SUBX:%.*]] = sub i8 [[TMP2]], [[X]]
 ; CHECK-NEXT:    [[SUBY:%.*]] = sub i8 [[TMP2]], [[Y]]
 ; CHECK-NEXT:    call void @use8(i8 [[SUBX]])
 ; CHECK-NEXT:    call void @use8(i8 [[SUBY]])
 ; CHECK-NEXT:    ret i8 [[MINXY]]
 ;
   %nx = xor i8 %x, -1
   %ny = xor i8 %y, -1
   %cmpxy = icmp ult i8 %nx, %ny
   %minxy = select i1 %cmpxy, i8 %nx, i8 %ny
   %subx = sub i8 %nx, %minxy
   %suby = sub i8 %ny, %minxy
   call void @use8(i8 %subx)
   call void @use8(i8 %suby)
   ret i8 %minxy
 }
 
 define i8 @umin_not_sub_rev(i8 %x, i8 %y) {
 ; CHECK-LABEL: @umin_not_sub_rev(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i8 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 [[Y]]
 ; CHECK-NEXT:    [[MINXY:%.*]] = xor i8 [[TMP2]], -1
 ; CHECK-NEXT:    [[SUBX:%.*]] = sub i8 [[X]], [[TMP2]]
 ; CHECK-NEXT:    [[SUBY:%.*]] = sub i8 [[Y]], [[TMP2]]
 ; CHECK-NEXT:    call void @use8(i8 [[SUBX]])
 ; CHECK-NEXT:    call void @use8(i8 [[SUBY]])
 ; CHECK-NEXT:    ret i8 [[MINXY]]
 ;

llvm/test/Transforms/InstCombine/vec_sext.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 
 define <4 x i32> @vec_select(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: @vec_select(
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A]], <4 x i32> [[SUB]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[SUB]], <4 x i32> [[A]]
 ; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %cmp = icmp slt <4 x i32> %b, zeroinitializer
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %sub = sub nsw <4 x i32> zeroinitializer, %a
   %t0 = icmp slt <4 x i32> %sext, zeroinitializer
   %sext3 = sext <4 x i1> %t0 to <4 x i32>
   %t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>
   %t2 = and <4 x i32> %a, %t1
   %t3 = and <4 x i32> %sext3, %sub
   %cond = or <4 x i32> %t2, %t3
   ret <4 x i32> %cond
 }
 
 define <4 x i32> @vec_select_alternate_sign_bit_test(<4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: @vec_select_alternate_sign_bit_test(
 ; CHECK-NEXT:    [[SUB:%.*]] = sub nsw <4 x i32> zeroinitializer, [[A:%.*]]
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp sgt <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
-; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[SUB]], <4 x i32> [[A]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt <4 x i32> [[B:%.*]], zeroinitializer
+; CHECK-NEXT:    [[TMP2:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A]], <4 x i32> [[SUB]]
 ; CHECK-NEXT:    ret <4 x i32> [[TMP2]]
 ;
   %cmp = icmp sgt <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
   %sext = sext <4 x i1> %cmp to <4 x i32>
   %sub = sub nsw <4 x i32> zeroinitializer, %a
   %t0 = icmp slt <4 x i32> %sext, zeroinitializer
   %sext3 = sext <4 x i1> %t0 to <4 x i32>
   %t1 = xor <4 x i32> %sext3, <i32 -1, i32 -1, i32 -1, i32 -1>

llvm/test/Transforms/InstCombine/xor.ll

 ; %cmp2 = icmp slt %x, %noty
 ; %res = select i1 %cmp2, i32 %x, i32 %noty
 ;
 ; Same transformations is valid for smin/umax/umin.
 
 define i32 @test39(i32 %x) {
 ; CHECK-LABEL: @test39(
 ; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[X:%.*]], 255
-; CHECK-NEXT:    [[RES:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 255
-; CHECK-NEXT:    ret i32 [[RES]]
+; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 255
+; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %1 = xor i32 %x, -1
   %2 = icmp sgt i32 %1, -256
   %3 = select i1 %2, i32 %1, i32 -256
   %res = xor i32 %3, -1
   ret i32 %res
 }
 
;
   %cmp1 = icmp ult i32 %z, %notx
   %umin = select i1 %cmp1, i32 %z, i32 %notx
   %res = xor i32 %umin, -1
   ret i32 %res
 }
 
 define i32 @test45(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test45(
-; CHECK-NEXT:    [[TMP1:%.*]] = icmp ult i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    [[TMP1:%.*]] = icmp ugt i32 [[Y:%.*]], [[X:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[Y]], i32 [[X]]
 ; CHECK-NEXT:    ret i32 [[TMP2]]
 ;
   %z = xor i32 %y, -1
   %notx = xor i32 %x, -1
   %cmp1 = icmp ult i32 %z, %notx
   %umin = select i1 %cmp1, i32 %z, i32 %notx
   %res = xor i32 %umin, -1
;
   %d = xor <2 x i32> %c, <i32 -1, i32 -1>
   ret <2 x i32> %d
 }
 
 define i32 @test50(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test50(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 1, [[X:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[Y:%.*]], 1
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[E:%.*]] = select i1 [[TMP3]], i32 [[TMP1]], i32 [[TMP2]]
 ; CHECK-NEXT:    ret i32 [[E]]
 ;
   %a = add i32 %x, -2
   %b = sub i32 -2, %y
   %c = icmp slt i32 %a, %b
   %d = select i1 %c, i32 %a, i32 %b
   %e = xor i32 %d, -1
   ret i32 %e
 }
 
 define <2 x i32> @test50vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @test50vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i32> <i32 1, i32 1>, [[X:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 1, i32 1>
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt <2 x i32> [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[E:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]]
 ; CHECK-NEXT:    ret <2 x i32> [[E]]
 ;
   %a = add <2 x i32> %x, <i32 -2, i32 -2>
   %b = sub <2 x i32> <i32 -2, i32 -2>, %y
   %c = icmp slt <2 x i32> %a, %b
   %d = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
   %e = xor <2 x i32> %d, <i32 -1, i32 -1>
   ret <2 x i32> %e
 }
 
 define i32 @test51(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test51(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 -3, [[X:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[Y:%.*]], -3
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt i32 [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt i32 [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[E:%.*]] = select i1 [[TMP3]], i32 [[TMP1]], i32 [[TMP2]]
 ; CHECK-NEXT:    ret i32 [[E]]
 ;
   %a = add i32 %x, 2
   %b = sub i32 2, %y
   %c = icmp sgt i32 %a, %b
   %d = select i1 %c, i32 %a, i32 %b
   %e = xor i32 %d, -1
   ret i32 %e
 }
 
 define <2 x i32> @test51vec(<2 x i32> %x, <2 x i32> %y) {
 ; CHECK-LABEL: @test51vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub <2 x i32> <i32 -3, i32 -3>, [[X:%.*]]
 ; CHECK-NEXT:    [[TMP2:%.*]] = add <2 x i32> [[Y:%.*]], <i32 -3, i32 -3>
-; CHECK-NEXT:    [[TMP3:%.*]] = icmp sgt <2 x i32> [[TMP2]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp slt <2 x i32> [[TMP1]], [[TMP2]]
 ; CHECK-NEXT:    [[E:%.*]] = select <2 x i1> [[TMP3]], <2 x i32> [[TMP1]], <2 x i32> [[TMP2]]
 ; CHECK-NEXT:    ret <2 x i32> [[E]]
 ;
   %a = add <2 x i32> %x, <i32 2, i32 2>
   %b = sub <2 x i32> <i32 2, i32 2>, %y
   %c = icmp sgt <2 x i32> %a, %b
   %d = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
   %e = xor <2 x i32> %d, <i32 -1, i32 -1>
   ret <2 x i32> %e
 }