The other 3-op patterns should also be theoretically handled, but
currently there's a bug in the inferred pattern complexity.
I'm not sure what the error handling strategy should be for potential
constant bus violations. I think the correct strategy is to never
produce mixed SGPR and VGPR operands in a typical VOP instruction,
which will trivially them. However, it's possible to still have hand
written MIR (or erroneously transforms) with these operands. When
these fold, the restriction will be violated. We currently don't have
any verifiers for reg bank legality. For now, just ignore the
It might be worth triggering a DAG fallback on verifier error.