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AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32
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Authored by arsenm on Wed, Jan 22, 6:14 PM.

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Summary

The other 3-op patterns should also be theoretically handled, but
currently there's a bug in the inferred pattern complexity.

I'm not sure what the error handling strategy should be for potential
constant bus violations. I think the correct strategy is to never
produce mixed SGPR and VGPR operands in a typical VOP instruction,
which will trivially them. However, it's possible to still have hand
written MIR (or erroneously transforms) with these operands. When
these fold, the restriction will be violated. We currently don't have
any verifiers for reg bank legality. For now, just ignore the
restriction.

It might be worth triggering a DAG fallback on verifier error.

Diff Detail

Event Timeline

arsenm created this revision.Wed, Jan 22, 6:14 PM
Herald added a project: Restricted Project. · View Herald TranscriptWed, Jan 22, 6:14 PM
arsenm updated this revision to Diff 239762.Wed, Jan 22, 6:45 PM

Fixed pattern that blocked or3 formation

This revision is now accepted and ready to land.Wed, Jan 22, 10:05 PM