GlobalISel: Support widening unmerge results with pointer source

[arsenm]

Fix to equal size case

[paquette]

Why is it better to generate a G_LSHR than a G_ANYEXT? On AArch64 I'd expect G_ANYEXT to be better, since we don't necessarily have to produce a real instruction there.

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

1451–1452

Some debug output explaining that this isn't supported in non-integral address spaces might be useful for people trying to get GISel going.

1483–1484

Debug output might be useful here too?

[paquette]

Why is it better to generate a G_LSHR than a G_ANYEXT? On AArch64 I'd expect G_ANYEXT to be better, since we don't necessarily have to produce a real instruction there.

Wait nevermind this is fine, this is legalization.

LGTM with inline comments.

[arsenm]

bc101ffd77738a5ec40fc16689eafaf1fb6fa8d6, but I moved the utility function change here to break the dependency on D72610

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

assert(!OrigTy.isVector() && !TargetTy.isVector() &&
          "GCD type of vector and scalar not implemented");
 
   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
                                   TargetTy.getSizeInBits());
   return LLT::scalar(GCD);
 }
 
 static LLT getLCMType(LLT Ty0, LLT Ty1) {
-  if (Ty0.isScalar() && Ty1.isScalar()) {
+  if (!Ty0.isVector() && !Ty1.isVector()) {
     unsigned Mul = Ty0.getSizeInBits() * Ty1.getSizeInBits();
     int GCDSize = greatestCommonDivisor(Ty0.getSizeInBits(),
                                         Ty1.getSizeInBits());
     return LLT::scalar(Mul / GCDSize);
   }
 
   if (Ty0.isVector() && !Ty1.isVector()) {
     assert(Ty0.getElementType() == Ty1 && "not yet handled");

 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
                                           LLT WideTy) {
   if (TypeIdx != 0)
     return UnableToLegalize;
 
   int NumDst = MI.getNumOperands() - 1;
   Register SrcReg = MI.getOperand(NumDst).getReg();
   LLT SrcTy = MRI.getType(SrcReg);
-  if (!SrcTy.isScalar())
+  if (SrcTy.isVector())
     return UnableToLegalize;
 
   Register Dst0Reg = MI.getOperand(0).getReg();
   LLT DstTy = MRI.getType(Dst0Reg);
   if (!DstTy.isScalar())
     return UnableToLegalize;
 
-  if (WideTy == SrcTy) {
+  if (WideTy.getSizeInBits() == SrcTy.getSizeInBits()) {
+    if (SrcTy.isPointer()) {
+      const DataLayout &DL = MIRBuilder.getDataLayout();
+      if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
+        return UnableToLegalize;
+
+      SrcTy = LLT::scalar(SrcTy.getSizeInBits());
+      SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0);
+    }
+
     // Theres no unmerge type to target. Directly extract the bits from the
     // source type
     unsigned DstSize = DstTy.getSizeInBits();
 
     MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
     for (int I = 1; I != NumDst; ++I) {
       auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);
       auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt);
       MIRBuilder.buildTrunc(MI.getOperand(I), Shr);
     }
 
     MI.eraseFromParent();
     return Legalized;
   }
 
   // TODO
   if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
     return UnableToLegalize;
 
   // Extend the source to a wider type.
   LLT LCMTy = getLCMType(SrcTy, WideTy);
 
   Register WideSrc = SrcReg;
-  if (LCMTy != SrcTy)
+  if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) {
+    // TODO: If this is an integral address space, cast to integer and anyext.
+    if (SrcTy.isPointer())
+      return UnableToLegalize;
+
     WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0);
+  }
+
   auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc);
 
   const int NumUnmerge = Unmerge->getNumOperands() - 1;
   const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();
 
   for (int I = 0; I != NumUnmerge; ++I) {
     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
 

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir

 
 ---
 name: test_unmerge_s8_p1
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
     ; CHECK-LABEL: name: test_unmerge_s8_p1
     ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
-    ; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](p1)
-    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s8)
-    ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s8)
-    ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s8)
-    ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s8)
-    ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s8)
-    ; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s8)
-    ; CHECK: [[ANYEXT6:%[0-9]+]]:_(s32) = G_ANYEXT [[UV6]](s8)
-    ; CHECK: [[ANYEXT7:%[0-9]+]]:_(s32) = G_ANYEXT [[UV7]](s8)
-    ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
-    ; CHECK: $vgpr1 = COPY [[ANYEXT1]](s32)
-    ; CHECK: $vgpr2 = COPY [[ANYEXT2]](s32)
-    ; CHECK: $vgpr3 = COPY [[ANYEXT3]](s32)
-    ; CHECK: $vgpr4 = COPY [[ANYEXT4]](s32)
-    ; CHECK: $vgpr5 = COPY [[ANYEXT5]](s32)
-    ; CHECK: $vgpr6 = COPY [[ANYEXT6]](s32)
-    ; CHECK: $vgpr7 = COPY [[ANYEXT7]](s32)
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+    ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+    ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+    ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C2]]
+    ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[C1]](s32)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
+    ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+    ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
+    ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY8]](s32)
+    ; CHECK: $vgpr1 = COPY [[COPY9]](s32)
+    ; CHECK: $vgpr2 = COPY [[COPY10]](s32)
+    ; CHECK: $vgpr3 = COPY [[COPY11]](s32)
+    ; CHECK: $vgpr4 = COPY [[COPY12]](s32)
+    ; CHECK: $vgpr5 = COPY [[COPY13]](s32)
+    ; CHECK: $vgpr6 = COPY [[COPY14]](s32)
+    ; CHECK: $vgpr7 = COPY [[COPY15]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s8), %2:_(s8), %3:_(s8), %4:_(s8), %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %0
     %10:_(s32) = G_ANYEXT %1
     %11:_(s32) = G_ANYEXT %2
     %12:_(s32) = G_ANYEXT %3
     %13:_(s32) = G_ANYEXT %4
     %14:_(s32) = G_ANYEXT %5
     %15:_(s32) = G_ANYEXT %6
     %16:_(s32) = G_ANYEXT %7
     %17:_(s32) = G_ANYEXT %8
     $vgpr0 = COPY %10
     $vgpr1 = COPY %11
     $vgpr2 = COPY %12
     $vgpr3 = COPY %13
     $vgpr4 = COPY %14
     $vgpr5 = COPY %15
     $vgpr6 = COPY %16
     $vgpr7 = COPY %17
 ...
 
 ---
+name: test_unmerge_s4_p1
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: test_unmerge_s4_p1
+    ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
+    ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C2]]
+    ; CHECK: [[LSHR2:%[0-9]+]]:_(s32) = G_LSHR [[AND]], [[COPY1]](s32)
+    ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+    ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C2]]
+    ; CHECK: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND1]], [[COPY3]](s32)
+    ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 12
+    ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+    ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C2]]
+    ; CHECK: [[LSHR4:%[0-9]+]]:_(s32) = G_LSHR [[AND2]], [[COPY5]](s32)
+    ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+    ; CHECK: [[LSHR5:%[0-9]+]]:_(s32) = G_LSHR [[AND3]], [[COPY7]](s32)
+    ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
+    ; CHECK: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND4]], [[COPY9]](s32)
+    ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
+    ; CHECK: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND5]], [[COPY11]](s32)
+    ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+    ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+    ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
+    ; CHECK: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[COPY13]](s32)
+    ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+    ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+    ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C2]]
+    ; CHECK: [[LSHR9:%[0-9]+]]:_(s32) = G_LSHR [[AND7]], [[COPY15]](s32)
+    ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+    ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+    ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
+    ; CHECK: [[LSHR10:%[0-9]+]]:_(s32) = G_LSHR [[AND8]], [[COPY17]](s32)
+    ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY19]], [[C2]]
+    ; CHECK: [[LSHR11:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C1]](s32)
+    ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C2]]
+    ; CHECK: [[LSHR12:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C3]](s32)
+    ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
+    ; CHECK: [[LSHR13:%[0-9]+]]:_(s32) = G_LSHR [[AND11]], [[C4]](s32)
+    ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+    ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[LSHR2]](s32)
+    ; CHECK: [[COPY24:%[0-9]+]]:_(s32) = COPY [[LSHR3]](s32)
+    ; CHECK: [[COPY25:%[0-9]+]]:_(s32) = COPY [[LSHR4]](s32)
+    ; CHECK: [[COPY26:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[COPY27:%[0-9]+]]:_(s32) = COPY [[LSHR5]](s32)
+    ; CHECK: [[COPY28:%[0-9]+]]:_(s32) = COPY [[LSHR6]](s32)
+    ; CHECK: [[COPY29:%[0-9]+]]:_(s32) = COPY [[LSHR7]](s32)
+    ; CHECK: [[COPY30:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+    ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY [[LSHR8]](s32)
+    ; CHECK: [[COPY32:%[0-9]+]]:_(s32) = COPY [[LSHR9]](s32)
+    ; CHECK: [[COPY33:%[0-9]+]]:_(s32) = COPY [[LSHR10]](s32)
+    ; CHECK: [[COPY34:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: [[COPY35:%[0-9]+]]:_(s32) = COPY [[LSHR11]](s32)
+    ; CHECK: [[COPY36:%[0-9]+]]:_(s32) = COPY [[LSHR12]](s32)
+    ; CHECK: [[COPY37:%[0-9]+]]:_(s32) = COPY [[LSHR13]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY22]](s32)
+    ; CHECK: $vgpr1 = COPY [[COPY23]](s32)
+    ; CHECK: $vgpr2 = COPY [[COPY24]](s32)
+    ; CHECK: $vgpr3 = COPY [[COPY25]](s32)
+    ; CHECK: $vgpr4 = COPY [[COPY26]](s32)
+    ; CHECK: $vgpr5 = COPY [[COPY27]](s32)
+    ; CHECK: $vgpr6 = COPY [[COPY28]](s32)
+    ; CHECK: $vgpr7 = COPY [[COPY29]](s32)
+    ; CHECK: $vgpr8 = COPY [[COPY30]](s32)
+    ; CHECK: $vgpr9 = COPY [[COPY31]](s32)
+    ; CHECK: $vgpr10 = COPY [[COPY32]](s32)
+    ; CHECK: $vgpr11 = COPY [[COPY33]](s32)
+    ; CHECK: $vgpr12 = COPY [[COPY34]](s32)
+    ; CHECK: $vgpr13 = COPY [[COPY35]](s32)
+    ; CHECK: $vgpr14 = COPY [[COPY36]](s32)
+    ; CHECK: $vgpr15 = COPY [[COPY37]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s4), %2:_(s4), %3:_(s4), %4:_(s4), %5:_(s4), %6:_(s4), %7:_(s4), %8:_(s4), %9:_(s4), %10:_(s4), %11:_(s4), %12:_(s4), %13:_(s4), %14:_(s4), %15:_(s4), %16:_(s4) = G_UNMERGE_VALUES %0
+    %17:_(s32) = G_ANYEXT %1
+    %18:_(s32) = G_ANYEXT %2
+    %19:_(s32) = G_ANYEXT %3
+    %20:_(s32) = G_ANYEXT %4
+    %21:_(s32) = G_ANYEXT %5
+    %22:_(s32) = G_ANYEXT %6
+    %23:_(s32) = G_ANYEXT %7
+    %24:_(s32) = G_ANYEXT %8
+    %25:_(s32) = G_ANYEXT %9
+    %26:_(s32) = G_ANYEXT %10
+    %27:_(s32) = G_ANYEXT %11
+    %28:_(s32) = G_ANYEXT %12
+    %29:_(s32) = G_ANYEXT %13
+    %30:_(s32) = G_ANYEXT %14
+    %31:_(s32) = G_ANYEXT %15
+    %32:_(s32) = G_ANYEXT %16
+    $vgpr0 = COPY %17
+    $vgpr1 = COPY %18
+    $vgpr2 = COPY %19
+    $vgpr3 = COPY %20
+    $vgpr4 = COPY %21
+    $vgpr5 = COPY %22
+    $vgpr6 = COPY %23
+    $vgpr7 = COPY %24
+    $vgpr8 = COPY %25
+    $vgpr9 = COPY %26
+    $vgpr10 = COPY %27
+    $vgpr11 = COPY %28
+    $vgpr12 = COPY %29
+    $vgpr13 = COPY %30
+    $vgpr14 = COPY %31
+    $vgpr15 = COPY %32
+...
+
+---
+name: test_unmerge_s16_p1
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: test_unmerge_s16_p1
+    ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV]], [[C]](s32)
+    ; CHECK: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[UV]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV1]](s32)
+    ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR1]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+    ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
+    ; CHECK: $vgpr2 = COPY [[COPY3]](s32)
+    ; CHECK: $vgpr3 = COPY [[COPY4]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s16), %2:_(s16), %3:_(s16), %4:_(s16) = G_UNMERGE_VALUES %0
+    %5:_(s32) = G_ANYEXT %1
+    %6:_(s32) = G_ANYEXT %2
+    %7:_(s32) = G_ANYEXT %3
+    %8:_(s32) = G_ANYEXT %4
+    $vgpr0 = COPY %5
+    $vgpr1 = COPY %6
+    $vgpr2 = COPY %7
+    $vgpr3 = COPY %8
+...
+
+---
+name: test_unmerge_s32_p1
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1
+    ; CHECK-LABEL: name: test_unmerge_s32_p1
+    ; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](p1)
+    ; CHECK: $vgpr0 = COPY [[UV]](s32)
+    ; CHECK: $vgpr1 = COPY [[UV1]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0
+    $vgpr0 = COPY %1
+    $vgpr1 = COPY %2
+...
+
+---
 name: test_unmerge_s16_s32
 body: |
   bb.0:
     liveins: $vgpr0
     ; CHECK-LABEL: name: test_unmerge_s16_s32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
     ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
     ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
     ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
     ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
     %0:_(s32) = COPY $vgpr0
     %1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
     %3:_(s32) = G_ANYEXT %1
     %4:_(s32) = G_ANYEXT %2
     $vgpr0 = COPY %3
     $vgpr1 = COPY %4
 ...
 
 ---
+name: test_unmerge_s16_p3
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; CHECK-LABEL: name: test_unmerge_s16_p3
+    ; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
+    ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
+    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
+    ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[PTRTOINT]](s32)
+    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
+    ; CHECK: $vgpr0 = COPY [[COPY1]](s32)
+    ; CHECK: $vgpr1 = COPY [[COPY2]](s32)
+    %0:_(p3) = COPY $vgpr0
+    %1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %0
+    %3:_(s32) = G_ANYEXT %1
+    %4:_(s32) = G_ANYEXT %2
+    $vgpr0 = COPY %3
+    $vgpr1 = COPY %4
+...
+
+---
 name: test_unmerge_s16_s64
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
     ; CHECK-LABEL: name: test_unmerge_s16_s64
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
     ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
     ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16