[X86][test] Add tests for -fpatchable-function-entry=N,M (where M>0) and its interaction with -fcf-protection=branch

[MaskRay]

Summary

And add tests for its interaction with -fcf-protection=branch

[merge_guards_bot]

Unit tests: fail. 62040 tests passed, 2 failed and 783 were skipped.

failed: libc++.std/thread/thread_mutex/thread_mutex_requirements/thread_mutex_requirements_mutex/thread_mutex_class/try_lock.pass.cpp
failed: libc++.std/thread/thread_mutex/thread_mutex_requirements/thread_mutex_requirements_mutex/thread_mutex_recursive/lock.pass.cpp

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[nickdesaulniers]

llvm/lib/Target/X86/X86MCInstLower.cpp

2646

See comments on D73070 about making nop emission generic.

llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll

38

Need to know where .Lfunc_end2 is placed, please add a CHECK for it.

llvm/test/CodeGen/X86/patchable-function-entry.ll

82

Ditto.

[MaskRay]

Delete code change.
This is a pure test patch now.

[merge_guards_bot]

Unit tests: fail. 62081 tests passed, 1 failed and 784 were skipped.

failed: Clang.Driver/cc-print-options.c

clang-tidy: unknown.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[nickdesaulniers]

llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll

28

Should the filename of this added test be s/ibt.ll/bti.ll?

llvm/test/CodeGen/X86/patchable-function-entry.ll

88

The comment about -ffunction-sections added to the aarch64 test in https://reviews.llvm.org/D73070 would be helpful here, too.

[MaskRay]

Improve tests

[MaskRay]

Fix a typo

-mbranch-protection=bti -> -fcf-protection=branch

[MaskRay]

llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll

28

Sorry, I made a typo.

It should be -fcf-protection=branch (https://gcc.gnu.org/onlinedocs/gcc/Instrumentation-Options.html)

This is the Intel technology which resembles to AArch64's IBT.

[nickdesaulniers]

llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll

28

Yes, and I think the name of the test is still misspelled, I think.

Consider the test modified in https://reviews.llvm.org/D73070 named llvm/test/CodeGen/AArch64/patchable-function-entry-bti.ll, but this file is named llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll. bti vs ibt. Not only is the order different, but bti is only (?) aarch64 specific, so maybe the filename of this test should have fcf, not bti (or ibt).

[merge_guards_bot]

Unit tests: pass. 62082 tests passed, 0 failed and 784 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[merge_guards_bot]

Unit tests: pass. 62083 tests passed, 0 failed and 784 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[MaskRay]

llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll

28

AArch64: Branch Target Identification (bti)
x86: Indirect Branch Tracking (ibt) (I recently added an lld option -z force-ibt, so I am confident here...)

I think the filename is correct, but my comment above made a typo...

This is the Intel technology which resembles to AArch64's IBT.

IBT->BTI.

[nickdesaulniers]

Ah, sorry then for my misunderstanding.

llvm/lib/Target/X86/X86AsmPrinter.h

public:
 
   void EmitInstruction(const MachineInstr *MI) override;
 
   void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override {
     AsmPrinter::EmitBasicBlockEnd(MBB);
     SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
   }
 
+  void emitPatchableFunctionPrefix(int N) override;
+
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                        const char *ExtraCode, raw_ostream &OS) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                              const char *ExtraCode, raw_ostream &OS) override;
 
   bool doInitialization(Module &M) override {
     SMShadowTracker.reset(0);
     SM.reset();

llvm/lib/Target/X86/X86MCInstLower.cpp

if (MI->isCall()) {
     SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
     // Then emit the call
     OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
     return;
   }
 
   EmitAndCountInstruction(TmpInst);
 }
+
+void X86AsmPrinter::emitPatchableFunctionPrefix(int N) {
+  // Emit 1-byte NOPs so that after a partial patch, the remaining are still
+  // valid.
+  while (N--)
+    OutStreamer->EmitInstruction(MCInstBuilder(X86::NOOP), getSubtargetInfo());
+}

llvm/test/CodeGen/X86/patchable-function-entry-ibt.ll

+; RUN: llc -mtriple=x86_64 %s -o - | FileCheck --check-prefixes=CHECK %s
+
+;; -fpatchable-function-entry=0 -fcf-protection=branch
+define void @f0() "patchable-function-entry"="0" "branch-target-enforcement" {
+; CHECK-LABEL: f0:
+; CHECK-NEXT: .Lfunc_begin0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:  endbr64
+; CHECK-NEXT:  retq
+; CHECK-NOT:   .section __patchable_function_entries
+  ret void
+}
+
+;; -fpatchable-function-entry=1 -fcf-protection=branch
+define void @f1() "patchable-function-entry"="1" {
+; CHECK-LABEL: f1:
+; CHECK-NEXT: .Lfunc_begin1:
+; CHECK:       endbr64
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  retq
+; CHECK:       .section __patchable_function_entries,"awo",@progbits,f1,unique,0
+; CHECK-NEXT:  .p2align 3
+; CHECK-NEXT:  .quad .Lfunc_begin1
+  ret void
+}
+
+;; -fpatchable-function-entry=2,1 -mbranch-protection=bti
+define void @f1_1() "patchable-function-entry"="1" "patchable-function-prefix"="1" {
+; CHECK-LABEL: .type f1_1,@function
+; CHECK-NEXT: .Ltmp0:
+; CHECK-NEXT: nop
+; CHECK-NEXT: f1_1:
+; CHECK-NEXT: .Lfunc_begin2:
+; CHECK:      # %bb.0:
+; CHECK-NEXT: endbr64
+; CHECK-NEXT: nop
+; CHECK-NEXT: retq
+; CHECK:      .size f1_1, .Lfunc_end2-f1_1
+; CHECK:      .section __patchable_function_entries,"awo",@progbits,f1,unique,0
+; CHECK-NEXT: .p2align 3
+; CHECK-NEXT: .quad .Ltmp0
+  ret void
+}
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 4, !"cf-protection-branch", i32 1}

llvm/test/CodeGen/X86/patchable-function-entry.ll

 ; NOFSECT      .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5,unique,2
 ; FSECT:       .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5,unique,3
 ; 32:          .p2align 2
 ; 32-NEXT:     .long .Lfunc_begin4
 ; 64:          .p2align 3
 ; 64-NEXT:     .quad .Lfunc_begin4
   ret void
 }
+
+;; -fpatchable-function-entry=3,2
+;; "patchable-function-prefix" emits data before the function entry label.
+define void @f3_2() "patchable-function-prefix"="2" "patchable-function-entry"="1" {
+; CHECK-LABEL: .type f3_2,@function
+; CHECK-NEXT: .Ltmp0: # @f3_2
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  nop
+; CHECK-NEXT:  f3_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:  nop
+;; .size does not include the prefix.
+; CHECK:       .size f3_2, .Lfunc_end5-f3_2
+; NOFSECT      .section __patchable_function_entries,"awo",@progbits,f0,unique,0
+; FSECT:       .section __patchable_function_entries,"awo",@progbits,f3_2,unique,4
+; 32:          .p2align 2
+; 32-NEXT:     .long .Ltmp0
+; 64:          .p2align 3
+; 64-NEXT:     .quad .Ltmp0
+  %frame = alloca i8, i32 16
+  ret void
+}