[PowerPC] Add the missing InstrAliasing for 64-bit rotate instructions

[steven.zhang]

Summary

We have the InstAlias rules for 32-bit rotate but missing the 64-bit one.

Rotate left immediate rotlwi ra,rs,n rlwinm ra,rs,n,0,31
Rotate left rotlw ra,rs,rb rlwnm ra,rs,rb,0,31

[merge_guards_bot]

Unit tests: fail. 61798 tests passed, 1 failed and 781 were skipped.

failed: libc++.std/thread/thread_threads/thread_thread_this/sleep_until.pass.cpp

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[steven.zhang]

Only alias the safe one.

[merge_guards_bot]

Unit tests: pass. 61801 tests passed, 0 failed and 781 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[steven.zhang]

ping

[jsji]

Good catch. This looks good to me. However, there are more than these, almost ALL 64 bits OPs are missing InstAlias.. Can we get some general way to support ALL of them, instead of fixing one by one like this?

[steven.zhang]

In D72676#1873555, @jsji wrote:

Good catch. This looks good to me. However, there are more than these, almost ALL 64 bits OPs are missing InstAlias.. Can we get some general way to support ALL of them, instead of fixing one by one like this?

PowerPC separate the 32bit and 64bit instructions into two files, as we didn't have the general way to define the instructions for 32bit/64bit, it is NOT easy to do it for instr alias also. Maybe, it could be a follow up of this patch ?

[jsji]

Fine for me, as long as you DO follow up to solve the problem for ALL 64 bit instructions.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 def ISEL8   : AForm_4<31, 15,
                      (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
                      "isel $rT, $rA, $rB, $cond", IIC_IntISEL,
                      []>;
 }  // Interpretation64Bit
 }  // hasSideEffects = 0
 }  // End FXU Operations.
 
+def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
+def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
+def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
 
 //===----------------------------------------------------------------------===//
 // Load/Store instructions.
 //
 
 
 // Sign extending loads.
 let PPC970_Unit = 2 in {

llvm/test/CodeGen/PowerPC/bperm.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
 target datalayout = "E-m:e-i64:64-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 ; Function Attrs: nounwind readnone
 define zeroext i32 @bs4(i32 zeroext %a) #0 {
 entry:
   %0 = tail call i32 @llvm.bswap.i32(i32 %a)
   ret i32 %0
 
 ; CHECK-LABEL: @bs4
-; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31
+; CHECK: rotlwi [[REG1:[0-9]+]], 3, 8
 ; CHECK: rlwimi [[REG1]], 3, 24, 16, 23
 ; CHECK: rlwimi [[REG1]], 3, 24, 0, 7
 ; CHECK: mr 3, [[REG1]]
 ; CHECK: blr
 }
 
 define i64 @bs8(i64 %x) #0 {
 entry: