[AMDGPU] Fix getInstrLatency() always returning 1

[rampitec]

Summary

We do not have InstrItinerary so generic getInstLatency() was always
defaulting to return 1 cycle. We need to use TargetSchedModel instead
to compute an instruction's latency.

llvm/lib/Target/AMDGPU/SIInstrInfo.h

 #include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/Compiler.h"
 #include <cassert>
 #include <cstdint>
 
 #define GET_INSTRINFO_HEADER
 #include "AMDGPUGenInstrInfo.inc"
 
 namespace llvm {
 
 class APInt;
 class MachineDominatorTree;
 class MachineRegisterInfo;
 class RegScavenger;
 class GCNSubtarget;
 class TargetRegisterClass;
 
 class SIInstrInfo final : public AMDGPUGenInstrInfo {
 private:
   const SIRegisterInfo RI;
   const GCNSubtarget &ST;
+  TargetSchedModel SchedModel;
 
   // The inverse predicate should have the negative value.
   enum BranchPredicate {
     INVALID_BR = 0,
     SCC_TRUE = 1,
     SCC_FALSE = -1,
     VCCNZ = 2,
     VCCZ = -2,

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

 // code. This is only for making it possible to write reasonably small tests for
 // long branches.
 static cl::opt<unsigned>
 BranchOffsetBits("amdgpu-s-branch-bits", cl::ReallyHidden, cl::init(16),
                  cl::desc("Restrict range of branch instructions (DEBUG)"));
 
 SIInstrInfo::SIInstrInfo(const GCNSubtarget &ST)
   : AMDGPUGenInstrInfo(AMDGPU::ADJCALLSTACKUP, AMDGPU::ADJCALLSTACKDOWN),
-    RI(ST), ST(ST) {}
+    RI(ST), ST(ST) {
+  SchedModel.init(&ST);
+}
 
 //===----------------------------------------------------------------------===//
 // TargetInstrInfo callbacks
 //===----------------------------------------------------------------------===//
 
 static unsigned getNumOperandsNoGlue(SDNode *Node) {
   unsigned N = Node->getNumOperands();
   while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
                                       const MachineInstr &MI,
                                       unsigned *PredCost) const {
   if (MI.isBundle()) {
     MachineBasicBlock::const_instr_iterator I(MI.getIterator());
     MachineBasicBlock::const_instr_iterator E(MI.getParent()->instr_end());
     unsigned Lat = 0, Count = 0;
     for (++I; I != E && I->isBundledWithPred(); ++I) {
       ++Count;
-      Lat = std::max(Lat, getInstrLatency(ItinData, *I, PredCost));
+      Lat = std::max(Lat, SchedModel.computeInstrLatency(&*I));
     }
     return Lat + Count - 1;
   }
 
-  return AMDGPUGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
+  return SchedModel.computeInstrLatency(&MI);
 }

llvm/test/CodeGen/AMDGPU/max.i16.ll

 ; GFX9-NEXT:    global_load_dword v6, v[0:1], off
 ; GFX9-NEXT:    global_load_dword v7, v[2:3], off
 ; GFX9-NEXT:    v_mov_b32_e32 v5, s5
 ; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, s4, v4
 ; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
 ; GFX9-NEXT:    s_waitcnt vmcnt(1)
 ; GFX9-NEXT:    v_mov_b32_e32 v8, v6
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_pk_max_i16 v6, v6, v7
-; GFX9-NEXT:    global_load_short_d16 v7, v[2:3], off offset:4
+; GFX9-NEXT:    v_mov_b32_e32 v9, v7
 ; GFX9-NEXT:    global_load_short_d16 v8, v[0:1], off offset:4
+; GFX9-NEXT:    global_load_short_d16 v9, v[2:3], off offset:4
+; GFX9-NEXT:    v_pk_max_i16 v6, v6, v7
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
-; GFX9-NEXT:    v_pk_max_i16 v0, v8, v7
+; GFX9-NEXT:    v_pk_max_i16 v0, v8, v9
 ; GFX9-NEXT:    global_store_dword v[4:5], v6, off
 ; GFX9-NEXT:    global_store_short v[4:5], v0, off offset:4
 ; GFX9-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
   %gep0 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %aptr, i32 %tid
   %gep1 = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %bptr, i32 %tid
   %outgep = getelementptr <3 x i16>, <3 x i16> addrspace(1)* %out, i32 %tid
   %a = load <3 x i16>, <3 x i16> addrspace(1)* %gep0, align 4

llvm/test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir

bb.0:
 
     ; GCN-LABEL: name: handleMove_bundle
     ; GCN: liveins: $sgpr4_sgpr5
     ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
     ; GCN: $vcc_hi = IMPLICIT_DEF
     ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
     ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4)
     ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
-    ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
     ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3)
+    ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
     ; GCN: $m0 = S_MOV_B32 0
     ; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]]
     ; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
     ; GCN:   DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
     ; GCN:   S_WAITCNT 0
     ; GCN: }
     ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec :: (store 4, addrspace 3)
     ; GCN: S_ENDPGM 0