[SVE] Add patterns for MUL immediate instruction.

[dancgr]

Summary

Add the missing MUL pattern for integer immediate instructions.

[efriedma]

Do we have any negative tests, for immediates that are outside the range of the sve mul immediate instruction?

[c-rhodes]

@dancgr Thanks for the patch! LGTM other than a minor nit (and Eli's comment).

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

384

nit: space (and below)

[dancgr]

In D72654#1818201, @efriedma wrote:

Do we have any negative tests, for immediates that are outside the range of the sve mul immediate instruction?

No, I will add some negative tests for immediates that are out of range.

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

384

Will fix this.

[dancgr]

Fix whitespace errors and add a couple negative tests for invalid input.

[efriedma]

LGTM

llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm-2.ll

1 ↗

(On Diff #238050)

"not llc"? Do we not have a pattern for a general SVE vector multiply yet? In that case, I guess this is fine for now. But please add a note explaining that.

We should probably prioritize adding those patterns.

[dancgr]

llvm/test/CodeGen/AArch64/sve-neg-int-arith-imm-2.ll

1 ↗

(On Diff #238050)

Agreed. I will do those patterns next and then update these tests on my next patch.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE] in {
   defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon", xor>;
   defm AND_ZI : sve_int_log_imm<0b10, "and", "bic", and>;
 
   defm SMAX_ZI   : sve_int_arith_imm1<0b00, "smax", smax>;
   defm SMIN_ZI   : sve_int_arith_imm1<0b10, "smin", smin>;
   defm UMAX_ZI   : sve_int_arith_imm1_unsigned<0b01, "umax", umax>;
   defm UMIN_ZI   : sve_int_arith_imm1_unsigned<0b11, "umin", umin>;
 
-  defm MUL_ZI    : sve_int_arith_imm2<"mul">;
+  defm MUL_ZI    : sve_int_arith_imm2<"mul", mul>;
   defm MUL_ZPmZ   : sve_int_bin_pred_arit_2<0b000, "mul", int_aarch64_sve_mul>;
   defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", int_aarch64_sve_smulh>;
   defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh", int_aarch64_sve_umulh>;
 
   defm SDIV_ZPmZ  : sve_int_bin_pred_arit_2_div<0b100, "sdiv", int_aarch64_sve_sdiv>;
   defm UDIV_ZPmZ  : sve_int_bin_pred_arit_2_div<0b101, "udiv", int_aarch64_sve_udiv>;
   defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", int_aarch64_sve_sdivr>;
   defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", int_aarch64_sve_udivr>;

llvm/lib/Target/AArch64/SVEInstrFormats.td

multiclass sve_int_arith_imm1_unsigned<bits<2> opc, string asm, SDPatternOperator op> {
   def _D : sve_int_arith_imm<0b11, { 0b1010, opc }, asm, ZPR64, imm0_255>;
 
   def : SVE_1_Op_Imm_Arith_Pat<nxv16i8, op, ZPR8, i32, SVEArithUImmPat, !cast<Instruction>(NAME # _B)>;
   def : SVE_1_Op_Imm_Arith_Pat<nxv8i16, op, ZPR16, i32, SVEArithUImmPat, !cast<Instruction>(NAME # _H)>;
   def : SVE_1_Op_Imm_Arith_Pat<nxv4i32, op, ZPR32, i32, SVEArithUImmPat, !cast<Instruction>(NAME # _S)>;
   def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithUImmPat, !cast<Instruction>(NAME # _D)>;
 }
 
-multiclass sve_int_arith_imm2<string asm> {
+multiclass sve_int_arith_imm2<string asm, SDPatternOperator op> {
   def _B : sve_int_arith_imm<0b00, 0b110000, asm, ZPR8,  simm8>;
   def _H : sve_int_arith_imm<0b01, 0b110000, asm, ZPR16, simm8>;
   def _S : sve_int_arith_imm<0b10, 0b110000, asm, ZPR32, simm8>;
   def _D : sve_int_arith_imm<0b11, 0b110000, asm, ZPR64, simm8>;
+
+  def : SVE_1_Op_Imm_Arith_Pat<nxv16i8, op, ZPR8, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _B)>;
+  def : SVE_1_Op_Imm_Arith_Pat<nxv8i16, op, ZPR16, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _H)>;
+  def : SVE_1_Op_Imm_Arith_Pat<nxv4i32, op, ZPR32, i32, SVEArithSImmPat, !cast<Instruction>(NAME # _S)>;
+  def : SVE_1_Op_Imm_Arith_Pat<nxv2i64, op, ZPR64, i64, SVEArithSImmPat, !cast<Instruction>(NAME # _D)>;
 }
 
 //===----------------------------------------------------------------------===//
 // SVE Bitwise Logical - Unpredicated Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_bin_cons_log<bits<2> opc, string asm>
 : I<(outs ZPR64:$Zd), (ins ZPR64:$Zn, ZPR64:$Zm),

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

 ; CHECK: umin z0.d, z0.d, #129
 ; CHECK-NEXT: ret
   %elt = insertelement <vscale x 2 x i64> undef, i64 129, i32 0
   %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %cmp = icmp ult <vscale x 2 x i64> %a, %splat
   %res = select <vscale x 2 x i1> %cmp, <vscale x 2 x i64> %a, <vscale x 2 x i64> %splat
   ret <vscale x 2 x i64> %res
 }
+
+;
+; MUL
+;
+define <vscale x 16 x i8> @mul_i8_neg(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: mul_i8_neg
+; CHECK: mul z0.b, z0.b, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 16 x i8> undef, i8 -17, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %res = mul <vscale x 16 x i8> %a, %splat
+  ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 16 x i8> @mul_i8_pos(<vscale x 16 x i8> %a) {
+; CHECK-LABEL: mul_i8_pos
+; CHECK: mul z0.b, z0.b, #105
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 16 x i8> undef, i8 105, i32 0
+  %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
+  %res = mul <vscale x 16 x i8> %a, %splat
+  ret <vscale x 16 x i8> %res
+}
+
+define <vscale x 8 x i16> @mul_i16_neg(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: mul_i16_neg
+; CHECK: mul z0.h, z0.h, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 8 x i16> undef, i16 -17, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %res = mul <vscale x 8 x i16> %a, %splat
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 8 x i16> @mul_i16_pos(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: mul_i16_pos
+; CHECK: mul z0.h, z0.h, #105
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 8 x i16> undef, i16 105, i32 0
+  %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
+  %res = mul <vscale x 8 x i16> %a, %splat
+  ret <vscale x 8 x i16> %res
+}
+
+define <vscale x 4 x i32> @mul_i32_neg(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: mul_i32_neg
+; CHECK: mul z0.s, z0.s, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 4 x i32> undef, i32 -17, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %res = mul <vscale x 4 x i32> %a, %splat
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 4 x i32> @mul_i32_pos(<vscale x 4 x i32> %a) {
+; CHECK-LABEL: mul_i32_pos
+; CHECK: mul z0.s, z0.s, #105
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 4 x i32> undef, i32 105, i32 0
+  %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
+  %res = mul <vscale x 4 x i32> %a, %splat
+  ret <vscale x 4 x i32> %res
+}
+
+define <vscale x 2 x i64> @mul_i64_neg(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: mul_i64_neg
+; CHECK: mul z0.d, z0.d, #-17
+; CHECK-NEXT: ret
+  %elt = insertelement <vscale x 2 x i64> undef, i64 -17, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %res = mul <vscale x 2 x i64> %a, %splat
+  ret <vscale x 2 x i64> %res
+}
+
+define <vscale x 2 x i64> @mul_i64_pos(<vscale x 2 x i64> %a) {
+; CHECK-LABEL: mul_i64_pos
+; CHECK: mul z0.d, z0.d, #105
+; CHECK-NEXT: ret
+ %elt = insertelement <vscale x 2 x i64> undef, i64 105, i32 0
+  %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
+  %res = mul <vscale x 2 x i64> %a, %splat
+  ret <vscale x 2 x i64> %res
+}