[ARM,MVE] Make `vqrshrun` generate the right instruction.

[simon_tatham]

Summary

A copy-paste error in arm_mve.td meant that the MVE vqrshrun
intrinsic family was generating the vqshrun machine instruction,
because in the IR intrinsic call, the rounding flag argument was set
to 0 rather than 1.

[dmgreen]

Yeah, I said these would be tough to read! LGTM

clang/include/clang/Basic/arm_mve.td

foreach U = [(unsignedflag Scalar)] in {
     defm vshrn   : VSHRN<HalfVector, imm_1toHalfN, (? 0,0,U,U)>;
     defm vqshrn  : VSHRN<HalfVector, imm_1toHalfN, (? 1,0,U,U)>;
     defm vrshrn  : VSHRN<HalfVector, imm_1toHalfN, (? 0,1,U,U)>;
     defm vqrshrn : VSHRN<HalfVector, imm_1toHalfN, (? 1,1,U,U)>;
   }
 }
 let params = [s16, s32], pnt = PNT_NType in {
   defm vqshrun  : VSHRN<UHalfVector, imm_1toHalfN, (? 1,0,1,0)>;
-  defm vqrshrun : VSHRN<UHalfVector, imm_1toHalfN, (? 1,0,1,0)>;
+  defm vqrshrun : VSHRN<UHalfVector, imm_1toHalfN, (? 1,1,1,0)>;
 }
 let params = T.Int, pnt = PNT_NType in {
   defm vsli : DyadicImmShift<Vector, imm_0toNm1>;
   defm vsri : DyadicImmShift<Vector, imm_1toN>;
 }
 
 multiclass VSHL_non_imm<string scalarSuffix, int q, int r,
                         PolymorphicNameType pnt_scalar_unpred = PNT_Type> {

clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm-dyadic.c

#ifdef POLYMORPHIC
     return vqrshrntq_m(a, b, 15, p);
 #else /* POLYMORPHIC */
     return vqrshrntq_m_n_u32(a, b, 15, p);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshrunbq_n_s16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 7, i32 1, i32 0, i32 1, i32 0, i32 0)
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 7, i32 1, i32 1, i32 1, i32 0, i32 0)
 // CHECK-NEXT:    ret <16 x i8> [[TMP0]]
 //
 uint8x16_t test_vqrshrunbq_n_s16(uint8x16_t a, int16x8_t b)
 {
 #ifdef POLYMORPHIC
     return vqrshrunbq(a, b, 7);
 #else /* POLYMORPHIC */
     return vqrshrunbq_n_s16(a, b, 7);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshrunbq_n_s32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 0, i32 1, i32 0, i32 0)
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, i32 1, i32 1, i32 1, i32 0, i32 0)
 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
 //
 uint16x8_t test_vqrshrunbq_n_s32(uint16x8_t a, int32x4_t b)
 {
 #ifdef POLYMORPHIC
     return vqrshrunbq(a, b, 1);
 #else /* POLYMORPHIC */
     return vqrshrunbq_n_s32(a, b, 1);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshruntq_n_s16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 0, i32 1, i32 0, i32 1)
+// CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.v16i8.v8i16(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, i32 1, i32 1, i32 0, i32 1)
 // CHECK-NEXT:    ret <16 x i8> [[TMP0]]
 //
 uint8x16_t test_vqrshruntq_n_s16(uint8x16_t a, int16x8_t b)
 {
 #ifdef POLYMORPHIC
     return vqrshruntq(a, b, 1);
 #else /* POLYMORPHIC */
     return vqrshruntq_n_s16(a, b, 1);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshruntq_n_s32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 3, i32 1, i32 0, i32 1, i32 0, i32 1)
+// CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.v8i16.v4i32(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 3, i32 1, i32 1, i32 1, i32 0, i32 1)
 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
 //
 uint16x8_t test_vqrshruntq_n_s32(uint16x8_t a, int32x4_t b)
 {
 #ifdef POLYMORPHIC
     return vqrshruntq(a, b, 3);
 #else /* POLYMORPHIC */
     return vqrshruntq_n_s32(a, b, 3);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshrunbq_m_n_s16(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
-// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 4, i32 1, i32 0, i32 1, i32 0, i32 0, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 4, i32 1, i32 1, i32 1, i32 0, i32 0, <8 x i1> [[TMP1]])
 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
 //
 uint8x16_t test_vqrshrunbq_m_n_s16(uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
 #ifdef POLYMORPHIC
     return vqrshrunbq_m(a, b, 4, p);
 #else /* POLYMORPHIC */
     return vqrshrunbq_m_n_s16(a, b, 4, p);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshrunbq_m_n_s32(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
-// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 10, i32 1, i32 0, i32 1, i32 0, i32 0, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 10, i32 1, i32 1, i32 1, i32 0, i32 0, <4 x i1> [[TMP1]])
 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 //
 uint16x8_t test_vqrshrunbq_m_n_s32(uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
 #ifdef POLYMORPHIC
     return vqrshrunbq_m(a, b, 10, p);
 #else /* POLYMORPHIC */
     return vqrshrunbq_m_n_s32(a, b, 10, p);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshruntq_m_n_s16(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
-// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 3, i32 1, i32 0, i32 1, i32 0, i32 1, <8 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vshrn.predicated.v16i8.v8i16.v8i1(<16 x i8> [[A:%.*]], <8 x i16> [[B:%.*]], i32 3, i32 1, i32 1, i32 1, i32 0, i32 1, <8 x i1> [[TMP1]])
 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
 //
 uint8x16_t test_vqrshruntq_m_n_s16(uint8x16_t a, int16x8_t b, mve_pred16_t p)
 {
 #ifdef POLYMORPHIC
     return vqrshruntq_m(a, b, 3, p);
 #else /* POLYMORPHIC */
     return vqrshruntq_m_n_s16(a, b, 3, p);
 #endif /* POLYMORPHIC */
 }
 
 // CHECK-LABEL: @test_vqrshruntq_m_n_s32(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
-// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 13, i32 1, i32 0, i32 1, i32 0, i32 1, <4 x i1> [[TMP1]])
+// CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshrn.predicated.v8i16.v4i32.v4i1(<8 x i16> [[A:%.*]], <4 x i32> [[B:%.*]], i32 13, i32 1, i32 1, i32 1, i32 0, i32 1, <4 x i1> [[TMP1]])
 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
 //
 uint16x8_t test_vqrshruntq_m_n_s32(uint16x8_t a, int32x4_t b, mve_pred16_t p)
 {
 #ifdef POLYMORPHIC
     return vqrshruntq_m(a, b, 13, p);
 #else /* POLYMORPHIC */
     return vqrshruntq_m_n_s32(a, b, 13, p);