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Differential D72263

GlobalISel: Correct result type for G_FCMP in lowerFPTOUI
ClosedPublic

Authored by arsenm on Jan 6 2020, 6:14 AM.

Details

Reviewers
Petar.Avramovic
paquette
aemerson
aditya_nandakumar
dsanders
Summary

Using the final result type doesn't make any sense. Use the natural
default boolean type for the select condition.

Diff Detail

Event Timeline

arsenm created this revision.Jan 6 2020, 6:14 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2020, 6:14 AM
Herald added subscribers: volkan, atanasyan, hiraditya and 3 others. · View Herald Transcript
paquette accepted this revision.Jan 6 2020, 1:37 PM

LGTM

(I feel like a verifier should have caught this?)

This revision is now accepted and ready to land.Jan 6 2020, 1:37 PM
arsenm added a comment.Jan 6 2020, 1:40 PM
In D72263#1806781, @paquette wrote:

LGTM

(I feel like a verifier should have caught this?)

The return type isn't necessarily wrong based on the target

arsenm closed this revision.Jan 6 2020, 2:23 PM

1060b9e23b8f9d2802835896947ec281ba3b4f6b

Revision Contents

PathSize
llvm/
lib/
CodeGen/
GlobalISel/
4 lines
test/
CodeGen/
Mips/
GlobalISel/
legalizer/
108 lines
llvm-ir/
9 lines

Diff 236345

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 3,990 Lines • ▼ Show 20 LinesLegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
// For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
// (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
const LLT S1 = LLT::scalar(1);
MachineInstrBuilder FCMP = MachineInstrBuilder FCMP =
MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, DstTy, Src, Threshold); MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
MI.eraseFromParent(); MI.eraseFromParent();
return Legalized; return Legalized;
} }
static CmpInst::Predicate minMaxToCompare(unsigned Opc) { static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
switch (Opc) { switch (Opc) {
▲ Show 20 Lines • Show All 432 Lines • Show Last 20 Lines

llvm/test/CodeGen/Mips/GlobalISel/legalizer/fptosi_and_fptoui.mir

Show First 20 Lines • Show All 345 Lines • ▼ Show 20 Lines bb.1.entry:
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000 ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]] ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32) ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: $v0 = COPY [[SELECT]](s32) ; FP32: $v0 = COPY [[SELECT]](s32)
; FP32: RetRA implicit $v0 ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou32 ; FP64-LABEL: name: f32tou32
; FP64: liveins: $f12 ; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000 ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]] ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32) ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: $v0 = COPY [[SELECT]](s32) ; FP64: $v0 = COPY [[SELECT]](s32)
; FP64: RetRA implicit $v0 ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12 %0:_(s32) = COPY $f12
%1:_(s32) = G_FPTOUI %0(s32) %1:_(s32) = G_FPTOUI %0(s32)
$v0 = COPY %1(s32) $v0 = COPY %1(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
Show All 10 Lines bb.1.entry:
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000 ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]] ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32) ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32) ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0 ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou16 ; FP64-LABEL: name: f32tou16
; FP64: liveins: $f12 ; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000 ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]] ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32) ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32) ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0 ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12 %0:_(s32) = COPY $f12
%1:_(s16) = G_FPTOUI %0(s32) %1:_(s16) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s16) %2:_(s32) = G_ZEXT %1(s16)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
Show All 10 Lines bb.1.entry:
; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000 ; FP32: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]] ; FP32: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32) ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32) ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0 ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f32tou8 ; FP64-LABEL: name: f32tou8
; FP64: liveins: $f12 ; FP64: liveins: $f12
; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12 ; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32) ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000 ; FP64: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]] ; FP64: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32) ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s32)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s32), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32) ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0 ; FP64: RetRA implicit $v0
%0:_(s32) = COPY $f12 %0:_(s32) = COPY $f12
%1:_(s8) = G_FPTOUI %0(s32) %1:_(s8) = G_FPTOUI %0(s32)
%2:_(s32) = G_ZEXT %1(s8) %2:_(s32) = G_ZEXT %1(s8)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines bb.1.entry:
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000 ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]] ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64) ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: $v0 = COPY [[SELECT]](s32) ; FP32: $v0 = COPY [[SELECT]](s32)
; FP32: RetRA implicit $v0 ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou32 ; FP64-LABEL: name: f64tou32
; FP64: liveins: $d6 ; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000 ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]] ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64) ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: $v0 = COPY [[SELECT]](s32) ; FP64: $v0 = COPY [[SELECT]](s32)
; FP64: RetRA implicit $v0 ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6 %0:_(s64) = COPY $d6
%1:_(s32) = G_FPTOUI %0(s64) %1:_(s32) = G_FPTOUI %0(s64)
$v0 = COPY %1(s32) $v0 = COPY %1(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
Show All 10 Lines bb.1.entry:
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000 ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]] ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64) ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32) ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0 ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou16 ; FP64-LABEL: name: f64tou16
; FP64: liveins: $d6 ; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000 ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]] ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64) ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32) ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0 ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6 %0:_(s64) = COPY $d6
%1:_(s16) = G_FPTOUI %0(s64) %1:_(s16) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s16) %2:_(s32) = G_ZEXT %1(s16)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...
Show All 10 Lines bb.1.entry:
; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) ; FP32: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000 ; FP32: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]] ; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64) ; FP32: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP32: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP32: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP32: $v0 = COPY [[AND]](s32) ; FP32: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP32: $v0 = COPY [[AND1]](s32)
; FP32: RetRA implicit $v0 ; FP32: RetRA implicit $v0
; FP64-LABEL: name: f64tou8 ; FP64-LABEL: name: f64tou8
; FP64: liveins: $d6 ; FP64: liveins: $d6
; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6 ; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64) ; FP64: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000 ; FP64: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x41E0000000000000
; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]] ; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[COPY]], [[C]]
; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64) ; FP64: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FSUB]](s64)
; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648 ; FP64: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]] ; FP64: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[FPTOSI1]], [[C1]]
; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]] ; FP64: [[FCMP:%[0-9]+]]:_(s32) = G_FCMP floatpred(ult), [[COPY]](s64), [[C]]
; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[FCMP]](s32), [[FPTOSI]], [[XOR]] ; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; FP64: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FCMP]](s32)
; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]] ; FP64: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C2]]
; FP64: $v0 = COPY [[AND]](s32) ; FP64: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[AND]](s32), [[FPTOSI]], [[XOR]]
; FP64: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; FP64: [[COPY2:%[0-9]+]]:_(s32) = COPY [[SELECT]](s32)
; FP64: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C3]]
; FP64: $v0 = COPY [[AND1]](s32)
; FP64: RetRA implicit $v0 ; FP64: RetRA implicit $v0
%0:_(s64) = COPY $d6 %0:_(s64) = COPY $d6
%1:_(s8) = G_FPTOUI %0(s64) %1:_(s8) = G_FPTOUI %0(s64)
%2:_(s32) = G_ZEXT %1(s8) %2:_(s32) = G_ZEXT %1(s8)
$v0 = COPY %2(s32) $v0 = COPY %2(s32)
RetRA implicit $v0 RetRA implicit $v0
... ...

llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines
; MIPS32-NEXT: sub.s $f1, $f12, $f0 ; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1 ; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $2, $f1 ; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768 ; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $2, $2, $3 ; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1 ; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0 ; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0 ; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3 ; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%conv = fptoui float %a to i32 %conv = fptoui float %a to i32
ret i32 %conv ret i32 %conv
} }
define zeroext i16 @f32tou16(float %a) { define zeroext i16 @f32tou16(float %a) {
; MIPS32-LABEL: f32tou16: ; MIPS32-LABEL: f32tou16:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12 ; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0 ; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224 ; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0 ; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0 ; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1 ; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $2, $f1 ; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768 ; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $2, $2, $3 ; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1 ; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0 ; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0 ; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3 ; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: andi $2, $2, 65535 ; MIPS32-NEXT: andi $2, $2, 65535
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%conv = fptoui float %a to i16 %conv = fptoui float %a to i16
ret i16 %conv ret i16 %conv
} }
define zeroext i8 @f32tou8(float %a) { define zeroext i8 @f32tou8(float %a) {
; MIPS32-LABEL: f32tou8: ; MIPS32-LABEL: f32tou8:
; MIPS32: # %bb.0: # %entry ; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12 ; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $1, $f0 ; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224 ; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0 ; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0 ; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1 ; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $2, $f1 ; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768 ; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $2, $2, $3 ; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1 ; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0 ; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0 ; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3 ; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: andi $2, $2, 255 ; MIPS32-NEXT: andi $2, $2, 255
; MIPS32-NEXT: jr $ra ; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop ; MIPS32-NEXT: nop
entry: entry:
%conv = fptoui float %a to i8 %conv = fptoui float %a to i8
ret i8 %conv ret i8 %conv
} }
Show All 28 Lines
; FP32-NEXT: sub.d $f4, $f12, $f2 ; FP32-NEXT: sub.d $f4, $f12, $f2
; FP32-NEXT: trunc.w.d $f0, $f4 ; FP32-NEXT: trunc.w.d $f0, $f4
; FP32-NEXT: mfc1 $2, $f0 ; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 32768 ; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $2, $2, $3 ; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1 ; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f2 ; FP32-NEXT: c.ult.d $f12, $f2
; FP32-NEXT: movf $3, $zero, $fcc0 ; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $2, $1, $3 ; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: jr $ra ; FP32-NEXT: jr $ra
; FP32-NEXT: nop ; FP32-NEXT: nop
; ;
; FP64-LABEL: f64tou32: ; FP64-LABEL: f64tou32:
; FP64: # %bb.0: # %entry ; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12 ; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0 ; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864 ; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0 ; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f1 ; FP64-NEXT: mtc1 $3, $f1
; FP64-NEXT: mthc1 $2, $f1 ; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: sub.d $f2, $f12, $f1 ; FP64-NEXT: sub.d $f2, $f12, $f1
; FP64-NEXT: trunc.w.d $f0, $f2 ; FP64-NEXT: trunc.w.d $f0, $f2
; FP64-NEXT: mfc1 $2, $f0 ; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 32768 ; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $2, $2, $3 ; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1 ; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f1 ; FP64-NEXT: c.ult.d $f12, $f1
; FP64-NEXT: movf $3, $zero, $fcc0 ; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $2, $1, $3 ; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: jr $ra ; FP64-NEXT: jr $ra
; FP64-NEXT: nop ; FP64-NEXT: nop
entry: entry:
%conv = fptoui double %a to i32 %conv = fptoui double %a to i32
ret i32 %conv ret i32 %conv
} }
Show All 9 Lines
; FP32-NEXT: sub.d $f4, $f12, $f2 ; FP32-NEXT: sub.d $f4, $f12, $f2
; FP32-NEXT: trunc.w.d $f0, $f4 ; FP32-NEXT: trunc.w.d $f0, $f4
; FP32-NEXT: mfc1 $2, $f0 ; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 32768 ; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $2, $2, $3 ; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1 ; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f2 ; FP32-NEXT: c.ult.d $f12, $f2
; FP32-NEXT: movf $3, $zero, $fcc0 ; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $2, $1, $3 ; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: andi $2, $2, 65535 ; FP32-NEXT: andi $2, $2, 65535
; FP32-NEXT: jr $ra ; FP32-NEXT: jr $ra
; FP32-NEXT: nop ; FP32-NEXT: nop
; ;
; FP64-LABEL: f64tou16: ; FP64-LABEL: f64tou16:
; FP64: # %bb.0: # %entry ; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12 ; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0 ; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864 ; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0 ; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f1 ; FP64-NEXT: mtc1 $3, $f1
; FP64-NEXT: mthc1 $2, $f1 ; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: sub.d $f2, $f12, $f1 ; FP64-NEXT: sub.d $f2, $f12, $f1
; FP64-NEXT: trunc.w.d $f0, $f2 ; FP64-NEXT: trunc.w.d $f0, $f2
; FP64-NEXT: mfc1 $2, $f0 ; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 32768 ; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $2, $2, $3 ; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1 ; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f1 ; FP64-NEXT: c.ult.d $f12, $f1
; FP64-NEXT: movf $3, $zero, $fcc0 ; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $2, $1, $3 ; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: andi $2, $2, 65535 ; FP64-NEXT: andi $2, $2, 65535
; FP64-NEXT: jr $ra ; FP64-NEXT: jr $ra
; FP64-NEXT: nop ; FP64-NEXT: nop
entry: entry:
%conv = fptoui double %a to i16 %conv = fptoui double %a to i16
ret i16 %conv ret i16 %conv
} }
Show All 10 Lines
; FP32-NEXT: sub.d $f4, $f12, $f2 ; FP32-NEXT: sub.d $f4, $f12, $f2
; FP32-NEXT: trunc.w.d $f0, $f4 ; FP32-NEXT: trunc.w.d $f0, $f4
; FP32-NEXT: mfc1 $2, $f0 ; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 32768 ; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $2, $2, $3 ; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1 ; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f2 ; FP32-NEXT: c.ult.d $f12, $f2
; FP32-NEXT: movf $3, $zero, $fcc0 ; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $2, $1, $3 ; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: andi $2, $2, 255 ; FP32-NEXT: andi $2, $2, 255
; FP32-NEXT: jr $ra ; FP32-NEXT: jr $ra
; FP32-NEXT: nop ; FP32-NEXT: nop
; ;
; FP64-LABEL: f64tou8: ; FP64-LABEL: f64tou8:
; FP64: # %bb.0: # %entry ; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12 ; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0 ; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864 ; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0 ; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f1 ; FP64-NEXT: mtc1 $3, $f1
; FP64-NEXT: mthc1 $2, $f1 ; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: sub.d $f2, $f12, $f1 ; FP64-NEXT: sub.d $f2, $f12, $f1
; FP64-NEXT: trunc.w.d $f0, $f2 ; FP64-NEXT: trunc.w.d $f0, $f2
; FP64-NEXT: mfc1 $2, $f0 ; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 32768 ; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $2, $2, $3 ; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1 ; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f1 ; FP64-NEXT: c.ult.d $f12, $f1
; FP64-NEXT: movf $3, $zero, $fcc0 ; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $2, $1, $3 ; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: andi $2, $2, 255 ; FP64-NEXT: andi $2, $2, 255
; FP64-NEXT: jr $ra ; FP64-NEXT: jr $ra
; FP64-NEXT: nop ; FP64-NEXT: nop
entry: entry:
%conv = fptoui double %a to i8 %conv = fptoui double %a to i8
ret i8 %conv ret i8 %conv
} }