Page MenuHomePhabricator

AMDGPU: Prepare to use scalar register indexing
ClosedPublic

Authored by arsenm on Jan 3 2020, 3:18 PM.

Details

Reviewers
rampitec
nhaehnle
Summary

Define pseudos mirroring the the VGPR indexing ones, and adjust the
operands in the s_movrel* instructions to avoid the result def.

Diff Detail

Event Timeline

arsenm created this revision.Jan 3 2020, 3:18 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 3 2020, 3:18 PM
arsenm updated this revision to Diff 236140.Jan 3 2020, 3:23 PM

Test update

rampitec added inline comments.Jan 20 2020, 11:17 AM
llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
425

It does not define anything. This is not good. It used to define a wrong register though, which is not good either. Can we have a version which will have a whole super reg def and then read the whole super reg as well?

arsenm marked an inline comment as done.Jan 20 2020, 12:46 PM
arsenm added inline comments.
llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
425

Do you mean just in the test? The way it works here is to keep the instruction definition matching the encoding. The pseudo-expansion adds the implicit use/def of the super register. The alternatives would be to multiply the number of movreld physical instruction definitions

rampitec accepted this revision.Jan 20 2020, 12:57 PM

LGTM. A verifier update is desirable though.

llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir
425

That is good to know. Although I think we need a verifier code to check for the presence of these impdef/impuse and update tests. Not necessarily in this change.

This revision is now accepted and ready to land.Jan 20 2020, 12:57 PM